1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1024CAG4A
4 ** MIMXRT1024CAG4B
5 ** MIMXRT1024DAG5A
6 ** MIMXRT1024DAG5B
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1024RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0
15 ** Version: rev. 1.0, 2021-08-10
16 ** Build: b220124
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2022 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 0.1 (2020-01-15)
34 ** Initial version.
35 ** - rev. 1.0 (2021-08-10)
36 ** Update header files to align with IMXRT1024RM Rev.1.
37 **
38 ** ###################################################################
39 */
40
41 /*!
42 * @file MIMXRT1024
43 * @version 1.0
44 * @date 240122
45 * @brief Device specific configuration file for MIMXRT1024 (implementation file)
46 *
47 * Provides a system configuration function and a global variable that contains
48 * the system frequency. It configures the device and initializes the oscillator
49 * (PLL) that is part of the microcontroller device.
50 */
51
52 #include <stdint.h>
53 #include "fsl_device_registers.h"
54 #include <string.h>
55
56
57 #define FLASH_CONFIG_ADDRESS (0x60000000U)
58 #define ROM_FLASH_INIT_ADDRESS (0x00210611U)
59
60 typedef int32_t (*flexspi_nor_init_t)(uint32_t flexspi_instance, void *config);
61
62 /* ----------------------------------------------------------------------------
63 -- Core clock
64 ---------------------------------------------------------------------------- */
65
66 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
67
68 /* ----------------------------------------------------------------------------
69 -- SystemInit()
70 ---------------------------------------------------------------------------- */
71
SystemInit(void)72 void SystemInit (void) {
73 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
74 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */
75 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
76 SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */
77 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
78 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
79
80 #if defined(__MCUXPRESSO)
81 extern uint32_t g_pfnVectors[]; /* Vector table defined in startup code */
82 SCB->VTOR = (uint32_t)g_pfnVectors;
83 #endif
84
85 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
86
87 /* Configure FLEXSPI_A_DQS */
88 IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
89
90 /* Disable I cache */
91 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
92 {
93 SCB_DisableICache();
94 }
95
96 /* Re-Configure FLEXSPI NOR via ROM API, for details please refer to the init function of ROM FLEXSPI NOR flash
97 driver which is in fsl_romapi.h and fsl_romapi.c in the devices\${soc}\drivers directory of SDK package */
98 uint8_t flexspi_nor_config[512];
99 memcpy((void *)flexspi_nor_config, (void *)FLASH_CONFIG_ADDRESS, sizeof(flexspi_nor_config));
100 flexspi_nor_config[12] = 1U; /* kFLEXSPIReadSampleClk_LoopbackFromDqsPad */
101 flexspi_nor_config[70] = 7U; /* kFLEXSPISerialClk_133MHz */
102
103 flexspi_nor_init_t flash_init = (flexspi_nor_init_t)ROM_FLASH_INIT_ADDRESS;
104 flash_init(0U, flexspi_nor_config);
105 #endif /* #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) */
106
107 /* Disable Watchdog Power Down Counter */
108 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
109 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
110
111 /* Watchdog disable */
112
113 #if (DISABLE_WDOG)
114 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
115 {
116 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
117 }
118 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
119 {
120 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
121 }
122 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
123 {
124 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
125 }
126 else
127 {
128 RTWDOG->CNT = 0xC520U;
129 RTWDOG->CNT = 0xD928U;
130 }
131 RTWDOG->TOVAL = 0xFFFF;
132 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
133 #endif /* (DISABLE_WDOG) */
134
135 /* Disable Systick which might be enabled by bootrom */
136 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
137 {
138 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
139 }
140
141 /* Enable instruction and data caches */
142 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
143 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
144 SCB_EnableICache();
145 }
146 #endif
147
148 SystemInitHook();
149 }
150
151 /* ----------------------------------------------------------------------------
152 -- SystemCoreClockUpdate()
153 ---------------------------------------------------------------------------- */
154
SystemCoreClockUpdate(void)155 void SystemCoreClockUpdate (void) {
156
157 uint32_t freq;
158 uint32_t PLL2MainClock;
159 uint32_t PLL3MainClock;
160
161 /* Check if system pll is bypassed */
162 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
163 {
164 PLL2MainClock = CPU_XTAL_CLK_HZ;
165 }
166 else
167 {
168 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
169 }
170 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
171
172 /* Check if usb1 pll is bypassed */
173 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
174 {
175 PLL3MainClock = CPU_XTAL_CLK_HZ;
176 }
177 else
178 {
179 PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
180 }
181
182 /* Periph_clk2_clk ---> Periph_clk */
183 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
184 {
185 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
186 {
187 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
188 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
189 freq = PLL3MainClock;
190 break;
191
192 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
193 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
194 freq = CPU_XTAL_CLK_HZ;
195 break;
196
197 /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
198 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
199 freq = CPU_XTAL_CLK_HZ;
200 break;
201
202 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
203 default:
204 freq = 0U;
205 break;
206 }
207
208 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
209 }
210 /* Pre_Periph_clk ---> Periph_clk */
211 else
212 {
213 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
214 {
215 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
216 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
217 freq = PLL2MainClock;
218 break;
219
220 /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
221 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
222 freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U;
223 break;
224
225 /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
226 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
227 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U;
228 break;
229
230 /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
231 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
232 freq = 500000000U / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
233 break;
234
235 default:
236 freq = 0U;
237 break;
238 }
239 }
240
241 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
242
243 }
244
245 /* ----------------------------------------------------------------------------
246 -- SystemInitHook()
247 ---------------------------------------------------------------------------- */
248
SystemInitHook(void)249 __attribute__ ((weak)) void SystemInitHook (void) {
250 /* Void implementation of the weak function. */
251 }
252
