1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_IOMUXC_H_
10 #define _FSL_IOMUXC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup iomuxc_driver
16 * @{
17 */
18
19 /*! @file */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24 /* Component ID definition, used by tools. */
25 #ifndef FSL_COMPONENT_ID
26 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
27 #endif
28
29 /*! @name Driver version */
30 /*@{*/
31 /*! @brief IOMUXC driver version 2.0.2. */
32 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
33 /*@}*/
34
35 /*!
36 * @name Pin function ID
37 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
38 *
39 * @{
40 */
41 #define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8188U
42 #define IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x401F8014U, 0x1U, 0x401F8420U, 0x0U, 0x401F8188U
43 #define IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x401F8014U, 0x2U, 0x401F83E0U, 0x0U, 0x401F8188U
44 #define IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x401F8014U, 0x3U, 0, 0, 0x401F8188U
45 #define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x4U, 0, 0, 0x401F8188U
46 #define IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8188U
47 #define IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x401F8014U, 0x6U, 0, 0, 0x401F8188U
48 #define IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x401F8014U, 0x7U, 0, 0, 0x401F8188U
49
50 #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F818CU
51 #define IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x401F8018U, 0x1U, 0x401F8424U, 0x0U, 0x401F818CU
52 #define IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x401F8018U, 0x2U, 0, 0, 0x401F818CU
53 #define IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x401F8018U, 0x3U, 0, 0, 0x401F818CU
54 #define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x4U, 0x401F83ACU, 0x0U, 0x401F818CU
55 #define IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F818CU
56 #define IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x401F8018U, 0x6U, 0x401F8320U, 0x0U, 0x401F818CU
57 #define IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x401F8018U, 0x7U, 0, 0, 0x401F818CU
58
59 #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F8190U
60 #define IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x401F801CU, 0x1U, 0x401F8428U, 0x0U, 0x401F8190U
61 #define IOMUXC_GPIO_EMC_02_LPUART4_TX 0x401F801CU, 0x2U, 0x401F83E8U, 0x0U, 0x401F8190U
62 #define IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x401F801CU, 0x3U, 0, 0, 0x401F8190U
63 #define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x4U, 0x401F83B8U, 0x0U, 0x401F8190U
64 #define IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F8190U
65 #define IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x401F801CU, 0x6U, 0x401F837CU, 0x0U, 0x401F8190U
66
67 #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8194U
68 #define IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x401F8020U, 0x1U, 0x401F842CU, 0x0U, 0x401F8194U
69 #define IOMUXC_GPIO_EMC_03_LPUART4_RX 0x401F8020U, 0x2U, 0x401F83E4U, 0x0U, 0x401F8194U
70 #define IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x401F8020U, 0x3U, 0, 0, 0x401F8194U
71 #define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x4U, 0x401F83B4U, 0x0U, 0x401F8194U
72 #define IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8194U
73 #define IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x401F8020U, 0x6U, 0x401F8380U, 0x0U, 0x401F8194U
74
75 #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8198U
76 #define IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x401F8024U, 0x1U, 0, 0, 0x401F8198U
77 #define IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x401F8024U, 0x2U, 0, 0, 0x401F8198U
78 #define IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x401F8024U, 0x3U, 0x401F8464U, 0x1U, 0x401F8198U
79 #define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x401F8024U, 0x4U, 0, 0, 0x401F8198U
80 #define IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8198U
81
82 #define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F819CU
83 #define IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x401F8028U, 0x1U, 0, 0, 0x401F819CU
84 #define IOMUXC_GPIO_EMC_05_SPDIF_IN 0x401F8028U, 0x2U, 0x401F8488U, 0x0U, 0x401F819CU
85 #define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x3U, 0x401F8468U, 0x1U, 0x401F819CU
86 #define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x401F8028U, 0x4U, 0, 0, 0x401F819CU
87 #define IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F819CU
88
89 #define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F81A0U
90 #define IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x401F802CU, 0x1U, 0, 0, 0x401F81A0U
91 #define IOMUXC_GPIO_EMC_06_LPUART3_TX 0x401F802CU, 0x2U, 0x401F83DCU, 0x0U, 0x401F81A0U
92 #define IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x401F802CU, 0x3U, 0, 0, 0x401F81A0U
93 #define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x401F802CU, 0x4U, 0, 0, 0x401F81A0U
94 #define IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F81A0U
95
96 #define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F81A4U
97 #define IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x401F8030U, 0x1U, 0, 0, 0x401F81A4U
98 #define IOMUXC_GPIO_EMC_07_LPUART3_RX 0x401F8030U, 0x2U, 0x401F83D8U, 0x0U, 0x401F81A4U
99 #define IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x401F8030U, 0x3U, 0x401F8460U, 0x1U, 0x401F81A4U
100 #define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x401F8030U, 0x4U, 0, 0, 0x401F81A4U
101 #define IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F81A4U
102
103 #define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F81A8U
104 #define IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x401F8034U, 0x1U, 0, 0, 0x401F81A8U
105 #define IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x401F8034U, 0x2U, 0, 0, 0x401F81A8U
106 #define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x3U, 0x401F845CU, 0x1U, 0x401F81A8U
107 #define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x401F8034U, 0x4U, 0, 0, 0x401F81A8U
108 #define IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F81A8U
109
110 #define IOMUXC_GPIO_EMC_09_SEMC_WE 0x401F8038U, 0x0U, 0, 0, 0x401F81ACU
111 #define IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x401F8038U, 0x1U, 0, 0, 0x401F81ACU
112 #define IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x401F8038U, 0x2U, 0x401F8324U, 0x1U, 0x401F81ACU
113 #define IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x401F8038U, 0x3U, 0x401F8458U, 0x1U, 0x401F81ACU
114 #define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x401F8038U, 0x4U, 0, 0, 0x401F81ACU
115 #define IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F81ACU
116
117 #define IOMUXC_GPIO_EMC_10_SEMC_CAS 0x401F803CU, 0x0U, 0, 0, 0x401F81B0U
118 #define IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x401F803CU, 0x1U, 0x401F84B0U, 0x0U, 0x401F81B0U
119 #define IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x401F803CU, 0x2U, 0x401F8398U, 0x0U, 0x401F81B0U
120 #define IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F81B0U
121 #define IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x401F803CU, 0x4U, 0, 0, 0x401F81B0U
122 #define IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F81B0U
123 #define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x401F803CU, 0x6U, 0, 0, 0x401F81B0U
124
125 #define IOMUXC_GPIO_EMC_11_SEMC_RAS 0x401F8040U, 0x0U, 0, 0, 0x401F81B4U
126 #define IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x401F8040U, 0x1U, 0, 0, 0x401F81B4U
127 #define IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x401F8040U, 0x2U, 0x401F8394U, 0x0U, 0x401F81B4U
128 #define IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x401F8040U, 0x3U, 0x401F844CU, 0x0U, 0x401F81B4U
129 #define IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x401F8040U, 0x4U, 0x401F83ACU, 0x1U, 0x401F81B4U
130 #define IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F81B4U
131 #define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x401F8040U, 0x6U, 0, 0, 0x401F81B4U
132
133 #define IOMUXC_GPIO_EMC_12_SEMC_CS0 0x401F8044U, 0x0U, 0, 0, 0x401F81B8U
134 #define IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x401F8044U, 0x1U, 0x401F84B4U, 0x0U, 0x401F81B8U
135 #define IOMUXC_GPIO_EMC_12_LPUART6_TX 0x401F8044U, 0x2U, 0x401F83F8U, 0x0U, 0x401F81B8U
136 #define IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x401F8044U, 0x3U, 0, 0, 0x401F81B8U
137 #define IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x401F8044U, 0x4U, 0x401F83B8U, 0x1U, 0x401F81B8U
138 #define IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F81B8U
139 #define IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x401F8044U, 0x6U, 0, 0, 0x401F81B8U
140
141 #define IOMUXC_GPIO_EMC_13_SEMC_BA0 0x401F8048U, 0x0U, 0, 0, 0x401F81BCU
142 #define IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x401F8048U, 0x1U, 0x401F84B8U, 0x0U, 0x401F81BCU
143 #define IOMUXC_GPIO_EMC_13_LPUART6_RX 0x401F8048U, 0x2U, 0x401F83F4U, 0x0U, 0x401F81BCU
144 #define IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x401F8048U, 0x3U, 0x401F8438U, 0x0U, 0x401F81BCU
145 #define IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x401F8048U, 0x4U, 0x401F83B4U, 0x1U, 0x401F81BCU
146 #define IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F81BCU
147 #define IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x401F8048U, 0x6U, 0, 0, 0x401F81BCU
148 #define IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x401F8048U, 0x7U, 0x401F8300U, 0x0U, 0x401F81BCU
149
150 #define IOMUXC_GPIO_EMC_14_SEMC_BA1 0x401F804CU, 0x0U, 0, 0, 0x401F81C0U
151 #define IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x401F804CU, 0x1U, 0x401F84A0U, 0x1U, 0x401F81C0U
152 #define IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x401F804CU, 0x2U, 0, 0, 0x401F81C0U
153 #define IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x401F804CU, 0x3U, 0x401F8434U, 0x1U, 0x401F81C0U
154 #define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F81C0U
155 #define IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F81C0U
156 #define IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x401F804CU, 0x6U, 0, 0, 0x401F81C0U
157
158 #define IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x401F8050U, 0x0U, 0, 0, 0x401F81C4U
159 #define IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x401F8050U, 0x1U, 0x401F84A4U, 0x1U, 0x401F81C4U
160 #define IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x401F8050U, 0x2U, 0, 0, 0x401F81C4U
161 #define IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x401F8050U, 0x3U, 0x401F8448U, 0x1U, 0x401F81C4U
162 #define IOMUXC_GPIO_EMC_15_WDOG1_B 0x401F8050U, 0x4U, 0, 0, 0x401F81C4U
163 #define IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F81C4U
164 #define IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x401F8050U, 0x6U, 0x401F8320U, 0x3U, 0x401F81C4U
165
166 #define IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x401F8054U, 0x0U, 0, 0, 0x401F81C8U
167 #define IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x401F8054U, 0x2U, 0, 0, 0x401F81C8U
168 #define IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x401F8054U, 0x3U, 0x401F8454U, 0x1U, 0x401F81C8U
169 #define IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F81C8U
170 #define IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x401F8054U, 0x6U, 0, 0, 0x401F81C8U
171
172 #define IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x401F8058U, 0x0U, 0, 0, 0x401F81CCU
173 #define IOMUXC_GPIO_EMC_17_MQS_LEFT 0x401F8058U, 0x2U, 0, 0, 0x401F81CCU
174 #define IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x401F8058U, 0x3U, 0x401F846CU, 0x1U, 0x401F81CCU
175 #define IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F81CCU
176 #define IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x401F8058U, 0x6U, 0, 0, 0x401F81CCU
177
178 #define IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x401F805CU, 0x0U, 0, 0, 0x401F81D0U
179 #define IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x401F805CU, 0x1U, 0x401F84A8U, 0x1U, 0x401F81D0U
180 #define IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x401F805CU, 0x2U, 0x401F8388U, 0x1U, 0x401F81D0U
181 #define IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x401F805CU, 0x3U, 0x401F8448U, 0x2U, 0x401F81D0U
182 #define IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x401F805CU, 0x4U, 0, 0, 0x401F81D0U
183 #define IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F81D0U
184 #define IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x401F805CU, 0x6U, 0, 0, 0x401F81D0U
185
186 #define IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x401F8060U, 0x0U, 0, 0, 0x401F81D4U
187 #define IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x401F8060U, 0x1U, 0x401F84ACU, 0x1U, 0x401F81D4U
188 #define IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x401F8060U, 0x2U, 0x401F8384U, 0x1U, 0x401F81D4U
189 #define IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x401F8060U, 0x3U, 0x401F8434U, 0x2U, 0x401F81D4U
190 #define IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x401F8060U, 0x4U, 0, 0, 0x401F81D4U
191 #define IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F81D4U
192 #define IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x401F8060U, 0x6U, 0, 0, 0x401F81D4U
193
194 #define IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x401F8064U, 0x0U, 0, 0, 0x401F81D8U
195 #define IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x401F8064U, 0x1U, 0x401F8334U, 0x1U, 0x401F81D8U
196 #define IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x401F8064U, 0x2U, 0x401F83CCU, 0x1U, 0x401F81D8U
197 #define IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x401F8064U, 0x3U, 0x401F8430U, 0x3U, 0x401F81D8U
198 #define IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x401F8064U, 0x4U, 0, 0, 0x401F81D8U
199 #define IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F81D8U
200 #define IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x401F8064U, 0x6U, 0, 0, 0x401F81D8U
201
202 #define IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x401F8068U, 0x0U, 0, 0, 0x401F81DCU
203 #define IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x401F8068U, 0x1U, 0x401F8344U, 0x1U, 0x401F81DCU
204 #define IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x401F8068U, 0x2U, 0, 0, 0x401F81DCU
205 #define IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x401F8068U, 0x3U, 0x401F8438U, 0x2U, 0x401F81DCU
206 #define IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x401F8068U, 0x4U, 0, 0, 0x401F81DCU
207 #define IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F81DCU
208 #define IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x401F8068U, 0x6U, 0, 0, 0x401F81DCU
209
210 #define IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x401F806CU, 0x0U, 0, 0, 0x401F81E0U
211 #define IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x401F806CU, 0x1U, 0x401F8330U, 0x1U, 0x401F81E0U
212 #define IOMUXC_GPIO_EMC_22_LPUART2_TX 0x401F806CU, 0x2U, 0x401F83D4U, 0x1U, 0x401F81E0U
213 #define IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x401F806CU, 0x3U, 0x401F843CU, 0x1U, 0x401F81E0U
214 #define IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x401F806CU, 0x4U, 0, 0, 0x401F81E0U
215 #define IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F81E0U
216 #define IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x401F806CU, 0x6U, 0, 0, 0x401F81E0U
217
218 #define IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x401F8070U, 0x0U, 0, 0, 0x401F81E4U
219 #define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x401F8070U, 0x1U, 0x401F8340U, 0x1U, 0x401F81E4U
220 #define IOMUXC_GPIO_EMC_23_LPUART2_RX 0x401F8070U, 0x2U, 0x401F83D0U, 0x1U, 0x401F81E4U
221 #define IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x401F8070U, 0x3U, 0x401F8440U, 0x1U, 0x401F81E4U
222 #define IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x401F8070U, 0x4U, 0, 0, 0x401F81E4U
223 #define IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F81E4U
224 #define IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x401F8070U, 0x6U, 0, 0, 0x401F81E4U
225
226 #define IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x401F8074U, 0x0U, 0, 0, 0x401F81E8U
227 #define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x401F8074U, 0x1U, 0x401F832CU, 0x1U, 0x401F81E8U
228 #define IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x401F8074U, 0x2U, 0, 0, 0x401F81E8U
229 #define IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x401F8074U, 0x3U, 0x401F8444U, 0x1U, 0x401F81E8U
230 #define IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x401F8074U, 0x4U, 0, 0, 0x401F81E8U
231 #define IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F81E8U
232 #define IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x401F8074U, 0x6U, 0, 0, 0x401F81E8U
233
234 #define IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x401F8078U, 0x0U, 0, 0, 0x401F81ECU
235 #define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x401F8078U, 0x1U, 0x401F833CU, 0x1U, 0x401F81ECU
236 #define IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x401F8078U, 0x2U, 0, 0, 0x401F81ECU
237 #define IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x401F8078U, 0x3U, 0, 0, 0x401F81ECU
238 #define IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x401F8078U, 0x4U, 0, 0, 0x401F81ECU
239 #define IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F81ECU
240 #define IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x401F8078U, 0x6U, 0, 0, 0x401F81ECU
241
242 #define IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x401F807CU, 0x0U, 0, 0, 0x401F81F0U
243 #define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x401F807CU, 0x1U, 0x401F8328U, 0x1U, 0x401F81F0U
244 #define IOMUXC_GPIO_EMC_26_LPUART8_TX 0x401F807CU, 0x2U, 0x401F8408U, 0x1U, 0x401F81F0U
245 #define IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x401F807CU, 0x3U, 0x401F844CU, 0x2U, 0x401F81F0U
246 #define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x401F807CU, 0x4U, 0, 0, 0x401F81F0U
247 #define IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F81F0U
248 #define IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x401F807CU, 0x6U, 0, 0, 0x401F81F0U
249
250 #define IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x401F8080U, 0x0U, 0, 0, 0x401F81F4U
251 #define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x401F8080U, 0x1U, 0x401F8338U, 0x1U, 0x401F81F4U
252 #define IOMUXC_GPIO_EMC_27_LPUART8_RX 0x401F8080U, 0x2U, 0x401F8404U, 0x1U, 0x401F81F4U
253 #define IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x401F8080U, 0x3U, 0x401F8450U, 0x2U, 0x401F81F4U
254 #define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x401F8080U, 0x4U, 0, 0, 0x401F81F4U
255 #define IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F81F4U
256 #define IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x401F8080U, 0x6U, 0, 0, 0x401F81F4U
257
258 #define IOMUXC_GPIO_EMC_28_SEMC_DQS 0x401F8084U, 0x0U, 0, 0, 0x401F81F8U
259 #define IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x401F8084U, 0x1U, 0x401F8354U, 0x1U, 0x401F81F8U
260 #define IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x401F8084U, 0x2U, 0x401F84BCU, 0x0U, 0x401F81F8U
261 #define IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x401F8084U, 0x3U, 0x401F846CU, 0x2U, 0x401F81F8U
262 #define IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x401F8084U, 0x4U, 0, 0, 0x401F81F8U
263 #define IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F81F8U
264 #define IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x401F8084U, 0x6U, 0, 0, 0x401F81F8U
265 #define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x401F8084U, 0x7U, 0, 0, 0x401F81F8U
266
267 #define IOMUXC_GPIO_EMC_29_SEMC_CKE 0x401F8088U, 0x0U, 0, 0, 0x401F81FCU
268 #define IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x401F8088U, 0x1U, 0x401F8364U, 0x1U, 0x401F81FCU
269 #define IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x401F8088U, 0x2U, 0x401F84C0U, 0x0U, 0x401F81FCU
270 #define IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x401F8088U, 0x3U, 0x401F8470U, 0x1U, 0x401F81FCU
271 #define IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x401F8088U, 0x4U, 0, 0, 0x401F81FCU
272 #define IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F81FCU
273 #define IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x401F8088U, 0x6U, 0, 0, 0x401F81FCU
274 #define IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x401F8088U, 0x7U, 0, 0, 0x401F81FCU
275
276 #define IOMUXC_GPIO_EMC_30_SEMC_CLK 0x401F808CU, 0x0U, 0, 0, 0x401F8200U
277 #define IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x401F808CU, 0x1U, 0x401F8350U, 0x1U, 0x401F8200U
278 #define IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x401F808CU, 0x2U, 0x401F83E0U, 0x1U, 0x401F8200U
279 #define IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x401F808CU, 0x3U, 0x401F8478U, 0x1U, 0x401F8200U
280 #define IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x401F808CU, 0x4U, 0, 0, 0x401F8200U
281 #define IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F8200U
282 #define IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x401F808CU, 0x6U, 0, 0, 0x401F8200U
283 #define IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x401F808CU, 0x7U, 0, 0, 0x401F8200U
284
285 #define IOMUXC_GPIO_EMC_31_SEMC_DM01 0x401F8090U, 0x0U, 0, 0, 0x401F8204U
286 #define IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x401F8090U, 0x1U, 0x401F8360U, 0x1U, 0x401F8204U
287 #define IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x401F8090U, 0x2U, 0, 0, 0x401F8204U
288 #define IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x401F8090U, 0x3U, 0x401F8474U, 0x1U, 0x401F8204U
289 #define IOMUXC_GPIO_EMC_31_WDOG2_B 0x401F8090U, 0x4U, 0, 0, 0x401F8204U
290 #define IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8204U
291 #define IOMUXC_GPIO_EMC_31_GPT2_CLK 0x401F8090U, 0x6U, 0, 0, 0x401F8204U
292 #define IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x401F8090U, 0x7U, 0, 0, 0x401F8204U
293
294 #define IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x401F8094U, 0x0U, 0, 0, 0x401F8208U
295 #define IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x401F8094U, 0x1U, 0x401F8410U, 0x1U, 0x401F8208U
296 #define IOMUXC_GPIO_EMC_32_LPUART4_TX 0x401F8094U, 0x2U, 0x401F83E8U, 0x2U, 0x401F8208U
297 #define IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x401F8094U, 0x3U, 0, 0, 0x401F8208U
298 #define IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x401F8094U, 0x4U, 0x401F83C0U, 0x1U, 0x401F8208U
299 #define IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x401F8094U, 0x5U, 0, 0, 0x401F8208U
300 #define IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x401F8094U, 0x7U, 0, 0, 0x401F8208U
301
302 #define IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x401F8098U, 0x0U, 0, 0, 0x401F820CU
303 #define IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x401F8098U, 0x1U, 0x401F8414U, 0x1U, 0x401F820CU
304 #define IOMUXC_GPIO_EMC_33_LPUART4_RX 0x401F8098U, 0x2U, 0x401F83E4U, 0x2U, 0x401F820CU
305 #define IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x401F8098U, 0x3U, 0x401F847CU, 0x1U, 0x401F820CU
306 #define IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x401F8098U, 0x4U, 0x401F83BCU, 0x1U, 0x401F820CU
307 #define IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x401F8098U, 0x5U, 0, 0, 0x401F820CU
308
309 #define IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x401F809CU, 0x0U, 0, 0, 0x401F8210U
310 #define IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x401F809CU, 0x1U, 0x401F8418U, 0x1U, 0x401F8210U
311 #define IOMUXC_GPIO_EMC_34_LPUART7_TX 0x401F809CU, 0x2U, 0x401F8400U, 0x1U, 0x401F8210U
312 #define IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x401F809CU, 0x3U, 0x401F8480U, 0x1U, 0x401F8210U
313 #define IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x401F809CU, 0x4U, 0x401F83C8U, 0x1U, 0x401F8210U
314 #define IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x401F809CU, 0x5U, 0, 0, 0x401F8210U
315 #define IOMUXC_GPIO_EMC_34_ENET_CRS 0x401F809CU, 0x6U, 0, 0, 0x401F8210U
316
317 #define IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x401F80A0U, 0x0U, 0, 0, 0x401F8214U
318 #define IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x401F80A0U, 0x1U, 0x401F841CU, 0x1U, 0x401F8214U
319 #define IOMUXC_GPIO_EMC_35_LPUART7_RX 0x401F80A0U, 0x2U, 0x401F83FCU, 0x1U, 0x401F8214U
320 #define IOMUXC_GPIO_EMC_35_USDHC2_WP 0x401F80A0U, 0x3U, 0x401F849CU, 0x1U, 0x401F8214U
321 #define IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x401F80A0U, 0x4U, 0x401F83C4U, 0x1U, 0x401F8214U
322 #define IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x401F80A0U, 0x5U, 0, 0, 0x401F8214U
323 #define IOMUXC_GPIO_EMC_35_ENET_COL 0x401F80A0U, 0x6U, 0, 0, 0x401F8214U
324
325 #define IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x401F80A4U, 0x0U, 0, 0, 0x401F8218U
326 #define IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x401F80A4U, 0x1U, 0x401F834CU, 0x1U, 0x401F8218U
327 #define IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x401F80A4U, 0x2U, 0, 0, 0x401F8218U
328 #define IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x401F80A4U, 0x3U, 0x401F8300U, 0x3U, 0x401F8218U
329 #define IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x401F80A4U, 0x4U, 0, 0, 0x401F8218U
330 #define IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x401F80A4U, 0x5U, 0, 0, 0x401F8218U
331 #define IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x401F80A4U, 0x6U, 0, 0, 0x401F8218U
332 #define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x7U, 0x401F8494U, 0x4U, 0x401F8218U
333
334 #define IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x401F80A8U, 0x0U, 0, 0, 0x401F821CU
335 #define IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x401F80A8U, 0x1U, 0x401F835CU, 0x1U, 0x401F821CU
336 #define IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x401F80A8U, 0x2U, 0, 0, 0x401F821CU
337 #define IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x401F80A8U, 0x3U, 0, 0, 0x401F821CU
338 #define IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x401F80A8U, 0x4U, 0, 0, 0x401F821CU
339 #define IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x401F80A8U, 0x5U, 0, 0, 0x401F821CU
340 #define IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x401F80A8U, 0x6U, 0, 0, 0x401F821CU
341 #define IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x401F80A8U, 0x7U, 0, 0, 0x401F821CU
342
343 #define IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x401F80ACU, 0x0U, 0, 0, 0x401F8220U
344 #define IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x401F80ACU, 0x1U, 0x401F8348U, 0x1U, 0x401F8220U
345 #define IOMUXC_GPIO_EMC_38_LPUART5_TX 0x401F80ACU, 0x2U, 0x401F83F0U, 0x1U, 0x401F8220U
346 #define IOMUXC_GPIO_EMC_38_MQS_LEFT 0x401F80ACU, 0x3U, 0, 0, 0x401F8220U
347 #define IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x401F80ACU, 0x4U, 0, 0, 0x401F8220U
348 #define IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x401F80ACU, 0x5U, 0, 0, 0x401F8220U
349 #define IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x401F80ACU, 0x6U, 0, 0, 0x401F8220U
350 #define IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x401F80ACU, 0x7U, 0x401F8490U, 0x3U, 0x401F8220U
351
352 #define IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x401F80B0U, 0x0U, 0, 0, 0x401F8224U
353 #define IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x401F80B0U, 0x1U, 0x401F8358U, 0x1U, 0x401F8224U
354 #define IOMUXC_GPIO_EMC_39_LPUART5_RX 0x401F80B0U, 0x2U, 0x401F83ECU, 0x1U, 0x401F8224U
355 #define IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x401F80B0U, 0x3U, 0x401F848CU, 0x2U, 0x401F8224U
356 #define IOMUXC_GPIO_EMC_39_WDOG1_B 0x401F80B0U, 0x4U, 0, 0, 0x401F8224U
357 #define IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x401F80B0U, 0x5U, 0, 0, 0x401F8224U
358 #define IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x401F80B0U, 0x6U, 0, 0, 0x401F8224U
359 #define IOMUXC_GPIO_EMC_39_GPT1_CLK 0x401F80B0U, 0x7U, 0, 0, 0x401F8224U
360
361 #define IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x401F80B4U, 0x0U, 0, 0, 0x401F8228U
362 #define IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x401F80B4U, 0x1U, 0x401F84BCU, 0x1U, 0x401F8228U
363 #define IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x401F80B4U, 0x2U, 0, 0, 0x401F8228U
364 #define IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x401F80B4U, 0x3U, 0x401F82FCU, 0x2U, 0x401F8228U
365 #define IOMUXC_GPIO_EMC_40_ENET_MDIO 0x401F80B4U, 0x4U, 0x401F8308U, 0x2U, 0x401F8228U
366 #define IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x401F80B4U, 0x5U, 0, 0, 0x401F8228U
367 #define IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x401F80B4U, 0x6U, 0, 0, 0x401F8228U
368 #define IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x401F80B4U, 0x7U, 0, 0, 0x401F8228U
369
370 #define IOMUXC_GPIO_EMC_41_SEMC_READY 0x401F80B8U, 0x0U, 0x401F8484U, 0x1U, 0x401F822CU
371 #define IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x401F80B8U, 0x1U, 0x401F84C0U, 0x1U, 0x401F822CU
372 #define IOMUXC_GPIO_EMC_41_SPDIF_IN 0x401F80B8U, 0x2U, 0x401F8488U, 0x1U, 0x401F822CU
373 #define IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F822CU
374 #define IOMUXC_GPIO_EMC_41_ENET_MDC 0x401F80B8U, 0x4U, 0, 0, 0x401F822CU
375 #define IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x401F80B8U, 0x5U, 0, 0, 0x401F822CU
376 #define IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x401F80B8U, 0x6U, 0, 0, 0x401F822CU
377 #define IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x401F80B8U, 0x7U, 0, 0, 0x401F822CU
378
379 #define IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x401F80BCU, 0x0U, 0, 0, 0x401F8230U
380 #define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F8230U
381 #define IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x401F80BCU, 0x7U, 0, 0, 0x401F8230U
382
383 #define IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x401F80C0U, 0x0U, 0, 0, 0x401F8234U
384 #define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F8234U
385 #define IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x401F80C0U, 0x7U, 0, 0, 0x401F8234U
386
387 #define IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x401F80C4U, 0x0U, 0, 0, 0x401F8238U
388 #define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F8238U
389 #define IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x401F80C4U, 0x7U, 0, 0, 0x401F8238U
390
391 #define IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x401F80C8U, 0x0U, 0, 0, 0x401F823CU
392 #define IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x401F80C8U, 0x1U, 0x401F8498U, 0x1U, 0x401F823CU
393 #define IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x401F80C8U, 0x2U, 0, 0, 0x401F823CU
394 #define IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x401F80C8U, 0x3U, 0x401F8430U, 0x1U, 0x401F823CU
395 #define IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x401F80C8U, 0x4U, 0x401F8494U, 0x0U, 0x401F823CU
396 #define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F823CU
397 #define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x6U, 0x401F848CU, 0x0U, 0x401F823CU
398 #define IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x401F80C8U, 0x7U, 0x401F8300U, 0x2U, 0x401F823CU
399
400 #define IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x401F80CCU, 0x0U, 0, 0, 0x401F8240U
401 #define IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x401F80CCU, 0x1U, 0, 0, 0x401F8240U
402 #define IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x401F80CCU, 0x2U, 0x401F8494U, 0x1U, 0x401F8240U
403 #define IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x401F80CCU, 0x3U, 0x401F8420U, 0x1U, 0x401F8240U
404 #define IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x401F80CCU, 0x4U, 0x401F8308U, 0x1U, 0x401F8240U
405 #define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F8240U
406 #define IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x401F80CCU, 0x6U, 0, 0, 0x401F8240U
407 #define IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x401F80CCU, 0x7U, 0, 0, 0x401F8240U
408
409 #define IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x401F80D0U, 0x0U, 0, 0, 0x401F8244U
410 #define IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x401F80D0U, 0x1U, 0x401F8320U, 0x2U, 0x401F8244U
411 #define IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x401F80D0U, 0x2U, 0x401F8490U, 0x1U, 0x401F8244U
412 #define IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x401F80D0U, 0x3U, 0x401F8424U, 0x1U, 0x401F8244U
413 #define IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x401F80D0U, 0x4U, 0, 0, 0x401F8244U
414 #define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F8244U
415 #define IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x401F80D0U, 0x6U, 0x401F82FCU, 0x0U, 0x401F8244U
416 #define IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x401F80D0U, 0x7U, 0x401F840CU, 0x0U, 0x401F8244U
417
418 #define IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x401F80D4U, 0x0U, 0, 0, 0x401F8248U
419 #define IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x401F80D4U, 0x1U, 0, 0, 0x401F8248U
420 #define IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x401F80D4U, 0x2U, 0, 0, 0x401F8248U
421 #define IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x401F80D4U, 0x3U, 0x401F8428U, 0x1U, 0x401F8248U
422 #define IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x401F80D4U, 0x4U, 0x401F8354U, 0x0U, 0x401F8248U
423 #define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F8248U
424 #define IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x401F80D4U, 0x6U, 0, 0, 0x401F8248U
425
426 #define IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x401F80D8U, 0x0U, 0, 0, 0x401F824CU
427 #define IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x401F80D8U, 0x1U, 0, 0, 0x401F824CU
428 #define IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x401F80D8U, 0x2U, 0, 0, 0x401F824CU
429 #define IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x401F80D8U, 0x3U, 0x401F842CU, 0x1U, 0x401F824CU
430 #define IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x401F80D8U, 0x4U, 0x401F8364U, 0x0U, 0x401F824CU
431 #define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F824CU
432 #define IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x401F80D8U, 0x6U, 0, 0, 0x401F824CU
433
434 #define IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x401F80DCU, 0x0U, 0x401F831CU, 0x1U, 0x401F8250U
435 #define IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x401F80DCU, 0x1U, 0x401F838CU, 0x1U, 0x401F8250U
436 #define IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x401F80DCU, 0x2U, 0, 0, 0x401F8250U
437 #define IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x401F80DCU, 0x3U, 0, 0, 0x401F8250U
438 #define IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x401F80DCU, 0x4U, 0x401F8304U, 0x1U, 0x401F8250U
439 #define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F8250U
440 #define IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x401F80DCU, 0x6U, 0, 0, 0x401F8250U
441
442 #define IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x401F80E0U, 0x0U, 0x401F8310U, 0x1U, 0x401F8254U
443 #define IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x401F80E0U, 0x1U, 0x401F8390U, 0x1U, 0x401F8254U
444 #define IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x401F80E0U, 0x2U, 0, 0, 0x401F8254U
445 #define IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x401F80E0U, 0x3U, 0, 0, 0x401F8254U
446 #define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F8254U
447 #define IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x401F80E0U, 0x6U, 0, 0, 0x401F8254U
448
449 #define IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x401F80E4U, 0x0U, 0x401F830CU, 0x1U, 0x401F8258U
450 #define IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x401F80E4U, 0x1U, 0x401F83A0U, 0x1U, 0x401F8258U
451 #define IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x401F80E4U, 0x2U, 0x401F83F0U, 0x0U, 0x401F8258U
452 #define IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x401F80E4U, 0x3U, 0, 0, 0x401F8258U
453 #define IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x401F80E4U, 0x4U, 0x401F8350U, 0x0U, 0x401F8258U
454 #define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F8258U
455 #define IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x401F80E4U, 0x6U, 0, 0, 0x401F8258U
456
457 #define IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x401F80E8U, 0x0U, 0x401F8314U, 0x1U, 0x401F825CU
458 #define IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x401F80E8U, 0x1U, 0x401F839CU, 0x1U, 0x401F825CU
459 #define IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x401F80E8U, 0x2U, 0x401F83ECU, 0x0U, 0x401F825CU
460 #define IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x401F80E8U, 0x3U, 0, 0, 0x401F825CU
461 #define IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x401F80E8U, 0x4U, 0x401F8360U, 0x0U, 0x401F825CU
462 #define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F825CU
463 #define IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x401F80E8U, 0x6U, 0, 0, 0x401F825CU
464
465 #define IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x401F80ECU, 0x0U, 0x401F8318U, 0x1U, 0x401F8260U
466 #define IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x401F80ECU, 0x1U, 0x401F83A8U, 0x1U, 0x401F8260U
467 #define IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x401F80ECU, 0x2U, 0, 0, 0x401F8260U
468 #define IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x401F80ECU, 0x3U, 0, 0, 0x401F8260U
469 #define IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x401F80ECU, 0x4U, 0x401F834CU, 0x0U, 0x401F8260U
470 #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F8260U
471 #define IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x401F80ECU, 0x6U, 0, 0, 0x401F8260U
472 #define IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x401F80ECU, 0x7U, 0, 0, 0x401F8260U
473
474 #define IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x401F80F0U, 0x0U, 0, 0, 0x401F8264U
475 #define IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x401F80F0U, 0x1U, 0x401F83A4U, 0x1U, 0x401F8264U
476 #define IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x401F80F0U, 0x2U, 0, 0, 0x401F8264U
477 #define IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x401F80F0U, 0x3U, 0, 0, 0x401F8264U
478 #define IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x401F80F0U, 0x4U, 0x401F835CU, 0x0U, 0x401F8264U
479 #define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F8264U
480 #define IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x401F80F0U, 0x6U, 0, 0, 0x401F8264U
481 #define IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x401F80F0U, 0x7U, 0, 0, 0x401F8264U
482
483 #define IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x401F80F4U, 0x0U, 0, 0, 0x401F8268U
484 #define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x1U, 0, 0, 0x401F8268U
485 #define IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x401F80F4U, 0x2U, 0x401F83DCU, 0x1U, 0x401F8268U
486 #define IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x401F80F4U, 0x3U, 0, 0, 0x401F8268U
487 #define IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x401F80F4U, 0x4U, 0x401F8348U, 0x0U, 0x401F8268U
488 #define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F8268U
489 #define IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x401F80F4U, 0x6U, 0, 0, 0x401F8268U
490 #define IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x401F80F4U, 0x7U, 0, 0, 0x401F8268U
491
492 #define IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x401F80F8U, 0x0U, 0, 0, 0x401F826CU
493 #define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x1U, 0x401F8324U, 0x2U, 0x401F826CU
494 #define IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x401F80F8U, 0x2U, 0x401F83D8U, 0x1U, 0x401F826CU
495 #define IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x401F80F8U, 0x3U, 0, 0, 0x401F826CU
496 #define IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x401F80F8U, 0x4U, 0x401F8358U, 0x0U, 0x401F826CU
497 #define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F826CU
498 #define IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x401F80F8U, 0x6U, 0, 0, 0x401F826CU
499
500 #define IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x401F8114U, 0x0U, 0, 0, 0x401F8288U
501 #define IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x401F8114U, 0x1U, 0x401F8328U, 0x0U, 0x401F8288U
502 #define IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x401F8114U, 0x2U, 0x401F83CCU, 0x0U, 0x401F8288U
503 #define IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x401F8114U, 0x3U, 0x401F8434U, 0x0U, 0x401F8288U
504 #define IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x401F8114U, 0x4U, 0, 0, 0x401F8288U
505 #define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8288U
506 #define IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x401F8114U, 0x6U, 0, 0, 0x401F8288U
507 #define IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x401F8114U, 0x7U, 0, 0, 0x401F8288U
508
509 #define IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x401F8118U, 0x0U, 0, 0, 0x401F828CU
510 #define IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x401F8118U, 0x1U, 0x401F8338U, 0x0U, 0x401F828CU
511 #define IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x401F8118U, 0x2U, 0, 0, 0x401F828CU
512 #define IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x401F8118U, 0x3U, 0x401F8444U, 0x0U, 0x401F828CU
513 #define IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x401F8118U, 0x4U, 0, 0, 0x401F828CU
514 #define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F828CU
515 #define IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x401F8118U, 0x6U, 0, 0, 0x401F828CU
516 #define IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x401F8118U, 0x7U, 0, 0, 0x401F828CU
517
518 #define IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x401F811CU, 0x0U, 0x401F8384U, 0x0U, 0x401F8290U
519 #define IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x401F811CU, 0x1U, 0x401F832CU, 0x0U, 0x401F8290U
520 #define IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x401F811CU, 0x2U, 0x401F83D4U, 0x0U, 0x401F8290U
521 #define IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x401F811CU, 0x3U, 0x401F8440U, 0x0U, 0x401F8290U
522 #define IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x401F811CU, 0x4U, 0, 0, 0x401F8290U
523 #define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F8290U
524 #define IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x401F811CU, 0x6U, 0, 0, 0x401F8290U
525 #define IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x401F811CU, 0x7U, 0x401F84B4U, 0x1U, 0x401F8290U
526
527 #define IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x401F8120U, 0x0U, 0x401F8388U, 0x0U, 0x401F8294U
528 #define IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x401F8120U, 0x1U, 0x401F833CU, 0x0U, 0x401F8294U
529 #define IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x401F8120U, 0x2U, 0x401F83D0U, 0x0U, 0x401F8294U
530 #define IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x401F8120U, 0x3U, 0x401F843CU, 0x0U, 0x401F8294U
531 #define IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 0x401F8120U, 0x4U, 0, 0, 0x401F8294U
532 #define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8294U
533 #define IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x401F8120U, 0x6U, 0, 0, 0x401F8294U
534 #define IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x401F8120U, 0x7U, 0x401F84B8U, 0x1U, 0x401F8294U
535
536 #define IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x401F8124U, 0x0U, 0, 0, 0x401F8298U
537 #define IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x401F8124U, 0x1U, 0x401F8330U, 0x0U, 0x401F8298U
538 #define IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x401F8124U, 0x2U, 0x401F83E8U, 0x1U, 0x401F8298U
539 #define IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x401F8124U, 0x3U, 0x401F8490U, 0x2U, 0x401F8298U
540 #define IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x401F8124U, 0x4U, 0, 0, 0x401F8298U
541 #define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8298U
542 #define IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x401F8124U, 0x6U, 0, 0, 0x401F8298U
543
544 #define IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x401F8128U, 0x0U, 0x401F82FCU, 0x1U, 0x401F829CU
545 #define IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x401F8128U, 0x1U, 0x401F8340U, 0x0U, 0x401F829CU
546 #define IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x401F8128U, 0x2U, 0x401F83E4U, 0x1U, 0x401F829CU
547 #define IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x401F8128U, 0x3U, 0x401F8494U, 0x3U, 0x401F829CU
548 #define IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x401F8128U, 0x4U, 0, 0, 0x401F829CU
549 #define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F829CU
550 #define IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x401F8128U, 0x6U, 0, 0, 0x401F829CU
551
552 #define IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x401F812CU, 0x0U, 0x401F848CU, 0x1U, 0x401F82A0U
553 #define IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x401F812CU, 0x1U, 0, 0, 0x401F82A0U
554 #define IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x401F812CU, 0x2U, 0, 0, 0x401F82A0U
555 #define IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x401F812CU, 0x3U, 0x401F8498U, 0x2U, 0x401F82A0U
556 #define IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x401F812CU, 0x4U, 0, 0, 0x401F82A0U
557 #define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F82A0U
558 #define IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x401F812CU, 0x6U, 0x401F8334U, 0x0U, 0x401F82A0U
559
560 #define IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x401F8130U, 0x0U, 0, 0, 0x401F82A4U
561 #define IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x401F8130U, 0x1U, 0, 0, 0x401F82A4U
562 #define IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x401F8130U, 0x2U, 0, 0, 0x401F82A4U
563 #define IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x401F8130U, 0x3U, 0x401F849CU, 0x0U, 0x401F82A4U
564 #define IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x401F8130U, 0x4U, 0, 0, 0x401F82A4U
565 #define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F82A4U
566 #define IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x401F8130U, 0x6U, 0x401F8344U, 0x0U, 0x401F82A4U
567
568 #define IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x401F8134U, 0x0U, 0x401F837CU, 0x1U, 0x401F82A8U
569 #define IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x401F8134U, 0x1U, 0, 0, 0x401F82A8U
570 #define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0, 0, 0x401F82A8U
571 #define IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x401F8134U, 0x3U, 0, 0, 0x401F82A8U
572 #define IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x401F8134U, 0x4U, 0, 0, 0x401F82A8U
573 #define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F82A8U
574
575 #define IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x401F8138U, 0x0U, 0x401F8380U, 0x1U, 0x401F82ACU
576 #define IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x401F8138U, 0x1U, 0, 0, 0x401F82ACU
577 #define IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x401F8138U, 0x2U, 0, 0, 0x401F82ACU
578 #define IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x401F8138U, 0x3U, 0, 0, 0x401F82ACU
579 #define IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x401F8138U, 0x4U, 0, 0, 0x401F82ACU
580 #define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F82ACU
581
582 #define IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x401F813CU, 0x0U, 0, 0, 0x401F82B0U
583 #define IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0x401F8410U, 0x0U, 0x401F82B0U
584 #define IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x401F813CU, 0x2U, 0x401F8430U, 0x0U, 0x401F82B0U
585 #define IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x401F813CU, 0x3U, 0x401F8454U, 0x0U, 0x401F82B0U
586 #define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F813CU, 0x4U, 0x401F838CU, 0x0U, 0x401F82B0U
587 #define IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x401F813CU, 0x5U, 0, 0, 0x401F82B0U
588 #define IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x401F813CU, 0x6U, 0, 0, 0x401F82B0U
589 #define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x401F813CU, 0x7U, 0x401F84A0U, 0x0U, 0x401F82B0U
590
591 #define IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x401F8140U, 0x0U, 0, 0, 0x401F82B4U
592 #define IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0x401F8414U, 0x0U, 0x401F82B4U
593 #define IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x401F8140U, 0x2U, 0, 0, 0x401F82B4U
594 #define IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x401F8140U, 0x3U, 0x401F8460U, 0x0U, 0x401F82B4U
595 #define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F8140U, 0x4U, 0x401F8390U, 0x0U, 0x401F82B4U
596 #define IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x401F8140U, 0x5U, 0, 0, 0x401F82B4U
597 #define IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x401F8140U, 0x6U, 0, 0, 0x401F82B4U
598 #define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x401F8140U, 0x7U, 0x401F84A4U, 0x0U, 0x401F82B4U
599
600 #define IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x401F8144U, 0x0U, 0, 0, 0x401F82B8U
601 #define IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0x401F8418U, 0x0U, 0x401F82B8U
602 #define IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x401F8144U, 0x2U, 0, 0, 0x401F82B8U
603 #define IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x401F8144U, 0x3U, 0x401F8458U, 0x0U, 0x401F82B8U
604 #define IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x401F8144U, 0x4U, 0x401F83A0U, 0x0U, 0x401F82B8U
605 #define IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x401F8144U, 0x5U, 0, 0, 0x401F82B8U
606 #define IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x401F8144U, 0x6U, 0x401F8308U, 0x0U, 0x401F82B8U
607 #define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x401F8144U, 0x7U, 0x401F84A8U, 0x0U, 0x401F82B8U
608
609 #define IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x401F8148U, 0x0U, 0, 0, 0x401F82BCU
610 #define IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x401F8148U, 0x1U, 0x401F841CU, 0x0U, 0x401F82BCU
611 #define IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x401F8148U, 0x2U, 0, 0, 0x401F82BCU
612 #define IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x401F8148U, 0x3U, 0x401F845CU, 0x0U, 0x401F82BCU
613 #define IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x401F8148U, 0x4U, 0x401F839CU, 0x0U, 0x401F82BCU
614 #define IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x401F8148U, 0x5U, 0, 0, 0x401F82BCU
615 #define IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x401F8148U, 0x6U, 0, 0, 0x401F82BCU
616
617 #define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x401F814CU, 0x0U, 0, 0, 0x401F82C0U
618 #define IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x401F814CU, 0x1U, 0, 0, 0x401F82C0U
619 #define IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x401F814CU, 0x2U, 0x401F8400U, 0x0U, 0x401F82C0U
620 #define IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x401F814CU, 0x3U, 0, 0, 0x401F82C0U
621 #define IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x401F814CU, 0x4U, 0x401F83A8U, 0x0U, 0x401F82C0U
622 #define IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x401F814CU, 0x5U, 0, 0, 0x401F82C0U
623 #define IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x401F814CU, 0x6U, 0, 0, 0x401F82C0U
624
625 #define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x401F8150U, 0x0U, 0, 0, 0x401F82C4U
626 #define IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x401F8150U, 0x1U, 0x401F8324U, 0x0U, 0x401F82C4U
627 #define IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x401F8150U, 0x2U, 0x401F83FCU, 0x0U, 0x401F82C4U
628 #define IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x401F8150U, 0x3U, 0x401F8464U, 0x0U, 0x401F82C4U
629 #define IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x401F8150U, 0x4U, 0x401F83A4U, 0x0U, 0x401F82C4U
630 #define IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x401F8150U, 0x5U, 0, 0, 0x401F82C4U
631 #define IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x401F8150U, 0x6U, 0, 0, 0x401F82C4U
632
633 #define IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x401F8154U, 0x0U, 0x401F8490U, 0x0U, 0x401F82C8U
634 #define IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x401F8154U, 0x1U, 0, 0, 0x401F82C8U
635 #define IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x401F8154U, 0x2U, 0, 0, 0x401F82C8U
636 #define IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x401F8154U, 0x3U, 0x401F8468U, 0x0U, 0x401F82C8U
637 #define IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x401F8154U, 0x4U, 0, 0, 0x401F82C8U
638 #define IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x401F8154U, 0x5U, 0, 0, 0x401F82C8U
639 #define IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x401F8154U, 0x6U, 0x401F84ACU, 0x0U, 0x401F82C8U
640
641 #define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x401F8158U, 0x0U, 0, 0, 0x401F82CCU
642 #define IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x401F8158U, 0x1U, 0, 0, 0x401F82CCU
643 #define IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x401F8158U, 0x2U, 0x401F83F8U, 0x1U, 0x401F82CCU
644 #define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x401F8158U, 0x3U, 0x401F84B0U, 0x1U, 0x401F82CCU
645 #define IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x401F8158U, 0x4U, 0, 0, 0x401F82CCU
646 #define IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x401F8158U, 0x5U, 0, 0, 0x401F82CCU
647
648 #define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x401F815CU, 0x0U, 0, 0, 0x401F82D0U
649 #define IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x401F815CU, 0x1U, 0, 0, 0x401F82D0U
650 #define IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x401F815CU, 0x2U, 0x401F83F4U, 0x1U, 0x401F82D0U
651 #define IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x401F815CU, 0x3U, 0, 0, 0x401F82D0U
652 #define IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x401F815CU, 0x4U, 0x401F8320U, 0x1U, 0x401F82D0U
653 #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x401F815CU, 0x5U, 0, 0, 0x401F82D0U
654
655 #define IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x401F8160U, 0x0U, 0, 0, 0x401F82D4U
656 #define IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x401F8160U, 0x1U, 0, 0, 0x401F82D4U
657 #define IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x401F8160U, 0x2U, 0x401F8408U, 0x0U, 0x401F82D4U
658 #define IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x401F8160U, 0x3U, 0x401F8394U, 0x1U, 0x401F82D4U
659 #define IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x401F8160U, 0x4U, 0, 0, 0x401F82D4U
660 #define IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x401F8160U, 0x5U, 0, 0, 0x401F82D4U
661 #define IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x401F8160U, 0x6U, 0, 0, 0x401F82D4U
662
663 #define IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x401F8164U, 0x0U, 0, 0, 0x401F82D8U
664 #define IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x401F8164U, 0x1U, 0, 0, 0x401F82D8U
665 #define IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x401F8164U, 0x2U, 0x401F8404U, 0x0U, 0x401F82D8U
666 #define IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x401F8164U, 0x3U, 0x401F8398U, 0x1U, 0x401F82D8U
667 #define IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x401F8164U, 0x4U, 0, 0, 0x401F82D8U
668 #define IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x401F8164U, 0x5U, 0, 0, 0x401F82D8U
669 #define IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x401F8164U, 0x6U, 0, 0, 0x401F82D8U
670
671 #define IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x401F8168U, 0x0U, 0, 0, 0x401F82DCU
672 #define IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x401F8168U, 0x1U, 0, 0, 0x401F82DCU
673 #define IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x401F8168U, 0x2U, 0x401F831CU, 0x0U, 0x401F82DCU
674 #define IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x401F8168U, 0x3U, 0x401F8304U, 0x0U, 0x401F82DCU
675 #define IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x401F8168U, 0x4U, 0, 0, 0x401F82DCU
676 #define IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x401F8168U, 0x5U, 0, 0, 0x401F82DCU
677 #define IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x401F8168U, 0x6U, 0, 0, 0x401F82DCU
678
679 #define IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x401F816CU, 0x0U, 0, 0, 0x401F82E0U
680 #define IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x401F816CU, 0x1U, 0, 0, 0x401F82E0U
681 #define IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x401F816CU, 0x2U, 0x401F8310U, 0x0U, 0x401F82E0U
682 #define IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x401F816CU, 0x3U, 0x401F846CU, 0x0U, 0x401F82E0U
683 #define IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x401F816CU, 0x4U, 0, 0, 0x401F82E0U
684 #define IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x401F816CU, 0x5U, 0, 0, 0x401F82E0U
685 #define IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x401F816CU, 0x6U, 0x401F8300U, 0x1U, 0x401F82E0U
686
687 #define IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x401F8170U, 0x0U, 0x401F8498U, 0x0U, 0x401F82E4U
688 #define IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x401F8170U, 0x1U, 0x401F8374U, 0x0U, 0x401F82E4U
689 #define IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x401F8170U, 0x2U, 0x401F830CU, 0x0U, 0x401F82E4U
690 #define IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x401F8170U, 0x3U, 0x401F847CU, 0x0U, 0x401F82E4U
691 #define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F8170U, 0x4U, 0x401F83ACU, 0x2U, 0x401F82E4U
692 #define IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x401F8170U, 0x5U, 0, 0, 0x401F82E4U
693 #define IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x401F8170U, 0x6U, 0, 0, 0x401F82E4U
694
695 #define IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x401F8174U, 0x0U, 0, 0, 0x401F82E8U
696 #define IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x401F8174U, 0x1U, 0x401F8378U, 0x0U, 0x401F82E8U
697 #define IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x401F8174U, 0x2U, 0x401F8314U, 0x0U, 0x401F82E8U
698 #define IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x401F8174U, 0x3U, 0x401F8480U, 0x0U, 0x401F82E8U
699 #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F8174U, 0x4U, 0, 0, 0x401F82E8U
700 #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x401F8174U, 0x5U, 0, 0, 0x401F82E8U
701
702 #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F8178U, 0x0U, 0, 0, 0x401F82ECU
703 #define IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x401F8178U, 0x1U, 0x401F8368U, 0x0U, 0x401F82ECU
704 #define IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x401F8178U, 0x2U, 0x401F8318U, 0x0U, 0x401F82ECU
705 #define IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x401F8178U, 0x3U, 0, 0, 0x401F82ECU
706 #define IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x401F8178U, 0x4U, 0x401F83B8U, 0x2U, 0x401F82ECU
707 #define IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x401F8178U, 0x5U, 0, 0, 0x401F82ECU
708
709 #define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F817CU, 0x0U, 0, 0, 0x401F82F0U
710 #define IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x401F817CU, 0x1U, 0x401F8370U, 0x0U, 0x401F82F0U
711 #define IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x401F817CU, 0x2U, 0, 0, 0x401F82F0U
712 #define IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x401F817CU, 0x3U, 0x401F8470U, 0x0U, 0x401F82F0U
713 #define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F817CU, 0x4U, 0x401F83B4U, 0x2U, 0x401F82F0U
714 #define IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x401F817CU, 0x5U, 0, 0, 0x401F82F0U
715
716 #define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F8180U, 0x0U, 0, 0, 0x401F82F4U
717 #define IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x401F8180U, 0x1U, 0x401F836CU, 0x0U, 0x401F82F4U
718 #define IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x401F8180U, 0x2U, 0, 0, 0x401F82F4U
719 #define IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x401F8180U, 0x3U, 0x401F8478U, 0x0U, 0x401F82F4U
720 #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F8180U, 0x4U, 0, 0, 0x401F82F4U
721 #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x401F8180U, 0x5U, 0, 0, 0x401F82F4U
722
723 #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8184U, 0x0U, 0, 0, 0x401F82F8U
724 #define IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x401F8184U, 0x1U, 0, 0, 0x401F82F8U
725 #define IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x401F8184U, 0x2U, 0, 0, 0x401F82F8U
726 #define IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x401F8184U, 0x3U, 0x401F8474U, 0x0U, 0x401F82F8U
727 #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8184U, 0x4U, 0, 0, 0x401F82F8U
728 #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x401F8184U, 0x5U, 0, 0, 0x401F82F8U
729
730 #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
731 #define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F840CU, 0x1U, 0x400A8018U
732
733 #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
734 #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
735
736 #define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U
737 #define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U
738
739 #define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU
740
741 #define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U
742
743 #define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U
744
745 /*@}*/
746
747 #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
748 #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
749
750 typedef enum _iomuxc_gpr_mode
751 {
752 kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
753 kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK,
754 kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK,
755 kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
756 kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
757 kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
758 kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
759 kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
760 } iomuxc_gpr_mode_t;
761
762 typedef enum _iomuxc_gpr_saimclk
763 {
764 kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
765 kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
766 kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
767 kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
768 kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
769 } iomuxc_gpr_saimclk_t;
770
771 typedef enum _iomuxc_mqs_pwm_oversample_rate
772 {
773 kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */
774 kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */
775 } iomuxc_mqs_pwm_oversample_rate_t;
776
777 #if defined(__cplusplus)
778 extern "C" {
779 #endif /*_cplusplus */
780
781 /*! @name Configuration */
782 /*@{*/
783
784 /*!
785 * @brief Sets the IOMUXC pin mux mode.
786 * @note The first five parameters can be filled with the pin function ID macros.
787 *
788 * This is an example to set the PTA6 as the lpuart0_tx:
789 * @code
790 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
791 * @endcode
792 *
793 * This is an example to set the PTA0 as GPIOA0:
794 * @code
795 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
796 * @endcode
797 *
798 * @param muxRegister The pin mux register.
799 * @param muxMode The pin mux mode.
800 * @param inputRegister The select input register.
801 * @param inputDaisy The input daisy.
802 * @param configRegister The config register.
803 * @param inputOnfield Software input on field.
804 */
IOMUXC_SetPinMux(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t inputOnfield)805 static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
806 uint32_t muxMode,
807 uint32_t inputRegister,
808 uint32_t inputDaisy,
809 uint32_t configRegister,
810 uint32_t inputOnfield)
811 {
812 *((volatile uint32_t *)muxRegister) =
813 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
814
815 if (inputRegister != 0UL)
816 {
817 *((volatile uint32_t *)inputRegister) = inputDaisy;
818 }
819 }
820
821 /*!
822 * @brief Sets the IOMUXC pin configuration.
823 * @note The previous five parameters can be filled with the pin function ID macros.
824 *
825 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
826 * @code
827 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
828 * @endcode
829 *
830 * @param muxRegister The pin mux register.
831 * @param muxMode The pin mux mode.
832 * @param inputRegister The select input register.
833 * @param inputDaisy The input daisy.
834 * @param configRegister The config register.
835 * @param configValue The pin config value.
836 */
IOMUXC_SetPinConfig(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t configValue)837 static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
838 uint32_t muxMode,
839 uint32_t inputRegister,
840 uint32_t inputDaisy,
841 uint32_t configRegister,
842 uint32_t configValue)
843 {
844 if (configRegister != 0UL)
845 {
846 *((volatile uint32_t *)configRegister) = configValue;
847 }
848 }
849
850 /*!
851 * @brief Sets IOMUXC general configuration for some mode.
852 *
853 * @param base The IOMUXC GPR base address.
854 * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
855 * @param enable True enable false disable.
856 */
IOMUXC_EnableMode(IOMUXC_GPR_Type * base,uint32_t mode,bool enable)857 static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
858 {
859 mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
860 IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
861 IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
862
863 if (enable)
864 {
865 base->GPR1 |= mode;
866 }
867 else
868 {
869 base->GPR1 &= ~mode;
870 }
871 }
872
873 /*!
874 * @brief Sets IOMUXC general configuration for SAI MCLK selection.
875 *
876 * @param base The IOMUXC GPR base address.
877 * @param mclk The SAI MCLK.
878 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
879 */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type * base,iomuxc_gpr_saimclk_t mclk,uint8_t clkSrc)880 static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
881 {
882 uint32_t gpr;
883
884 if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
885 {
886 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
887 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
888 }
889 else
890 {
891 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
892 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
893 }
894 }
895
896 /*!
897 * @brief Enters or exit MQS software reset.
898 *
899 * @param base The IOMUXC GPR base address.
900 * @param enable Enter or exit MQS software reset.
901 */
IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type * base,bool enable)902 static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)
903 {
904 if (enable)
905 {
906 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
907 }
908 else
909 {
910 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
911 }
912 }
913
914 /*!
915 * @brief Enables or disables MQS.
916 *
917 * @param base The IOMUXC GPR base address.
918 * @param enable Enable or disable the MQS.
919 */
IOMUXC_MQSEnable(IOMUXC_GPR_Type * base,bool enable)920 static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
921 {
922 if (enable)
923 {
924 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
925 }
926 else
927 {
928 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
929 }
930 }
931
932 /*!
933 * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
934 *
935 * @param base The IOMUXC GPR base address.
936 * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
937 * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.
938 */
939
IOMUXC_MQSConfig(IOMUXC_GPR_Type * base,iomuxc_mqs_pwm_oversample_rate_t rate,uint8_t divider)940 static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
941 {
942 uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
943 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
944 }
945
946 /*@}*/
947
948 #if defined(__cplusplus)
949 }
950 #endif /*_cplusplus */
951
952 /*! @}*/
953
954 #endif /* _FSL_IOMUXC_H_ */
955
