1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1015CAF4A
4 **                          MIMXRT1015DAF5A
5 **
6 **     Compilers:           Freescale C/C++ for Embedded ARM
7 **                          GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    IMXRT1015RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0
13 **     Version:             rev. 1.3, 2021-08-10
14 **     Build:               b210810
15 **
16 **     Abstract:
17 **         Provides a system configuration function and a global variable that
18 **         contains the system frequency. It configures the device and initializes
19 **         the oscillator (PLL) that is part of the microcontroller device.
20 **
21 **     Copyright 2016 Freescale Semiconductor, Inc.
22 **     Copyright 2016-2021 NXP
23 **     All rights reserved.
24 **
25 **     SPDX-License-Identifier: BSD-3-Clause
26 **
27 **     http:                 www.nxp.com
28 **     mail:                 support@nxp.com
29 **
30 **     Revisions:
31 **     - rev. 0.1 (2018-11-05)
32 **         Initial version.
33 **     - rev. 1.0 (2019-01-18)
34 **         Rev.0 Header GA
35 **     - rev. 1.1 (2019-02-20)
36 **         Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP.
37 **     - rev. 1.2 (2019-04-29)
38 **         Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
39 **     - rev. 1.3 (2021-08-10)
40 **         Update header files to align with IMXRT1015RM Rev.1.
41 **
42 ** ###################################################################
43 */
44 
45 /*!
46  * @file MIMXRT1015
47  * @version 1.3
48  * @date 2021-08-10
49  * @brief Device specific configuration file for MIMXRT1015 (implementation file)
50  *
51  * Provides a system configuration function and a global variable that contains
52  * the system frequency. It configures the device and initializes the oscillator
53  * (PLL) that is part of the microcontroller device.
54  */
55 
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58 
59 
60 
61 /* ----------------------------------------------------------------------------
62    -- Core clock
63    ---------------------------------------------------------------------------- */
64 
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66 
67 /* ----------------------------------------------------------------------------
68    -- SystemInit()
69    ---------------------------------------------------------------------------- */
70 
SystemInit(void)71 void SystemInit (void) {
72 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
73   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
74 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
75 
76 #if defined(__MCUXPRESSO)
77     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
78     SCB->VTOR = (uint32_t)g_pfnVectors;
79 #endif
80 
81 /* Disable Watchdog Power Down Counter */
82     WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
83     WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
84 
85 /* Watchdog disable */
86 
87 #if (DISABLE_WDOG)
88     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
89     {
90         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
91     }
92     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
93     {
94         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
95     }
96     if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
97     {
98         RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
99     }
100     else
101     {
102         RTWDOG->CNT = 0xC520U;
103         RTWDOG->CNT = 0xD928U;
104     }
105     RTWDOG->TOVAL = 0xFFFF;
106     RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
107 #endif /* (DISABLE_WDOG) */
108 
109     /* Disable Systick which might be enabled by bootrom */
110     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
111     {
112         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
113     }
114 
115 /* Enable instruction and data caches */
116 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
117     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
118         SCB_EnableICache();
119     }
120 #endif
121 
122   SystemInitHook();
123 }
124 
125 /* ----------------------------------------------------------------------------
126    -- SystemCoreClockUpdate()
127    ---------------------------------------------------------------------------- */
128 
SystemCoreClockUpdate(void)129 void SystemCoreClockUpdate (void) {
130 
131     uint32_t freq;
132     uint32_t PLL2MainClock;
133     uint32_t PLL3MainClock;
134 
135     /* Check if system pll is bypassed */
136     if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
137     {
138         PLL2MainClock = CPU_XTAL_CLK_HZ;
139     }
140     else
141     {
142         PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
143     }
144     PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
145 
146     /* Check if usb1 pll is bypassed */
147     if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
148     {
149         PLL3MainClock = CPU_XTAL_CLK_HZ;
150     }
151     else
152     {
153         PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
154     }
155 
156     /* Periph_clk2_clk ---> Periph_clk */
157     if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
158     {
159         switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
160         {
161             /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
162             case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
163                 freq = PLL3MainClock;
164                 break;
165 
166             /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
167             case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
168                 freq = CPU_XTAL_CLK_HZ;
169                 break;
170 
171             /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
172             case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
173                 freq = CPU_XTAL_CLK_HZ;
174                 break;
175 
176             case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
177             default:
178                 freq = 0U;
179                 break;
180         }
181 
182         freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
183     }
184     /* Pre_Periph_clk ---> Periph_clk */
185     else
186     {
187         switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
188         {
189             /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
190             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
191                 freq = PLL2MainClock;
192                 break;
193 
194             /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
195             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
196                 freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U;
197                 break;
198 
199             /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
200             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
201                 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U;
202                 break;
203 
204             /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
205             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
206                 freq = 500000000U / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
207                 break;
208 
209             default:
210                 freq = 0U;
211                 break;
212         }
213     }
214 
215     SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
216 
217 }
218 
219 /* ----------------------------------------------------------------------------
220    -- SystemInitHook()
221    ---------------------------------------------------------------------------- */
222 
SystemInitHook(void)223 __attribute__ ((weak)) void SystemInitHook (void) {
224   /* Void implementation of the weak function. */
225 }
226