1/*
2** ###################################################################
3**     Processors:          MIMX9352CVUXK_cm33
4**                          MIMX9352DVUXM_cm33
5**
6**     Compiler:            IAR ANSI C/C++ Compiler for ARM
7**     Reference manual:    IMX93RM, Internal, November. 2021
8**     Version:             rev. 1.0, 2021-11-16
9**     Build:               b220830
10**
11**     Abstract:
12**         Linker file for the IAR ANSI C/C++ Compiler for ARM
13**
14**     Copyright 2016 Freescale Semiconductor, Inc.
15**     Copyright 2016-2022 NXP
16**     All rights reserved.
17**
18**     SPDX-License-Identifier: BSD-3-Clause
19**
20**     http:                 www.nxp.com
21**     mail:                 support@nxp.com
22**
23** ###################################################################
24*/
25
26/* Memory region from [0x80000000-0x80001FFF] is reserved for ROM header */
27/* Memory region from [0x20040000-0x2007FFFF] is reserved for A55 ATF */
28
29define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000478 : 0;
30define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000477 : 0;
31
32define symbol m_interrupts_start       = 0x80002000;
33define symbol m_interrupts_end         = 0x80002477;
34
35define symbol m_text_start             = 0x80002478;
36define symbol m_text_end               = 0x803FFFFF;
37
38define symbol m_m33_suspend_ram_start  = 0x20000000;
39define symbol m_m33_suspend_ram_end    = 0x20001FFF;
40
41define symbol m_a55_suspend_ram_start  = 0x20002000;
42define symbol m_a55_suspend_ram_end    = 0x20002FFF;
43
44define symbol m_interrupts_ram_start   = 0x0FFE0000;
45define symbol m_interrupts_ram_end     = 0x0FFE0000 + __ram_vector_table_offset__;
46
47define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
48define symbol m_data_end               = 0x0FFFFFFF;
49
50define symbol m_data_2_start           = 0x20008000;
51define symbol m_data_2_end             = 0x2003FFFF;
52
53/* Sizes */
54if (isdefinedsymbol(__stack_size__)) {
55  define symbol __size_cstack__        = __stack_size__;
56} else {
57  define symbol __size_cstack__        = 0x0400;
58}
59
60if (isdefinedsymbol(__heap_size__)) {
61  define symbol __size_heap__          = __heap_size__;
62} else {
63  define symbol __size_heap__          = 0x0400;
64}
65
66define exported symbol __VECTOR_TABLE  = m_interrupts_start;
67define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
68define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
69
70define memory mem with size = 4G;
71define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
72                          | mem:[from m_text_start to m_text_end];
73define region DATA_region = mem:[from m_data_start to m_data_end]
74                          | mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
75define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
76define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
77define region M33_SUSPEND_region = mem:[from m_m33_suspend_ram_start to m_m33_suspend_ram_end];
78define region A55_SUSPEND_region = mem:[from m_a55_suspend_ram_start to m_a55_suspend_ram_end];
79
80define block CSTACK    with alignment = 8, size = __size_cstack__   { };
81define block HEAP      with alignment = 8, size = __size_heap__     { };
82define block RW        { readwrite };
83define block ZI        { zi };
84define block QACCESS_CODE_VAR   with alignment = 32 { section CodeQuickAccess };
85define block QACCESS_DATA_VAR   with alignment = 32 { section DataQuickAccess };
86
87initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess };
88do not initialize  { section .noinit, section M33SuspendRam, section A55SuspendRam };
89
90keep{section .resource_table};
91
92place at address mem: m_interrupts_start    { readonly section .intvec };
93".resource_table": place at address mem: m_text_start {section .resource_table};
94place in TEXT_region                        { readonly };
95place in DATA_region                        { block QACCESS_CODE_VAR };
96place in DATA_region                        { block QACCESS_DATA_VAR };
97place in DATA_region                        { block RW };
98place in DATA_region                        { block ZI };
99place in DATA_region                        { last block HEAP };
100place in CSTACK_region                      { block CSTACK };
101place in m_interrupts_ram_region            { section m_interrupts_ram };
102place in M33_SUSPEND_region                 { section M33SuspendRam };
103place in A55_SUSPEND_region                 { section A55SuspendRam };
104