1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "fsl_common.h"
9 #include "clock_config.h"
10 
11 /*******************************************************************************
12  * Definitions
13  ******************************************************************************/
14 
15 /* OSC 27M configuration */
16 const osc_config_t g_osc27MConfig = {
17     .oscMode = kOSC_OscMode, .oscDiv = 1U,
18 };
19 
20 /* OSC 25M configuration */
21 const osc_config_t g_osc25MConfig = {
22     .oscMode = kOSC_OscMode, .oscDiv = 1U,
23 };
24 
25 /* AUDIO PLL1 configuration */
26 const ccm_analog_frac_pll_config_t g_audioPll1Config = {
27     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
28     .refDiv = 5U,                   /*!< PLL input = 25 / 5 = 5M */
29     .fractionDiv = 0U,
30     .intDiv = 64U, /*!< Integer and fractional Divider output  = 5 * (1 + 64) * 8 = 2600MHZ */
31     .outDiv = 4U,  /*!< Pll out frequency  = 2600 / 4 = 650MHZ */
32 };
33 
34 /* AUDIO PLL2 configuration */
35 const ccm_analog_frac_pll_config_t g_audioPll2Config = {
36     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
37     .refDiv = 5U,                   /*!< PLL input = 25 / 5 = 5M */
38     .fractionDiv = 0U,
39     .intDiv = 64U, /*!< Integer and fractional Divider output  = 5 * (1 + 64) * 8 = 2600MHZ */
40     .outDiv = 4U,  /*!< Pll out frequency  = 2600 / 4 = 650MHZ */
41 };
42 
43 /* VIDEO PLL1 configuration */
44 const ccm_analog_frac_pll_config_t g_videoPll1Config = {
45     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
46     .refDiv = 5U,                   /*!< PLL input = 25 / 5 = 5M */
47     .fractionDiv = 0U,
48     .intDiv = 64U, /*!< Integer and fractional Divider output  = 5 * (1 + 64) * 8 = 2600MHZ */
49     .outDiv = 4U,  /*!< Pll out frequency  = 2600 / 4 = 650MHZ */
50 };
51 
52 /* SYSTEM PLL1 configuration */
53 const ccm_analog_sscg_pll_config_t g_sysPll1Config = {
54     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
55     .refDiv1 = 1U,                  /*!< PLL1 input = 25 / 1 = 25MHZ */
56     .loopDivider1 = 32U,            /*!< PLL1 output  = 25 * 32 * 2 = 1600MHZ */
57     .refDiv2 = 24U,                 /*!< PLL2 input  = 1600 / 24 = 66.66MHZ */
58     .loopDivider2 = 12U,            /*!< PLL2 output  = 12 * 66.66 * 2 = 1600MHZ */
59     .outDiv = 1U,                   /*!< PLL output = 1600 / 2 / 1 = 800MHZ */
60 };
61 
62 /* SYSTEM PLL2 configuration */
63 const ccm_analog_sscg_pll_config_t g_sysPll2Config = {
64     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
65     .refDiv1 = 1U,                  /*!< PLL1 input = 25 / 1 = 25MHZ */
66     .loopDivider1 = 32U,            /*!< PLL1 output  = 25 * 32 * 2 = 1600MHZ */
67     .refDiv2 = 16U,                 /*!< PLL2 input  = 1600 / 16 = 100MHZ */
68     .loopDivider2 = 10U,            /*!< PLL2 output  = 10 * 100 * 2 = 2000MHZ */
69     .outDiv = 1U,                   /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
70 };
71 
72 /* SYSTEM PLL3 configuration */
73 const ccm_analog_sscg_pll_config_t g_sysPll3Config = {
74     .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
75     .refDiv1 = 1U,                  /*!< PLL1 input = 25 / 1 = 25MHZ */
76     .loopDivider1 = 32U,            /*!< PLL1 output  = 25 * 32 * 2 = 1600MHZ */
77     .refDiv2 = 16U,                 /*!< PLL2 input  = 1600 / 16 = 100MHZ */
78     .loopDivider2 = 10U,            /*!< PLL2 output  = 10 * 100 * 2 = 2000MHZ */
79     .outDiv = 1U,                   /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
80 };
81 
82 /*******************************************************************************
83  * Variables
84  ******************************************************************************/
85 
86 /*******************************************************************************
87  * Code
88  ******************************************************************************/
BOARD_BootClockRUN(void)89 void BOARD_BootClockRUN(void)
90 {
91     /* OSC configuration */
92     CLOCK_InitOSC25M(&g_osc25MConfig);
93     CLOCK_InitOSC27M(&g_osc27MConfig);
94 
95     /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
96      * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
97      * would also do configuration on the SYSTEM PLL1 to 800Mhz and SYSTEM PLL2 to 1000Mhz by U-Boot.*/
98 
99     /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */
100     CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m);
101     CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m);
102     /* switch AXI M4 root to 25M first in order to configure the SYSTEM PLL2. */
103     CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m);
104     CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m);
105 
106     CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
107     CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
108     CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */
109 
110     CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */
111     CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */
112     CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */
113 
114     CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */
115     CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1);   /* change back to SYSTEM PLL1*/
116 
117     CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
118     CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
119 
120     CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U);
121     CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */
122 
123     CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
124     CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);                     /* Set root clock to 80MHZ/ 1= 80MHZ */
125 
126     CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
127 
128     /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
129      * enters the low power status.*/
130     // CLOCK_EnableClock(kCLOCK_Sim_m);
131     // CLOCK_EnableClock(kCLOCK_Sim_main);
132     // CLOCK_EnableClock(kCLOCK_Sim_s);
133     // CLOCK_EnableClock(kCLOCK_Sim_wakeup);
134     // CLOCK_EnableClock(kCLOCK_Debug);
135     // CLOCK_EnableClock(kCLOCK_Dram);
136     // CLOCK_EnableClock(kCLOCK_Sec_Debug);
137 
138     /* Disable unused PLL */
139     CLOCK_DeinitSysPll3();
140     CLOCK_DeinitVideoPll1();
141     CLOCK_DeinitAudioPll1();
142     CLOCK_DeinitAudioPll2();
143     /* Update core clock */
144     SystemCoreClockUpdate();
145 }
146