1 /*
2 * Copyright 2019-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_IOMUXC_H_
8 #define _FSL_IOMUXC_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup iomuxc_driver
14 * @{
15 */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
25 #endif
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief IOMUXC driver version 2.0.1. */
30 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
31 /*@}*/
32
33 /*!
34 * @name Pin function ID
35 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
36 *
37 * @{
38 */
39 #define IOMUXC_BOOT_MODE0_SRC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
40 #define IOMUXC_BOOT_MODE1_SRC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
41 #define IOMUXC_BOOT_MODE2_SRC_BOOT_MODE2 0x30330020, 0x0, 0x00000000, 0x0, 0x3033025C
42 #define IOMUXC_BOOT_MODE2_I2C1_SCL 0x30330020, 0x1, 0x3033055C, 0x3, 0x3033025C
43 #define IOMUXC_BOOT_MODE3_SRC_BOOT_MODE3 0x30330024, 0x0, 0x00000000, 0x0, 0x30330260
44 #define IOMUXC_BOOT_MODE3_I2C1_SDA 0x30330024, 0x1, 0x3033056C, 0x3, 0x30330260
45 #define IOMUXC_JTAG_MOD_JTAG_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
46 #define IOMUXC_JTAG_TDI_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
47 #define IOMUXC_JTAG_TMS_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
48 #define IOMUXC_JTAG_TCK_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
49 #define IOMUXC_JTAG_TDO_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
50 #define IOMUXC_RTC_XTALI_SNVS_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000
51 #define IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
52 #define IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
53 #define IOMUXC_ONOFF_SNVS_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
54 #define IOMUXC_POR_B_SNVS_POR_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330288
55 #define IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B 0x00000000, 0x0, 0x00000000, 0x0, 0x3033028C
56 #define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
57 #define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
58 #define IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
59 #define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
60 #define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
61 #define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
62 #define IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
63 #define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
64 #define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
65 #define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
66 #define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
67 #define IOMUXC_GPIO1_IO02_SJC_DE_B 0x30330030, 0x7, 0x00000000, 0x0, 0x30330298
68 #define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
69 #define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
70 #define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
71 #define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
72 #define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
73 #define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
74 #define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
75 #define IOMUXC_GPIO1_IO05_M7_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
76 #define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
77 #define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
78 #define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
79 #define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
80 #define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
81 #define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
82 #define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
83 #define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
84 #define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
85 #define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
86 #define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
87 #define IOMUXC_GPIO1_IO08_PWM1_OUT 0x30330048, 0x2, 0x00000000, 0x0, 0x303302B0
88 #define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
89 #define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
90 #define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
91 #define IOMUXC_GPIO1_IO09_PWM2_OUT 0x3033004C, 0x2, 0x00000000, 0x0, 0x303302B4
92 #define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
93 #define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
94 #define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
95 #define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
96 #define IOMUXC_GPIO1_IO10_PWM3_OUT 0x30330050, 0x2, 0x00000000, 0x0, 0x303302B8
97 #define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
98 #define IOMUXC_GPIO1_IO11_PWM2_OUT 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
99 #define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
100 #define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
101 #define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
102 #define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
103 #define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
104 #define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
105 #define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
106 #define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
107 #define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
108 #define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330598, 0x2, 0x303302C8
109 #define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
110 #define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
111 #define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
112 #define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x303305B8, 0x2, 0x303302CC
113 #define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
114 #define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
115 #define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
116 #define IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x30330068, 0x2, 0x00000000, 0x0, 0x303302D0
117 #define IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x30330068, 0x3, 0x30330540, 0x1, 0x303302D0
118 #define IOMUXC_ENET_MDC_SPDIF1_OUT 0x30330068, 0x4, 0x00000000, 0x0, 0x303302D0
119 #define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
120 #define IOMUXC_ENET_MDC_USDHC3_STROBE 0x30330068, 0x6, 0x3033059C, 0x1, 0x303302D0
121 #define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
122 #define IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x3033006C, 0x2, 0x00000000, 0x0, 0x303302D4
123 #define IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x3033006C, 0x3, 0x3033053C, 0x1, 0x303302D4
124 #define IOMUXC_ENET_MDIO_SPDIF1_IN 0x3033006C, 0x4, 0x303305CC, 0x1, 0x303302D4
125 #define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
126 #define IOMUXC_ENET_MDIO_USDHC3_DATA5 0x3033006C, 0x6, 0x30330550, 0x1, 0x303302D4
127 #define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
128 #define IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x30330070, 0x2, 0x00000000, 0x0, 0x303302D8
129 #define IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x30330070, 0x3, 0x30330538, 0x1, 0x303302D8
130 #define IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x30330070, 0x4, 0x30330568, 0x1, 0x303302D8
131 #define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
132 #define IOMUXC_ENET_TD3_USDHC3_DATA6 0x30330070, 0x6, 0x30330584, 0x1, 0x303302D8
133 #define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
134 #define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x303305A4, 0x0, 0x303302DC
135 #define IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x30330074, 0x2, 0x00000000, 0x0, 0x303302DC
136 #define IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x30330074, 0x3, 0x30330540, 0x2, 0x303302DC
137 #define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
138 #define IOMUXC_ENET_TD2_USDHC3_DATA7 0x30330074, 0x6, 0x3033054C, 0x1, 0x303302DC
139 #define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
140 #define IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x30330078, 0x2, 0x00000000, 0x0, 0x303302E0
141 #define IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x30330078, 0x3, 0x3033053C, 0x2, 0x303302E0
142 #define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
143 #define IOMUXC_ENET_TD1_USDHC3_CD_B 0x30330078, 0x6, 0x30330598, 0x3, 0x303302E0
144 #define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
145 #define IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x3033007C, 0x2, 0x00000000, 0x0, 0x303302E4
146 #define IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x3033007C, 0x3, 0x30330538, 0x2, 0x303302E4
147 #define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
148 #define IOMUXC_ENET_TD0_USDHC3_WP 0x3033007C, 0x6, 0x303305B8, 0x3, 0x303302E4
149 #define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
150 #define IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x30330080, 0x2, 0x00000000, 0x0, 0x303302E8
151 #define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
152 #define IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x30330080, 0x6, 0x303305B4, 0x1, 0x303302E8
153 #define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
154 #define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
155 #define IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x30330084, 0x2, 0x00000000, 0x0, 0x303302EC
156 #define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
157 #define IOMUXC_ENET_TXC_USDHC3_DATA1 0x30330084, 0x6, 0x303305B0, 0x1, 0x303302EC
158 #define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x30330574, 0x0, 0x303302F0
159 #define IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x30330088, 0x2, 0x00000000, 0x0, 0x303302F0
160 #define IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x30330088, 0x3, 0x30330540, 0x3, 0x303302F0
161 #define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
162 #define IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x30330088, 0x6, 0x303305E4, 0x1, 0x303302F0
163 #define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
164 #define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x303305C8, 0x0, 0x303302F4
165 #define IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x3033008C, 0x2, 0x00000000, 0x0, 0x303302F4
166 #define IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x3033008C, 0x3, 0x3033053C, 0x3, 0x303302F4
167 #define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
168 #define IOMUXC_ENET_RXC_USDHC3_DATA3 0x3033008C, 0x6, 0x303305E0, 0x1, 0x303302F4
169 #define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x3033057C, 0x0, 0x303302F8
170 #define IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x30330090, 0x2, 0x00000000, 0x0, 0x303302F8
171 #define IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x30330090, 0x3, 0x30330538, 0x3, 0x303302F8
172 #define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
173 #define IOMUXC_ENET_RD0_USDHC3_DATA4 0x30330090, 0x6, 0x30330558, 0x1, 0x303302F8
174 #define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x30330554, 0x0, 0x303302FC
175 #define IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x30330094, 0x2, 0x00000000, 0x0, 0x303302FC
176 #define IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x30330094, 0x3, 0x30330534, 0x1, 0x303302FC
177 #define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
178 #define IOMUXC_ENET_RD1_USDHC3_RESET_B 0x30330094, 0x6, 0x00000000, 0x0, 0x303302FC
179 #define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
180 #define IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x30330098, 0x2, 0x00000000, 0x0, 0x30330300
181 #define IOMUXC_ENET_RD2_PDM_CLK 0x30330098, 0x3, 0x00000000, 0x0, 0x30330300
182 #define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
183 #define IOMUXC_ENET_RD2_USDHC3_CLK 0x30330098, 0x6, 0x303305A0, 0x1, 0x30330300
184 #define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
185 #define IOMUXC_ENET_RD3_SAI7_MCLK 0x3033009C, 0x2, 0x00000000, 0x0, 0x30330304
186 #define IOMUXC_ENET_RD3_SPDIF1_IN 0x3033009C, 0x3, 0x303305CC, 0x5, 0x30330304
187 #define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
188 #define IOMUXC_ENET_RD3_USDHC3_CMD 0x3033009C, 0x6, 0x303305DC, 0x1, 0x30330304
189 #define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
190 #define IOMUXC_SD1_CLK_ENET1_MDC 0x303300A0, 0x1, 0x00000000, 0x0, 0x30330308
191 #define IOMUXC_SD1_CLK_UART1_TX 0x303300A0, 0x4, 0x00000000, 0x0, 0x30330308
192 #define IOMUXC_SD1_CLK_UART1_RX 0x303300A0, 0x4, 0x303304F4, 0x4, 0x30330308
193 #define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
194 #define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
195 #define IOMUXC_SD1_CMD_ENET1_MDIO 0x303300A4, 0x1, 0x303304C0, 0x3, 0x3033030C
196 #define IOMUXC_SD1_CMD_UART1_RX 0x303300A4, 0x4, 0x303304F4, 0x5, 0x3033030C
197 #define IOMUXC_SD1_CMD_UART1_TX 0x303300A4, 0x4, 0x00000000, 0x0, 0x3033030C
198 #define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
199 #define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
200 #define IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x303300A8, 0x1, 0x00000000, 0x0, 0x30330310
201 #define IOMUXC_SD1_DATA0_UART1_RTS_B 0x303300A8, 0x4, 0x303304F0, 0x4, 0x30330310
202 #define IOMUXC_SD1_DATA0_UART1_CTS_B 0x303300A8, 0x4, 0x00000000, 0x0, 0x30330310
203 #define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
204 #define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
205 #define IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x303300AC, 0x1, 0x00000000, 0x0, 0x30330314
206 #define IOMUXC_SD1_DATA1_UART1_CTS_B 0x303300AC, 0x4, 0x00000000, 0x0, 0x30330314
207 #define IOMUXC_SD1_DATA1_UART1_RTS_B 0x303300AC, 0x4, 0x303304F0, 0x5, 0x30330314
208 #define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
209 #define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
210 #define IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x303300B0, 0x1, 0x3033057C, 0x1, 0x30330318
211 #define IOMUXC_SD1_DATA2_UART2_TX 0x303300B0, 0x4, 0x00000000, 0x0, 0x30330318
212 #define IOMUXC_SD1_DATA2_UART2_RX 0x303300B0, 0x4, 0x303304FC, 0x4, 0x30330318
213 #define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
214 #define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
215 #define IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x303300B4, 0x1, 0x30330554, 0x1, 0x3033031C
216 #define IOMUXC_SD1_DATA3_UART2_RX 0x303300B4, 0x4, 0x303304FC, 0x5, 0x3033031C
217 #define IOMUXC_SD1_DATA3_UART2_TX 0x303300B4, 0x4, 0x00000000, 0x0, 0x3033031C
218 #define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
219 #define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
220 #define IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x303300B8, 0x1, 0x00000000, 0x0, 0x30330320
221 #define IOMUXC_SD1_DATA4_I2C1_SCL 0x303300B8, 0x3, 0x3033055C, 0x1, 0x30330320
222 #define IOMUXC_SD1_DATA4_UART2_RTS_B 0x303300B8, 0x4, 0x303304F8, 0x4, 0x30330320
223 #define IOMUXC_SD1_DATA4_UART2_CTS_B 0x303300B8, 0x4, 0x00000000, 0x0, 0x30330320
224 #define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
225 #define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
226 #define IOMUXC_SD1_DATA5_ENET1_TX_ER 0x303300BC, 0x1, 0x00000000, 0x0, 0x30330324
227 #define IOMUXC_SD1_DATA5_I2C1_SDA 0x303300BC, 0x3, 0x3033056C, 0x1, 0x30330324
228 #define IOMUXC_SD1_DATA5_UART2_CTS_B 0x303300BC, 0x4, 0x00000000, 0x0, 0x30330324
229 #define IOMUXC_SD1_DATA5_UART2_RTS_B 0x303300BC, 0x4, 0x303304F8, 0x5, 0x30330324
230 #define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
231 #define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
232 #define IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x303300C0, 0x1, 0x30330574, 0x1, 0x30330328
233 #define IOMUXC_SD1_DATA6_I2C2_SCL 0x303300C0, 0x3, 0x303305D0, 0x1, 0x30330328
234 #define IOMUXC_SD1_DATA6_UART3_TX 0x303300C0, 0x4, 0x00000000, 0x0, 0x30330328
235 #define IOMUXC_SD1_DATA6_UART3_RX 0x303300C0, 0x4, 0x30330504, 0x4, 0x30330328
236 #define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
237 #define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
238 #define IOMUXC_SD1_DATA7_ENET1_RX_ER 0x303300C4, 0x1, 0x303305C8, 0x1, 0x3033032C
239 #define IOMUXC_SD1_DATA7_I2C2_SDA 0x303300C4, 0x3, 0x30330560, 0x1, 0x3033032C
240 #define IOMUXC_SD1_DATA7_UART3_RX 0x303300C4, 0x4, 0x30330504, 0x5, 0x3033032C
241 #define IOMUXC_SD1_DATA7_UART3_TX 0x303300C4, 0x4, 0x00000000, 0x0, 0x3033032C
242 #define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
243 #define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
244 #define IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x303300C8, 0x1, 0x303305A4, 0x1, 0x30330330
245 #define IOMUXC_SD1_RESET_B_I2C3_SCL 0x303300C8, 0x3, 0x30330588, 0x1, 0x30330330
246 #define IOMUXC_SD1_RESET_B_UART3_RTS_B 0x303300C8, 0x4, 0x30330500, 0x2, 0x30330330
247 #define IOMUXC_SD1_RESET_B_UART3_CTS_B 0x303300C8, 0x4, 0x00000000, 0x0, 0x30330330
248 #define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
249 #define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
250 #define IOMUXC_SD1_STROBE_I2C3_SDA 0x303300CC, 0x3, 0x303305BC, 0x1, 0x30330334
251 #define IOMUXC_SD1_STROBE_UART3_CTS_B 0x303300CC, 0x4, 0x00000000, 0x0, 0x30330334
252 #define IOMUXC_SD1_STROBE_UART3_RTS_B 0x303300CC, 0x4, 0x30330500, 0x3, 0x30330334
253 #define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
254 #define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
255 #define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
256 #define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
257 #define IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x303300D4, 0x1, 0x303304E4, 0x1, 0x3033033C
258 #define IOMUXC_SD2_CLK_ECSPI2_SCLK 0x303300D4, 0x2, 0x30330580, 0x1, 0x3033033C
259 #define IOMUXC_SD2_CLK_UART4_RX 0x303300D4, 0x3, 0x3033050C, 0x4, 0x3033033C
260 #define IOMUXC_SD2_CLK_UART4_TX 0x303300D4, 0x3, 0x00000000, 0x0, 0x3033033C
261 #define IOMUXC_SD2_CLK_SAI5_MCLK 0x303300D4, 0x4, 0x30330594, 0x1, 0x3033033C
262 #define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
263 #define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
264 #define IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x303300D8, 0x1, 0x303304D0, 0x1, 0x30330340
265 #define IOMUXC_SD2_CMD_ECSPI2_MOSI 0x303300D8, 0x2, 0x30330590, 0x1, 0x30330340
266 #define IOMUXC_SD2_CMD_UART4_TX 0x303300D8, 0x3, 0x00000000, 0x0, 0x30330340
267 #define IOMUXC_SD2_CMD_UART4_RX 0x303300D8, 0x3, 0x3033050C, 0x5, 0x30330340
268 #define IOMUXC_SD2_CMD_PDM_CLK 0x303300D8, 0x4, 0x00000000, 0x0, 0x30330340
269 #define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
270 #define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
271 #define IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x303300DC, 0x1, 0x303304D4, 0x1, 0x30330344
272 #define IOMUXC_SD2_DATA0_I2C4_SDA 0x303300DC, 0x2, 0x3033058C, 0x1, 0x30330344
273 #define IOMUXC_SD2_DATA0_UART2_RX 0x303300DC, 0x3, 0x303304FC, 0x6, 0x30330344
274 #define IOMUXC_SD2_DATA0_UART2_TX 0x303300DC, 0x3, 0x00000000, 0x0, 0x30330344
275 #define IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x303300DC, 0x4, 0x30330534, 0x2, 0x30330344
276 #define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
277 #define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
278 #define IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x303300E0, 0x1, 0x303304EC, 0x1, 0x30330348
279 #define IOMUXC_SD2_DATA1_I2C4_SCL 0x303300E0, 0x2, 0x303305D4, 0x1, 0x30330348
280 #define IOMUXC_SD2_DATA1_UART2_TX 0x303300E0, 0x3, 0x00000000, 0x0, 0x30330348
281 #define IOMUXC_SD2_DATA1_UART2_RX 0x303300E0, 0x3, 0x303304FC, 0x7, 0x30330348
282 #define IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x303300E0, 0x4, 0x30330538, 0x4, 0x30330348
283 #define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
284 #define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
285 #define IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x303300E4, 0x1, 0x303304E8, 0x1, 0x3033034C
286 #define IOMUXC_SD2_DATA2_ECSPI2_SS0 0x303300E4, 0x2, 0x30330570, 0x2, 0x3033034C
287 #define IOMUXC_SD2_DATA2_SPDIF1_OUT 0x303300E4, 0x3, 0x00000000, 0x0, 0x3033034C
288 #define IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x303300E4, 0x4, 0x3033053C, 0x4, 0x3033034C
289 #define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
290 #define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
291 #define IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x303300E8, 0x1, 0x00000000, 0x0, 0x30330350
292 #define IOMUXC_SD2_DATA3_ECSPI2_MISO 0x303300E8, 0x2, 0x30330578, 0x1, 0x30330350
293 #define IOMUXC_SD2_DATA3_SPDIF1_IN 0x303300E8, 0x3, 0x303305CC, 0x2, 0x30330350
294 #define IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x303300E8, 0x4, 0x30330540, 0x4, 0x30330350
295 #define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
296 #define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
297 #define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
298 #define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
299 #define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
300 #define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
301 #define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
302 #define IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x303300F0, 0x6, 0x00000000, 0x0, 0x30330358
303 #define IOMUXC_NAND_ALE_NAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
304 #define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
305 #define IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x303300F4, 0x3, 0x30330534, 0x3, 0x3033035C
306 #define IOMUXC_NAND_ALE_UART3_RX 0x303300F4, 0x4, 0x30330504, 0x6, 0x3033035C
307 #define IOMUXC_NAND_ALE_UART3_TX 0x303300F4, 0x4, 0x00000000, 0x0, 0x3033035C
308 #define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
309 #define IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x303300F4, 0x6, 0x00000000, 0x0, 0x3033035C
310 #define IOMUXC_NAND_CE0_B_NAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
311 #define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
312 #define IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x303300F8, 0x3, 0x30330538, 0x5, 0x30330360
313 #define IOMUXC_NAND_CE0_B_UART3_TX 0x303300F8, 0x4, 0x00000000, 0x0, 0x30330360
314 #define IOMUXC_NAND_CE0_B_UART3_RX 0x303300F8, 0x4, 0x30330504, 0x7, 0x30330360
315 #define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
316 #define IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x303300F8, 0x6, 0x00000000, 0x0, 0x30330360
317 #define IOMUXC_NAND_CE1_B_NAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
318 #define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
319 #define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x3033059C, 0x0, 0x30330364
320 #define IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x303300FC, 0x3, 0x30330534, 0x4, 0x30330364
321 #define IOMUXC_NAND_CE1_B_I2C4_SCL 0x303300FC, 0x4, 0x303305D4, 0x2, 0x30330364
322 #define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
323 #define IOMUXC_NAND_CE1_B_CORESIGHT_TRACE00 0x303300FC, 0x6, 0x00000000, 0x0, 0x30330364
324 #define IOMUXC_NAND_CE2_B_NAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
325 #define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
326 #define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x30330550, 0x0, 0x30330368
327 #define IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x30330100, 0x3, 0x30330538, 0x6, 0x30330368
328 #define IOMUXC_NAND_CE2_B_I2C4_SDA 0x30330100, 0x4, 0x3033058C, 0x2, 0x30330368
329 #define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
330 #define IOMUXC_NAND_CE2_B_CORESIGHT_TRACE01 0x30330100, 0x6, 0x00000000, 0x0, 0x30330368
331 #define IOMUXC_NAND_CE3_B_NAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
332 #define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
333 #define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x30330584, 0x0, 0x3033036C
334 #define IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x30330104, 0x3, 0x3033053C, 0x5, 0x3033036C
335 #define IOMUXC_NAND_CE3_B_I2C3_SDA 0x30330104, 0x4, 0x303305BC, 0x2, 0x3033036C
336 #define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
337 #define IOMUXC_NAND_CE3_B_CORESIGHT_TRACE02 0x30330104, 0x6, 0x00000000, 0x0, 0x3033036C
338 #define IOMUXC_NAND_CLE_NAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
339 #define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
340 #define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x3033054C, 0x0, 0x30330370
341 #define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
342 #define IOMUXC_NAND_CLE_CORESIGHT_TRACE03 0x30330108, 0x6, 0x00000000, 0x0, 0x30330370
343 #define IOMUXC_NAND_DATA00_NAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
344 #define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
345 #define IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x3033010C, 0x3, 0x3033053C, 0x6, 0x30330374
346 #define IOMUXC_NAND_DATA00_UART4_RX 0x3033010C, 0x4, 0x3033050C, 0x6, 0x30330374
347 #define IOMUXC_NAND_DATA00_UART4_TX 0x3033010C, 0x4, 0x00000000, 0x0, 0x30330374
348 #define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
349 #define IOMUXC_NAND_DATA00_CORESIGHT_TRACE04 0x3033010C, 0x6, 0x00000000, 0x0, 0x30330374
350 #define IOMUXC_NAND_DATA01_NAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
351 #define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
352 #define IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x30330110, 0x3, 0x30330540, 0x5, 0x30330378
353 #define IOMUXC_NAND_DATA01_UART4_TX 0x30330110, 0x4, 0x00000000, 0x0, 0x30330378
354 #define IOMUXC_NAND_DATA01_UART4_RX 0x30330110, 0x4, 0x3033050C, 0x7, 0x30330378
355 #define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
356 #define IOMUXC_NAND_DATA01_CORESIGHT_TRACE05 0x30330110, 0x6, 0x00000000, 0x0, 0x30330378
357 #define IOMUXC_NAND_DATA02_NAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
358 #define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
359 #define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330598, 0x0, 0x3033037C
360 #define IOMUXC_NAND_DATA02_I2C4_SDA 0x30330114, 0x4, 0x3033058C, 0x3, 0x3033037C
361 #define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
362 #define IOMUXC_NAND_DATA02_CORESIGHT_TRACE06 0x30330114, 0x6, 0x00000000, 0x0, 0x3033037C
363 #define IOMUXC_NAND_DATA03_NAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
364 #define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
365 #define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x303305B8, 0x0, 0x30330380
366 #define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
367 #define IOMUXC_NAND_DATA03_CORESIGHT_TRACE07 0x30330118, 0x6, 0x00000000, 0x0, 0x30330380
368 #define IOMUXC_NAND_DATA04_NAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
369 #define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
370 #define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x303305B4, 0x0, 0x30330384
371 #define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
372 #define IOMUXC_NAND_DATA04_CORESIGHT_TRACE08 0x3033011C, 0x6, 0x00000000, 0x0, 0x30330384
373 #define IOMUXC_NAND_DATA05_NAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
374 #define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
375 #define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x303305B0, 0x0, 0x30330388
376 #define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
377 #define IOMUXC_NAND_DATA05_CORESIGHT_TRACE09 0x30330120, 0x6, 0x00000000, 0x0, 0x30330388
378 #define IOMUXC_NAND_DATA06_NAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
379 #define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
380 #define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x303305E4, 0x0, 0x3033038C
381 #define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
382 #define IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x30330124, 0x6, 0x00000000, 0x0, 0x3033038C
383 #define IOMUXC_NAND_DATA07_NAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
384 #define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
385 #define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x303305E0, 0x0, 0x30330390
386 #define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
387 #define IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x30330128, 0x6, 0x00000000, 0x0, 0x30330390
388 #define IOMUXC_NAND_DQS_NAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
389 #define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
390 #define IOMUXC_NAND_DQS_PDM_CLK 0x3033012C, 0x3, 0x00000000, 0x0, 0x30330394
391 #define IOMUXC_NAND_DQS_I2C3_SCL 0x3033012C, 0x4, 0x30330588, 0x2, 0x30330394
392 #define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
393 #define IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x3033012C, 0x6, 0x00000000, 0x0, 0x30330394
394 #define IOMUXC_NAND_RE_B_NAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
395 #define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
396 #define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x30330558, 0x0, 0x30330398
397 #define IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x30330130, 0x3, 0x30330538, 0x7, 0x30330398
398 #define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
399 #define IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x30330130, 0x6, 0x00000000, 0x0, 0x30330398
400 #define IOMUXC_NAND_READY_B_NAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
401 #define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
402 #define IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x30330134, 0x3, 0x30330540, 0x6, 0x3033039C
403 #define IOMUXC_NAND_READY_B_I2C3_SCL 0x30330134, 0x4, 0x30330588, 0x3, 0x3033039C
404 #define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
405 #define IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x30330134, 0x6, 0x00000000, 0x0, 0x3033039C
406 #define IOMUXC_NAND_WE_B_NAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
407 #define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x303305A0, 0x0, 0x303303A0
408 #define IOMUXC_NAND_WE_B_I2C3_SDA 0x30330138, 0x4, 0x303305BC, 0x3, 0x303303A0
409 #define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
410 #define IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x30330138, 0x6, 0x00000000, 0x0, 0x303303A0
411 #define IOMUXC_NAND_WP_B_NAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
412 #define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x303305DC, 0x0, 0x303303A4
413 #define IOMUXC_NAND_WP_B_I2C4_SDA 0x3033013C, 0x4, 0x3033058C, 0x4, 0x303303A4
414 #define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
415 #define IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x3033013C, 0x6, 0x00000000, 0x0, 0x303303A4
416 #define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
417 #define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
418 #define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
419 #define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
420 #define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
421 #define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
422 #define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
423 #define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
424 #define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
425 #define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
426 #define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
427 #define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
428 #define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
429 #define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
430 #define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
431 #define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
432 #define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
433 #define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
434 #define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
435 #define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
436 #define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x30330594, 0x0, 0x303303C0
437 #define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
438 #define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
439 #define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
440 #define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
441 #define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x303305AC, 0x0, 0x30330418
442 #define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0x0, 0x30330418
443 #define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
444 #define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
445 #define IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x303301B0, 0x6, 0x3033053C, 0x7, 0x30330418
446 #define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
447 #define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
448 #define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
449 #define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0x0, 0x3033041C
450 #define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
451 #define IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x303301B4, 0x6, 0x30330538, 0x8, 0x3033041C
452 #define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
453 #define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
454 #define IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x303301B8, 0x3, 0x00000000, 0x0, 0x30330420
455 #define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
456 #define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0x0, 0x30330420
457 #define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
458 #define IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x303301B8, 0x6, 0x30330540, 0x7, 0x30330420
459 #define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
460 #define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
461 #define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
462 #define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0x0, 0x30330424
463 #define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
464 #define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
465 #define IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x303301BC, 0x6, 0x3033053C, 0x8, 0x30330424
466 #define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
467 #define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
468 #define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
469 #define IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x303301C0, 0x6, 0x30330538, 0x9, 0x30330428
470 #define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
471 #define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
472 #define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
473 #define IOMUXC_SAI2_TXD0_SRC_BOOT_MODE4 0x303301C4, 0x6, 0x00000000, 0x0, 0x3033042C
474 #define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
475 #define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x30330594, 0x2, 0x30330430
476 #define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
477 #define IOMUXC_SAI2_MCLK_SAI3_MCLK 0x303301C8, 0x6, 0x303305C0, 0x1, 0x30330430
478 #define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
479 #define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x303305F0, 0x0, 0x30330434
480 #define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
481 #define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
482 #define IOMUXC_SAI3_RXFS_SPDIF1_IN 0x303301CC, 0x4, 0x303305CC, 0x3, 0x30330434
483 #define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
484 #define IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x303301CC, 0x6, 0x30330534, 0x5, 0x30330434
485 #define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
486 #define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x303305E8, 0x0, 0x30330438
487 #define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
488 #define IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x303301D0, 0x3, 0x303305AC, 0x2, 0x30330438
489 #define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0x0, 0x30330438
490 #define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
491 #define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
492 #define IOMUXC_SAI3_RXC_PDM_CLK 0x303301D0, 0x6, 0x00000000, 0x0, 0x30330438
493 #define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
494 #define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
495 #define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
496 #define IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x303301D4, 0x3, 0x00000000, 0x0, 0x3033043C
497 #define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
498 #define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0x0, 0x3033043C
499 #define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
500 #define IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x303301D4, 0x6, 0x30330538, 0x10, 0x3033043C
501 #define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
502 #define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x303305EC, 0x0, 0x30330440
503 #define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x1, 0x30330440
504 #define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
505 #define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
506 #define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0x0, 0x30330440
507 #define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
508 #define IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x303301D8, 0x6, 0x30330540, 0x9, 0x30330440
509 #define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
510 #define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
511 #define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x1, 0x30330444
512 #define IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x303301DC, 0x3, 0x00000000, 0x0, 0x30330444
513 #define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0x0, 0x30330444
514 #define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
515 #define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
516 #define IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x303301DC, 0x6, 0x3033053C, 0x9, 0x30330444
517 #define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
518 #define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
519 #define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x1, 0x30330448
520 #define IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x303301E0, 0x4, 0x30330568, 0x2, 0x30330448
521 #define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
522 #define IOMUXC_SAI3_TXD_SRC_BOOT_MODE5 0x303301E0, 0x6, 0x00000000, 0x0, 0x30330448
523 #define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x303305C0, 0x0, 0x3033044C
524 #define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
525 #define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x30330594, 0x3, 0x3033044C
526 #define IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x303301E4, 0x4, 0x00000000, 0x0, 0x3033044C
527 #define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
528 #define IOMUXC_SAI3_MCLK_SPDIF1_IN 0x303301E4, 0x6, 0x303305CC, 0x4, 0x3033044C
529 #define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
530 #define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
531 #define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
532 #define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x303305CC, 0x0, 0x30330454
533 #define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
534 #define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
535 #define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x30330568, 0x0, 0x30330458
536 #define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
537 #define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
538 #define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x303305D8, 0x0, 0x3033045C
539 #define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
540 #define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0x0, 0x3033045C
541 #define IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x303301F4, 0x2, 0x3033055C, 0x2, 0x3033045C
542 #define IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x303301F4, 0x3, 0x303304E4, 0x3, 0x3033045C
543 #define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
544 #define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x303305A8, 0x0, 0x30330460
545 #define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0x0, 0x30330460
546 #define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
547 #define IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x303301F8, 0x2, 0x3033056C, 0x2, 0x30330460
548 #define IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x303301F8, 0x3, 0x303304D0, 0x3, 0x30330460
549 #define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
550 #define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x303305C4, 0x0, 0x30330464
551 #define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0x0, 0x30330464
552 #define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
553 #define IOMUXC_ECSPI1_MISO_I2C2_SCL 0x303301FC, 0x2, 0x303305D0, 0x2, 0x30330464
554 #define IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x303301FC, 0x3, 0x303304D4, 0x3, 0x30330464
555 #define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
556 #define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x30330564, 0x0, 0x30330468
557 #define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
558 #define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0x0, 0x30330468
559 #define IOMUXC_ECSPI1_SS0_I2C2_SDA 0x30330200, 0x2, 0x30330560, 0x2, 0x30330468
560 #define IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x30330200, 0x3, 0x303304D8, 0x2, 0x30330468
561 #define IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x30330200, 0x4, 0x303304EC, 0x3, 0x30330468
562 #define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
563 #define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x30330580, 0x0, 0x3033046C
564 #define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
565 #define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0x0, 0x3033046C
566 #define IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x30330204, 0x2, 0x30330588, 0x4, 0x3033046C
567 #define IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x30330204, 0x3, 0x303304DC, 0x2, 0x3033046C
568 #define IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x30330204, 0x4, 0x303304E8, 0x3, 0x3033046C
569 #define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
570 #define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x30330590, 0x0, 0x30330470
571 #define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0x0, 0x30330470
572 #define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
573 #define IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x30330208, 0x2, 0x303305BC, 0x4, 0x30330470
574 #define IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x30330208, 0x3, 0x303304E0, 0x2, 0x30330470
575 #define IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x30330208, 0x4, 0x00000000, 0x0, 0x30330470
576 #define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
577 #define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x30330578, 0x0, 0x30330474
578 #define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0x0, 0x30330474
579 #define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
580 #define IOMUXC_ECSPI2_MISO_I2C4_SCL 0x3033020C, 0x2, 0x303305D4, 0x3, 0x30330474
581 #define IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x3033020C, 0x3, 0x30330594, 0x4, 0x30330474
582 #define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
583 #define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x30330570, 0x0, 0x30330478
584 #define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
585 #define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0x0, 0x30330478
586 #define IOMUXC_ECSPI2_SS0_I2C4_SDA 0x30330210, 0x2, 0x3033058C, 0x5, 0x30330478
587 #define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
588 #define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x3033055C, 0x0, 0x3033047C
589 #define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
590 #define IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x30330214, 0x3, 0x303305D8, 0x1, 0x3033047C
591 #define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
592 #define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x3033056C, 0x0, 0x30330480
593 #define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
594 #define IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x30330218, 0x3, 0x303305A8, 0x1, 0x30330480
595 #define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
596 #define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x303305D0, 0x0, 0x30330484
597 #define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
598 #define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330598, 0x1, 0x30330484
599 #define IOMUXC_I2C2_SCL_ECSPI1_MISO 0x3033021C, 0x3, 0x303305C4, 0x1, 0x30330484
600 #define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
601 #define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x30330560, 0x0, 0x30330488
602 #define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
603 #define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x303305B8, 0x1, 0x30330488
604 #define IOMUXC_I2C2_SDA_ECSPI1_SS0 0x30330220, 0x3, 0x30330564, 0x1, 0x30330488
605 #define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
606 #define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x30330588, 0x0, 0x3033048C
607 #define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
608 #define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
609 #define IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x30330224, 0x3, 0x30330580, 0x2, 0x3033048C
610 #define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
611 #define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x303305BC, 0x0, 0x30330490
612 #define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
613 #define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
614 #define IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x30330228, 0x3, 0x30330590, 0x2, 0x30330490
615 #define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
616 #define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x303305D4, 0x0, 0x30330494
617 #define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
618 #define IOMUXC_I2C4_SCL_ECSPI2_MISO 0x3033022C, 0x3, 0x30330578, 0x2, 0x30330494
619 #define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
620 #define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x3033058C, 0x0, 0x30330498
621 #define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
622 #define IOMUXC_I2C4_SDA_ECSPI2_SS0 0x30330230, 0x3, 0x30330570, 0x1, 0x30330498
623 #define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
624 #define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
625 #define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0x0, 0x3033049C
626 #define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
627 #define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
628 #define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0x0, 0x303304A0
629 #define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
630 #define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
631 #define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
632 #define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
633 #define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0x0, 0x303304A4
634 #define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
635 #define IOMUXC_UART2_RXD_GPT1_COMPARE3 0x3033023C, 0x3, 0x00000000, 0x0, 0x303304A4
636 #define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
637 #define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0x0, 0x303304A8
638 #define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
639 #define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
640 #define IOMUXC_UART2_TXD_GPT1_COMPARE2 0x30330240, 0x3, 0x00000000, 0x0, 0x303304A8
641 #define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
642 #define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
643 #define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0x0, 0x303304AC
644 #define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0x0, 0x303304AC
645 #define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
646 #define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
647 #define IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x30330244, 0x3, 0x303305EC, 0x1, 0x303304AC
648 #define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
649 #define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0x0, 0x303304B0
650 #define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
651 #define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
652 #define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0x0, 0x303304B0
653 #define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
654 #define IOMUXC_UART3_TXD_GPT1_CLK 0x30330248, 0x3, 0x303305E8, 0x1, 0x303304B0
655 #define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
656 #define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
657 #define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0x0, 0x303304B4
658 #define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0x0, 0x303304B4
659 #define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
660 #define IOMUXC_UART4_RXD_GPT1_COMPARE1 0x3033024C, 0x3, 0x00000000, 0x0, 0x303304B4
661 #define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
662 #define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0x0, 0x303304B8
663 #define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
664 #define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
665 #define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0x0, 0x303304B8
666 #define IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x30330250, 0x3, 0x303305F0, 0x1, 0x303304B8
667 #define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
668
669 /*@}*/
670
671 #if defined(__cplusplus)
672 extern "C" {
673 #endif /*__cplusplus */
674
675 /*! @name Configuration */
676 /*@{*/
677
678 /*!
679 * @brief Sets the IOMUXC pin mux mode.
680 * @note The first five parameters can be filled with the pin function ID macros.
681 *
682 * This is an example to set the I2C4_SDA as the pwm1_OUT:
683 * @code
684 * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
685 * @endcode
686 *
687 *
688 * @param muxRegister The pin mux register_
689 * @param muxMode The pin mux mode_
690 * @param inputRegister The select input register_
691 * @param inputDaisy The input daisy_
692 * @param configRegister The config register_
693 * @param inputOnfield The pad->module input inversion_
694 */
IOMUXC_SetPinMux(uintptr_t muxRegister,uint32_t muxMode,uintptr_t inputRegister,uint32_t inputDaisy,uintptr_t configRegister,uint32_t inputOnfield)695 static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
696 uint32_t muxMode,
697 uintptr_t inputRegister,
698 uint32_t inputDaisy,
699 uintptr_t configRegister,
700 uint32_t inputOnfield)
701 {
702 *((volatile uint32_t *)muxRegister) =
703 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
704
705 if (inputRegister)
706 {
707 *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
708 }
709 }
710 /*!
711 * @brief Sets the IOMUXC pin configuration.
712 * @note The previous five parameters can be filled with the pin function ID macros.
713 *
714 * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
715 * @code
716 * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
717 * @endcode
718 *
719 * @param muxRegister The pin mux register_
720 * @param muxMode The pin mux mode_
721 * @param inputRegister The select input register_
722 * @param inputDaisy The input daisy_
723 * @param configRegister The config register_
724 * @param configValue The pin config value_
725 */
IOMUXC_SetPinConfig(uintptr_t muxRegister,uint32_t muxMode,uintptr_t inputRegister,uint32_t inputDaisy,uintptr_t configRegister,uint32_t configValue)726 static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
727 uint32_t muxMode,
728 uintptr_t inputRegister,
729 uint32_t inputDaisy,
730 uintptr_t configRegister,
731 uint32_t configValue)
732 {
733 if (configRegister)
734 {
735 *((volatile uint32_t *)configRegister) = configValue;
736 }
737 }
738 /*@}*/
739
740 #if defined(__cplusplus)
741 }
742 #endif /*__cplusplus */
743
744 /*! @}*/
745
746 #endif /* _FSL_IOMUXC_H_ */
747
