1 /*
2  * Copyright 2018 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "fsl_common.h"
9 #include "clock_config.h"
10 
11 /*******************************************************************************
12  * Definitions
13  ******************************************************************************/
14 /* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
15 /* AUDIO PLL1 configuration */
16 const ccm_analog_frac_pll_config_t g_audioPll1Config = {
17     .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
18     .mainDiv = 655U,
19     .dsm = 23593U,
20     .preDiv = 5U,
21     .postDiv = 2U, /*!< AUDIO PLL1 frequency  = 786432000HZ */
22 };
23 
24 /* AUDIO PLL2 configuration */
25 const ccm_analog_frac_pll_config_t g_audioPll2Config = {
26     .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
27     .mainDiv = 301U,
28     .dsm = 3670U,
29     .preDiv = 5U,
30     .postDiv = 1U, /*!< AUDIO PLL2 frequency  = 722534399HZ */
31 };
32 
33 /* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
34 /* SYSTEM PLL1 configuration */
35 const ccm_analog_integer_pll_config_t g_sysPll1Config = {
36     .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
37     .mainDiv = 400U,
38     .preDiv = 3U,
39     .postDiv = 2U, /*!< SYSTEM PLL1 frequency  = 800MHZ */
40 };
41 
42 /* SYSTEM PLL2 configuration */
43 const ccm_analog_integer_pll_config_t g_sysPll2Config = {
44     .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
45     .mainDiv = 250U,
46     .preDiv = 3U,
47     .postDiv = 1U, /*!< SYSTEM PLL2 frequency  = 1000MHZ */
48 };
49 
50 /* SYSTEM PLL3 configuration */
51 const ccm_analog_integer_pll_config_t g_sysPll3Config = {
52     .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
53     .mainDiv = 250,
54     .preDiv = 2U,
55     .postDiv = 2U, /*!< SYSTEM PLL3 frequency  = 750MHZ */
56 };
57 
58 /*******************************************************************************
59  * Variables
60  ******************************************************************************/
61 
62 /*******************************************************************************
63  * Code
64  ******************************************************************************/
BOARD_BootClockRUN(void)65 void BOARD_BootClockRUN(void)
66 {
67     /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
68      * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
69      * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
70      * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
71      * the SOC hang.
72      */
73 
74     /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
75     CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
76     //    CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
77     /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
78     //    CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
79     CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
80 
81     //    CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
82     //    CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
83     //    CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
84 
85     CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 786432000HZ */
86     CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 722534399HZ */
87 
88     CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
89     CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
90 
91     //    CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
92 
93     CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
94     CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
95 
96     CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U);                    /* Set root clock to 800MHZ/ 2= 400MHZ */
97     CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
98 
99     //    CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
100     //    CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
101 
102     CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
103     CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);                     /* Set root clock to 80MHZ/ 1= 80MHZ */
104 
105     CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
106     /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
107      * enters the low power status.*/
108     CLOCK_EnableClock(kCLOCK_Sim_display);
109     CLOCK_EnableClock(kCLOCK_Sim_m);
110     CLOCK_EnableClock(kCLOCK_Sim_main);
111     CLOCK_EnableClock(kCLOCK_Sim_s);
112     CLOCK_EnableClock(kCLOCK_Sim_wakeup);
113     CLOCK_EnableClock(kCLOCK_Debug);
114     CLOCK_EnableClock(kCLOCK_Dram);
115     CLOCK_EnableClock(kCLOCK_Sec_Debug);
116 
117     /* Update core clock */
118     SystemCoreClockUpdate();
119 }
120