1 /*
2  * Copyright 2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef _FSL_SOC_MIPI_DSI_H_
8 #define _FSL_SOC_MIPI_DSI_H_
9 
10 #include "fsl_common.h"
11 
12 /*!
13  * @addtogroup soc_mipi_dsi
14  * @{
15  */
16 
17 /*******************************************************************************
18  * Definitions
19  ******************************************************************************/
20 
21 /* Component ID definition, used by tools. */
22 #ifndef FSL_COMPONENT_ID
23 #define FSL_COMPONENT_ID "platform.drivers.soc_mipi_dsi"
24 #endif
25 
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief Driver version 2.0.0. */
29 #define FSL_SOC_MIPI_DSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
30 /*@}*/
31 
32 #if (defined(FSL_FEATURE_LDB_COMBO_PHY) && FSL_FEATURE_LDB_COMBO_PHY)
33 typedef MIPI_DSI_LVDS_COMBO_CSR_Type MIPI_DSI_CSR_Type;
34 #define MIPI_DSI_CSR_ULPS_CTRL(csr)      ((csr)->ULPS_CTRL)
35 #define MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_MASK
36 #define MIPI_DSI_CSR_PXL2DPI(csr)        ((csr)->PXL2DPI_CTRL)
37 #else
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr)      ((csr)->TX_ULPS_ENABLE)
39 #define MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE_MASK
40 #define MIPI_DSI_CSR_PXL2DPI(csr)        ((csr)->PXL2DPI_CONFIG)
41 #endif
42 
43 /*******************************************************************************
44  * API
45  ******************************************************************************/
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 
51 /*!
52  * @brief Get MIPI_DSI_CSR to control related MIPI DSI.
53  *
54  * @param base MIPI DSI host peripheral base address.
55  * @return The MIPI_DSI_CSR to control MIPI DSI.
56  */
SOC_MIPI_DSI_GetCsr(MIPI_DSI_HOST_Type * base)57 static inline MIPI_DSI_CSR_Type* SOC_MIPI_DSI_GetCsr(MIPI_DSI_HOST_Type *base)
58 {
59     return (MIPI_DSI_CSR_Type *)((uint32_t)(base) - (uint32_t)FSL_FEATURE_DSI_CSR_OFFSET);
60 }
61 
62 /*!
63  * @brief Enable or disable the TX ULPS.
64  *
65  * @param base MIPI DSI host peripheral base address.
66  * @param enable Use true to enable, false to disable.
67  */
SOC_MIPI_DSI_EnableUlps(MIPI_DSI_HOST_Type * base,bool enable)68 static inline void SOC_MIPI_DSI_EnableUlps(MIPI_DSI_HOST_Type *base, bool enable)
69 {
70     MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base);
71 
72     if (enable)
73     {
74         MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK;
75     }
76     else
77     {
78         MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U;
79     }
80 }
81 
82 /*!
83  * @brief Set pixel-link to DPI format mapping.
84  *
85  * @param base MIPI DSI host peripheral base address.
86  * @param pxl2dpi The map relationship.
87  */
SOC_MIPI_DSI_SetPixelDpiMap(MIPI_DSI_HOST_Type * base,uint32_t pxl2dpi)88 static inline void SOC_MIPI_DSI_SetPixelDpiMap(MIPI_DSI_HOST_Type *base, uint32_t pxl2dpi)
89 {
90     MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base);
91 
92     MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi;
93 }
94 
95 #ifdef __cplusplus
96 }
97 #endif
98 
99 /*!
100  * @}
101  */
102 
103 #endif /* _FSL_SOC_MIPI_DSI_H_ */
104