1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC845_FEATURES_H_ 33 #define _LPC845_FEATURES_H_ 34 35 /* SOC module features */ 36 37 #if defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48) 38 /* @brief ACOMP availability on the SoC. */ 39 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 40 /* @brief ADC availability on the SoC. */ 41 #define FSL_FEATURE_SOC_ADC_COUNT (1) 42 /* @brief CAPT availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CAPT_COUNT (1) 44 /* @brief CRC availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CRC_COUNT (1) 46 /* @brief CTIMER availability on the SoC. */ 47 #define FSL_FEATURE_SOC_CTIMER_COUNT (1) 48 /* @brief DAC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DAC_COUNT (2) 50 /* @brief DMA availability on the SoC. */ 51 #define FSL_FEATURE_SOC_DMA_COUNT (1) 52 /* @brief GPIO availability on the SoC. */ 53 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 54 /* @brief I2C availability on the SoC. */ 55 #define FSL_FEATURE_SOC_I2C_COUNT (4) 56 /* @brief INPUTMUX availability on the SoC. */ 57 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 58 /* @brief IOCON availability on the SoC. */ 59 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 60 /* @brief MRT availability on the SoC. */ 61 #define FSL_FEATURE_SOC_MRT_COUNT (1) 62 /* @brief MTB availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MTB_COUNT (1) 64 /* @brief PINT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_PINT_COUNT (1) 66 /* @brief PMU availability on the SoC. */ 67 #define FSL_FEATURE_SOC_PMU_COUNT (1) 68 /* @brief SCT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_SCT_COUNT (1) 70 /* @brief SPI availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SPI_COUNT (2) 72 /* @brief SWM availability on the SoC. */ 73 #define FSL_FEATURE_SOC_SWM_COUNT (1) 74 /* @brief SYSCON availability on the SoC. */ 75 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 76 /* @brief USART availability on the SoC. */ 77 #define FSL_FEATURE_SOC_USART_COUNT (5) 78 /* @brief WWDT availability on the SoC. */ 79 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 80 #elif defined(CPU_LPC845M301JHI33) 81 /* @brief ACOMP availability on the SoC. */ 82 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 83 /* @brief ADC availability on the SoC. */ 84 #define FSL_FEATURE_SOC_ADC_COUNT (1) 85 /* @brief CRC availability on the SoC. */ 86 #define FSL_FEATURE_SOC_CRC_COUNT (1) 87 /* @brief CTIMER availability on the SoC. */ 88 #define FSL_FEATURE_SOC_CTIMER_COUNT (1) 89 /* @brief DAC availability on the SoC. */ 90 #define FSL_FEATURE_SOC_DAC_COUNT (1) 91 /* @brief DMA availability on the SoC. */ 92 #define FSL_FEATURE_SOC_DMA_COUNT (1) 93 /* @brief GPIO availability on the SoC. */ 94 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 95 /* @brief I2C availability on the SoC. */ 96 #define FSL_FEATURE_SOC_I2C_COUNT (4) 97 /* @brief INPUTMUX availability on the SoC. */ 98 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 99 /* @brief IOCON availability on the SoC. */ 100 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 101 /* @brief MRT availability on the SoC. */ 102 #define FSL_FEATURE_SOC_MRT_COUNT (1) 103 /* @brief MTB availability on the SoC. */ 104 #define FSL_FEATURE_SOC_MTB_COUNT (1) 105 /* @brief PINT availability on the SoC. */ 106 #define FSL_FEATURE_SOC_PINT_COUNT (1) 107 /* @brief PMU availability on the SoC. */ 108 #define FSL_FEATURE_SOC_PMU_COUNT (1) 109 /* @brief SCT availability on the SoC. */ 110 #define FSL_FEATURE_SOC_SCT_COUNT (1) 111 /* @brief SPI availability on the SoC. */ 112 #define FSL_FEATURE_SOC_SPI_COUNT (2) 113 /* @brief SWM availability on the SoC. */ 114 #define FSL_FEATURE_SOC_SWM_COUNT (1) 115 /* @brief SYSCON availability on the SoC. */ 116 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 117 /* @brief USART availability on the SoC. */ 118 #define FSL_FEATURE_SOC_USART_COUNT (5) 119 /* @brief WWDT availability on the SoC. */ 120 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 121 #endif 122 123 /* ACOMP module features */ 124 125 /* @brief Has INTENA bitfile in CTRL reigster. */ 126 #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1) 127 128 /* ADC module features */ 129 130 /* @brief Do not has input select (register INSEL). */ 131 #define FSL_FEATURE_ADC_HAS_NO_INSEL (1) 132 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 133 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) 134 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 135 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0) 136 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 137 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0) 138 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 139 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0) 140 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 141 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1) 142 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 143 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1) 144 /* @brief Has startup register. */ 145 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (0) 146 /* @brief Has ADC Trim register */ 147 #define FSL_FEATURE_ADC_HAS_TRIM_REG (1) 148 /* @brief Has Calibration register. */ 149 #define FSL_FEATURE_ADC_HAS_CALIB_REG (0) 150 151 /* CAPT module features */ 152 153 #if defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48) 154 /* @brief Has DMA bitfile in CTRL reigster. */ 155 #define FSL_FEATURE_CAPT_HAS_CTRL_DMA (1) 156 #endif /* defined(CPU_LPC845M301JBD48) || defined(CPU_LPC845M301JBD64) || defined(CPU_LPC845M301JHI48) */ 157 158 /* CLOCK module features */ 159 160 /* @brief GPIOINT clock source. */ 161 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1) 162 163 /* CTIMER module features */ 164 165 /* @brief CTIMER has no capture channel. */ 166 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 167 /* @brief CTIMER has no capture 2 interrupt. */ 168 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 169 /* @brief CTIMER capture 3 interrupt. */ 170 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 171 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 172 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 173 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 174 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 175 /* @brief Writing a zero asserts the CTIMER reset. */ 176 #define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1) 177 /* @brief CTIMER Has register MSR */ 178 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 179 180 /* DAC module features */ 181 182 /* @brief Has DMA_ENA bitfile in CTRL reigster. */ 183 #define FSL_FEATURE_DAC_HAS_CTRL_DMA_ENA (1) 184 185 /* DMA module features */ 186 187 /* @brief Number of channels */ 188 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25) 189 /* @brief Align size of DMA descriptor */ 190 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 191 /* @brief DMA head link descriptor table align size */ 192 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 193 194 /* FAIM module features */ 195 196 /* @brief Size of the FAIM */ 197 #define FSL_FEATURE_FAIM_SIZE (32) 198 /* @brief Page count of the FAIM */ 199 #define FSL_FEATURE_FAIM_PAGE_COUNT (8) 200 201 /* INPUTMUX module features */ 202 203 /* @brief Inputmux clock source. */ 204 #define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1) 205 206 /* IOCON module features */ 207 208 /* No feature definitions */ 209 210 /* MRT module features */ 211 212 /* @brief number of channels. */ 213 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 214 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 215 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 216 /* @brief Has no INUSE bitfile in STAT reigster. */ 217 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 218 /* @brief Writing a zero asserts the MRT reset. */ 219 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 220 221 /* NVIC module features */ 222 223 /* @brief Number of connected outputs. */ 224 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 225 226 /* PINT module features */ 227 228 /* @brief Number of connected outputs */ 229 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 230 231 /* SCT module features */ 232 233 /* @brief Number of events */ 234 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8) 235 /* @brief Number of states */ 236 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (8) 237 /* @brief Number of match capture */ 238 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8) 239 /* @brief Number of outputs */ 240 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7) 241 /* @brief Writing a zero asserts the SCT reset. */ 242 #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) 243 244 /* SPI module features */ 245 246 /* @brief Has SPOL0 bitfile in CFG reigster. */ 247 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 248 /* @brief Has SPOL1 bitfile in CFG reigster. */ 249 #define FSL_FEATURE_SPI_HAS_SSEL1 (1) 250 /* @brief Has SPOL2 bitfile in CFG reigster. */ 251 #define FSL_FEATURE_SPI_HAS_SSEL2 (1) 252 /* @brief Has SPOL3 bitfile in CFG reigster. */ 253 #define FSL_FEATURE_SPI_HAS_SSEL3 (1) 254 255 /* SWM module features */ 256 257 /* @brief Has SWM PINENABLE0 ACMP I3. */ 258 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1) 259 /* @brief Has SWM PINENABLE0 ACMP I4. */ 260 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1) 261 /* @brief Has SWM PINENABLE0 ACMP I5. */ 262 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1) 263 /* @brief Has SWM PINENABLE1. */ 264 #define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1) 265 266 /* SYSCON module features */ 267 268 /* @brief Pointer to ROM IAP entry functions */ 269 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1) 270 /* @brief IAP Reinvoke ISP command parameter is pointer */ 271 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) 272 /* @brief Flash page size in bytes */ 273 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 274 /* @brief Flash sector size in bytes */ 275 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 276 /* @brief Flash size in bytes */ 277 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536) 278 /* @brief IAP has Flash read & write function */ 279 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 280 /* @brief IAP has FAIM read & write function */ 281 #define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1) 282 /* @brief IAP has read Flash signature function */ 283 #define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0) 284 /* @brief IAP has read extended Flash signature function */ 285 #define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1) 286 /* @brief Starter register discontinuous. */ 287 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 288 /* @brief Has PINTSEL register. */ 289 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 290 291 /* USART module features */ 292 293 /* @brief Has OSR (register OSR). */ 294 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (1) 295 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 296 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1) 297 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 298 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (1) 299 300 /* WKT module features */ 301 302 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 303 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1) 304 305 /* WWDT module features */ 306 307 /* @brief Has no RESET register. */ 308 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 309 310 #endif /* _LPC845_FEATURES_H_ */ 311 312
