1 /* 2 ** ################################################################### 3 ** Processors: LPC844M201JBD48 4 ** LPC844M201JBD64 5 ** LPC844M201JHI33 6 ** LPC844M201JHI48 7 ** 8 ** Compilers: GNU C Compiler 9 ** IAR ANSI C/C++ Compiler for ARM 10 ** Keil ARM C/C++ Compiler 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: LPC84x User manual Rev.1.6 8 Dec 2017 14 ** Version: rev. 1.2, 2017-06-08 15 ** Build: b210815 16 ** 17 ** Abstract: 18 ** Provides a system configuration function and a global variable that 19 ** contains the system frequency. It configures the device and initializes 20 ** the oscillator (PLL) that is part of the microcontroller device. 21 ** 22 ** Copyright 2016 Freescale Semiconductor, Inc. 23 ** Copyright 2016-2021 NXP 24 ** All rights reserved. 25 ** 26 ** SPDX-License-Identifier: BSD-3-Clause 27 ** 28 ** http: www.nxp.com 29 ** mail: support@nxp.com 30 ** 31 ** Revisions: 32 ** - rev. 1.0 (2016-08-12) 33 ** Initial version. 34 ** - rev. 1.1 (2016-11-25) 35 ** Update CANFD and Classic CAN register. 36 ** Add MAC TIMERSTAMP registers. 37 ** - rev. 1.2 (2017-06-08) 38 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 39 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 40 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 41 ** 42 ** ################################################################### 43 */ 44 45 /*! 46 * @file LPC844 47 * @version 1.2 48 * @date 2017-06-08 49 * @brief Device specific configuration file for LPC844 (implementation file) 50 * 51 * Provides a system configuration function and a global variable that contains 52 * the system frequency. It configures the device and initializes the oscillator 53 * (PLL) that is part of the microcontroller device. 54 */ 55 56 #include <stdint.h> 57 #include "fsl_device_registers.h" 58 59 60 61 62 63 /* ---------------------------------------------------------------------------- 64 -- Core clock 65 ---------------------------------------------------------------------------- */ 66 67 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 68 69 /* ---------------------------------------------------------------------------- 70 -- SystemInit() 71 ---------------------------------------------------------------------------- */ 72 SystemInit(void)73void SystemInit (void) { 74 75 #if defined(__MCUXPRESSO) 76 extern void(*const g_pfnVectors[]) (void); 77 SCB->VTOR = (uint32_t) &g_pfnVectors; 78 #else 79 extern void *__Vectors; 80 SCB->VTOR = (uint32_t) &__Vectors; 81 #endif 82 FLASH_CTRL->FLASHCFG &= ~FLASH_CTRL_FLASHCFG_FLASHTIM_MASK; /* set 1 system clock flash access time. */ 83 SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 84 SystemInitHook(); 85 } 86 87 /* ---------------------------------------------------------------------------- 88 -- SystemCoreClockUpdate() 89 ---------------------------------------------------------------------------- */ 90 SystemCoreClockUpdate(void)91void SystemCoreClockUpdate (void) { 92 uint32_t wdt_osc = 0U; 93 uint32_t fro_osc = 0U; 94 95 /* Determine clock frequency according to clock register values */ 96 switch ((SYSCON->FROOSCCTRL ) & 0x03U) { 97 case 0U: fro_osc = 18000000U; break; 98 case 1U: fro_osc = 24000000U; break; 99 case 2U: fro_osc = 30000000U; break; 100 case 3U: fro_osc = 30000000U; break; 101 default: fro_osc = 0U; break; 102 } 103 if (((SYSCON->FROOSCCTRL >> SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT) & 0x01U) == 0U) { 104 fro_osc = fro_osc >> 1U; 105 } 106 107 switch ((SYSCON->WDTOSCCTRL >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) & 0x0FU) { 108 case 0U: wdt_osc = 0U; break; 109 case 1U: wdt_osc = 600000U; break; 110 case 2U: wdt_osc = 1050000U; break; 111 case 3U: wdt_osc = 1400000U; break; 112 case 4U: wdt_osc = 1750000U; break; 113 case 5U: wdt_osc = 2100000U; break; 114 case 6U: wdt_osc = 2400000U; break; 115 case 7U: wdt_osc = 2700000U; break; 116 case 8U: wdt_osc = 3000000U; break; 117 case 9U: wdt_osc = 3250000U; break; 118 case 10U: wdt_osc = 3500000U; break; 119 case 11U: wdt_osc = 3750000U; break; 120 case 12U: wdt_osc = 4000000U; break; 121 case 13U: wdt_osc = 4200000U; break; 122 case 14U: wdt_osc = 4400000U; break; 123 case 15U: wdt_osc = 4600000U; break; 124 default: wdt_osc = 0U; break; 125 } 126 wdt_osc /= (((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U); 127 128 switch (SYSCON->MAINCLKPLLSEL & 0x01U) { 129 case 0U: /* main_clk_pre_pll */ 130 switch (SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) { 131 case 0U: /* Free running oscillator (FRO) */ 132 SystemCoreClock = fro_osc; 133 break; 134 case 1U: /* System oscillator */ 135 SystemCoreClock = CLK_OSC_IN; 136 break; 137 case 2U: /* watchdog oscillator */ 138 SystemCoreClock = wdt_osc; 139 break; 140 case 3U: /* Free running oscillator (FRO) / 2 */ 141 SystemCoreClock = (fro_osc >> 1U); 142 break; 143 default: 144 SystemCoreClock = 0U; 145 break; 146 } 147 break; 148 case 1U: /* System PLL Clock Out */ 149 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) { 150 case 0U: /* Free running oscillator (FRO) */ 151 SystemCoreClock = fro_osc * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 152 break; 153 case 1U: /* System oscillator */ 154 SystemCoreClock = CLK_OSC_IN * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 155 break; 156 case 2U: /* watchdog oscillator */ 157 SystemCoreClock = wdt_osc * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 158 break; 159 case 3U: /* Free running oscillator (FRO) / 2 */ 160 SystemCoreClock = (fro_osc >> 1U) * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 161 break; 162 default: 163 SystemCoreClock = 0U; 164 break; 165 } 166 break; 167 default: 168 SystemCoreClock = 0U; 169 break; 170 } 171 172 SystemCoreClock /= SYSCON->SYSAHBCLKDIV; 173 } 174 175 /* ---------------------------------------------------------------------------- 176 -- SystemInitHook() 177 ---------------------------------------------------------------------------- */ 178 SystemInitHook(void)179__attribute__ ((weak)) void SystemInitHook (void) { 180 /* Void implementation of the weak function. */ 181 } 182
