1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC834_FEATURES_H_ 33 #define _LPC834_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ADC availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ADC_COUNT (1) 39 /* @brief CRC availability on the SoC. */ 40 #define FSL_FEATURE_SOC_CRC_COUNT (1) 41 /* @brief DMA availability on the SoC. */ 42 #define FSL_FEATURE_SOC_DMA_COUNT (1) 43 /* @brief GPIO availability on the SoC. */ 44 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 45 /* @brief I2C availability on the SoC. */ 46 #define FSL_FEATURE_SOC_I2C_COUNT (1) 47 /* @brief INPUTMUX availability on the SoC. */ 48 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 49 /* @brief IOCON availability on the SoC. */ 50 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 51 /* @brief MRT availability on the SoC. */ 52 #define FSL_FEATURE_SOC_MRT_COUNT (1) 53 /* @brief MTB availability on the SoC. */ 54 #define FSL_FEATURE_SOC_MTB_COUNT (1) 55 /* @brief PINT availability on the SoC. */ 56 #define FSL_FEATURE_SOC_PINT_COUNT (1) 57 /* @brief PMU availability on the SoC. */ 58 #define FSL_FEATURE_SOC_PMU_COUNT (1) 59 /* @brief SCT availability on the SoC. */ 60 #define FSL_FEATURE_SOC_SCT_COUNT (1) 61 /* @brief SPI availability on the SoC. */ 62 #define FSL_FEATURE_SOC_SPI_COUNT (2) 63 /* @brief SWM availability on the SoC. */ 64 #define FSL_FEATURE_SOC_SWM_COUNT (1) 65 /* @brief SYSCON availability on the SoC. */ 66 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 67 /* @brief USART availability on the SoC. */ 68 #define FSL_FEATURE_SOC_USART_COUNT (1) 69 /* @brief WWDT availability on the SoC. */ 70 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 71 72 /* ADC module features */ 73 74 /* @brief Do not has input select (register INSEL). */ 75 #define FSL_FEATURE_ADC_HAS_NO_INSEL (1) 76 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 77 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (0) 78 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 79 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0) 80 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 81 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0) 82 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 83 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0) 84 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 85 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1) 86 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 87 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1) 88 /* @brief Has startup register. */ 89 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (0) 90 /* @brief Has ADC Trim register */ 91 #define FSL_FEATURE_ADC_HAS_TRIM_REG (1) 92 /* @brief Has Calibration register. */ 93 #define FSL_FEATURE_ADC_HAS_CALIB_REG (0) 94 95 /* CLOCK module features */ 96 97 /* @brief GPIOINT clock source. */ 98 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (0) 99 100 /* DMA module features */ 101 102 /* @brief Number of channels */ 103 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (18) 104 /* @brief Align size of DMA descriptor */ 105 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 106 /* @brief DMA head link descriptor table align size */ 107 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 108 109 /* INPUTMUX module features */ 110 111 /* @brief Inputmux clock source. */ 112 #define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1) 113 114 /* IOCON module features */ 115 116 /* No feature definitions */ 117 118 /* MRT module features */ 119 120 /* @brief number of channels. */ 121 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 122 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 123 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 124 /* @brief Has no INUSE bitfile in STAT reigster. */ 125 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 126 /* @brief Writing a zero asserts the MRT reset. */ 127 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 128 129 /* NVIC module features */ 130 131 /* @brief Number of connected outputs. */ 132 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 133 134 /* PINT module features */ 135 136 /* @brief Number of connected outputs */ 137 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 138 139 /* SCT module features */ 140 141 /* @brief Number of events */ 142 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8) 143 /* @brief Number of states */ 144 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (8) 145 /* @brief Number of match capture */ 146 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8) 147 /* @brief Number of outputs */ 148 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (6) 149 /* @brief Writing a zero asserts the SCT reset. */ 150 #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) 151 152 /* SPI module features */ 153 154 /* @brief Has SPOL0 bitfile in CFG reigster. */ 155 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 156 /* @brief Has SPOL1 bitfile in CFG reigster. */ 157 #define FSL_FEATURE_SPI_HAS_SSEL1 (1) 158 /* @brief Has SPOL2 bitfile in CFG reigster. */ 159 #define FSL_FEATURE_SPI_HAS_SSEL2 (1) 160 /* @brief Has SPOL3 bitfile in CFG reigster. */ 161 #define FSL_FEATURE_SPI_HAS_SSEL3 (1) 162 163 /* SWM module features */ 164 165 /* @brief Has SWM PINENABLE0 ACMP I3. */ 166 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (0) 167 /* @brief Has SWM PINENABLE0 ACMP I4. */ 168 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (0) 169 /* @brief Has SWM PINENABLE0 ACMP I5. */ 170 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (0) 171 172 /* SYSCON module features */ 173 174 /* @brief Pointer to ROM IAP entry functions */ 175 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x1fff1ff1) 176 /* @brief IAP Reinvoke ISP command parameter is pointer */ 177 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) 178 /* @brief Flash page size in bytes */ 179 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 180 /* @brief Flash sector size in bytes */ 181 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 182 /* @brief Flash size in bytes */ 183 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (32768) 184 /* @brief IAP has Flash read & write function */ 185 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 186 /* @brief Starter register discontinuous. */ 187 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 188 /* @brief Has PINTSEL register. */ 189 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 190 191 /* USART module features */ 192 193 /* @brief Has OSR (register OSR). */ 194 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (1) 195 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 196 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1) 197 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 198 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (1) 199 200 /* WKT module features */ 201 202 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 203 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1) 204 205 /* WWDT module features */ 206 207 /* @brief Has no RESET register. */ 208 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 209 210 #endif /* _LPC834_FEATURES_H_ */ 211 212
