1 /* 2 * Copyright 2017 NXP 3 * All rights reserved. 4 * 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_INPUTMUX_CONNECTIONS_ 10 #define _FSL_INPUTMUX_CONNECTIONS_ 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 /* Component ID definition, used by tools. */ 16 #ifndef FSL_COMPONENT_ID 17 #define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" 18 #endif 19 20 /*! 21 * @addtogroup inputmux_driver 22 * @{ 23 */ 24 25 /*! 26 * @name Input multiplexing connections 27 * @{ 28 */ 29 30 /*! @brief Periphinmux IDs */ 31 #define DMA_ITRIG_INMUX_ID 0x00U 32 #define DMA_OTRIG_PMUX_ID 0x4000U 33 #define SCT0_INMUX_ID 0x4020U 34 #define PMUX_SHIFT 16U 35 36 /*! @brief INPUTMUX connections type */ 37 typedef enum _inputmux_connection_t 38 { 39 /*!< DMA ITRIG INMUX. */ 40 kINPUTMUX_AdcASeqaIrqToDma = 0U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 41 kINPUTMUX_AdcBSeqbIrqToDma = 1U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 42 kINPUTMUX_SctDma0ToDma = 2U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 43 kINPUTMUX_SctDma1ToDma = 3U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 44 kINPUTMUX_AcmpOToDma = 4U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 45 kINPUTMUX_PinInt0ToDma = 5U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 46 kINPUTMUX_PinInt1ToDma = 6U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 47 kINPUTMUX_DmaTriggerMux0ToDma = 7U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 48 kINPUTMUX_DmaTriggerMux1ToDma = 8U + (DMA_ITRIG_INMUX_ID << PMUX_SHIFT), 49 50 /*!< DMA INMUX. */ 51 kINPUTMUX_DmaChannel0TrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 52 kINPUTMUX_DmaChannel1TrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 53 kINPUTMUX_DmaChannel2TrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 54 kINPUTMUX_DmaChannel3TrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 55 kINPUTMUX_DmaChannel4TrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 56 kINPUTMUX_DmaChannel5TrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 57 kINPUTMUX_DmaChannel6TrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 58 kINPUTMUX_DmaChannel7TrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 59 kINPUTMUX_DmaChannel8TrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 60 kINPUTMUX_DmaChannel9TrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 61 kINPUTMUX_DmaChannel10TrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 62 kINPUTMUX_DmaChannel11TrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 63 kINPUTMUX_DmaChannel12TrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 64 kINPUTMUX_DmaChannel13TrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 65 kINPUTMUX_DmaChannel14TrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 66 kINPUTMUX_DmaChannel15TrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 67 kINPUTMUX_DmaChannel16TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 68 kINPUTMUX_DmaChannel17TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 69 70 /*!< SCT INMUX. */ 71 kINPUTMUX_SctPin0ToSct0 = 0U + (SCT0_INMUX_ID << PMUX_SHIFT), 72 kINPUTMUX_SctPin1ToSct0 = 1U + (SCT0_INMUX_ID << PMUX_SHIFT), 73 kINPUTMUX_SctPin2ToSct0 = 2U + (SCT0_INMUX_ID << PMUX_SHIFT), 74 kINPUTMUX_SctPin3ToSct0 = 3U + (SCT0_INMUX_ID << PMUX_SHIFT), 75 kINPUTMUX_AdcThcmpIrqToSct0 = 4U + (SCT0_INMUX_ID << PMUX_SHIFT), 76 kINPUTMUX_AcmpOToSct0 = 5U + (SCT0_INMUX_ID << PMUX_SHIFT), 77 kINPUTMUX_ArmTxevToSct0 = 6U + (SCT0_INMUX_ID << PMUX_SHIFT), 78 kINPUTMUX_DebugHaltedToSct0 =7U + (SCT0_INMUX_ID << PMUX_SHIFT), 79 80 } inputmux_connection_t; 81 82 /*@}*/ 83 84 #endif /* _FSL_INPUTMUX_CONNECTIONS_ */ 85
