1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC822_FEATURES_H_ 33 #define _LPC822_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ACOMP availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 39 /* @brief ADC availability on the SoC. */ 40 #define FSL_FEATURE_SOC_ADC_COUNT (1) 41 /* @brief CRC availability on the SoC. */ 42 #define FSL_FEATURE_SOC_CRC_COUNT (1) 43 /* @brief DMA availability on the SoC. */ 44 #define FSL_FEATURE_SOC_DMA_COUNT (1) 45 /* @brief GPIO availability on the SoC. */ 46 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 47 /* @brief I2C availability on the SoC. */ 48 #define FSL_FEATURE_SOC_I2C_COUNT (4) 49 /* @brief INPUTMUX availability on the SoC. */ 50 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 51 /* @brief IOCON availability on the SoC. */ 52 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 53 /* @brief MRT availability on the SoC. */ 54 #define FSL_FEATURE_SOC_MRT_COUNT (1) 55 /* @brief MTB availability on the SoC. */ 56 #define FSL_FEATURE_SOC_MTB_COUNT (1) 57 /* @brief PINT availability on the SoC. */ 58 #define FSL_FEATURE_SOC_PINT_COUNT (1) 59 /* @brief PMU availability on the SoC. */ 60 #define FSL_FEATURE_SOC_PMU_COUNT (1) 61 /* @brief SCT availability on the SoC. */ 62 #define FSL_FEATURE_SOC_SCT_COUNT (1) 63 /* @brief SPI availability on the SoC. */ 64 #define FSL_FEATURE_SOC_SPI_COUNT (2) 65 /* @brief SWM availability on the SoC. */ 66 #define FSL_FEATURE_SOC_SWM_COUNT (1) 67 /* @brief SYSCON availability on the SoC. */ 68 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 69 /* @brief USART availability on the SoC. */ 70 #define FSL_FEATURE_SOC_USART_COUNT (3) 71 /* @brief WWDT availability on the SoC. */ 72 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 73 74 /* ACOMP module features */ 75 76 /* @brief Has INTENA bitfile in CTRL reigster. */ 77 #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (0) 78 79 /* ADC module features */ 80 81 /* @brief Do not has input select (register INSEL). */ 82 #define FSL_FEATURE_ADC_HAS_NO_INSEL (1) 83 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 84 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (0) 85 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 86 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0) 87 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 88 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0) 89 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 90 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0) 91 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 92 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1) 93 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 94 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1) 95 /* @brief Has startup register. */ 96 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (0) 97 /* @brief Has ADC Trim register */ 98 #define FSL_FEATURE_ADC_HAS_TRIM_REG (1) 99 /* @brief Has Calibration register. */ 100 #define FSL_FEATURE_ADC_HAS_CALIB_REG (0) 101 102 /* CLOCK module features */ 103 104 /* @brief GPIOINT clock source. */ 105 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (0) 106 107 /* DMA module features */ 108 109 /* @brief Number of channels */ 110 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (18) 111 /* @brief Align size of DMA descriptor */ 112 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 113 /* @brief DMA head link descriptor table align size */ 114 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 115 116 /* INPUTMUX module features */ 117 118 /* @brief Inputmux clock source. */ 119 #define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1) 120 121 /* IOCON module features */ 122 123 /* No feature definitions */ 124 125 /* MRT module features */ 126 127 /* @brief number of channels. */ 128 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 129 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 130 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 131 /* @brief Has no INUSE bitfile in STAT reigster. */ 132 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 133 /* @brief Writing a zero asserts the MRT reset. */ 134 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 135 136 /* NVIC module features */ 137 138 /* @brief Number of connected outputs. */ 139 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 140 141 /* PINT module features */ 142 143 /* @brief Number of connected outputs */ 144 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 145 146 /* SCT module features */ 147 148 /* @brief Number of events */ 149 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8) 150 /* @brief Number of states */ 151 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (8) 152 /* @brief Number of match capture */ 153 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8) 154 /* @brief Number of outputs */ 155 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (6) 156 /* @brief Writing a zero asserts the SCT reset. */ 157 #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) 158 159 /* SPI module features */ 160 161 /* @brief Has SPOL0 bitfile in CFG reigster. */ 162 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 163 /* @brief Has SPOL1 bitfile in CFG reigster. */ 164 #define FSL_FEATURE_SPI_HAS_SSEL1 (1) 165 /* @brief Has SPOL2 bitfile in CFG reigster. */ 166 #define FSL_FEATURE_SPI_HAS_SSEL2 (1) 167 /* @brief Has SPOL3 bitfile in CFG reigster. */ 168 #define FSL_FEATURE_SPI_HAS_SSEL3 (1) 169 170 /* SWM module features */ 171 172 /* @brief Has SWM PINENABLE0 ACMP I3. */ 173 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1) 174 /* @brief Has SWM PINENABLE0 ACMP I4. */ 175 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1) 176 /* @brief Has SWM PINENABLE0 ACMP I5. */ 177 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (0) 178 179 /* SYSCON module features */ 180 181 /* @brief Pointer to ROM IAP entry functions */ 182 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x1fff1ff1) 183 /* @brief IAP Reinvoke ISP command parameter is pointer */ 184 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) 185 /* @brief Flash page size in bytes */ 186 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 187 /* @brief Flash sector size in bytes */ 188 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 189 /* @brief Flash size in bytes */ 190 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (16384) 191 /* @brief IAP has Flash read & write function */ 192 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 193 /* @brief Starter register discontinuous. */ 194 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 195 /* @brief Has PINTSEL register. */ 196 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 197 198 /* USART module features */ 199 200 /* @brief Has OSR (register OSR). */ 201 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (1) 202 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 203 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1) 204 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 205 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (1) 206 207 /* WKT module features */ 208 209 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 210 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1) 211 212 /* WWDT module features */ 213 214 /* @brief Has no RESET register. */ 215 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 216 217 #endif /* _LPC822_FEATURES_H_ */ 218 219
