1 /* 2 ** ################################################################### 3 ** Processors: LPC812M101JD20 4 ** LPC812M101JDH16 5 ** LPC812M101JDH20 6 ** LPC812M101JTB16 7 ** 8 ** Compilers: GNU C Compiler 9 ** IAR ANSI C/C++ Compiler for ARM 10 ** Keil ARM C/C++ Compiler 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: LPC81x User manual Rev.1.6 2 April 2014 14 ** Version: rev. 1.2, 2017-06-08 15 ** Build: b201015 16 ** 17 ** Abstract: 18 ** Provides a system configuration function and a global variable that 19 ** contains the system frequency. It configures the device and initializes 20 ** the oscillator (PLL) that is part of the microcontroller device. 21 ** 22 ** Copyright 2016 Freescale Semiconductor, Inc. 23 ** Copyright 2016-2020 NXP 24 ** All rights reserved. 25 ** 26 ** SPDX-License-Identifier: BSD-3-Clause 27 ** 28 ** http: www.nxp.com 29 ** mail: support@nxp.com 30 ** 31 ** Revisions: 32 ** - rev. 1.0 (2016-08-12) 33 ** Initial version. 34 ** - rev. 1.1 (2016-11-25) 35 ** Update CANFD and Classic CAN register. 36 ** Add MAC TIMERSTAMP registers. 37 ** - rev. 1.2 (2017-06-08) 38 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 39 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 40 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 41 ** 42 ** ################################################################### 43 */ 44 45 /*! 46 * @file LPC812 47 * @version 1.2 48 * @date 2017-06-08 49 * @brief Device specific configuration file for LPC812 (implementation file) 50 * 51 * Provides a system configuration function and a global variable that contains 52 * the system frequency. It configures the device and initializes the oscillator 53 * (PLL) that is part of the microcontroller device. 54 */ 55 56 #include <stdint.h> 57 #include "fsl_device_registers.h" 58 59 /* get system pll input freq */ CLOCK_GetSystemPLLInClkRate(void)60static uint32_t CLOCK_GetSystemPLLInClkRate(void) 61 { 62 uint32_t freq = 0U; 63 64 switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) 65 { 66 /* source from external clock in */ 67 case 0x00U: 68 freq = CLK_IRC_12MHZ; 69 break; 70 /* source from the IRC clock */ 71 case 0x01U: 72 freq = CLK_OSC_IN; 73 break; 74 /* source from external clock clock */ 75 case 0x03U: 76 freq = EXT_CLK_IN; 77 break; 78 79 default: 80 /* default source from the IRC clock */ 81 freq = CLK_IRC_12MHZ; 82 break; 83 } 84 85 return freq; 86 } 87 88 /* get system pll output freq*/ Clock_GetPLLFreq(uint32_t PLLReg,uint32_t inputRate)89static uint32_t Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate) 90 { 91 uint32_t m_val = ((PLLReg & 0x1FU) + 1U); 92 93 return (inputRate * m_val); 94 } 95 96 97 98 /* ---------------------------------------------------------------------------- 99 -- Core clock 100 ---------------------------------------------------------------------------- */ 101 102 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 103 104 /* ---------------------------------------------------------------------------- 105 -- SystemInit() 106 ---------------------------------------------------------------------------- */ 107 SystemInit(void)108void SystemInit (void) { 109 110 #if defined(__MCUXPRESSO) 111 extern void(*const g_pfnVectors[]) (void); 112 SCB->VTOR = (uint32_t) &g_pfnVectors; 113 #else 114 extern void *__Vectors; 115 SCB->VTOR = (uint32_t) &__Vectors; 116 #endif 117 SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 118 SystemInitHook(); 119 } 120 121 /* ---------------------------------------------------------------------------- 122 -- SystemCoreClockUpdate() 123 ---------------------------------------------------------------------------- */ 124 SystemCoreClockUpdate(void)125void SystemCoreClockUpdate (void) { 126 uint32_t wdt_osc = 0U; 127 uint32_t irc_clk = 12000000U; 128 129 switch ((SYSCON->WDTOSCCTRL >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) & 0x0FU) { 130 case 0U: wdt_osc = 0U; break; 131 case 1U: wdt_osc = 600000U; break; 132 case 2U: wdt_osc = 1050000U; break; 133 case 3U: wdt_osc = 1400000U; break; 134 case 4U: wdt_osc = 1750000U; break; 135 case 5U: wdt_osc = 2100000U; break; 136 case 6U: wdt_osc = 2400000U; break; 137 case 7U: wdt_osc = 2700000U; break; 138 case 8U: wdt_osc = 3000000U; break; 139 case 9U: wdt_osc = 3250000U; break; 140 case 10U: wdt_osc = 3500000U; break; 141 case 11U: wdt_osc = 3750000U; break; 142 case 12U: wdt_osc = 4000000U; break; 143 case 13U: wdt_osc = 4200000U; break; 144 case 14U: wdt_osc = 4400000U; break; 145 case 15U: wdt_osc = 4600000U; break; 146 default: wdt_osc = 0U; break; 147 } 148 wdt_osc /= (((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U); 149 150 switch (SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) 151 { 152 case 0U: /* IRC */ 153 SystemCoreClock = irc_clk; 154 break; 155 case 1U: /* System PLL input */ 156 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) { 157 case 0U: /* IRC */ 158 SystemCoreClock = irc_clk; 159 break; 160 case 1U: /* System oscillator */ 161 SystemCoreClock = CLK_OSC_IN; 162 break; 163 case 3U: /* CLKIN */ 164 SystemCoreClock = EXT_CLK_IN; 165 break; 166 default: 167 SystemCoreClock = irc_clk; /* default is IRC */ 168 break; 169 } 170 break; 171 case 2U: /* watchdog oscillator */ 172 SystemCoreClock = wdt_osc; 173 break; 174 case 3U: /* System PLL */ 175 SystemCoreClock = Clock_GetPLLFreq((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK), CLOCK_GetSystemPLLInClkRate()); 176 break; 177 default: 178 SystemCoreClock = 0U; 179 break; 180 } 181 182 SystemCoreClock /= SYSCON->SYSAHBCLKDIV; 183 } 184 185 /* ---------------------------------------------------------------------------- 186 -- SystemInitHook() 187 ---------------------------------------------------------------------------- */ 188 SystemInitHook(void)189__attribute__ ((weak)) void SystemInitHook (void) { 190 /* Void implementation of the weak function. */ 191 } 192
