1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b190506 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2019 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC812_FEATURES_H_ 33 #define _LPC812_FEATURES_H_ 34 35 /* SOC module features */ 36 37 #if defined(CPU_LPC812M101JD20) 38 /* @brief CRC availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CRC_COUNT (1) 40 /* @brief GPIO availability on the SoC. */ 41 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 42 /* @brief I2C availability on the SoC. */ 43 #define FSL_FEATURE_SOC_I2C_COUNT (1) 44 /* @brief IOCON availability on the SoC. */ 45 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 46 /* @brief MRT availability on the SoC. */ 47 #define FSL_FEATURE_SOC_MRT_COUNT (1) 48 /* @brief MTB availability on the SoC. */ 49 #define FSL_FEATURE_SOC_MTB_COUNT (1) 50 /* @brief PINT availability on the SoC. */ 51 #define FSL_FEATURE_SOC_PINT_COUNT (1) 52 /* @brief PMU availability on the SoC. */ 53 #define FSL_FEATURE_SOC_PMU_COUNT (1) 54 /* @brief SCT availability on the SoC. */ 55 #define FSL_FEATURE_SOC_SCT_COUNT (1) 56 /* @brief SPI availability on the SoC. */ 57 #define FSL_FEATURE_SOC_SPI_COUNT (1) 58 /* @brief SWM availability on the SoC. */ 59 #define FSL_FEATURE_SOC_SWM_COUNT (1) 60 /* @brief SYSCON availability on the SoC. */ 61 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 62 /* @brief USART availability on the SoC. */ 63 #define FSL_FEATURE_SOC_USART_COUNT (2) 64 /* @brief WWDT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 66 #elif defined(CPU_LPC812M101JDH16) || defined(CPU_LPC812M101JDH20) || defined(CPU_LPC812M101JTB16) 67 /* @brief CRC availability on the SoC. */ 68 #define FSL_FEATURE_SOC_CRC_COUNT (1) 69 /* @brief GPIO availability on the SoC. */ 70 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 71 /* @brief I2C availability on the SoC. */ 72 #define FSL_FEATURE_SOC_I2C_COUNT (1) 73 /* @brief IOCON availability on the SoC. */ 74 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 75 /* @brief MRT availability on the SoC. */ 76 #define FSL_FEATURE_SOC_MRT_COUNT (1) 77 /* @brief MTB availability on the SoC. */ 78 #define FSL_FEATURE_SOC_MTB_COUNT (1) 79 /* @brief PINT availability on the SoC. */ 80 #define FSL_FEATURE_SOC_PINT_COUNT (1) 81 /* @brief PMU availability on the SoC. */ 82 #define FSL_FEATURE_SOC_PMU_COUNT (1) 83 /* @brief SCT availability on the SoC. */ 84 #define FSL_FEATURE_SOC_SCT_COUNT (1) 85 /* @brief SPI availability on the SoC. */ 86 #define FSL_FEATURE_SOC_SPI_COUNT (2) 87 /* @brief SWM availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SWM_COUNT (1) 89 /* @brief SYSCON availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 91 /* @brief USART availability on the SoC. */ 92 #define FSL_FEATURE_SOC_USART_COUNT (3) 93 /* @brief WWDT availability on the SoC. */ 94 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 95 #endif 96 97 /* ACOMP module features */ 98 99 /* @brief Has INTENA bitfile in CTRL reigster. */ 100 #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (0) 101 102 /* CLOCK module features */ 103 104 /* @brief GPIOINT clock source. */ 105 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (0) 106 107 /* IOCON module features */ 108 109 /* No feature definitions */ 110 111 /* MRT module features */ 112 113 /* @brief Writing a zero asserts the MRT reset. */ 114 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 115 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 116 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 117 /* @brief Has no INUSE bitfile in STAT reigster. */ 118 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 119 /* @brief number of channels. */ 120 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 121 122 /* NVIC module features */ 123 124 /* @brief Number of connected outputs. */ 125 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 126 127 /* PINT module features */ 128 129 /* @brief Number of connected outputs */ 130 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 131 132 /* SCT module features */ 133 134 /* @brief Number of events */ 135 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (6) 136 /* @brief Number of states */ 137 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (2) 138 /* @brief Number of match capture */ 139 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (5) 140 /* @brief Writing a zero asserts the SCT reset. */ 141 #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) 142 /* @brief Do not has DMA request register (register DMAREQ0). */ 143 #define FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST (1) 144 /* @brief Number of outputs */ 145 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (4) 146 147 /* SPI module features */ 148 149 /* @brief Has SPOL0 bitfile in CFG reigster. */ 150 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 151 /* @brief Has SPOL1 bitfile in CFG reigster. */ 152 #define FSL_FEATURE_SPI_HAS_SSEL1 (0) 153 /* @brief Has SPOL2 bitfile in CFG reigster. */ 154 #define FSL_FEATURE_SPI_HAS_SSEL2 (0) 155 /* @brief Has SPOL3 bitfile in CFG reigster. */ 156 #define FSL_FEATURE_SPI_HAS_SSEL3 (0) 157 158 /* SWM module features */ 159 160 /* @brief Has SWM PINENABLE0 ACMP I3. */ 161 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (0) 162 /* @brief Has SWM PINENABLE0 ACMP I4. */ 163 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (0) 164 /* @brief Has SWM PINENABLE0 ACMP I5. */ 165 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (0) 166 167 /* SYSCON module features */ 168 169 /* @brief Pointer to ROM IAP entry functions */ 170 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x1fff1ff1) 171 /* @brief Flash page size in bytes */ 172 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 173 /* @brief Flash sector size in bytes */ 174 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 175 /* @brief Flash size in bytes */ 176 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (16384) 177 /* @brief IAP has Flash read & write function */ 178 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 179 /* @brief Starter register discontinuous. */ 180 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 181 /* @brief Has PINTSEL register. */ 182 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 183 184 /* USART module features */ 185 186 /* @brief Has OSR (register OSR). */ 187 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (0) 188 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 189 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (0) 190 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 191 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (0) 192 193 /* WKT module features */ 194 195 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 196 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (0) 197 198 /* WWDT module features */ 199 200 /* @brief Has no RESET register. */ 201 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 202 203 #endif /* _LPC812_FEATURES_H_ */ 204 205
