1 /* 2 ** ################################################################### 3 ** Processor: LPC810M021FN8 4 ** Compilers: GNU C Compiler 5 ** IAR ANSI C/C++ Compiler for ARM 6 ** Keil ARM C/C++ Compiler 7 ** MCUXpresso Compiler 8 ** 9 ** Reference manual: LPC81x User manual Rev.1.6 2 April 2014 10 ** Version: rev. 1.2, 2017-06-08 11 ** Build: b201015 12 ** 13 ** Abstract: 14 ** Provides a system configuration function and a global variable that 15 ** contains the system frequency. It configures the device and initializes 16 ** the oscillator (PLL) that is part of the microcontroller device. 17 ** 18 ** Copyright 2016 Freescale Semiconductor, Inc. 19 ** Copyright 2016-2020 NXP 20 ** All rights reserved. 21 ** 22 ** SPDX-License-Identifier: BSD-3-Clause 23 ** 24 ** http: www.nxp.com 25 ** mail: support@nxp.com 26 ** 27 ** Revisions: 28 ** - rev. 1.0 (2016-08-12) 29 ** Initial version. 30 ** - rev. 1.1 (2016-11-25) 31 ** Update CANFD and Classic CAN register. 32 ** Add MAC TIMERSTAMP registers. 33 ** - rev. 1.2 (2017-06-08) 34 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 35 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 36 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 37 ** 38 ** ################################################################### 39 */ 40 41 /*! 42 * @file LPC810 43 * @version 1.2 44 * @date 2017-06-08 45 * @brief Device specific configuration file for LPC810 (implementation file) 46 * 47 * Provides a system configuration function and a global variable that contains 48 * the system frequency. It configures the device and initializes the oscillator 49 * (PLL) that is part of the microcontroller device. 50 */ 51 52 #include <stdint.h> 53 #include "fsl_device_registers.h" 54 55 /* get system pll input freq */ CLOCK_GetSystemPLLInClkRate(void)56static uint32_t CLOCK_GetSystemPLLInClkRate(void) 57 { 58 uint32_t freq = 0U; 59 60 switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) 61 { 62 /* source from external clock in */ 63 case 0x00U: 64 freq = CLK_IRC_12MHZ; 65 break; 66 /* source from the IRC clock */ 67 case 0x01U: 68 freq = CLK_OSC_IN; 69 break; 70 /* source from external clock clock */ 71 case 0x03U: 72 freq = EXT_CLK_IN; 73 break; 74 75 default: 76 /* default source from the IRC clock */ 77 freq = CLK_IRC_12MHZ; 78 break; 79 } 80 81 return freq; 82 } 83 84 /* get system pll output freq*/ Clock_GetPLLFreq(uint32_t PLLReg,uint32_t inputRate)85static uint32_t Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate) 86 { 87 uint32_t m_val = ((PLLReg & 0x1FU) + 1U); 88 89 return (inputRate * m_val); 90 } 91 92 93 94 /* ---------------------------------------------------------------------------- 95 -- Core clock 96 ---------------------------------------------------------------------------- */ 97 98 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 99 100 /* ---------------------------------------------------------------------------- 101 -- SystemInit() 102 ---------------------------------------------------------------------------- */ 103 SystemInit(void)104void SystemInit (void) { 105 106 #if defined(__MCUXPRESSO) 107 extern void(*const g_pfnVectors[]) (void); 108 SCB->VTOR = (uint32_t) &g_pfnVectors; 109 #else 110 extern void *__Vectors; 111 SCB->VTOR = (uint32_t) &__Vectors; 112 #endif 113 SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 114 SystemInitHook(); 115 } 116 117 /* ---------------------------------------------------------------------------- 118 -- SystemCoreClockUpdate() 119 ---------------------------------------------------------------------------- */ 120 SystemCoreClockUpdate(void)121void SystemCoreClockUpdate (void) { 122 uint32_t wdt_osc = 0U; 123 uint32_t irc_clk = 12000000U; 124 125 switch ((SYSCON->WDTOSCCTRL >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) & 0x0FU) { 126 case 0U: wdt_osc = 0U; break; 127 case 1U: wdt_osc = 600000U; break; 128 case 2U: wdt_osc = 1050000U; break; 129 case 3U: wdt_osc = 1400000U; break; 130 case 4U: wdt_osc = 1750000U; break; 131 case 5U: wdt_osc = 2100000U; break; 132 case 6U: wdt_osc = 2400000U; break; 133 case 7U: wdt_osc = 2700000U; break; 134 case 8U: wdt_osc = 3000000U; break; 135 case 9U: wdt_osc = 3250000U; break; 136 case 10U: wdt_osc = 3500000U; break; 137 case 11U: wdt_osc = 3750000U; break; 138 case 12U: wdt_osc = 4000000U; break; 139 case 13U: wdt_osc = 4200000U; break; 140 case 14U: wdt_osc = 4400000U; break; 141 case 15U: wdt_osc = 4600000U; break; 142 default: wdt_osc = 0U; break; 143 } 144 wdt_osc /= (((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U); 145 146 switch (SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) 147 { 148 case 0U: /* IRC */ 149 SystemCoreClock = irc_clk; 150 break; 151 case 1U: /* System PLL input */ 152 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) { 153 case 0U: /* IRC */ 154 SystemCoreClock = irc_clk; 155 break; 156 case 1U: /* System oscillator */ 157 SystemCoreClock = CLK_OSC_IN; 158 break; 159 case 3U: /* CLKIN */ 160 SystemCoreClock = EXT_CLK_IN; 161 break; 162 default: 163 SystemCoreClock = irc_clk; /* default is IRC */ 164 break; 165 } 166 break; 167 case 2U: /* watchdog oscillator */ 168 SystemCoreClock = wdt_osc; 169 break; 170 case 3U: /* System PLL */ 171 SystemCoreClock = Clock_GetPLLFreq((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK), CLOCK_GetSystemPLLInClkRate()); 172 break; 173 default: 174 SystemCoreClock = 0U; 175 break; 176 } 177 178 SystemCoreClock /= SYSCON->SYSAHBCLKDIV; 179 } 180 181 /* ---------------------------------------------------------------------------- 182 -- SystemInitHook() 183 ---------------------------------------------------------------------------- */ 184 SystemInitHook(void)185__attribute__ ((weak)) void SystemInitHook (void) { 186 /* Void implementation of the weak function. */ 187 } 188
