1 /* 2 * Copyright 2017, NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_RESET_H_ 9 #define _FSL_RESET_H_ 10 11 #include <assert.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <string.h> 15 #include "fsl_device_registers.h" 16 17 /*! 18 * @addtogroup reset 19 * @{ 20 */ 21 22 /******************************************************************************* 23 * Definitions 24 ******************************************************************************/ 25 26 /*! @name Driver version */ 27 /*@{*/ 28 /*! @brief reset driver version 2.0.1. */ 29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 30 /*@}*/ 31 32 /*! 33 * @brief Enumeration for peripheral reset control bits 34 * 35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers 36 */ 37 typedef enum _SYSCON_RSTn 38 { 39 kFLASH_RST_N_SHIFT_RSTn = 0 | 4U, /**< Flash controller reset control */ 40 kI2C0_RST_N_SHIFT_RSTn = 0 | 5U, /**< I2C0 reset control */ 41 kGPIO0_RST_N_SHIFT_RSTn = 0 | 6U, /**< GPIO0 reset control */ 42 kSWM_RST_N_SHIFT_RSTn = 0 | 7U, /**< SWM reset control */ 43 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */ 44 kMRT_RST_N_SHIFT_RSTn = 0 | 10U, /**< Multi-rate timer(MRT) reset control */ 45 kSPI0_RST_N_SHIFT_RSTn = 0 | 11U, /**< SPI0 reset control. */ 46 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */ 47 kUART0_RST_N_SHIFT_RSTn = 0 | 14U, /**< UART0 reset control */ 48 kUART1_RST_N_SHIFT_RSTn = 0 | 15U, /**< UART1 reset control */ 49 kIOCON_RST_N_SHIFT_RSTn = 0 | 18U, /**< IOCON reset control */ 50 kACMP_RST_N_SHIFT_RSTn = 0 | 19U, /**< Analog comparator reset control */ 51 kI2C1_RST_N_SHIFT_RSTn = 0 | 21U, /**< I2C1 reset control */ 52 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */ 53 kCTIMER0_RST_N_SHIFT_RSTn = 0 | 25U, /**< CTIMER0 reset control */ 54 kDAC0_RST_N_SHIFT_RSTn = 0 | 27U, /**< DAC0 reset control */ 55 kGPIOINT_RST_N_SHIFT_RSTn = 0 | 28U, /**< GPIOINT reset control */ 56 57 kCAPT_RST_N_SHIFT_RSTn = 65536 | 0U, /**< Capacitive Touch reset control */ 58 kFRG0_RST_N_SHIFT_RSTn = 65536 | 3U, /**< Fractional baud rate generator 0 reset control */ 59 kPLU_RST_N_SHIFT_RSTn = 65536 | 5U, /**< PLU reset control */ 60 } SYSCON_RSTn_t; 61 62 /** Array initializers with peripheral reset bits **/ 63 #define FLASH_RSTS_N \ 64 { \ 65 kFLASH_RST_N_SHIFT_RSTn \ 66 } /* Reset bits for Flash peripheral */ 67 #define I2C_RSTS_N \ 68 { \ 69 kI2C0_RST_N_SHIFT_RSTn, kI2C1_RST_N_SHIFT_RSTn \ 70 } /* Reset bits for I2C peripheral */ 71 #define GPIO_RSTS_N \ 72 { \ 73 kGPIO0_RST_N_SHIFT_RSTn \ 74 } /* Reset bits for GPIO peripheral */ 75 #define SWM_RSTS_N \ 76 { \ 77 kSWM_RST_N_SHIFT_RSTn \ 78 } /* Reset bits for SWM peripheral */ 79 #define WKT_RSTS_N \ 80 { \ 81 kWKT_RST_N_SHIFT_RSTn \ 82 } /* Reset bits for WKT peripheral */ 83 #define MRT_RSTS_N \ 84 { \ 85 kMRT_RST_N_SHIFT_RSTn \ 86 } /* Reset bits for MRT peripheral */ 87 #define SPI_RSTS_N \ 88 { \ 89 kSPI0_RST_N_SHIFT_RSTn \ 90 } /* Reset bits for SPI peripheral */ 91 #define CRC_RSTS_N \ 92 { \ 93 kCRC_RST_SHIFT_RSTn \ 94 } /* Reset bits for CRC peripheral */ 95 #define UART_RSTS_N \ 96 { \ 97 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn \ 98 } /* Reset bits for UART peripheral */ 99 #define IOCON_RSTS_N \ 100 { \ 101 kIOCON_RST_N_SHIFT_RSTn \ 102 } /* Reset bits for IOCON peripheral */ 103 #define ACMP_RSTS_N \ 104 { \ 105 kACMP_RST_N_SHIFT_RSTn \ 106 } /* Reset bits for ACMP peripheral */ 107 #define ADC_RSTS_N \ 108 { \ 109 kADC_RST_N_SHIFT_RSTn \ 110 } /* Reset bits for ADC peripheral */ 111 #define CTIMER_RSTS_N \ 112 { \ 113 kCTIMER0_RST_N_SHIFT_RSTn \ 114 } /* Reset bits for CTIMER peripheral */ 115 #define DAC_RSTS_N \ 116 { \ 117 kDAC0_RST_N_SHIFT_RSTn \ 118 } /* Reset bits for DAC peripheral */ 119 #define GPIOINT_RSTS_N \ 120 { \ 121 kGPIOINT_RST_N_SHIFT_RSTn \ 122 } /* Reset bits for GPIOINT peripheral */ 123 #define CAPT_RSTS_N \ 124 { \ 125 kCAPT_RST_N_SHIFT_RSTn \ 126 } /* Reset bits for CAPT peripheral */ 127 #define FRG_RSTS_N \ 128 { \ 129 kFRG0_RST_N_SHIFT_RSTn \ 130 } /* Reset bits for FRG peripheral */ 131 #define PLU_RSTS_N \ 132 { \ 133 kPLU_RST_N_SHIFT_RSTn \ 134 } /* Reset bits for PLU peripheral */ 135 136 typedef SYSCON_RSTn_t reset_ip_name_t; 137 138 /******************************************************************************* 139 * API 140 ******************************************************************************/ 141 #if defined(__cplusplus) 142 extern "C" { 143 #endif 144 145 /*! 146 * @brief Reset peripheral module. 147 * 148 * Reset peripheral module. 149 * 150 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 151 * and reset bit position in the reset register. 152 */ 153 void RESET_PeripheralReset(reset_ip_name_t peripheral); 154 155 #if defined(__cplusplus) 156 } 157 #endif 158 159 /*! @} */ 160 161 #endif /* _FSL_RESET_H_ */ 162
