1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2018-01-09 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-01-09) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _LPC802_FEATURES_H_ 26 #define _LPC802_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ACOMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 32 /* @brief ADC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_ADC_COUNT (1) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief CTIMER availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CTIMER_COUNT (1) 38 /* @brief GPIO availability on the SoC. */ 39 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 40 /* @brief I2C availability on the SoC. */ 41 #define FSL_FEATURE_SOC_I2C_COUNT (1) 42 /* @brief IOCON availability on the SoC. */ 43 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 44 /* @brief MRT availability on the SoC. */ 45 #define FSL_FEATURE_SOC_MRT_COUNT (1) 46 /* @brief PINT availability on the SoC. */ 47 #define FSL_FEATURE_SOC_PINT_COUNT (1) 48 /* @brief PMU availability on the SoC. */ 49 #define FSL_FEATURE_SOC_PMU_COUNT (1) 50 /* @brief SPI availability on the SoC. */ 51 #define FSL_FEATURE_SOC_SPI_COUNT (1) 52 /* @brief SWM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_SWM_COUNT (1) 54 /* @brief SYSCON availability on the SoC. */ 55 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 56 /* @brief USART availability on the SoC. */ 57 #define FSL_FEATURE_SOC_USART_COUNT (2) 58 /* @brief WWDT availability on the SoC. */ 59 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 60 61 /* ACOMP module features */ 62 63 /* @brief Has INTENA bitfile in CTRL reigster. */ 64 #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1) 65 66 /* ADC module features */ 67 68 /* @brief Do not has input select (register INSEL). */ 69 #define FSL_FEATURE_ADC_HAS_NO_INSEL (1) 70 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 71 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) 72 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 73 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0) 74 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 75 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0) 76 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 77 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0) 78 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 79 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1) 80 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 81 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) 82 /* @brief Has startup register. */ 83 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (0) 84 /* @brief Has ADC Trim register */ 85 #define FSL_FEATURE_ADC_HAS_TRIM_REG (0) 86 /* @brief Has Calibration register. */ 87 #define FSL_FEATURE_ADC_HAS_CALIB_REG (0) 88 /* @brief Has no Calibration function. */ 89 #define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1) 90 91 /* CLOCK module features */ 92 93 /* @brief GPIOINT clock source. */ 94 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1) 95 96 /* CTIMER module features */ 97 98 /* @brief CTIMER has no capture channel. */ 99 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 100 /* @brief CTIMER has no capture 2 interrupt. */ 101 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 102 /* @brief CTIMER capture 3 interrupt. */ 103 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (0) 104 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 105 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 106 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 107 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (0) 108 /* @brief Writing a zero asserts the CTIMER reset. */ 109 #define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1) 110 /* @brief CTIMER Has register MSR */ 111 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 112 113 /* IOCON module features */ 114 115 /* No feature definitions */ 116 117 /* MRT module features */ 118 119 /* @brief number of channels. */ 120 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (2) 121 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 122 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 123 /* @brief Has no INUSE bitfile in STAT reigster. */ 124 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 125 /* @brief Writing a zero asserts the MRT reset. */ 126 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 127 128 /* NVIC module features */ 129 130 /* @brief Number of connected outputs. */ 131 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 132 133 /* PINT module features */ 134 135 /* @brief Number of connected outputs */ 136 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 137 138 /* SPI module features */ 139 140 /* @brief Has SPOL0 bitfile in CFG reigster. */ 141 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 142 /* @brief Has SPOL1 bitfile in CFG reigster. */ 143 #define FSL_FEATURE_SPI_HAS_SSEL1 (1) 144 /* @brief Has SPOL2 bitfile in CFG reigster. */ 145 #define FSL_FEATURE_SPI_HAS_SSEL2 (0) 146 /* @brief Has SPOL3 bitfile in CFG reigster. */ 147 #define FSL_FEATURE_SPI_HAS_SSEL3 (0) 148 149 /* SWM module features */ 150 151 /* @brief Has SWM PINENABLE0 ACMP I3. */ 152 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1) 153 /* @brief Has SWM PINENABLE0 ACMP I4. */ 154 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1) 155 /* @brief Has SWM PINENABLE0 ACMP I5. */ 156 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (0) 157 158 /* SYSCON module features */ 159 160 /* @brief Pointer to ROM IAP entry functions */ 161 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1) 162 /* @brief IAP Reinvoke ISP command parameter is pointer */ 163 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) 164 /* @brief Flash page size in bytes */ 165 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 166 /* @brief Flash sector size in bytes */ 167 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 168 /* @brief Flash size in bytes */ 169 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (16256) 170 /* @brief IAP has Flash read & write function */ 171 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 172 /* @brief Starter register discontinuous. */ 173 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 174 /* @brief Has PINTSEL register. */ 175 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 176 /* @brief Has fixed reference clock for flash controller */ 177 #define FSL_FEATURE_SYSCON_HAS_FLASH_REFERENCE_CLOCK (1) 178 179 /* USART module features */ 180 181 /* @brief Has OSR (register OSR). */ 182 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (1) 183 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 184 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1) 185 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 186 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (1) 187 188 /* WKT module features */ 189 190 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 191 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1) 192 193 /* WWDT module features */ 194 195 /* @brief Has LPOSC as clock source. */ 196 #define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (1) 197 /* @brief Has no RESET register. */ 198 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 199 200 #endif /* _LPC802_FEATURES_H_ */ 201 202
