1 /*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24 /* clang-format off */
25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26 !!GlobalInfo
27 product: Clocks v6.0
28 processor: LPC55S16
29 mcu_data: ksdk2_0
30 processor_version: 0.0.4
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32 /* clang-format on */
33
34 #include "fsl_power.h"
35 #include "fsl_clock.h"
36 #include "clock_config.h"
37
38 /*******************************************************************************
39 * Definitions
40 ******************************************************************************/
41
42 /*******************************************************************************
43 * Variables
44 ******************************************************************************/
45 /* System clock frequency. */
46 extern uint32_t SystemCoreClock;
47
48 /*******************************************************************************
49 ************************ BOARD_InitBootClocks function ************************
50 ******************************************************************************/
BOARD_InitBootClocks(void)51 void BOARD_InitBootClocks(void)
52 {
53 BOARD_BootClockPLL150M();
54 }
55
56 /*******************************************************************************
57 ******************** Configuration BOARD_BootClockFRO12M **********************
58 ******************************************************************************/
59 /* clang-format off */
60 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
61 !!Configuration
62 name: BOARD_BootClockFRO12M
63 outputs:
64 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
65 - {id: System_clock.outFreq, value: 12 MHz}
66 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
67 /* clang-format on */
68
69 /*******************************************************************************
70 * Variables for BOARD_BootClockFRO12M configuration
71 ******************************************************************************/
72 /*******************************************************************************
73 * Code for BOARD_BootClockFRO12M configuration
74 ******************************************************************************/
BOARD_BootClockFRO12M(void)75 void BOARD_BootClockFRO12M(void)
76 {
77 #ifndef SDK_SECONDARY_CORE
78 /*!< Set up the clock sources */
79 /*!< Configure FRO192M */
80 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
81 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
82 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
83
84 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
85 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
86
87 /*!< Set up dividers */
88 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
89
90 /*!< Set up clock selectors - Attach clocks to the peripheries */
91 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
92
93 /*< Set SystemCoreClock variable. */
94 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
95 #endif
96 }
97
98 /*******************************************************************************
99 ******************* Configuration BOARD_BootClockFROHF96M *********************
100 ******************************************************************************/
101 /* clang-format off */
102 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
103 !!Configuration
104 name: BOARD_BootClockFROHF96M
105 outputs:
106 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
107 - {id: System_clock.outFreq, value: 96 MHz}
108 settings:
109 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
110 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
111 sources:
112 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
113 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
114 /* clang-format on */
115
116 /*******************************************************************************
117 * Variables for BOARD_BootClockFROHF96M configuration
118 ******************************************************************************/
119 /*******************************************************************************
120 * Code for BOARD_BootClockFROHF96M configuration
121 ******************************************************************************/
BOARD_BootClockFROHF96M(void)122 void BOARD_BootClockFROHF96M(void)
123 {
124 #ifndef SDK_SECONDARY_CORE
125 /*!< Set up the clock sources */
126 /*!< Configure FRO192M */
127 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
128 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
129 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
130
131 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
132
133 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
134 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
135
136 /*!< Set up dividers */
137 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
138
139 /*!< Set up clock selectors - Attach clocks to the peripheries */
140 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
141
142 /*< Set SystemCoreClock variable. */
143 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
144 #endif
145 }
146
147 /*******************************************************************************
148 ******************** Configuration BOARD_BootClockPLL100M *********************
149 ******************************************************************************/
150 /* clang-format off */
151 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
152 !!Configuration
153 name: BOARD_BootClockPLL100M
154 outputs:
155 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
156 - {id: System_clock.outFreq, value: 100 MHz}
157 settings:
158 - {id: PLL0_Mode, value: Normal}
159 - {id: ENABLE_CLKIN_ENA, value: Enabled}
160 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
161 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
162 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
163 - {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
164 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
165 sources:
166 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
167 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
168 /* clang-format on */
169
170 /*******************************************************************************
171 * Variables for BOARD_BootClockPLL100M configuration
172 ******************************************************************************/
173 /*******************************************************************************
174 * Code for BOARD_BootClockPLL100M configuration
175 ******************************************************************************/
BOARD_BootClockPLL100M(void)176 void BOARD_BootClockPLL100M(void)
177 {
178 #ifndef SDK_SECONDARY_CORE
179 /*!< Set up the clock sources */
180 /*!< Configure FRO192M */
181 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
182 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
183 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
184
185 /*!< Configure XTAL32M */
186 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
187 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
188 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
189 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
190 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
191
192 POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
193 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
194
195 /*!< Set up PLL */
196 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
197 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
198 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
199 const pll_setup_t pll0Setup = {
200 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
201 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
202 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
203 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
204 .pllRate = 100000000U,
205 .flags = PLL_SETUPFLAG_WAITLOCK
206 };
207 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
208
209 /*!< Set up dividers */
210 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
211
212 /*!< Set up clock selectors - Attach clocks to the peripheries */
213 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
214
215 /*< Set SystemCoreClock variable. */
216 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
217 #endif
218 }
219
220 /*******************************************************************************
221 ******************** Configuration BOARD_BootClockPLL150M *********************
222 ******************************************************************************/
223 /* clang-format off */
224 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
225 !!Configuration
226 name: BOARD_BootClockPLL150M
227 called_from_default_init: true
228 outputs:
229 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
230 - {id: System_clock.outFreq, value: 150 MHz}
231 settings:
232 - {id: PLL0_Mode, value: Normal}
233 - {id: ENABLE_CLKIN_ENA, value: Enabled}
234 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
235 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
236 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
237 - {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
238 - {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
239 - {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
240 sources:
241 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
242 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
243 /* clang-format on */
244
245 /*******************************************************************************
246 * Variables for BOARD_BootClockPLL150M configuration
247 ******************************************************************************/
248 /*******************************************************************************
249 * Code for BOARD_BootClockPLL150M configuration
250 ******************************************************************************/
BOARD_BootClockPLL150M(void)251 void BOARD_BootClockPLL150M(void)
252 {
253 #ifndef SDK_SECONDARY_CORE
254 /*!< Set up the clock sources */
255 /*!< Configure FRO192M */
256 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
257 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
258 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
259
260 /*!< Configure XTAL32M */
261 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
262 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
263 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
264 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
265 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
266
267 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
268 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
269
270 /*!< Set up PLL */
271 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
272 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
273 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
274 const pll_setup_t pll0Setup = {
275 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
276 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
277 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
278 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
279 .pllRate = 150000000U,
280 .flags = PLL_SETUPFLAG_WAITLOCK
281 };
282 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
283
284 /*!< Set up dividers */
285 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
286
287 /*!< Set up clock selectors - Attach clocks to the peripheries */
288 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
289
290 /*< Set SystemCoreClock variable. */
291 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
292 #endif
293 }
294
295 /*******************************************************************************
296 ******************* Configuration BOARD_BootClockPLL1_150M ********************
297 ******************************************************************************/
298 /* clang-format off */
299 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
300 !!Configuration
301 name: BOARD_BootClockPLL1_150M
302 outputs:
303 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
304 - {id: System_clock.outFreq, value: 150 MHz}
305 settings:
306 - {id: PLL1_Mode, value: Normal}
307 - {id: ENABLE_CLKIN_ENA, value: Enabled}
308 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
309 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
310 - {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
311 - {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
312 - {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
313 - {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
314 sources:
315 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
316 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
317 /* clang-format on */
318
319 /*******************************************************************************
320 * Variables for BOARD_BootClockPLL1_150M configuration
321 ******************************************************************************/
322 /*******************************************************************************
323 * Code for BOARD_BootClockPLL1_150M configuration
324 ******************************************************************************/
BOARD_BootClockPLL1_150M(void)325 void BOARD_BootClockPLL1_150M(void)
326 {
327 #ifndef SDK_SECONDARY_CORE
328 /*!< Set up the clock sources */
329 /*!< Configure FRO192M */
330 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
331 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
332 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
333
334 /*!< Configure XTAL32M */
335 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
336 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
337 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
338 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
339 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
340
341 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
342 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
343
344 /*!< Set up PLL1 */
345 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
346 POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
347 const pll_setup_t pll1Setup = {
348 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
349 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
350 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
351 .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
352 .pllRate = 150000000U,
353 .flags = PLL_SETUPFLAG_WAITLOCK
354 };
355 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
356
357 /*!< Set up dividers */
358 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
359
360 /*!< Set up clock selectors - Attach clocks to the peripheries */
361 CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
362
363 /*< Set SystemCoreClock variable. */
364 SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
365 #endif
366 }
367
368