1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC54S018_FEATURES_H_ 33 #define _LPC54S018_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ADC availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ADC_COUNT (1) 39 /* @brief AES availability on the SoC. */ 40 #define FSL_FEATURE_SOC_AES_COUNT (1) 41 /* @brief ASYNC_SYSCON availability on the SoC. */ 42 #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) 43 /* @brief LPC_CAN availability on the SoC. */ 44 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) 45 /* @brief CRC availability on the SoC. */ 46 #define FSL_FEATURE_SOC_CRC_COUNT (1) 47 /* @brief CTIMER availability on the SoC. */ 48 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 49 /* @brief DMA availability on the SoC. */ 50 #define FSL_FEATURE_SOC_DMA_COUNT (1) 51 /* @brief DMIC availability on the SoC. */ 52 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 53 /* @brief EMC availability on the SoC. */ 54 #define FSL_FEATURE_SOC_EMC_COUNT (1) 55 /* @brief LPC_ENET availability on the SoC. */ 56 #define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) 57 /* @brief FLEXCOMM availability on the SoC. */ 58 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11) 59 /* @brief GINT availability on the SoC. */ 60 #define FSL_FEATURE_SOC_GINT_COUNT (2) 61 /* @brief GPIO availability on the SoC. */ 62 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 63 /* @brief I2C availability on the SoC. */ 64 #define FSL_FEATURE_SOC_I2C_COUNT (10) 65 /* @brief I2S availability on the SoC. */ 66 #define FSL_FEATURE_SOC_I2S_COUNT (2) 67 /* @brief INPUTMUX availability on the SoC. */ 68 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 69 /* @brief IOCON availability on the SoC. */ 70 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 71 /* @brief LCD availability on the SoC. */ 72 #define FSL_FEATURE_SOC_LCD_COUNT (1) 73 /* @brief MPU availability on the SoC. */ 74 #define FSL_FEATURE_SOC_MPU_COUNT (1) 75 /* @brief MRT availability on the SoC. */ 76 #define FSL_FEATURE_SOC_MRT_COUNT (1) 77 /* @brief PINT availability on the SoC. */ 78 #define FSL_FEATURE_SOC_PINT_COUNT (1) 79 /* @brief PUF availability on the SoC. */ 80 #define FSL_FEATURE_SOC_PUF_COUNT (1) 81 /* @brief RIT availability on the SoC. */ 82 #define FSL_FEATURE_SOC_RIT_COUNT (1) 83 /* @brief LPC_RNG availability on the SoC. */ 84 #define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) 85 /* @brief RTC availability on the SoC. */ 86 #define FSL_FEATURE_SOC_RTC_COUNT (1) 87 /* @brief SCT availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SCT_COUNT (1) 89 /* @brief SDIF availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 91 /* @brief SHA availability on the SoC. */ 92 #define FSL_FEATURE_SOC_SHA_COUNT (1) 93 /* @brief SMARTCARD availability on the SoC. */ 94 #define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) 95 /* @brief SPI availability on the SoC. */ 96 #define FSL_FEATURE_SOC_SPI_COUNT (11) 97 /* @brief SPIFI availability on the SoC. */ 98 #define FSL_FEATURE_SOC_SPIFI_COUNT (1) 99 /* @brief SYSCON availability on the SoC. */ 100 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 101 /* @brief USART availability on the SoC. */ 102 #define FSL_FEATURE_SOC_USART_COUNT (10) 103 /* @brief USB availability on the SoC. */ 104 #define FSL_FEATURE_SOC_USB_COUNT (1) 105 /* @brief USBFSH availability on the SoC. */ 106 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 107 /* @brief USBHSD availability on the SoC. */ 108 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 109 /* @brief USBHSH availability on the SoC. */ 110 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 111 /* @brief UTICK availability on the SoC. */ 112 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 113 /* @brief WWDT availability on the SoC. */ 114 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 115 116 /* ADC module features */ 117 118 /* @brief Do not has input select (register INSEL). */ 119 #define FSL_FEATURE_ADC_HAS_NO_INSEL (0) 120 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 121 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) 122 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 123 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) 124 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 125 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) 126 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 127 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) 128 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 129 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) 130 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 131 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) 132 /* @brief Has startup register. */ 133 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) 134 /* @brief Has ADC Trim register */ 135 #define FSL_FEATURE_ADC_HAS_TRIM_REG (0) 136 /* @brief Has Calibration register. */ 137 #define FSL_FEATURE_ADC_HAS_CALIB_REG (1) 138 139 /* CAN module features */ 140 141 /* @brief Support CANFD or not */ 142 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) 143 144 /* CTIMER module features */ 145 146 /* @brief CTIMER has no capture channel. */ 147 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 148 /* @brief CTIMER has no capture 2 interrupt. */ 149 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 150 /* @brief CTIMER capture 3 interrupt. */ 151 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 152 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 153 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 154 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 155 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 156 /* @brief CTIMER Has register MSR */ 157 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 158 159 /* DMA module features */ 160 161 /* @brief Number of channels */ 162 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) 163 /* @brief Align size of DMA descriptor */ 164 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 165 /* @brief DMA head link descriptor table align size */ 166 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 167 168 /* FLEXCOMM module features */ 169 170 /* @brief FLEXCOMM0 USART INDEX 0 */ 171 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 172 /* @brief FLEXCOMM0 SPI INDEX 0 */ 173 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 174 /* @brief FLEXCOMM0 I2C INDEX 0 */ 175 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 176 /* @brief FLEXCOMM1 USART INDEX 1 */ 177 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 178 /* @brief FLEXCOMM1 SPI INDEX 1 */ 179 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 180 /* @brief FLEXCOMM1 I2C INDEX 1 */ 181 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 182 /* @brief FLEXCOMM2 USART INDEX 2 */ 183 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 184 /* @brief FLEXCOMM2 SPI INDEX 2 */ 185 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 186 /* @brief FLEXCOMM2 I2C INDEX 2 */ 187 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 188 /* @brief FLEXCOMM3 USART INDEX 3 */ 189 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 190 /* @brief FLEXCOMM3 SPI INDEX 3 */ 191 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 192 /* @brief FLEXCOMM3 I2C INDEX 3 */ 193 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 194 /* @brief FLEXCOMM4 USART INDEX 4 */ 195 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 196 /* @brief FLEXCOMM4 SPI INDEX 4 */ 197 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 198 /* @brief FLEXCOMM4 I2C INDEX 4 */ 199 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 200 /* @brief FLEXCOMM5 USART INDEX 5 */ 201 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 202 /* @brief FLEXCOMM5 SPI INDEX 5 */ 203 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 204 /* @brief FLEXCOMM5 I2C INDEX 5 */ 205 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 206 /* @brief FLEXCOMM6 USART INDEX 6 */ 207 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 208 /* @brief FLEXCOMM6 SPI INDEX 6 */ 209 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 210 /* @brief FLEXCOMM6 I2C INDEX 6 */ 211 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 212 /* @brief FLEXCOMM7 I2S INDEX 0 */ 213 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) 214 /* @brief FLEXCOMM7 USART INDEX 7 */ 215 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 216 /* @brief FLEXCOMM7 SPI INDEX 7 */ 217 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 218 /* @brief FLEXCOMM7 I2C INDEX 7 */ 219 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 220 /* @brief FLEXCOMM7 I2S INDEX 1 */ 221 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) 222 /* @brief FLEXCOMM4 USART INDEX 8 */ 223 #define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8) 224 /* @brief FLEXCOMM4 SPI INDEX 8 */ 225 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 226 /* @brief FLEXCOMM4 I2C INDEX 8 */ 227 #define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8) 228 /* @brief FLEXCOMM5 USART INDEX 9 */ 229 #define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9) 230 /* @brief FLEXCOMM5 SPI INDEX 9 */ 231 #define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9) 232 /* @brief FLEXCOMM5 I2C INDEX 9 */ 233 #define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9) 234 /* @brief I2S has DMIC interconnection */ 235 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 236 (((x) == FLEXCOMM0) ? (0) : \ 237 (((x) == FLEXCOMM1) ? (0) : \ 238 (((x) == FLEXCOMM2) ? (0) : \ 239 (((x) == FLEXCOMM3) ? (0) : \ 240 (((x) == FLEXCOMM4) ? (0) : \ 241 (((x) == FLEXCOMM5) ? (0) : \ 242 (((x) == FLEXCOMM6) ? (0) : \ 243 (((x) == FLEXCOMM7) ? (1) : \ 244 (((x) == FLEXCOMM8) ? (0) : \ 245 (((x) == FLEXCOMM9) ? (0) : \ 246 (((x) == FLEXCOMM10) ? (0) : (-1)))))))))))) 247 248 /* I2S module features */ 249 250 /* @brief I2S support dual channel transfer. */ 251 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 252 /* @brief I2S has DMIC interconnection */ 253 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 254 255 /* IOCON module features */ 256 257 /* @brief Func bit field width */ 258 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 259 260 /* MRT module features */ 261 262 /* @brief number of channels. */ 263 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 264 265 /* interrupt module features */ 266 267 /* @brief Lowest interrupt request number. */ 268 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 269 /* @brief Highest interrupt request number. */ 270 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) 271 272 /* PINT module features */ 273 274 /* @brief Number of connected outputs */ 275 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 276 277 /* PUF module features */ 278 279 /* No feature definitions */ 280 281 /* RTC module features */ 282 283 /* @brief RTC has no reset control */ 284 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 285 286 /* SCT module features */ 287 288 /* @brief Number of events */ 289 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 290 /* @brief Number of states */ 291 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) 292 /* @brief Number of match capture */ 293 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 294 /* @brief Number of outputs */ 295 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 296 297 /* SDIF module features */ 298 299 /* @brief FIFO depth, every location is a WORD */ 300 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 301 /* @brief Max DMA buffer size */ 302 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 303 /* @brief Max source clock in HZ */ 304 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 305 306 /* SHA module features */ 307 308 /* @brief Has dedicated DMA controller. */ 309 #define FSL_FEATURE_SHA_HAS_MEMADDR_DMA (1) 310 311 /* SPI module features */ 312 313 /* @brief SSEL pin count. */ 314 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 315 316 /* SPIFI module features */ 317 318 /* @brief SPIFI start address */ 319 #define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) 320 /* @brief SPIFI end address */ 321 #define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) 322 323 /* SYSCON module features */ 324 325 /* @brief Pointer to ROM IAP entry functions */ 326 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) 327 /* @brief IAP Reinvoke ISP command parameter is pointer */ 328 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (1) 329 /* @brief RIT has no reset control */ 330 #define FSL_FEATURE_RIT_HAS_NO_RESET (1) 331 332 /* SysTick module features */ 333 334 /* @brief Systick has external reference clock. */ 335 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 336 /* @brief Systick external reference clock is core clock divided by this value. */ 337 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 338 339 /* USB module features */ 340 341 /* @brief Size of the USB dedicated RAM */ 342 #define FSL_FEATURE_USB_USB_RAM (0x00002000) 343 /* @brief Base address of the USB dedicated RAM */ 344 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 345 /* @brief USB version */ 346 #define FSL_FEATURE_USB_VERSION (200) 347 /* @brief Number of the endpoint in USB FS */ 348 #define FSL_FEATURE_USB_EP_NUM (5) 349 350 /* USBFSH module features */ 351 352 /* @brief Size of the USB dedicated RAM */ 353 #define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) 354 /* @brief Base address of the USB dedicated RAM */ 355 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 356 /* @brief USBFSH version */ 357 #define FSL_FEATURE_USBFSH_VERSION (200) 358 359 /* USBHSD module features */ 360 361 /* @brief Size of the USB dedicated RAM */ 362 #define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) 363 /* @brief Base address of the USB dedicated RAM */ 364 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 365 /* @brief USBHSD version */ 366 #define FSL_FEATURE_USBHSD_VERSION (300) 367 /* @brief Number of the endpoint in USB HS */ 368 #define FSL_FEATURE_USBHSD_EP_NUM (6) 369 370 /* USBHSH module features */ 371 372 /* @brief Size of the USB dedicated RAM */ 373 #define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) 374 /* @brief Base address of the USB dedicated RAM */ 375 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 376 /* @brief USBHSH version */ 377 #define FSL_FEATURE_USBHSH_VERSION (300) 378 379 /* WWDT module features */ 380 381 /* @brief Has no RESET register. */ 382 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 383 384 #endif /* _LPC54S018_FEATURES_H_ */ 385 386
