1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, UART0-UART9. */ 14 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 15 * instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 #define RTE_USART3 0 23 #define RTE_USART3_DMA_EN 0 24 #define RTE_USART4 0 25 #define RTE_USART4_DMA_EN 0 26 #define RTE_USART5 0 27 #define RTE_USART5_DMA_EN 0 28 #define RTE_USART6 0 29 #define RTE_USART6_DMA_EN 0 30 #define RTE_USART7 0 31 #define RTE_USART7_DMA_EN 0 32 #define RTE_USART8 0 33 #define RTE_USART8_DMA_EN 0 34 #define RTE_USART9 0 35 #define RTE_USART9_DMA_EN 0 36 37 /* USART configuration. */ 38 #define USART_RX_BUFFER_LEN 64 39 #define USART0_RX_BUFFER_ENABLE 0 40 #define USART1_RX_BUFFER_ENABLE 0 41 #define USART2_RX_BUFFER_ENABLE 0 42 #define USART3_RX_BUFFER_ENABLE 0 43 #define USART4_RX_BUFFER_ENABLE 0 44 #define USART5_RX_BUFFER_ENABLE 0 45 #define USART6_RX_BUFFER_ENABLE 0 46 #define USART7_RX_BUFFER_ENABLE 0 47 #define USART8_RX_BUFFER_ENABLE 0 48 #define USART9_RX_BUFFER_ENABLE 0 49 50 #define RTE_USART0_PIN_INIT USART0_InitPins 51 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 52 #define RTE_USART0_DMA_TX_CH 1 53 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 54 #define RTE_USART0_DMA_RX_CH 0 55 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 56 57 #define RTE_USART1_PIN_INIT USART1_InitPins 58 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 59 #define RTE_USART1_DMA_TX_CH 3 60 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 61 #define RTE_USART1_DMA_RX_CH 2 62 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 63 64 #define RTE_USART2_PIN_INIT USART2_InitPins 65 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 66 #define RTE_USART2_DMA_TX_CH 5 67 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 68 #define RTE_USART2_DMA_RX_CH 4 69 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 70 71 #define RTE_USART3_PIN_INIT USART3_InitPins 72 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 73 #define RTE_USART3_DMA_TX_CH 7 74 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 75 #define RTE_USART3_DMA_RX_CH 6 76 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 77 78 #define RTE_USART4_PIN_INIT USART4_InitPins 79 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 80 #define RTE_USART4_DMA_TX_CH 9 81 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 82 #define RTE_USART4_DMA_RX_CH 8 83 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 84 85 #define RTE_USART5_PIN_INIT USART5_InitPins 86 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 87 #define RTE_USART5_DMA_TX_CH 11 88 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 89 #define RTE_USART5_DMA_RX_CH 10 90 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 91 92 #define RTE_USART6_PIN_INIT USART6_InitPins 93 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 94 #define RTE_USART6_DMA_TX_CH 13 95 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 96 #define RTE_USART6_DMA_RX_CH 12 97 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 98 99 #define RTE_USART7_PIN_INIT USART7_InitPins 100 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 101 #define RTE_USART7_DMA_TX_CH 15 102 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 103 #define RTE_USART7_DMA_RX_CH 14 104 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 105 106 #define RTE_USART8_PIN_INIT USART8_InitPins 107 #define RTE_USART8_PIN_DEINIT USART8_DeinitPins 108 #define RTE_USART8_DMA_TX_CH 17 109 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 110 #define RTE_USART8_DMA_RX_CH 16 111 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 112 113 #define RTE_USART9_PIN_INIT USART9_InitPins 114 #define RTE_USART9_PIN_DEINIT USART9_DeinitPins 115 #define RTE_USART9_DMA_TX_CH 19 116 #define RTE_USART9_DMA_TX_DMA_BASE DMA0 117 #define RTE_USART9_DMA_RX_CH 18 118 #define RTE_USART9_DMA_RX_DMA_BASE DMA0 119 120 /* I2C Select, I2C0 -I2C9*/ 121 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 122 */ 123 #define RTE_I2C0 0 124 #define RTE_I2C0_DMA_EN 0 125 #define RTE_I2C1 0 126 #define RTE_I2C1_DMA_EN 0 127 #define RTE_I2C2 0 128 #define RTE_I2C2_DMA_EN 0 129 #define RTE_I2C3 0 130 #define RTE_I2C3_DMA_EN 0 131 #define RTE_I2C4 0 132 #define RTE_I2C4_DMA_EN 0 133 #define RTE_I2C5 0 134 #define RTE_I2C5_DMA_EN 0 135 #define RTE_I2C6 0 136 #define RTE_I2C6_DMA_EN 0 137 #define RTE_I2C7 0 138 #define RTE_I2C7_DMA_EN 0 139 #define RTE_I2C8 0 140 #define RTE_I2C8_DMA_EN 0 141 #define RTE_I2C9 0 142 #define RTE_I2C9_DMA_EN 0 143 144 /*I2C configuration*/ 145 #define RTE_I2C0_Master_DMA_BASE DMA0 146 #define RTE_I2C0_Master_DMA_CH 1 147 148 #define RTE_I2C1_Master_DMA_BASE DMA0 149 #define RTE_I2C1_Master_DMA_CH 3 150 151 #define RTE_I2C2_Master_DMA_BASE DMA0 152 #define RTE_I2C2_Master_DMA_CH 5 153 154 #define RTE_I2C3_Master_DMA_BASE DMA0 155 #define RTE_I2C3_Master_DMA_CH 7 156 157 #define RTE_I2C4_Master_DMA_BASE DMA0 158 #define RTE_I2C4_Master_DMA_CH 9 159 160 #define RTE_I2C5_Master_DMA_BASE DMA0 161 #define RTE_I2C5_Master_DMA_CH 11 162 163 #define RTE_I2C6_Master_DMA_BASE DMA0 164 #define RTE_I2C6_Master_DMA_CH 13 165 166 #define RTE_I2C7_Master_DMA_BASE DMA0 167 #define RTE_I2C7_Master_DMA_CH 15 168 169 #define RTE_I2C8_Master_DMA_BASE DMA0 170 #define RTE_I2C8_Master_DMA_CH 17 171 172 #define RTE_I2C9_Master_DMA_BASE DMA0 173 #define RTE_I2C9_Master_DMA_CH 19 174 175 /* SPI select, SPI0 - SPI9.*/ 176 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 177 */ 178 #define RTE_SPI0 0 179 #define RTE_SPI0_DMA_EN 0 180 #define RTE_SPI1 0 181 #define RTE_SPI1_DMA_EN 0 182 #define RTE_SPI2 0 183 #define RTE_SPI2_DMA_EN 0 184 #define RTE_SPI3 0 185 #define RTE_SPI3_DMA_EN 0 186 #define RTE_SPI4 0 187 #define RTE_SPI4_DMA_EN 0 188 #define RTE_SPI5 0 189 #define RTE_SPI5_DMA_EN 0 190 #define RTE_SPI6 0 191 #define RTE_SPI6_DMA_EN 0 192 #define RTE_SPI7 0 193 #define RTE_SPI7_DMA_EN 0 194 #define RTE_SPI8 0 195 #define RTE_SPI8_DMA_EN 0 196 #define RTE_SPI9 0 197 #define RTE_SPI9_DMA_EN 0 198 199 /* SPI configuration. */ 200 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 201 #define RTE_SPI0_PIN_INIT SPI0_InitPins 202 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 203 #define RTE_SPI0_DMA_TX_CH 1 204 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 205 #define RTE_SPI0_DMA_RX_CH 0 206 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 207 208 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 209 #define RTE_SPI1_PIN_INIT SPI1_InitPins 210 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 211 #define RTE_SPI1_DMA_TX_CH 3 212 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 213 #define RTE_SPI1_DMA_RX_CH 2 214 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 215 216 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 217 #define RTE_SPI2_PIN_INIT SPI2_InitPins 218 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 219 #define RTE_SPI2_DMA_TX_CH 5 220 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 221 #define RTE_SPI2_DMA_RX_CH 4 222 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 223 224 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 225 #define RTE_SPI3_PIN_INIT SPI3_InitPins 226 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 227 #define RTE_SPI3_DMA_TX_CH 7 228 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 229 #define RTE_SPI3_DMA_RX_CH 6 230 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 231 232 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 233 #define RTE_SPI4_PIN_INIT SPI4_InitPins 234 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 235 #define RTE_SPI4_DMA_TX_CH 9 236 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 237 #define RTE_SPI4_DMA_RX_CH 8 238 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 239 240 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 241 #define RTE_SPI5_PIN_INIT SPI5_InitPins 242 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 243 #define RTE_SPI5_DMA_TX_CH 11 244 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 245 #define RTE_SPI5_DMA_RX_CH 10 246 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 247 248 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 249 #define RTE_SPI6_PIN_INIT SPI6_InitPins 250 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 251 #define RTE_SPI6_DMA_TX_CH 13 252 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 253 #define RTE_SPI6_DMA_RX_CH 12 254 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 255 256 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 257 #define RTE_SPI7_PIN_INIT SPI7_InitPins 258 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 259 #define RTE_SPI7_DMA_TX_CH 15 260 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 261 #define RTE_SPI7_DMA_RX_CH 14 262 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 263 264 #define RTE_SPI8_SSEL_NUM kSPI_Ssel0 265 #define RTE_SPI8_PIN_INIT SPI8_InitPins 266 #define RTE_SPI8_PIN_DEINIT SPI8_DeinitPins 267 #define RTE_SPI8_DMA_TX_CH 17 268 #define RTE_SPI8_DMA_TX_DMA_BASE DMA0 269 #define RTE_SPI8_DMA_RX_CH 16 270 #define RTE_SPI8_DMA_RX_DMA_BASE DMA0 271 272 #define RTE_SPI9_SSEL_NUM kSPI_Ssel0 273 #define RTE_SPI9_PIN_INIT SPI9_InitPins 274 #define RTE_SPI9_PIN_DEINIT SPI9_DeinitPins 275 #define RTE_SPI9_DMA_TX_CH 23 276 #define RTE_SPI9_DMA_TX_DMA_BASE DMA0 277 #define RTE_SPI9_DMA_RX_CH 22 278 #define RTE_SPI9_DMA_RX_DMA_BASE DMA0 279 280 #endif /* _RTE_DEVICE_H */ 281
