1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, 2021 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9 #ifndef _FSL_POWER_H_
10 #define _FSL_POWER_H_
11
12 #include "fsl_common.h"
13
14 /*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17
18 /*!
19 * @addtogroup power
20 * @{
21 */
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief power driver version 2.1.0. */
26 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
27 /*@}*/
28
29 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
30 #define PDRCFG0 0x0U
31 #define PDRCFG1 0x1U
32
33 typedef enum pd_bits
34 {
35 kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
36 kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
37 kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
38 kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
39 kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
40 kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
41 kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
42 kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
43 kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
44 kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
45 kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
46 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
47 kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
48 kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
49 kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
50 kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
51 kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
52 kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
53 kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
54 kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
55 kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
56 kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
57 kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
58 kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
59
60 kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
61 kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
62 kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
63 kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
64 kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
65 kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
66
67 /*
68 This enum member has no practical meaning,it is used to avoid MISRA issue,
69 user should not trying to use it.
70 */
71 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
72 } pd_bit_t;
73
74 /* Power mode configuration API parameter */
75 typedef enum _power_mode_config
76 {
77 kPmu_Sleep = 0U,
78 kPmu_Deep_Sleep = 1U,
79 kPmu_Deep_PowerDown = 2U,
80 } power_mode_cfg_t;
81
82 /*!
83 * @brief The enumeration of BOD status flags.
84 */
85 typedef enum _power_bod_status
86 {
87 kBod_ResetStatusFlag = SYSCON_BODCTRL_BODRSTSTAT_MASK, /*!< BOD reset has occurred. */
88 kBod_InterruptStatusFlag = SYSCON_BODCTRL_BODINTSTAT_MASK, /*!< BOD interrupt has occurred */
89 } power_bod_status_t;
90
91 /*!
92 * @brief The enumeration of BOD reset level.
93 */
94 typedef enum _power_bod_reset_level
95 {
96 kBod_ResetLevel0 = 0U, /*!< Reset Level0: 1.5V. */
97 kBod_ResetLevel1, /*!< Reset Level0: 1.85V. */
98 kBod_ResetLevel2, /*!< Reset Level0: 2.0V. */
99 kBod_ResetLevel3, /*!< Reset Level0: 2.3V. */
100 } power_bod_reset_level_t;
101
102 /*!
103 * @brief The enumeration of BOD interrupt level.
104 */
105 typedef enum _power_bod_interrupt_level
106 {
107 kBod_InterruptLevel0 = 0U, /*!< Interrupt level: 2.05V. */
108 kBod_InterruptLevel1, /*!< Interrupt level: 2.45V. */
109 kBod_InterruptLevel2, /*!< Interrupt level: 2.75V. */
110 kBod_InterruptLevel3, /*!< Interrupt level: 3.05V. */
111 } power_bod_interrupt_level_t;
112
113 /*!
114 * @brief The configuration of power bod, including reset level, interrupt level, and so on.
115 */
116 typedef struct _power_bod_config
117 {
118 bool enableReset; /*!< Enable/disable BOD reset function. */
119 power_bod_reset_level_t resetLevel; /*!< BOD reset level, please refer to @ref power_bod_reset_level_t. */
120 bool enableInterrupt; /*!< Enable/disable BOD interrupt function. */
121 power_bod_interrupt_level_t
122 interruptLevel; /*!< BOD interrupt level, please refer to @ref power_bod_interrupt_level_t. */
123 } power_bod_config_t;
124
125 /*******************************************************************************
126 * API
127 ******************************************************************************/
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /*!
134 * @name Power Configuration
135 * @{
136 */
137
138 /*!
139 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
140 *
141 * @param en peripheral for which to enable the PDRUNCFG bit
142 * @return none
143 */
POWER_EnablePD(pd_bit_t en)144 static inline void POWER_EnablePD(pd_bit_t en)
145 {
146 /* PDRUNCFGSET */
147 SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
148 }
149
150 /*!
151 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
152 *
153 * @param en peripheral for which to disable the PDRUNCFG bit
154 * @return none
155 */
POWER_DisablePD(pd_bit_t en)156 static inline void POWER_DisablePD(pd_bit_t en)
157 {
158 /* PDRUNCFGCLR */
159 SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
160 }
161
162 /*!
163 * @brief API to enable deep sleep bit in the ARM Core.
164 *
165 * @return none
166 */
POWER_EnableDeepSleep(void)167 static inline void POWER_EnableDeepSleep(void)
168 {
169 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
170 }
171
172 /*!
173 * @brief API to disable deep sleep bit in the ARM Core.
174 *
175 * @return none
176 */
POWER_DisableDeepSleep(void)177 static inline void POWER_DisableDeepSleep(void)
178 {
179 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
180 }
181
182 /*!
183 * @brief API to power down flash controller.
184 *
185 * @return none
186 */
POWER_PowerDownFlash(void)187 static inline void POWER_PowerDownFlash(void)
188 {
189 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
190 /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
191 CLOCK_DisableClock(kCLOCK_Flash);
192
193 /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
194 CLOCK_DisableClock(kCLOCK_Fmc);
195 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
196 }
197
198 /*!
199 * @brief API to power up flash controller.
200 *
201 * @return none
202 */
POWER_PowerUpFlash(void)203 static inline void POWER_PowerUpFlash(void)
204 {
205 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
206 /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
207 CLOCK_EnableClock(kCLOCK_Fmc);
208 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
209 }
210
211 /*!
212 * @brief Power Library API to power the PLLs.
213 *
214 * @return none
215 */
216 void POWER_SetPLL(void);
217
218 /*!
219 * @brief Power Library API to power the USB PHY.
220 *
221 * @return none
222 */
223 void POWER_SetUsbPhy(void);
224
225 /*!
226 * @brief Power Library API to enter different power mode.
227 *
228 * @param mode Power mode configuration
229 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
230 * during power mode selected.
231 * @return none
232 */
233 void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
234
235 /*!
236 * @brief Power Library API to enter sleep mode.
237 *
238 * @return none
239 */
240 void POWER_EnterSleep(void);
241
242 /*!
243 * @brief Power Library API to enter deep sleep mode.
244 *
245 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
246 * powered on during deep sleep
247 * @return none
248 */
249 void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
250
251 /*!
252 * @brief Power Library API to enter deep power down mode.
253 *
254 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
255 during deep power
256 * down mode, but this is has no effect as the voltages are cut off.
257
258 * @return none
259 */
260 void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
261
262 /*!
263 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
264 *
265 * @param freq - The desired frequency at which the part would like to operate,
266 * note that the voltage and flash wait states should be set before changing frequency
267 * @return none
268 */
269 void POWER_SetVoltageForFreq(uint32_t freq);
270
271 /*!
272 * @brief Power Library API to return the library version.
273 *
274 * @return version number of the power library
275 */
276 uint32_t POWER_GetLibVersion(void);
277
278 /*!
279 * @brief Initialize BOD, including enabling/disabling BOD interrupt, enabling/disabling BOD reset, setting BOD
280 * interrupt level, and reset level.
281 *
282 * @param bodConfig Pointer the the structure @ref power_bod_config_t.
283 */
284 void POWER_InitBod(const power_bod_config_t *bodConfig);
285
286 /*!
287 * @brief Get default BOD configuration.
288 *
289 * @code
290 * bodConfig->enableReset = true;
291 * bodConfig->resetLevel = kBod_ResetLevel0;
292 * bodConfig->enableInterrupt = false;
293 * bodConfig->interruptLevel = kBod_InterruptLevel0;
294 * @endcode
295 *
296 * @param bodConfig Pointer the the structure @ref power_bod_config_t.
297 */
298 void POWER_GetDefaultBodConfig(power_bod_config_t *bodConfig);
299
300 /*!
301 * @brief De-initialize BOD.
302 */
POWER_DeinitBod(void)303 static inline void POWER_DeinitBod(void)
304 {
305 SYSCON->BODCTRL &= ~(SYSCON_BODCTRL_BODRSTENA_MASK | SYSCON_BODCTRL_BODINTENA_MASK);
306 }
307
308 /*!
309 * @brief Get Bod status flags.
310 *
311 * @return uint32_t
312 */
POWER_GetBodStatusFlags(void)313 static inline uint32_t POWER_GetBodStatusFlags(void)
314 {
315 return (uint32_t)((SYSCON->BODCTRL) & (SYSCON_BODCTRL_BODRSTSTAT_MASK | SYSCON_BODCTRL_BODINTSTAT_MASK));
316 }
317
318 /*!
319 * @brief Clear Bod status flags.
320 *
321 * @param mask The mask of status flags to clear, should be the OR'ed value of @ref power_bod_status_t.
322 */
POWER_ClearBodStatusFlags(uint32_t mask)323 static inline void POWER_ClearBodStatusFlags(uint32_t mask)
324 {
325 SYSCON->BODCTRL = mask;
326 }
327
328 /*@}*/
329
330 #ifdef __cplusplus
331 }
332 #endif
333
334 /*!
335 * @}
336 */
337
338 #endif /* _FSL_POWER_H_ */
339
