1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016, NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _FSL_RESET_H_ 11 #define _FSL_RESET_H_ 12 13 #include <assert.h> 14 #include <stdbool.h> 15 #include <stdint.h> 16 #include <string.h> 17 #include "fsl_device_registers.h" 18 19 /*! 20 * @addtogroup reset 21 * @{ 22 */ 23 24 /******************************************************************************* 25 * Definitions 26 ******************************************************************************/ 27 28 /*! @name Driver version */ 29 /*@{*/ 30 /*! @brief reset driver version 2.0.1. */ 31 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 32 /*@}*/ 33 34 /*! 35 * @brief Enumeration for peripheral reset control bits 36 * 37 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers 38 */ 39 typedef enum _SYSCON_RSTn 40 { 41 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ 42 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ 43 kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ 44 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ 45 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ 46 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ 47 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ 48 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ 49 kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ 50 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ 51 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ 52 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ 53 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ 54 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ 55 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ 56 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ 57 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ 58 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ 59 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ 60 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ 61 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ 62 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ 63 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ 64 kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ 65 kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ 66 kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ 67 kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ 68 kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ 69 kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ 70 kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ 71 } SYSCON_RSTn_t; 72 73 /** Array initializers with peripheral reset bits **/ 74 #define ADC_RSTS \ 75 { \ 76 kADC0_RST_SHIFT_RSTn \ 77 } /* Reset bits for ADC peripheral */ 78 #define CRC_RSTS \ 79 { \ 80 kCRC_RST_SHIFT_RSTn \ 81 } /* Reset bits for CRC peripheral */ 82 #define DMA_RSTS_N \ 83 { \ 84 kDMA_RST_SHIFT_RSTn \ 85 } /* Reset bits for DMA peripheral */ 86 #define DMIC_RSTS \ 87 { \ 88 kDMIC_RST_SHIFT_RSTn \ 89 } /* Reset bits for ADC peripheral */ 90 #define FLEXCOMM_RSTS \ 91 { \ 92 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ 93 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ 94 } /* Reset bits for FLEXCOMM peripheral */ 95 #define GINT_RSTS \ 96 { \ 97 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ 98 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ 99 #define GPIO_RSTS_N \ 100 { \ 101 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ 102 } /* Reset bits for GPIO peripheral */ 103 #define INPUTMUX_RSTS \ 104 { \ 105 kMUX_RST_SHIFT_RSTn \ 106 } /* Reset bits for INPUTMUX peripheral */ 107 #define IOCON_RSTS \ 108 { \ 109 kIOCON_RST_SHIFT_RSTn \ 110 } /* Reset bits for IOCON peripheral */ 111 #define FLASH_RSTS \ 112 { \ 113 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ 114 } /* Reset bits for Flash peripheral */ 115 #define MRT_RSTS \ 116 { \ 117 kMRT_RST_SHIFT_RSTn \ 118 } /* Reset bits for MRT peripheral */ 119 #define PINT_RSTS \ 120 { \ 121 kPINT_RST_SHIFT_RSTn \ 122 } /* Reset bits for PINT peripheral */ 123 #define SCT_RSTS \ 124 { \ 125 kSCT0_RST_SHIFT_RSTn \ 126 } /* Reset bits for SCT peripheral */ 127 #define CTIMER_RSTS \ 128 { \ 129 kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ 130 kCT32B4_RST_SHIFT_RSTn \ 131 } /* Reset bits for TIMER peripheral */ 132 #define USB_RSTS \ 133 { \ 134 kUSB_RST_SHIFT_RSTn \ 135 } /* Reset bits for USB peripheral */ 136 #define UTICK_RSTS \ 137 { \ 138 kUTICK_RST_SHIFT_RSTn \ 139 } /* Reset bits for UTICK peripheral */ 140 #define WWDT_RSTS \ 141 { \ 142 kWWDT_RST_SHIFT_RSTn \ 143 } /* Reset bits for WWDT peripheral */ 144 145 typedef SYSCON_RSTn_t reset_ip_name_t; 146 147 /******************************************************************************* 148 * API 149 ******************************************************************************/ 150 #if defined(__cplusplus) 151 extern "C" { 152 #endif 153 154 /*! 155 * @brief Assert reset to peripheral. 156 * 157 * Asserts reset signal to specified peripheral module. 158 * 159 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register 160 * and reset bit position in the reset register. 161 */ 162 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 163 164 /*! 165 * @brief Clear reset to peripheral. 166 * 167 * Clears reset signal to specified peripheral module, allows it to operate. 168 * 169 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register 170 * and reset bit position in the reset register. 171 */ 172 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 173 174 /*! 175 * @brief Reset peripheral module. 176 * 177 * Reset peripheral module. 178 * 179 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 180 * and reset bit position in the reset register. 181 */ 182 void RESET_PeripheralReset(reset_ip_name_t peripheral); 183 184 /*! 185 * @brief Set slave core to reset state and hold. 186 */ 187 void RESET_SetSlaveCoreReset(void); 188 189 /*! 190 * @brief Release slave core from reset state. 191 */ 192 void RESET_ClearSlaveCoreReset(void); 193 194 /*! 195 * @brief Reset slave core with the boot entry. 196 */ 197 void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer); 198 199 #if defined(__cplusplus) 200 } 201 #endif 202 203 /*! @} */ 204 205 #endif /* _FSL_RESET_H_ */ 206
