1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <stdint.h> 10 #include "fsl_common.h" 11 #include "clock_config.h" 12 #include "board.h" 13 #include "fsl_debug_console.h" 14 15 #ifdef SDK_PRIMARY_CORE 16 /* Address of RAM, where the image for core1 should be copied */ 17 #define CORE1_BOOT_ADDRESS (void *)0x20010000 18 19 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) 20 extern uint32_t Image$$CORE1_REGION$$Base; 21 extern uint32_t Image$$CORE1_REGION$$Length; 22 #define CORE1_IMAGE_START &Image$$CORE1_REGION$$Base 23 #elif defined(__ICCARM__) 24 extern unsigned char core1_image_start[]; 25 #define CORE1_IMAGE_START core1_image_start 26 #endif 27 #endif 28 29 /******************************************************************************* 30 * Variables 31 ******************************************************************************/ 32 33 /* Clock rate on the CLKIN pin */ 34 const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; 35 36 /******************************************************************************* 37 * Code 38 ******************************************************************************/ 39 /* Initialize debug console. */ BOARD_InitDebugConsole(void)40status_t BOARD_InitDebugConsole(void) 41 { 42 #if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) 43 status_t result; 44 45 /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ 46 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); 47 48 RESET_PeripheralReset(BOARD_DEBUG_UART_RST); 49 result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM, 50 BOARD_DEBUG_UART_CLK_FREQ); 51 assert(kStatus_Success == result); 52 return result; 53 #else 54 return kStatus_Success; 55 #endif 56 } 57 58 #ifdef SDK_PRIMARY_CORE 59 /* Start the secondary core. */ BOARD_StartSecondaryCore(void)60void BOARD_StartSecondaryCore(void) 61 { 62 /* Calculate size of the secondary core image - not required on MCUXpresso. MCUXpresso copies the image to RAM during 63 * startup 64 * automatically */ 65 #if (defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__ICCARM__)) 66 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) 67 uint32_t core1_image_size = (uint32_t)&Image$$CORE1_REGION$$Length; 68 #elif defined(__ICCARM__) 69 #pragma section = "__sec_core" 70 uint32_t core1_image_size = (uint32_t)__section_end("__sec_core") - (uint32_t)&core1_image_start; 71 #endif 72 73 /* Copy core1 application from FLASH to RAM. Primary core code is executed from FLASH, Secondary from RAM 74 * for maximal effectivity.*/ 75 memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, core1_image_size); 76 #endif 77 /* Boot source for Core 1 from RAM */ 78 SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4)); 79 SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(*(uint32_t *)CORE1_BOOT_ADDRESS); 80 81 uint32_t temp = SYSCON->CPUCTRL; 82 temp |= 0xc0c48000U; 83 SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CM0RSTEN_MASK | SYSCON_CPUCTRL_CM0CLKEN_MASK; 84 SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) & (~SYSCON_CPUCTRL_CM0RSTEN_MASK); 85 } 86 #endif 87
