1 /*
2 ** ###################################################################
3 **     Processors:          LPC54016JBD100
4 **                          LPC54016JBD208
5 **                          LPC54016JET100
6 **                          LPC54016JET180
7 **
8 **     Compilers:           GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
14 **     Version:             rev. 1.2, 2017-06-08
15 **     Build:               b230321
16 **
17 **     Abstract:
18 **         Provides a system configuration function and a global variable that
19 **         contains the system frequency. It configures the device and initializes
20 **         the oscillator (PLL) that is part of the microcontroller device.
21 **
22 **     Copyright 2016 Freescale Semiconductor, Inc.
23 **     Copyright 2016-2023 NXP
24 **     All rights reserved.
25 **
26 **     SPDX-License-Identifier: BSD-3-Clause
27 **
28 **     http:                 www.nxp.com
29 **     mail:                 support@nxp.com
30 **
31 **     Revisions:
32 **     - rev. 1.0 (2016-08-12)
33 **         Initial version.
34 **     - rev. 1.1 (2016-11-25)
35 **         Update CANFD and Classic CAN register.
36 **         Add MAC TIMERSTAMP registers.
37 **     - rev. 1.2 (2017-06-08)
38 **         Remove RTC_CTRL_RTC_OSC_BYPASS.
39 **         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
40 **         Remove RESET and HALT from SYSCON_AHBCLKDIV.
41 **
42 ** ###################################################################
43 */
44 
45 /*!
46  * @file LPC54016
47  * @version 1.2
48  * @date 2017-06-08
49  * @brief Device specific configuration file for LPC54016 (implementation file)
50  *
51  * Provides a system configuration function and a global variable that contains
52  * the system frequency. It configures the device and initializes the oscillator
53  * (PLL) that is part of the microcontroller device.
54  */
55 
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58 
59 #define NVALMAX (0x100)
60 #define PVALMAX (0x20)
61 #define MVALMAX (0x8000)
62 #define PLL_MDEC_VAL_P (0)                                       /* MDEC is in bits  16:0 */
63 #define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
64 #define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
65 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
66 #define PLL_PDEC_VAL_P (0)                                       /* PDEC is in bits  6:0 */
67 #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
68 
69 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
70                                             48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
71 /* Get WATCH DOG Clk */
getWdtOscFreq(void)72 static uint32_t getWdtOscFreq(void)
73 {
74     uint8_t freq_sel, div_sel;
75     if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
76     {
77         return 0U;
78     }
79     else
80     {
81         div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
82         freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
83         return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
84     }
85 }
86 /* Find decoded N value for raw NDEC value */
pllDecodeN(uint32_t NDEC)87 static uint32_t pllDecodeN(uint32_t NDEC)
88 {
89     uint32_t n, x, i;
90 
91     /* Find NDec */
92     switch (NDEC)
93     {
94         case 0x3FF:
95             n = 0UL;
96             break;
97         case 0x302:
98             n = 1UL;
99             break;
100         case 0x202:
101             n = 2UL;
102             break;
103         default:
104             x = 0x080UL;
105             n = 0xFFFFFFFFUL;
106             for (i = NVALMAX; i >= 3UL; i--)
107             {
108                 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
109                 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
110                 {
111                     /* Decoded value of NDEC */
112                     n = i;
113                 }
114                 if (n != 0xFFFFFFFFUL)
115                 {
116                     break;
117                 }
118             }
119             break;
120     }
121     return n;
122 }
123 
124 /* Find decoded P value for raw PDEC value */
pllDecodeP(uint32_t PDEC)125 static uint32_t pllDecodeP(uint32_t PDEC)
126 {
127     uint32_t p, x, i;
128     /* Find PDec */
129     switch (PDEC)
130     {
131         case 0x7F:
132             p = 0UL;
133             break;
134         case 0x62:
135             p = 1UL;
136             break;
137         case 0x42:
138             p = 2UL;
139             break;
140         default:
141             x = 0x10UL;
142             p = 0xFFFFFFFFUL;
143             for (i = PVALMAX; i >= 3UL; i--)
144             {
145                 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
146                 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
147                 {
148                     /* Decoded value of PDEC */
149                     p = i;
150                 }
151                 if (p != 0xFFFFFFFFUL)
152                 {
153                     break;
154                 }
155             }
156             break;
157     }
158     return p;
159 }
160 
161 /* Find decoded M value for raw MDEC value */
pllDecodeM(uint32_t MDEC)162 static uint32_t pllDecodeM(uint32_t MDEC)
163 {
164     uint32_t m, i, x;
165 
166     /* Find MDec */
167     switch (MDEC)
168     {
169         case 0x1FFFF:
170             m = 0UL;
171             break;
172         case 0x18003:
173             m = 1UL;
174             break;
175         case 0x10003:
176             m = 2UL;
177             break;
178         default:
179             x = 0x04000UL;
180             m = 0xFFFFFFFFUL;
181             for (i = MVALMAX; i >= 3UL; i--)
182             {
183                 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
184                 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
185                 {
186                     /* Decoded value of MDEC */
187                     m = i;
188                 }
189                 if (m != 0xFFFFFFFFUL)
190                 {
191                     break;
192                 }
193             }
194             break;
195     }
196     return m;
197 }
198 
199 /* Get predivider (N) from PLL NDEC setting */
findPllPreDiv(uint32_t ctrlReg,uint32_t nDecReg)200 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
201 {
202     uint32_t preDiv = 1;
203 
204     /* Direct input is not used? */
205     if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
206     {
207         /* Decode NDEC value to get (N) pre divider */
208         preDiv = pllDecodeN(nDecReg & 0x3FFUL);
209         if (preDiv == 0UL)
210         {
211             preDiv = 1;
212         }
213     }
214     /* Adjusted by 1, directi is used to bypass */
215     return preDiv;
216 }
217 
218 /* Get postdivider (P) from PLL PDEC setting */
findPllPostDiv(uint32_t ctrlReg,uint32_t pDecReg)219 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
220 {
221     uint32_t postDiv = 1;
222 
223     /* Direct input is not used? */
224     if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
225     {
226         /* Decode PDEC value to get (P) post divider */
227         postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
228         if (postDiv == 0UL)
229         {
230             postDiv = 2;
231         }
232     }
233     /* Adjusted by 1, directo is used to bypass */
234     return postDiv;
235 }
236 
237 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
findPllMMult(uint32_t ctrlReg,uint32_t mDecReg)238 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
239 {
240     uint32_t mMult = 1;
241 
242     /* Decode MDEC value to get (M) multiplier */
243     mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
244     if (mMult == 0UL)
245     {
246         mMult = 1;
247     }
248     return mMult;
249 }
250 
251 
252 
253 /* ----------------------------------------------------------------------------
254    -- Core clock
255    ---------------------------------------------------------------------------- */
256 
257 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
258 
259 /* ----------------------------------------------------------------------------
260    -- SystemInit()
261    ---------------------------------------------------------------------------- */
262 
SystemInit(void)263 void SystemInit (void) {
264 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
265   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
266 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
267 
268 #if defined(__MCUXPRESSO)
269     extern void(*const g_pfnVectors[]) (void);
270     SCB->VTOR = (uint32_t) &g_pfnVectors;
271 #else
272     extern void *__Vectors;
273     SCB->VTOR = (uint32_t) &__Vectors;
274 #endif
275     SYSCON->ARMTRACECLKDIV = 0;
276 /* Optionally enable RAM banks that may be off by default at reset */
277 #if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
278     SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
279 
280 #endif
281     SYSCON->MAINCLKSELA = 0U;
282     SYSCON->MAINCLKSELB = 0U;
283   SystemInitHook();
284 }
285 
286 /* ----------------------------------------------------------------------------
287    -- SystemCoreClockUpdate()
288    ---------------------------------------------------------------------------- */
289 
SystemCoreClockUpdate(void)290 void SystemCoreClockUpdate (void) {
291 uint32_t clkRate = 0;
292     uint32_t prediv, postdiv;
293     uint64_t workRate;
294 
295     switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
296     {
297         case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
298             switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
299             {
300                 case 0x00: /* FRO 12 MHz (fro_12m) */
301                     clkRate = CLK_FRO_12MHZ;
302                     break;
303                 case 0x01: /* CLKIN Source (clk_in) */
304                     clkRate = CLK_CLK_IN;
305                     break;
306                 case 0x02: /* Watchdog oscillator (wdt_clk) */
307                     clkRate = getWdtOscFreq();
308                     break;
309                 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
310                     if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
311                     {
312                         clkRate = CLK_FRO_96MHZ;
313                     }
314                     else
315                     {
316                         clkRate = CLK_FRO_48MHZ;
317                     }
318                     break;
319             }
320             break;
321         case 0x02: /* System PLL clock (pll_clk)*/
322             switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
323             {
324                 case 0x00: /* FRO 12 MHz (fro_12m) */
325                     clkRate = CLK_FRO_12MHZ;
326                     break;
327                 case 0x01: /* CLKIN Source (clk_in) */
328                     clkRate = CLK_CLK_IN;
329                     break;
330                 case 0x02: /* Watchdog oscillator (wdt_clk) */
331                     clkRate = getWdtOscFreq();
332                     break;
333                 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
334                     clkRate = CLK_RTC_32K_CLK;
335                     break;
336                 default:
337                     clkRate = 0UL;
338                     break;
339             }
340             if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
341             {
342                 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
343                 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
344                 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
345                 /* Adjust input clock */
346                 clkRate = clkRate / prediv;
347 
348                 /* MDEC used for rate */
349                 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
350                 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
351                 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
352             }
353             break;
354         case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
355             clkRate = CLK_RTC_32K_CLK;
356             break;
357         default:
358             clkRate = 0UL;
359             break;
360     }
361     SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
362 }
363 
364 /* ----------------------------------------------------------------------------
365    -- SystemInitHook()
366    ---------------------------------------------------------------------------- */
367 
SystemInitHook(void)368 __attribute__ ((weak)) void SystemInitHook (void) {
369   /* Void implementation of the weak function. */
370 }
371