1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC54005_FEATURES_H_ 33 #define _LPC54005_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ADC availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ADC_COUNT (1) 39 /* @brief ASYNC_SYSCON availability on the SoC. */ 40 #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) 41 /* @brief CRC availability on the SoC. */ 42 #define FSL_FEATURE_SOC_CRC_COUNT (1) 43 /* @brief CTIMER availability on the SoC. */ 44 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 45 /* @brief DMA availability on the SoC. */ 46 #define FSL_FEATURE_SOC_DMA_COUNT (1) 47 /* @brief DMIC availability on the SoC. */ 48 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 49 /* @brief EMC availability on the SoC. */ 50 #define FSL_FEATURE_SOC_EMC_COUNT (1) 51 /* @brief FLEXCOMM availability on the SoC. */ 52 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11) 53 /* @brief GINT availability on the SoC. */ 54 #define FSL_FEATURE_SOC_GINT_COUNT (2) 55 /* @brief GPIO availability on the SoC. */ 56 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 57 /* @brief I2C availability on the SoC. */ 58 #define FSL_FEATURE_SOC_I2C_COUNT (10) 59 /* @brief I2S availability on the SoC. */ 60 #define FSL_FEATURE_SOC_I2S_COUNT (2) 61 /* @brief INPUTMUX availability on the SoC. */ 62 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 63 /* @brief IOCON availability on the SoC. */ 64 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 65 /* @brief MPU availability on the SoC. */ 66 #define FSL_FEATURE_SOC_MPU_COUNT (1) 67 /* @brief MRT availability on the SoC. */ 68 #define FSL_FEATURE_SOC_MRT_COUNT (1) 69 /* @brief PINT availability on the SoC. */ 70 #define FSL_FEATURE_SOC_PINT_COUNT (1) 71 /* @brief RIT availability on the SoC. */ 72 #define FSL_FEATURE_SOC_RIT_COUNT (1) 73 /* @brief LPC_RNG availability on the SoC. */ 74 #define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) 75 /* @brief RTC availability on the SoC. */ 76 #define FSL_FEATURE_SOC_RTC_COUNT (1) 77 /* @brief SCT availability on the SoC. */ 78 #define FSL_FEATURE_SOC_SCT_COUNT (1) 79 /* @brief SDIF availability on the SoC. */ 80 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 81 /* @brief SHA availability on the SoC. */ 82 #define FSL_FEATURE_SOC_SHA_COUNT (1) 83 /* @brief SMARTCARD availability on the SoC. */ 84 #define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) 85 /* @brief SPI availability on the SoC. */ 86 #define FSL_FEATURE_SOC_SPI_COUNT (11) 87 /* @brief SPIFI availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SPIFI_COUNT (1) 89 /* @brief SYSCON availability on the SoC. */ 90 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 91 /* @brief USART availability on the SoC. */ 92 #define FSL_FEATURE_SOC_USART_COUNT (10) 93 /* @brief USB availability on the SoC. */ 94 #define FSL_FEATURE_SOC_USB_COUNT (1) 95 /* @brief USBFSH availability on the SoC. */ 96 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 97 /* @brief USBHSD availability on the SoC. */ 98 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 99 /* @brief USBHSH availability on the SoC. */ 100 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 101 /* @brief UTICK availability on the SoC. */ 102 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 103 /* @brief WWDT availability on the SoC. */ 104 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 105 106 /* ADC module features */ 107 108 /* @brief Do not has input select (register INSEL). */ 109 #define FSL_FEATURE_ADC_HAS_NO_INSEL (0) 110 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 111 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) 112 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 113 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) 114 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 115 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) 116 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 117 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) 118 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 119 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) 120 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 121 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) 122 /* @brief Has startup register. */ 123 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) 124 /* @brief Has ADC Trim register */ 125 #define FSL_FEATURE_ADC_HAS_TRIM_REG (0) 126 /* @brief Has Calibration register. */ 127 #define FSL_FEATURE_ADC_HAS_CALIB_REG (1) 128 129 /* CTIMER module features */ 130 131 /* @brief CTIMER has no capture channel. */ 132 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 133 /* @brief CTIMER has no capture 2 interrupt. */ 134 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 135 /* @brief CTIMER capture 3 interrupt. */ 136 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 137 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 138 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 139 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 140 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 141 /* @brief CTIMER Has register MSR */ 142 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 143 144 /* DMA module features */ 145 146 /* @brief Number of channels */ 147 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) 148 /* @brief Align size of DMA descriptor */ 149 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 150 /* @brief DMA head link descriptor table align size */ 151 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 152 153 /* FLEXCOMM module features */ 154 155 /* @brief FLEXCOMM0 USART INDEX 0 */ 156 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 157 /* @brief FLEXCOMM0 SPI INDEX 0 */ 158 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 159 /* @brief FLEXCOMM0 I2C INDEX 0 */ 160 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 161 /* @brief FLEXCOMM1 USART INDEX 1 */ 162 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 163 /* @brief FLEXCOMM1 SPI INDEX 1 */ 164 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 165 /* @brief FLEXCOMM1 I2C INDEX 1 */ 166 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 167 /* @brief FLEXCOMM2 USART INDEX 2 */ 168 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 169 /* @brief FLEXCOMM2 SPI INDEX 2 */ 170 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 171 /* @brief FLEXCOMM2 I2C INDEX 2 */ 172 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 173 /* @brief FLEXCOMM3 USART INDEX 3 */ 174 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 175 /* @brief FLEXCOMM3 SPI INDEX 3 */ 176 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 177 /* @brief FLEXCOMM3 I2C INDEX 3 */ 178 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 179 /* @brief FLEXCOMM4 USART INDEX 4 */ 180 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 181 /* @brief FLEXCOMM4 SPI INDEX 4 */ 182 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 183 /* @brief FLEXCOMM4 I2C INDEX 4 */ 184 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 185 /* @brief FLEXCOMM5 USART INDEX 5 */ 186 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 187 /* @brief FLEXCOMM5 SPI INDEX 5 */ 188 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 189 /* @brief FLEXCOMM5 I2C INDEX 5 */ 190 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 191 /* @brief FLEXCOMM6 USART INDEX 6 */ 192 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 193 /* @brief FLEXCOMM6 SPI INDEX 6 */ 194 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 195 /* @brief FLEXCOMM6 I2C INDEX 6 */ 196 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 197 /* @brief FLEXCOMM7 I2S INDEX 0 */ 198 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) 199 /* @brief FLEXCOMM7 USART INDEX 7 */ 200 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 201 /* @brief FLEXCOMM7 SPI INDEX 7 */ 202 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 203 /* @brief FLEXCOMM7 I2C INDEX 7 */ 204 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 205 /* @brief FLEXCOMM7 I2S INDEX 1 */ 206 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) 207 /* @brief FLEXCOMM4 USART INDEX 8 */ 208 #define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8) 209 /* @brief FLEXCOMM4 SPI INDEX 8 */ 210 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 211 /* @brief FLEXCOMM4 I2C INDEX 8 */ 212 #define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8) 213 /* @brief FLEXCOMM5 USART INDEX 9 */ 214 #define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9) 215 /* @brief FLEXCOMM5 SPI INDEX 9 */ 216 #define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9) 217 /* @brief FLEXCOMM5 I2C INDEX 9 */ 218 #define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9) 219 /* @brief I2S has DMIC interconnection */ 220 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 221 (((x) == FLEXCOMM0) ? (0) : \ 222 (((x) == FLEXCOMM1) ? (0) : \ 223 (((x) == FLEXCOMM2) ? (0) : \ 224 (((x) == FLEXCOMM3) ? (0) : \ 225 (((x) == FLEXCOMM4) ? (0) : \ 226 (((x) == FLEXCOMM5) ? (0) : \ 227 (((x) == FLEXCOMM6) ? (0) : \ 228 (((x) == FLEXCOMM7) ? (1) : \ 229 (((x) == FLEXCOMM8) ? (0) : \ 230 (((x) == FLEXCOMM9) ? (0) : \ 231 (((x) == FLEXCOMM10) ? (0) : (-1)))))))))))) 232 233 /* I2S module features */ 234 235 /* @brief I2S support dual channel transfer. */ 236 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 237 /* @brief I2S has DMIC interconnection */ 238 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 239 240 /* IOCON module features */ 241 242 /* @brief Func bit field width */ 243 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 244 245 /* MRT module features */ 246 247 /* @brief number of channels. */ 248 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 249 250 /* interrupt module features */ 251 252 /* @brief Lowest interrupt request number. */ 253 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 254 /* @brief Highest interrupt request number. */ 255 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) 256 257 /* PINT module features */ 258 259 /* @brief Number of connected outputs */ 260 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 261 262 /* RTC module features */ 263 264 /* @brief RTC has no reset control */ 265 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 266 267 /* SCT module features */ 268 269 /* @brief Number of events */ 270 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 271 /* @brief Number of states */ 272 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) 273 /* @brief Number of match capture */ 274 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 275 /* @brief Number of outputs */ 276 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 277 278 /* SDIF module features */ 279 280 /* @brief FIFO depth, every location is a WORD */ 281 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 282 /* @brief Max DMA buffer size */ 283 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 284 /* @brief Max source clock in HZ */ 285 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 286 287 /* SHA module features */ 288 289 /* @brief Has dedicated DMA controller. */ 290 #define FSL_FEATURE_SHA_HAS_MEMADDR_DMA (1) 291 292 /* SPI module features */ 293 294 /* @brief SSEL pin count. */ 295 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 296 297 /* SPIFI module features */ 298 299 /* @brief SPIFI start address */ 300 #define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) 301 /* @brief SPIFI end address */ 302 #define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) 303 304 /* SYSCON module features */ 305 306 /* @brief Pointer to ROM IAP entry functions */ 307 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) 308 /* @brief IAP Reinvoke ISP command parameter is pointer */ 309 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (1) 310 /* @brief RIT has no reset control */ 311 #define FSL_FEATURE_RIT_HAS_NO_RESET (1) 312 313 /* SysTick module features */ 314 315 /* @brief Systick has external reference clock. */ 316 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 317 /* @brief Systick external reference clock is core clock divided by this value. */ 318 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 319 320 /* USB module features */ 321 322 /* @brief Size of the USB dedicated RAM */ 323 #define FSL_FEATURE_USB_USB_RAM (0x00002000) 324 /* @brief Base address of the USB dedicated RAM */ 325 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 326 /* @brief USB version */ 327 #define FSL_FEATURE_USB_VERSION (200) 328 /* @brief Number of the endpoint in USB FS */ 329 #define FSL_FEATURE_USB_EP_NUM (5) 330 331 /* USBFSH module features */ 332 333 /* @brief Size of the USB dedicated RAM */ 334 #define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) 335 /* @brief Base address of the USB dedicated RAM */ 336 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 337 /* @brief USBFSH version */ 338 #define FSL_FEATURE_USBFSH_VERSION (200) 339 340 /* USBHSD module features */ 341 342 /* @brief Size of the USB dedicated RAM */ 343 #define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) 344 /* @brief Base address of the USB dedicated RAM */ 345 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 346 /* @brief USBHSD version */ 347 #define FSL_FEATURE_USBHSD_VERSION (300) 348 /* @brief Number of the endpoint in USB HS */ 349 #define FSL_FEATURE_USBHSD_EP_NUM (6) 350 /* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */ 351 #define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1) 352 353 /* USBHSH module features */ 354 355 /* @brief Size of the USB dedicated RAM */ 356 #define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) 357 /* @brief Base address of the USB dedicated RAM */ 358 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 359 /* @brief USBHSH version */ 360 #define FSL_FEATURE_USBHSH_VERSION (300) 361 362 /* WWDT module features */ 363 364 /* @brief Has no RESET register. */ 365 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 366 367 #endif /* _LPC54005_FEATURES_H_ */ 368 369
