1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _RTE_DEVICE_H 10 #define _RTE_DEVICE_H 11 12 #include "pin_mux.h" 13 14 /* UART Select, UART0-UART7. */ 15 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 16 * instance. */ 17 #define RTE_USART0 0 18 #define RTE_USART0_DMA_EN 0 19 #define RTE_USART1 0 20 #define RTE_USART1_DMA_EN 0 21 #define RTE_USART2 0 22 #define RTE_USART2_DMA_EN 0 23 #define RTE_USART3 0 24 #define RTE_USART3_DMA_EN 0 25 #define RTE_USART4 0 26 #define RTE_USART4_DMA_EN 0 27 #define RTE_USART5 0 28 #define RTE_USART5_DMA_EN 0 29 #define RTE_USART6 0 30 #define RTE_USART6_DMA_EN 0 31 #define RTE_USART7 0 32 #define RTE_USART7_DMA_EN 0 33 34 /* USART configuration. */ 35 #define USART_RX_BUFFER_LEN 64 36 #define USART0_RX_BUFFER_ENABLE 0 37 #define USART1_RX_BUFFER_ENABLE 0 38 #define USART2_RX_BUFFER_ENABLE 0 39 #define USART3_RX_BUFFER_ENABLE 0 40 #define USART4_RX_BUFFER_ENABLE 0 41 #define USART5_RX_BUFFER_ENABLE 0 42 #define USART6_RX_BUFFER_ENABLE 0 43 #define USART7_RX_BUFFER_ENABLE 0 44 45 #define RTE_USART0_PIN_INIT USART0_InitPins 46 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 47 #define RTE_USART0_DMA_TX_CH 1 48 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 49 #define RTE_USART0_DMA_RX_CH 0 50 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 51 52 #define RTE_USART1_PIN_INIT USART1_InitPins 53 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 54 #define RTE_USART1_DMA_TX_CH 3 55 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 56 #define RTE_USART1_DMA_RX_CH 2 57 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 58 59 #define RTE_USART2_PIN_INIT USART2_InitPins 60 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 61 #define RTE_USART2_DMA_TX_CH 5 62 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 63 #define RTE_USART2_DMA_RX_CH 4 64 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 65 66 #define RTE_USART3_PIN_INIT USART3_InitPins 67 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 68 #define RTE_USART3_DMA_TX_CH 7 69 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 70 #define RTE_USART3_DMA_RX_CH 6 71 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 72 73 #define RTE_USART4_PIN_INIT USART4_InitPins 74 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 75 #define RTE_USART4_DMA_TX_CH 9 76 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 77 #define RTE_USART4_DMA_RX_CH 8 78 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 79 80 #define RTE_USART5_PIN_INIT USART5_InitPins 81 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 82 #define RTE_USART5_DMA_TX_CH 11 83 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 84 #define RTE_USART5_DMA_RX_CH 10 85 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 86 87 #define RTE_USART6_PIN_INIT USART6_InitPins 88 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 89 #define RTE_USART6_DMA_TX_CH 13 90 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 91 #define RTE_USART6_DMA_RX_CH 12 92 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 93 94 #define RTE_USART7_PIN_INIT USART7_InitPins 95 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 96 #define RTE_USART7_DMA_TX_CH 15 97 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 98 #define RTE_USART7_DMA_RX_CH 14 99 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 100 101 /* I2C Select, I2C0 -I2C7*/ 102 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 103 */ 104 #define RTE_I2C0 0 105 #define RTE_I2C0_DMA_EN 0 106 #define RTE_I2C1 0 107 #define RTE_I2C1_DMA_EN 0 108 #define RTE_I2C2 0 109 #define RTE_I2C2_DMA_EN 0 110 #define RTE_I2C3 0 111 #define RTE_I2C3_DMA_EN 0 112 #define RTE_I2C4 0 113 #define RTE_I2C4_DMA_EN 0 114 #define RTE_I2C5 0 115 #define RTE_I2C5_DMA_EN 0 116 #define RTE_I2C6 0 117 #define RTE_I2C6_DMA_EN 0 118 #define RTE_I2C7 0 119 #define RTE_I2C7_DMA_EN 0 120 121 /*I2C configuration*/ 122 #define RTE_I2C0_Master_DMA_BASE DMA0 123 #define RTE_I2C0_Master_DMA_CH 1 124 125 #define RTE_I2C1_Master_DMA_BASE DMA0 126 #define RTE_I2C1_Master_DMA_CH 3 127 128 #define RTE_I2C2_Master_DMA_BASE DMA0 129 #define RTE_I2C2_Master_DMA_CH 5 130 131 #define RTE_I2C3_Master_DMA_BASE DMA0 132 #define RTE_I2C3_Master_DMA_CH 7 133 134 #define RTE_I2C4_Master_DMA_BASE DMA0 135 #define RTE_I2C4_Master_DMA_CH 9 136 137 #define RTE_I2C5_Master_DMA_BASE DMA0 138 #define RTE_I2C5_Master_DMA_CH 11 139 140 #define RTE_I2C6_Master_DMA_BASE DMA0 141 #define RTE_I2C6_Master_DMA_CH 13 142 143 #define RTE_I2C7_Master_DMA_BASE DMA0 144 #define RTE_I2C7_Master_DMA_CH 15 145 146 /* SPI select, SPI0 - SPI7.*/ 147 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 148 */ 149 #define RTE_SPI0 0 150 #define RTE_SPI0_DMA_EN 0 151 #define RTE_SPI1 0 152 #define RTE_SPI1_DMA_EN 0 153 #define RTE_SPI2 0 154 #define RTE_SPI2_DMA_EN 0 155 #define RTE_SPI3 0 156 #define RTE_SPI3_DMA_EN 0 157 #define RTE_SPI4 0 158 #define RTE_SPI4_DMA_EN 0 159 #define RTE_SPI5 0 160 #define RTE_SPI5_DMA_EN 0 161 #define RTE_SPI6 0 162 #define RTE_SPI6_DMA_EN 0 163 #define RTE_SPI7 0 164 #define RTE_SPI7_DMA_EN 0 165 166 /* SPI configuration. */ 167 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 168 #define RTE_SPI0_PIN_INIT SPI0_InitPins 169 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 170 #define RTE_SPI0_DMA_TX_CH 1 171 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 172 #define RTE_SPI0_DMA_RX_CH 0 173 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 174 175 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 176 #define RTE_SPI1_PIN_INIT SPI1_InitPins 177 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 178 #define RTE_SPI1_DMA_TX_CH 3 179 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 180 #define RTE_SPI1_DMA_RX_CH 2 181 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 182 183 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 184 #define RTE_SPI2_PIN_INIT SPI2_InitPins 185 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 186 #define RTE_SPI2_DMA_TX_CH 5 187 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 188 #define RTE_SPI2_DMA_RX_CH 4 189 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 190 191 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 192 #define RTE_SPI3_PIN_INIT SPI3_InitPins 193 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 194 #define RTE_SPI3_DMA_TX_CH 7 195 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 196 #define RTE_SPI3_DMA_RX_CH 6 197 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 198 199 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 200 #define RTE_SPI4_PIN_INIT SPI4_InitPins 201 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 202 #define RTE_SPI4_DMA_TX_CH 9 203 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 204 #define RTE_SPI4_DMA_RX_CH 8 205 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 206 207 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 208 #define RTE_SPI5_PIN_INIT SPI5_InitPins 209 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 210 #define RTE_SPI5_DMA_TX_CH 11 211 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 212 #define RTE_SPI5_DMA_RX_CH 10 213 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 214 215 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 216 #define RTE_SPI6_PIN_INIT SPI6_InitPins 217 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 218 #define RTE_SPI6_DMA_TX_CH 13 219 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 220 #define RTE_SPI6_DMA_RX_CH 12 221 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 222 223 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 224 #define RTE_SPI7_PIN_INIT SPI7_InitPins 225 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 226 #define RTE_SPI7_DMA_TX_CH 15 227 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 228 #define RTE_SPI7_DMA_RX_CH 14 229 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 230 231 #endif /* _RTE_DEVICE_H */ 232
