1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016, NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _FSL_RESET_H_ 11 #define _FSL_RESET_H_ 12 13 #include <assert.h> 14 #include <stdbool.h> 15 #include <stdint.h> 16 #include <string.h> 17 #include "fsl_device_registers.h" 18 19 /*! 20 * @addtogroup reset 21 * @{ 22 */ 23 24 /******************************************************************************* 25 * Definitions 26 ******************************************************************************/ 27 28 /*! @name Driver version */ 29 /*@{*/ 30 /*! @brief reset driver version 2.0.1. */ 31 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 32 /*@}*/ 33 34 /*! 35 * @brief Enumeration for peripheral reset control bits 36 * 37 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers 38 */ 39 typedef enum _SYSCON_RSTn 40 { 41 kRSTn_IpInvalid = 0U, 42 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ 43 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ 44 kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ 45 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ 46 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ 47 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ 48 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ 49 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ 50 kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ 51 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ 52 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ 53 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ 54 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ 55 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ 56 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ 57 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ 58 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ 59 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ 60 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ 61 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ 62 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ 63 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ 64 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ 65 kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ 66 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer0 reset control */ 67 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer1 reset control */ 68 kCTIMER3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CTimer3 reset control */ 69 } SYSCON_RSTn_t; 70 71 /** Array initializers with peripheral reset bits **/ 72 #define ADC_RSTS \ 73 { \ 74 kADC0_RST_SHIFT_RSTn \ 75 } /* Reset bits for ADC peripheral */ 76 #define CRC_RSTS \ 77 { \ 78 kCRC_RST_SHIFT_RSTn \ 79 } /* Reset bits for CRC peripheral */ 80 #define DMA_RSTS_N \ 81 { \ 82 kDMA_RST_SHIFT_RSTn \ 83 } /* Reset bits for DMA peripheral */ 84 #define FLEXCOMM_RSTS \ 85 { \ 86 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ 87 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ 88 } /* Reset bits for FLEXCOMM peripheral */ 89 #define GINT_RSTS \ 90 { \ 91 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ 92 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ 93 #define GPIO_RSTS_N \ 94 { \ 95 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ 96 } /* Reset bits for GPIO peripheral */ 97 #define INPUTMUX_RSTS \ 98 { \ 99 kMUX_RST_SHIFT_RSTn \ 100 } /* Reset bits for INPUTMUX peripheral */ 101 #define IOCON_RSTS \ 102 { \ 103 kIOCON_RST_SHIFT_RSTn \ 104 } /* Reset bits for IOCON peripheral */ 105 #define FLASH_RSTS \ 106 { \ 107 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ 108 } /* Reset bits for Flash peripheral */ 109 #define MRT_RSTS \ 110 { \ 111 kMRT_RST_SHIFT_RSTn \ 112 } /* Reset bits for MRT peripheral */ 113 #define PINT_RSTS \ 114 { \ 115 kPINT_RST_SHIFT_RSTn \ 116 } /* Reset bits for PINT peripheral */ 117 #define SCT_RSTS \ 118 { \ 119 kSCT0_RST_SHIFT_RSTn \ 120 } /* Reset bits for SCT peripheral */ 121 #define CTIMER_RSTS \ 122 { \ 123 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kRSTn_IpInvalid, kCTIMER3_RST_SHIFT_RSTn \ 124 } /* Reset bits for TIMER peripheral */ 125 #define USB_RSTS \ 126 { \ 127 kUSB_RST_SHIFT_RSTn \ 128 } /* Reset bits for USB peripheral */ 129 #define UTICK_RSTS \ 130 { \ 131 kUTICK_RST_SHIFT_RSTn \ 132 } /* Reset bits for UTICK peripheral */ 133 #define WWDT_RSTS \ 134 { \ 135 kWWDT_RST_SHIFT_RSTn \ 136 } /* Reset bits for WWDT peripheral */ 137 138 typedef SYSCON_RSTn_t reset_ip_name_t; 139 140 /******************************************************************************* 141 * API 142 ******************************************************************************/ 143 #if defined(__cplusplus) 144 extern "C" { 145 #endif 146 147 /*! 148 * @brief Assert reset to peripheral. 149 * 150 * Asserts reset signal to specified peripheral module. 151 * 152 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register 153 * and reset bit position in the reset register. 154 */ 155 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 156 157 /*! 158 * @brief Clear reset to peripheral. 159 * 160 * Clears reset signal to specified peripheral module, allows it to operate. 161 * 162 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register 163 * and reset bit position in the reset register. 164 */ 165 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 166 167 /*! 168 * @brief Reset peripheral module. 169 * 170 * Reset peripheral module. 171 * 172 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 173 * and reset bit position in the reset register. 174 */ 175 void RESET_PeripheralReset(reset_ip_name_t peripheral); 176 177 #if defined(__cplusplus) 178 } 179 #endif 180 181 /*! @} */ 182 183 #endif /* _FSL_RESET_H_ */ 184
