1 /*
2  * Copyright 2016-2020 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "fsl_cache.h"
9 /*******************************************************************************
10  * Definitions
11  ******************************************************************************/
12 
13 /* Component ID definition, used by tools. */
14 #ifndef FSL_COMPONENT_ID
15 #define FSL_COMPONENT_ID "platform.drivers.cache_lpcac"
16 #endif
17 
18 #define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */
19 
20 /*******************************************************************************
21  * Code
22  ******************************************************************************/
23 /*!
24  * brief Invalidates L1 instrument cache by range.
25  *
26  * param address  The start address of the memory to be invalidated.
27  * param size_byte  The memory size.
28  */
L1CACHE_InvalidateICacheByRange(uint32_t address,uint32_t size_byte)29 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
30 {
31     if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
32     {
33         L1CACHE_InvalidateCodeCache();
34     }
35 }
36