1 /*
2  * Copyright (c) 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2020 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include "fsl_cache.h"
10 /*******************************************************************************
11  * Definitions
12  ******************************************************************************/
13 
14 /* Component ID definition, used by tools. */
15 #ifndef FSL_COMPONENT_ID
16 #define FSL_COMPONENT_ID "platform.drivers.cache_lplmem"
17 #endif
18 
19 #define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */
20 
21 /*******************************************************************************
22  * Code
23  ******************************************************************************/
24 /*!
25  * brief Invalidates L1 instrument cache by range.
26  *
27  * param address  The start address of the memory to be invalidated.
28  * param size_byte  The memory size.
29  */
L1CACHE_InvalidateICacheByRange(uint32_t address,uint32_t size_byte)30 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
31 {
32     if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
33     {
34         L1CACHE_InvalidateCodeCache();
35     }
36 }
37