1 /* 2 ** ################################################################### 3 ** Processors: K32L2B31VFM0A 4 ** K32L2B31VFT0A 5 ** K32L2B31VLH0A 6 ** K32L2B31VMP0A 7 ** 8 ** Compilers: Freescale C/C++ for Embedded ARM 9 ** GNU C Compiler 10 ** IAR ANSI C/C++ Compiler for ARM 11 ** Keil ARM C/C++ Compiler 12 ** MCUXpresso Compiler 13 ** 14 ** Reference manual: K32L2B3xRM, Rev.0, July 2019 15 ** Version: rev. 1.0, 2019-07-30 16 ** Build: b191223 17 ** 18 ** Abstract: 19 ** CMSIS Peripheral Access Layer for K32L2B31A 20 ** 21 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 22 ** Copyright 2016-2019 NXP 23 ** All rights reserved. 24 ** 25 ** SPDX-License-Identifier: BSD-3-Clause 26 ** 27 ** http: www.nxp.com 28 ** mail: support@nxp.com 29 ** 30 ** Revisions: 31 ** - rev. 1.0 (2019-07-30) 32 ** Initial version. 33 ** 34 ** ################################################################### 35 */ 36 37 /*! 38 * @file K32L2B31A.h 39 * @version 1.0 40 * @date 2019-07-30 41 * @brief CMSIS Peripheral Access Layer for K32L2B31A 42 * 43 * CMSIS Peripheral Access Layer for K32L2B31A 44 */ 45 46 #ifndef _K32L2B31A_H_ 47 #define _K32L2B31A_H_ /**< Symbol preventing repeated inclusion */ 48 49 /** Memory map major version (memory maps with equal major version number are 50 * compatible) */ 51 #define MCU_MEM_MAP_VERSION 0x0100U 52 /** Memory map minor version */ 53 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 54 55 /* ---------------------------------------------------------------------------- 56 -- Interrupt vector numbers 57 ---------------------------------------------------------------------------- */ 58 59 /*! 60 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 61 * @{ 62 */ 63 64 /** Interrupt Number Definitions */ 65 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 66 67 typedef enum IRQn 68 { 69 /* Auxiliary constants */ 70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 71 72 /* Core interrupts */ 73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 78 79 /* Device specific interrupts */ 80 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ 81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ 82 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ 83 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ 84 Reserved20_IRQn = 4, /**< Reserved interrupt */ 85 FTFA_IRQn = 5, /**< Command complete and read collision */ 86 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 87 LLWU_IRQn = 7, /**< Low leakage wakeup */ 88 I2C0_IRQn = 8, /**< I2C0 interrupt */ 89 I2C1_IRQn = 9, /**< I2C1 interrupt */ 90 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ 91 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ 92 LPUART0_IRQn = 12, /**< LPUART0 status and error */ 93 LPUART1_IRQn = 13, /**< LPUART1 status and error */ 94 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */ 95 ADC0_IRQn = 15, /**< ADC0 interrupt */ 96 CMP0_IRQn = 16, /**< CMP0 interrupt */ 97 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ 98 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ 99 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ 100 RTC_IRQn = 20, /**< RTC alarm */ 101 RTC_Seconds_IRQn = 21, /**< RTC seconds */ 102 PIT_IRQn = 22, /**< PIT interrupt */ 103 Reserved39_IRQn = 23, /**< Reserved interrupt */ 104 USB0_IRQn = 24, /**< USB0 interrupt */ 105 DAC0_IRQn = 25, /**< DAC0 interrupt */ 106 Reserved42_IRQn = 26, /**< Reserved interrupt */ 107 Reserved43_IRQn = 27, /**< Reserved interrupt */ 108 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ 109 LCD_IRQn = 29, /**< LCD interrupt */ 110 PORTA_IRQn = 30, /**< PORTA Pin detect */ 111 PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */ 112 } IRQn_Type; 113 114 /*! 115 * @} 116 */ /* end of group Interrupt_vector_numbers */ 117 118 /* ---------------------------------------------------------------------------- 119 -- Cortex M0 Core Configuration 120 ---------------------------------------------------------------------------- */ 121 122 /*! 123 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 124 * @{ 125 */ 126 127 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 128 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 129 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 130 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 131 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 132 133 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 134 #include "system_K32L2B31A.h" /* Device specific configuration file */ 135 136 /*! 137 * @} 138 */ /* end of group Cortex_Core_Configuration */ 139 140 /* ---------------------------------------------------------------------------- 141 -- Mapping Information 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup Mapping_Information Mapping Information 146 * @{ 147 */ 148 149 /** Mapping Information */ 150 /*! 151 * @addtogroup edma_request 152 * @{ 153 */ 154 155 /******************************************************************************* 156 * Definitions 157 ******************************************************************************/ 158 159 /*! 160 * @brief Structure for the DMA hardware request 161 * 162 * Defines the structure for the DMA hardware request collections. The user can configure the 163 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 164 * of the hardware request varies according to the to SoC. 165 */ 166 typedef enum _dma_request_source 167 { 168 kDmaRequestMux0Disable = 0 | 0x100U, /**< DMAMUX TriggerDisabled */ 169 kDmaRequestMux0Reserved1 = 1 | 0x100U, /**< Reserved1 */ 170 kDmaRequestMux0LPUART0Rx = 2 | 0x100U, /**< LPUART0 Receive */ 171 kDmaRequestMux0LPUART0Tx = 3 | 0x100U, /**< LPUART0 Transmit */ 172 kDmaRequestMux0LPUART1Rx = 4 | 0x100U, /**< LPUART1 Receive */ 173 kDmaRequestMux0LPUART1Tx = 5 | 0x100U, /**< LPUART1 Transmit */ 174 kDmaRequestMux0UART2Rx = 6 | 0x100U, /**< UART2 Receive */ 175 kDmaRequestMux0UART2Tx = 7 | 0x100U, /**< UART2 Transmit */ 176 kDmaRequestMux0Reserved8 = 8 | 0x100U, /**< Reserved8 */ 177 kDmaRequestMux0Reserved9 = 9 | 0x100U, /**< Reserved9 */ 178 kDmaRequestMux0FlexIOChannel0 = 10 | 0x100U, /**< FlexIO Channel 0 */ 179 kDmaRequestMux0FlexIOChannel1 = 11 | 0x100U, /**< FlexIO Channel 1 */ 180 kDmaRequestMux0FlexIOChannel2 = 12 | 0x100U, /**< FlexIO Channel 2 */ 181 kDmaRequestMux0FlexIOChannel3 = 13 | 0x100U, /**< FlexIO Channel 3 */ 182 kDmaRequestMux0SPI0Rx = 16 | 0x100U, /**< SPI0 Receive */ 183 kDmaRequestMux0SPI0Tx = 17 | 0x100U, /**< SPI0 Transmit */ 184 kDmaRequestMux0SPI1Rx = 18 | 0x100U, /**< SPI1 Receive */ 185 kDmaRequestMux0SPI1Tx = 19 | 0x100U, /**< SPI1 Transmit */ 186 kDmaRequestMux0Reserved20 = 20 | 0x100U, /**< Reserved20 */ 187 kDmaRequestMux0Reserved21 = 21 | 0x100U, /**< Reserved21 */ 188 kDmaRequestMux0I2C0 = 22 | 0x100U, /**< I2C0 */ 189 kDmaRequestMux0I2C1 = 23 | 0x100U, /**< I2C1 */ 190 kDmaRequestMux0TPM0Channel0 = 24 | 0x100U, /**< TPM0 channel 0 */ 191 kDmaRequestMux0TPM0Channel1 = 25 | 0x100U, /**< TPM0 channel 1 */ 192 kDmaRequestMux0TPM0Channel2 = 26 | 0x100U, /**< TPM0 channel 2 */ 193 kDmaRequestMux0TPM0Channel3 = 27 | 0x100U, /**< TPM0 channel 3 */ 194 kDmaRequestMux0TPM0Channel4 = 28 | 0x100U, /**< TPM0 channel 4 */ 195 kDmaRequestMux0TPM0Channel5 = 29 | 0x100U, /**< TPM0 channel 5 */ 196 kDmaRequestMux0Reserved30 = 30 | 0x100U, /**< Reserved30 */ 197 kDmaRequestMux0Reserved31 = 31 | 0x100U, /**< Reserved31 */ 198 kDmaRequestMux0TPM1Channel0 = 32 | 0x100U, /**< TPM1 channel 0 */ 199 kDmaRequestMux0TPM1Channel1 = 33 | 0x100U, /**< TPM1 channel 1 */ 200 kDmaRequestMux0TPM2Channel0 = 34 | 0x100U, /**< TPM2 channel 0 */ 201 kDmaRequestMux0TPM2Channel1 = 35 | 0x100U, /**< TPM2 channel 1 */ 202 kDmaRequestMux0Reserved36 = 36 | 0x100U, /**< Reserved36 */ 203 kDmaRequestMux0Reserved37 = 37 | 0x100U, /**< Reserved37 */ 204 kDmaRequestMux0Reserved38 = 38 | 0x100U, /**< Reserved38 */ 205 kDmaRequestMux0Reserved39 = 39 | 0x100U, /**< Reserved39 */ 206 kDmaRequestMux0ADC0 = 40 | 0x100U, /**< ADC0 */ 207 kDmaRequestMux0Reserved41 = 41 | 0x100U, /**< Reserved41 */ 208 kDmaRequestMux0CMP0 = 42 | 0x100U, /**< CMP0 */ 209 kDmaRequestMux0Reserved43 = 43 | 0x100U, /**< Reserved43 */ 210 kDmaRequestMux0Reserved44 = 44 | 0x100U, /**< Reserved44 */ 211 kDmaRequestMux0DAC0 = 45 | 0x100U, /**< DAC0 */ 212 kDmaRequestMux0Reserved46 = 46 | 0x100U, /**< Reserved46 */ 213 kDmaRequestMux0Reserved47 = 47 | 0x100U, /**< Reserved47 */ 214 kDmaRequestMux0Reserved48 = 48 | 0x100U, /**< Reserved48 */ 215 kDmaRequestMux0PortA = 49 | 0x100U, /**< GPIO Port A */ 216 kDmaRequestMux0Reserved50 = 50 | 0x100U, /**< Reserved50 */ 217 kDmaRequestMux0PortC = 51 | 0x100U, /**< GPIO Port C */ 218 kDmaRequestMux0PortD = 52 | 0x100U, /**< GPIO Port D */ 219 kDmaRequestMux0Reserved53 = 53 | 0x100U, /**< Reserved53 */ 220 kDmaRequestMux0TPM0Overflow = 54 | 0x100U, /**< TPM0 overflow */ 221 kDmaRequestMux0TPM1Overflow = 55 | 0x100U, /**< TPM1 overflow */ 222 kDmaRequestMux0TPM2Overflow = 56 | 0x100U, /**< TPM2 overflow */ 223 kDmaRequestMux0Reserved57 = 57 | 0x100U, /**< Reserved57 */ 224 kDmaRequestMux0Reserved58 = 58 | 0x100U, /**< Reserved58 */ 225 kDmaRequestMux0Reserved59 = 59 | 0x100U, /**< Reserved59 */ 226 kDmaRequestMux0AlwaysOn60 = 60 | 0x100U, /**< DMAMUX Always Enabled slot */ 227 kDmaRequestMux0AlwaysOn61 = 61 | 0x100U, /**< DMAMUX Always Enabled slot */ 228 kDmaRequestMux0AlwaysOn62 = 62 | 0x100U, /**< DMAMUX Always Enabled slot */ 229 kDmaRequestMux0AlwaysOn63 = 63 | 0x100U, /**< DMAMUX Always Enabled slot */ 230 } dma_request_source_t; 231 232 /* @} */ 233 234 /*! 235 * @} 236 */ /* end of group Mapping_Information */ 237 238 /* ---------------------------------------------------------------------------- 239 -- Device Peripheral Access Layer 240 ---------------------------------------------------------------------------- */ 241 242 /*! 243 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 244 * @{ 245 */ 246 247 /* 248 ** Start of section using anonymous unions 249 */ 250 251 #if defined(__ARMCC_VERSION) 252 #if (__ARMCC_VERSION >= 6010050) 253 #pragma clang diagnostic push 254 #else 255 #pragma push 256 #pragma anon_unions 257 #endif 258 #elif defined(__CWCC__) 259 #pragma push 260 #pragma cpp_extensions on 261 #elif defined(__GNUC__) 262 /* anonymous unions are enabled by default */ 263 #elif defined(__IAR_SYSTEMS_ICC__) 264 #pragma language = extended 265 #else 266 #error Not supported compiler type 267 #endif 268 269 /* ---------------------------------------------------------------------------- 270 -- ADC Peripheral Access Layer 271 ---------------------------------------------------------------------------- */ 272 273 /*! 274 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 275 * @{ 276 */ 277 278 /** ADC - Register Layout Typedef */ 279 typedef struct 280 { 281 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 282 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 283 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 284 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 285 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 286 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 287 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 288 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 289 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 290 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 291 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 292 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 293 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 294 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 295 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 296 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 297 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 298 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 299 uint8_t RESERVED_0[4]; 300 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 301 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 302 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 303 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 304 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 305 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 306 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 307 } ADC_Type; 308 309 /* ---------------------------------------------------------------------------- 310 -- ADC Register Masks 311 ---------------------------------------------------------------------------- */ 312 313 /*! 314 * @addtogroup ADC_Register_Masks ADC Register Masks 315 * @{ 316 */ 317 318 /*! @name SC1 - ADC Status and Control Registers 1 */ 319 /*! @{ */ 320 #define ADC_SC1_ADCH_MASK (0x1FU) 321 #define ADC_SC1_ADCH_SHIFT (0U) 322 /*! ADCH - Input channel select 323 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 324 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 325 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 326 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 327 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 328 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 329 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 330 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 331 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 332 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 333 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 334 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 335 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 336 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 337 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 338 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 339 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 340 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 341 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 342 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 343 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 344 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 345 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 346 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 347 * 0b11000..Reserved. 348 * 0b11001..Reserved. 349 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is 350 * selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap 351 * (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when 352 * DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 353 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is 354 * determined by SC2[REFSEL]. 0b11111..Module is disabled. 355 */ 356 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 357 #define ADC_SC1_DIFF_MASK (0x20U) 358 #define ADC_SC1_DIFF_SHIFT (5U) 359 /*! DIFF - Differential Mode Enable 360 * 0b0..Single-ended conversions and input channels are selected. 361 * 0b1..Differential conversions and input channels are selected. 362 */ 363 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) 364 #define ADC_SC1_AIEN_MASK (0x40U) 365 #define ADC_SC1_AIEN_SHIFT (6U) 366 /*! AIEN - Interrupt Enable 367 * 0b0..Conversion complete interrupt is disabled. 368 * 0b1..Conversion complete interrupt is enabled. 369 */ 370 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 371 #define ADC_SC1_COCO_MASK (0x80U) 372 #define ADC_SC1_COCO_SHIFT (7U) 373 /*! COCO - Conversion Complete Flag 374 * 0b0..Conversion is not completed. 375 * 0b1..Conversion is completed. 376 */ 377 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 378 /*! @} */ 379 380 /* The count of ADC_SC1 */ 381 #define ADC_SC1_COUNT (2U) 382 383 /*! @name CFG1 - ADC Configuration Register 1 */ 384 /*! @{ */ 385 #define ADC_CFG1_ADICLK_MASK (0x3U) 386 #define ADC_CFG1_ADICLK_SHIFT (0U) 387 /*! ADICLK - Input Clock Select 388 * 0b00..Bus clock 389 * 0b01..Bus clock divided by 2(BUSCLK/2) 390 * 0b10..Alternate clock (ALTCLK) 391 * 0b11..Asynchronous clock (ADACK) 392 */ 393 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 394 #define ADC_CFG1_MODE_MASK (0xCU) 395 #define ADC_CFG1_MODE_SHIFT (2U) 396 /*! MODE - Conversion mode selection 397 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's 398 * complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit 399 * conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is 400 * differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; 401 * when DIFF=1, it is differential 16-bit conversion with 2's complement output 402 */ 403 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 404 #define ADC_CFG1_ADLSMP_MASK (0x10U) 405 #define ADC_CFG1_ADLSMP_SHIFT (4U) 406 /*! ADLSMP - Sample Time Configuration 407 * 0b0..Short sample time. 408 * 0b1..Long sample time. 409 */ 410 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 411 #define ADC_CFG1_ADIV_MASK (0x60U) 412 #define ADC_CFG1_ADIV_SHIFT (5U) 413 /*! ADIV - Clock Divide Select 414 * 0b00..The divide ratio is 1 and the clock rate is input clock. 415 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 416 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 417 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. 418 */ 419 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 420 #define ADC_CFG1_ADLPC_MASK (0x80U) 421 #define ADC_CFG1_ADLPC_SHIFT (7U) 422 /*! ADLPC - Low-Power Configuration 423 * 0b0..Normal power configuration. 424 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed. 425 */ 426 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 427 /*! @} */ 428 429 /*! @name CFG2 - ADC Configuration Register 2 */ 430 /*! @{ */ 431 #define ADC_CFG2_ADLSTS_MASK (0x3U) 432 #define ADC_CFG2_ADLSTS_SHIFT (0U) 433 /*! ADLSTS - Long Sample Time Select 434 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 435 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 436 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 437 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time. 438 */ 439 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 440 #define ADC_CFG2_ADHSC_MASK (0x4U) 441 #define ADC_CFG2_ADHSC_SHIFT (2U) 442 /*! ADHSC - High-Speed Configuration 443 * 0b0..Normal conversion sequence selected. 444 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 445 */ 446 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 447 #define ADC_CFG2_ADACKEN_MASK (0x8U) 448 #define ADC_CFG2_ADACKEN_SHIFT (3U) 449 /*! ADACKEN - Asynchronous Clock Output Enable 450 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion 451 * is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC. 452 */ 453 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 454 #define ADC_CFG2_MUXSEL_MASK (0x10U) 455 #define ADC_CFG2_MUXSEL_SHIFT (4U) 456 /*! MUXSEL - ADC Mux Select 457 * 0b0..ADxxa channels are selected. 458 * 0b1..ADxxb channels are selected. 459 */ 460 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) 461 /*! @} */ 462 463 /*! @name R - ADC Data Result Register */ 464 /*! @{ */ 465 #define ADC_R_D_MASK (0xFFFFU) 466 #define ADC_R_D_SHIFT (0U) 467 /*! D - Data result 468 */ 469 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 470 /*! @} */ 471 472 /* The count of ADC_R */ 473 #define ADC_R_COUNT (2U) 474 475 /*! @name CV1 - Compare Value Registers */ 476 /*! @{ */ 477 #define ADC_CV1_CV_MASK (0xFFFFU) 478 #define ADC_CV1_CV_SHIFT (0U) 479 /*! CV - Compare Value. 480 */ 481 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 482 /*! @} */ 483 484 /*! @name CV2 - Compare Value Registers */ 485 /*! @{ */ 486 #define ADC_CV2_CV_MASK (0xFFFFU) 487 #define ADC_CV2_CV_SHIFT (0U) 488 /*! CV - Compare Value. 489 */ 490 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 491 /*! @} */ 492 493 /*! @name SC2 - Status and Control Register 2 */ 494 /*! @{ */ 495 #define ADC_SC2_REFSEL_MASK (0x3U) 496 #define ADC_SC2_REFSEL_SHIFT (0U) 497 /*! REFSEL - Voltage Reference Selection 498 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 499 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or 500 * internal sources depending on the MCU configuration. See the chip configuration information for details 501 * specific to this MCU 502 * 0b10..Reserved 503 * 0b11..Reserved 504 */ 505 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 506 #define ADC_SC2_DMAEN_MASK (0x4U) 507 #define ADC_SC2_DMAEN_SHIFT (2U) 508 /*! DMAEN - DMA Enable 509 * 0b0..DMA is disabled. 510 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any 511 * of the SC1n[COCO] flags is asserted. 512 */ 513 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 514 #define ADC_SC2_ACREN_MASK (0x8U) 515 #define ADC_SC2_ACREN_SHIFT (3U) 516 /*! ACREN - Compare Function Range Enable 517 * 0b0..Range function disabled. Only CV1 is compared. 518 * 0b1..Range function enabled. Both CV1 and CV2 are compared. 519 */ 520 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 521 #define ADC_SC2_ACFGT_MASK (0x10U) 522 #define ADC_SC2_ACFGT_SHIFT (4U) 523 /*! ACFGT - Compare Function Greater Than Enable 524 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality 525 * based on the values placed in CV1 and CV2. 526 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the 527 * values placed in CV1 and CV2. 528 */ 529 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 530 #define ADC_SC2_ACFE_MASK (0x20U) 531 #define ADC_SC2_ACFE_SHIFT (5U) 532 /*! ACFE - Compare Function Enable 533 * 0b0..Compare function disabled. 534 * 0b1..Compare function enabled. 535 */ 536 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 537 #define ADC_SC2_ADTRG_MASK (0x40U) 538 #define ADC_SC2_ADTRG_SHIFT (6U) 539 /*! ADTRG - Conversion Trigger Select 540 * 0b0..Software trigger selected. 541 * 0b1..Hardware trigger selected. 542 */ 543 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 544 #define ADC_SC2_ADACT_MASK (0x80U) 545 #define ADC_SC2_ADACT_SHIFT (7U) 546 /*! ADACT - Conversion Active 547 * 0b0..Conversion not in progress. 548 * 0b1..Conversion in progress. 549 */ 550 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 551 /*! @} */ 552 553 /*! @name SC3 - Status and Control Register 3 */ 554 /*! @{ */ 555 #define ADC_SC3_AVGS_MASK (0x3U) 556 #define ADC_SC3_AVGS_SHIFT (0U) 557 /*! AVGS - Hardware Average Select 558 * 0b00..4 samples averaged. 559 * 0b01..8 samples averaged. 560 * 0b10..16 samples averaged. 561 * 0b11..32 samples averaged. 562 */ 563 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 564 #define ADC_SC3_AVGE_MASK (0x4U) 565 #define ADC_SC3_AVGE_SHIFT (2U) 566 /*! AVGE - Hardware Average Enable 567 * 0b0..Hardware average function disabled. 568 * 0b1..Hardware average function enabled. 569 */ 570 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 571 #define ADC_SC3_ADCO_MASK (0x8U) 572 #define ADC_SC3_ADCO_SHIFT (3U) 573 /*! ADCO - Continuous Conversion Enable 574 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after 575 * initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is 576 * enabled, that is, AVGE=1, after initiating a conversion. 577 */ 578 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 579 #define ADC_SC3_CALF_MASK (0x40U) 580 #define ADC_SC3_CALF_SHIFT (6U) 581 /*! CALF - Calibration Failed Flag 582 * 0b0..Calibration completed normally. 583 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. 584 */ 585 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 586 #define ADC_SC3_CAL_MASK (0x80U) 587 #define ADC_SC3_CAL_SHIFT (7U) 588 /*! CAL - Calibration 589 */ 590 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 591 /*! @} */ 592 593 /*! @name OFS - ADC Offset Correction Register */ 594 /*! @{ */ 595 #define ADC_OFS_OFS_MASK (0xFFFFU) 596 #define ADC_OFS_OFS_SHIFT (0U) 597 /*! OFS - Offset Error Correction Value 598 */ 599 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 600 /*! @} */ 601 602 /*! @name PG - ADC Plus-Side Gain Register */ 603 /*! @{ */ 604 #define ADC_PG_PG_MASK (0xFFFFU) 605 #define ADC_PG_PG_SHIFT (0U) 606 /*! PG - Plus-Side Gain 607 */ 608 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 609 /*! @} */ 610 611 /*! @name MG - ADC Minus-Side Gain Register */ 612 /*! @{ */ 613 #define ADC_MG_MG_MASK (0xFFFFU) 614 #define ADC_MG_MG_SHIFT (0U) 615 /*! MG - Minus-Side Gain 616 */ 617 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) 618 /*! @} */ 619 620 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ 621 /*! @{ */ 622 #define ADC_CLPD_CLPD_MASK (0x3FU) 623 #define ADC_CLPD_CLPD_SHIFT (0U) 624 /*! CLPD - Calibration Value 625 */ 626 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 627 /*! @} */ 628 629 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ 630 /*! @{ */ 631 #define ADC_CLPS_CLPS_MASK (0x3FU) 632 #define ADC_CLPS_CLPS_SHIFT (0U) 633 /*! CLPS - Calibration Value 634 */ 635 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 636 /*! @} */ 637 638 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ 639 /*! @{ */ 640 #define ADC_CLP4_CLP4_MASK (0x3FFU) 641 #define ADC_CLP4_CLP4_SHIFT (0U) 642 /*! CLP4 - Calibration Value 643 */ 644 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 645 /*! @} */ 646 647 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ 648 /*! @{ */ 649 #define ADC_CLP3_CLP3_MASK (0x1FFU) 650 #define ADC_CLP3_CLP3_SHIFT (0U) 651 /*! CLP3 - Calibration Value 652 */ 653 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 654 /*! @} */ 655 656 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ 657 /*! @{ */ 658 #define ADC_CLP2_CLP2_MASK (0xFFU) 659 #define ADC_CLP2_CLP2_SHIFT (0U) 660 /*! CLP2 - Calibration Value 661 */ 662 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 663 /*! @} */ 664 665 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ 666 /*! @{ */ 667 #define ADC_CLP1_CLP1_MASK (0x7FU) 668 #define ADC_CLP1_CLP1_SHIFT (0U) 669 /*! CLP1 - Calibration Value 670 */ 671 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 672 /*! @} */ 673 674 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ 675 /*! @{ */ 676 #define ADC_CLP0_CLP0_MASK (0x3FU) 677 #define ADC_CLP0_CLP0_SHIFT (0U) 678 /*! CLP0 - Calibration Value 679 */ 680 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 681 /*! @} */ 682 683 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ 684 /*! @{ */ 685 #define ADC_CLMD_CLMD_MASK (0x3FU) 686 #define ADC_CLMD_CLMD_SHIFT (0U) 687 /*! CLMD - Calibration Value 688 */ 689 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) 690 /*! @} */ 691 692 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ 693 /*! @{ */ 694 #define ADC_CLMS_CLMS_MASK (0x3FU) 695 #define ADC_CLMS_CLMS_SHIFT (0U) 696 /*! CLMS - Calibration Value 697 */ 698 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) 699 /*! @} */ 700 701 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ 702 /*! @{ */ 703 #define ADC_CLM4_CLM4_MASK (0x3FFU) 704 #define ADC_CLM4_CLM4_SHIFT (0U) 705 /*! CLM4 - Calibration Value 706 */ 707 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) 708 /*! @} */ 709 710 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ 711 /*! @{ */ 712 #define ADC_CLM3_CLM3_MASK (0x1FFU) 713 #define ADC_CLM3_CLM3_SHIFT (0U) 714 /*! CLM3 - Calibration Value 715 */ 716 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) 717 /*! @} */ 718 719 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ 720 /*! @{ */ 721 #define ADC_CLM2_CLM2_MASK (0xFFU) 722 #define ADC_CLM2_CLM2_SHIFT (0U) 723 /*! CLM2 - Calibration Value 724 */ 725 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) 726 /*! @} */ 727 728 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ 729 /*! @{ */ 730 #define ADC_CLM1_CLM1_MASK (0x7FU) 731 #define ADC_CLM1_CLM1_SHIFT (0U) 732 /*! CLM1 - Calibration Value 733 */ 734 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) 735 /*! @} */ 736 737 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ 738 /*! @{ */ 739 #define ADC_CLM0_CLM0_MASK (0x3FU) 740 #define ADC_CLM0_CLM0_SHIFT (0U) 741 /*! CLM0 - Calibration Value 742 */ 743 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) 744 /*! @} */ 745 746 /*! 747 * @} 748 */ /* end of group ADC_Register_Masks */ 749 750 /* ADC - Peripheral instance base addresses */ 751 /** Peripheral ADC0 base address */ 752 #define ADC0_BASE (0x4003B000u) 753 /** Peripheral ADC0 base pointer */ 754 #define ADC0 ((ADC_Type *)ADC0_BASE) 755 /** Array initializer of ADC peripheral base addresses */ 756 #define ADC_BASE_ADDRS \ 757 { \ 758 ADC0_BASE \ 759 } 760 /** Array initializer of ADC peripheral base pointers */ 761 #define ADC_BASE_PTRS \ 762 { \ 763 ADC0 \ 764 } 765 /** Interrupt vectors for the ADC peripheral type */ 766 #define ADC_IRQS \ 767 { \ 768 ADC0_IRQn \ 769 } 770 771 /*! 772 * @} 773 */ /* end of group ADC_Peripheral_Access_Layer */ 774 775 /* ---------------------------------------------------------------------------- 776 -- CMP Peripheral Access Layer 777 ---------------------------------------------------------------------------- */ 778 779 /*! 780 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 781 * @{ 782 */ 783 784 /** CMP - Register Layout Typedef */ 785 typedef struct 786 { 787 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 788 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 789 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 790 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 791 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 792 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 793 } CMP_Type; 794 795 /* ---------------------------------------------------------------------------- 796 -- CMP Register Masks 797 ---------------------------------------------------------------------------- */ 798 799 /*! 800 * @addtogroup CMP_Register_Masks CMP Register Masks 801 * @{ 802 */ 803 804 /*! @name CR0 - CMP Control Register 0 */ 805 /*! @{ */ 806 #define CMP_CR0_HYSTCTR_MASK (0x3U) 807 #define CMP_CR0_HYSTCTR_SHIFT (0U) 808 /*! HYSTCTR - Comparator hard block hysteresis control 809 * 0b00..Level 0 810 * 0b01..Level 1 811 * 0b10..Level 2 812 * 0b11..Level 3 813 */ 814 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 815 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 816 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 817 /*! FILTER_CNT - Filter Sample Count 818 * 0b000..Filter is disabled. SE = 0, COUT = COUTA. 819 * 0b001..One sample must agree. The comparator output is simply sampled. 820 * 0b010..2 consecutive samples must agree. 821 * 0b011..3 consecutive samples must agree. 822 * 0b100..4 consecutive samples must agree. 823 * 0b101..5 consecutive samples must agree. 824 * 0b110..6 consecutive samples must agree. 825 * 0b111..7 consecutive samples must agree. 826 */ 827 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 828 /*! @} */ 829 830 /*! @name CR1 - CMP Control Register 1 */ 831 /*! @{ */ 832 #define CMP_CR1_EN_MASK (0x1U) 833 #define CMP_CR1_EN_SHIFT (0U) 834 /*! EN - Comparator Module Enable 835 * 0b0..Analog Comparator is disabled. 836 * 0b1..Analog Comparator is enabled. 837 */ 838 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 839 #define CMP_CR1_OPE_MASK (0x2U) 840 #define CMP_CR1_OPE_SHIFT (1U) 841 /*! OPE - Comparator Output Pin Enable 842 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has 843 * no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on 844 * the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has 845 * no effect. 846 */ 847 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 848 #define CMP_CR1_COS_MASK (0x4U) 849 #define CMP_CR1_COS_SHIFT (2U) 850 /*! COS - Comparator Output Select 851 * 0b0..Set the filtered comparator output (CMPO) to equal COUT. 852 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. 853 */ 854 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 855 #define CMP_CR1_INV_MASK (0x8U) 856 #define CMP_CR1_INV_SHIFT (3U) 857 /*! INV - Comparator INVERT 858 * 0b0..Does not invert the comparator output. 859 * 0b1..Inverts the comparator output. 860 */ 861 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 862 #define CMP_CR1_PMODE_MASK (0x10U) 863 #define CMP_CR1_PMODE_SHIFT (4U) 864 /*! PMODE - Power Mode Select 865 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower 866 * current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation 867 * delay and higher current consumption. 868 */ 869 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 870 #define CMP_CR1_TRIGM_MASK (0x20U) 871 #define CMP_CR1_TRIGM_SHIFT (5U) 872 /*! TRIGM - Trigger Mode Enable 873 * 0b0..Trigger mode is disabled. 874 * 0b1..Trigger mode is enabled. 875 */ 876 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) 877 #define CMP_CR1_WE_MASK (0x40U) 878 #define CMP_CR1_WE_SHIFT (6U) 879 /*! WE - Windowing Enable 880 * 0b0..Windowing mode is not selected. 881 * 0b1..Windowing mode is selected. 882 */ 883 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 884 #define CMP_CR1_SE_MASK (0x80U) 885 #define CMP_CR1_SE_SHIFT (7U) 886 /*! SE - Sample Enable 887 * 0b0..Sampling mode is not selected. 888 * 0b1..Sampling mode is selected. 889 */ 890 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 891 /*! @} */ 892 893 /*! @name FPR - CMP Filter Period Register */ 894 /*! @{ */ 895 #define CMP_FPR_FILT_PER_MASK (0xFFU) 896 #define CMP_FPR_FILT_PER_SHIFT (0U) 897 /*! FILT_PER - Filter Sample Period 898 */ 899 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 900 /*! @} */ 901 902 /*! @name SCR - CMP Status and Control Register */ 903 /*! @{ */ 904 #define CMP_SCR_COUT_MASK (0x1U) 905 #define CMP_SCR_COUT_SHIFT (0U) 906 /*! COUT - Analog Comparator Output 907 */ 908 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 909 #define CMP_SCR_CFF_MASK (0x2U) 910 #define CMP_SCR_CFF_SHIFT (1U) 911 /*! CFF - Analog Comparator Flag Falling 912 * 0b0..Falling-edge on COUT has not been detected. 913 * 0b1..Falling-edge on COUT has occurred. 914 */ 915 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 916 #define CMP_SCR_CFR_MASK (0x4U) 917 #define CMP_SCR_CFR_SHIFT (2U) 918 /*! CFR - Analog Comparator Flag Rising 919 * 0b0..Rising-edge on COUT has not been detected. 920 * 0b1..Rising-edge on COUT has occurred. 921 */ 922 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 923 #define CMP_SCR_IEF_MASK (0x8U) 924 #define CMP_SCR_IEF_SHIFT (3U) 925 /*! IEF - Comparator Interrupt Enable Falling 926 * 0b0..Interrupt is disabled. 927 * 0b1..Interrupt is enabled. 928 */ 929 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 930 #define CMP_SCR_IER_MASK (0x10U) 931 #define CMP_SCR_IER_SHIFT (4U) 932 /*! IER - Comparator Interrupt Enable Rising 933 * 0b0..Interrupt is disabled. 934 * 0b1..Interrupt is enabled. 935 */ 936 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 937 #define CMP_SCR_DMAEN_MASK (0x40U) 938 #define CMP_SCR_DMAEN_SHIFT (6U) 939 /*! DMAEN - DMA Enable Control 940 * 0b0..DMA is disabled. 941 * 0b1..DMA is enabled. 942 */ 943 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 944 /*! @} */ 945 946 /*! @name DACCR - DAC Control Register */ 947 /*! @{ */ 948 #define CMP_DACCR_VOSEL_MASK (0x3FU) 949 #define CMP_DACCR_VOSEL_SHIFT (0U) 950 /*! VOSEL - DAC Output Voltage Select 951 */ 952 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 953 #define CMP_DACCR_VRSEL_MASK (0x40U) 954 #define CMP_DACCR_VRSEL_SHIFT (6U) 955 /*! VRSEL - Supply Voltage Reference Source Select 956 * 0b0..Vin1 is selected as resistor ladder network supply reference. 957 * 0b1..Vin2 is selected as resistor ladder network supply reference. 958 */ 959 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 960 #define CMP_DACCR_DACEN_MASK (0x80U) 961 #define CMP_DACCR_DACEN_SHIFT (7U) 962 /*! DACEN - DAC Enable 963 * 0b0..DAC is disabled. 964 * 0b1..DAC is enabled. 965 */ 966 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 967 /*! @} */ 968 969 /*! @name MUXCR - MUX Control Register */ 970 /*! @{ */ 971 #define CMP_MUXCR_MSEL_MASK (0x7U) 972 #define CMP_MUXCR_MSEL_SHIFT (0U) 973 /*! MSEL - Minus Input Mux Control 974 * 0b000..IN0 975 * 0b001..IN1 976 * 0b010..IN2 977 * 0b011..IN3 978 * 0b100..IN4 979 * 0b101..IN5 980 * 0b110..IN6 981 * 0b111..IN7 982 */ 983 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 984 #define CMP_MUXCR_PSEL_MASK (0x38U) 985 #define CMP_MUXCR_PSEL_SHIFT (3U) 986 /*! PSEL - Plus Input Mux Control 987 * 0b000..IN0 988 * 0b001..IN1 989 * 0b010..IN2 990 * 0b011..IN3 991 * 0b100..IN4 992 * 0b101..IN5 993 * 0b110..IN6 994 * 0b111..IN7 995 */ 996 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 997 #define CMP_MUXCR_PSTM_MASK (0x80U) 998 #define CMP_MUXCR_PSTM_SHIFT (7U) 999 /*! PSTM - Pass Through Mode Enable 1000 * 0b0..Pass Through Mode is disabled. 1001 * 0b1..Pass Through Mode is enabled. 1002 */ 1003 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) 1004 /*! @} */ 1005 1006 /*! 1007 * @} 1008 */ /* end of group CMP_Register_Masks */ 1009 1010 /* CMP - Peripheral instance base addresses */ 1011 /** Peripheral CMP0 base address */ 1012 #define CMP0_BASE (0x40073000u) 1013 /** Peripheral CMP0 base pointer */ 1014 #define CMP0 ((CMP_Type *)CMP0_BASE) 1015 /** Array initializer of CMP peripheral base addresses */ 1016 #define CMP_BASE_ADDRS \ 1017 { \ 1018 CMP0_BASE \ 1019 } 1020 /** Array initializer of CMP peripheral base pointers */ 1021 #define CMP_BASE_PTRS \ 1022 { \ 1023 CMP0 \ 1024 } 1025 /** Interrupt vectors for the CMP peripheral type */ 1026 #define CMP_IRQS \ 1027 { \ 1028 CMP0_IRQn \ 1029 } 1030 1031 /*! 1032 * @} 1033 */ /* end of group CMP_Peripheral_Access_Layer */ 1034 1035 /* ---------------------------------------------------------------------------- 1036 -- DAC Peripheral Access Layer 1037 ---------------------------------------------------------------------------- */ 1038 1039 /*! 1040 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 1041 * @{ 1042 */ 1043 1044 /** DAC - Register Layout Typedef */ 1045 typedef struct 1046 { 1047 struct 1048 { /* offset: 0x0, array step: 0x2 */ 1049 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 1050 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 1051 } DAT[2]; 1052 uint8_t RESERVED_0[28]; 1053 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 1054 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 1055 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 1056 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 1057 } DAC_Type; 1058 1059 /* ---------------------------------------------------------------------------- 1060 -- DAC Register Masks 1061 ---------------------------------------------------------------------------- */ 1062 1063 /*! 1064 * @addtogroup DAC_Register_Masks DAC Register Masks 1065 * @{ 1066 */ 1067 1068 /*! @name DATL - DAC Data Low Register */ 1069 /*! @{ */ 1070 #define DAC_DATL_DATA0_MASK (0xFFU) 1071 #define DAC_DATL_DATA0_SHIFT (0U) 1072 /*! DATA0 - DATA0 1073 */ 1074 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) 1075 /*! @} */ 1076 1077 /* The count of DAC_DATL */ 1078 #define DAC_DATL_COUNT (2U) 1079 1080 /*! @name DATH - DAC Data High Register */ 1081 /*! @{ */ 1082 #define DAC_DATH_DATA1_MASK (0xFU) 1083 #define DAC_DATH_DATA1_SHIFT (0U) 1084 /*! DATA1 - DATA1 1085 */ 1086 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) 1087 /*! @} */ 1088 1089 /* The count of DAC_DATH */ 1090 #define DAC_DATH_COUNT (2U) 1091 1092 /*! @name SR - DAC Status Register */ 1093 /*! @{ */ 1094 #define DAC_SR_DACBFRPBF_MASK (0x1U) 1095 #define DAC_SR_DACBFRPBF_SHIFT (0U) 1096 /*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag 1097 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP]. 1098 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP]. 1099 */ 1100 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) 1101 #define DAC_SR_DACBFRPTF_MASK (0x2U) 1102 #define DAC_SR_DACBFRPTF_SHIFT (1U) 1103 /*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag 1104 * 0b0..The DAC buffer read pointer is not zero. 1105 * 0b1..The DAC buffer read pointer is zero. 1106 */ 1107 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) 1108 /*! @} */ 1109 1110 /*! @name C0 - DAC Control Register */ 1111 /*! @{ */ 1112 #define DAC_C0_DACBBIEN_MASK (0x1U) 1113 #define DAC_C0_DACBBIEN_SHIFT (0U) 1114 /*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable 1115 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled. 1116 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled. 1117 */ 1118 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) 1119 #define DAC_C0_DACBTIEN_MASK (0x2U) 1120 #define DAC_C0_DACBTIEN_SHIFT (1U) 1121 /*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable 1122 * 0b0..The DAC buffer read pointer top flag interrupt is disabled. 1123 * 0b1..The DAC buffer read pointer top flag interrupt is enabled. 1124 */ 1125 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) 1126 #define DAC_C0_LPEN_MASK (0x8U) 1127 #define DAC_C0_LPEN_SHIFT (3U) 1128 /*! LPEN - DAC Low Power Control 1129 * 0b0..High-Power mode 1130 * 0b1..Low-Power mode 1131 */ 1132 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) 1133 #define DAC_C0_DACSWTRG_MASK (0x10U) 1134 #define DAC_C0_DACSWTRG_SHIFT (4U) 1135 /*! DACSWTRG - DAC Software Trigger 1136 * 0b0..The DAC soft trigger is not valid. 1137 * 0b1..The DAC soft trigger is valid. 1138 */ 1139 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) 1140 #define DAC_C0_DACTRGSEL_MASK (0x20U) 1141 #define DAC_C0_DACTRGSEL_SHIFT (5U) 1142 /*! DACTRGSEL - DAC Trigger Select 1143 * 0b0..The DAC hardware trigger is selected. 1144 * 0b1..The DAC software trigger is selected. 1145 */ 1146 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) 1147 #define DAC_C0_DACRFS_MASK (0x40U) 1148 #define DAC_C0_DACRFS_SHIFT (6U) 1149 /*! DACRFS - DAC Reference Select 1150 * 0b0..The DAC selects DACREF_1 as the reference voltage. 1151 * 0b1..The DAC selects DACREF_2 as the reference voltage. 1152 */ 1153 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) 1154 #define DAC_C0_DACEN_MASK (0x80U) 1155 #define DAC_C0_DACEN_SHIFT (7U) 1156 /*! DACEN - DAC Enable 1157 * 0b0..The DAC system is disabled. 1158 * 0b1..The DAC system is enabled. 1159 */ 1160 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) 1161 /*! @} */ 1162 1163 /*! @name C1 - DAC Control Register 1 */ 1164 /*! @{ */ 1165 #define DAC_C1_DACBFEN_MASK (0x1U) 1166 #define DAC_C1_DACBFEN_SHIFT (0U) 1167 /*! DACBFEN - DAC Buffer Enable 1168 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer. 1169 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means 1170 * converted data can be from any word of the buffer. 1171 */ 1172 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) 1173 #define DAC_C1_DACBFMD_MASK (0x6U) 1174 #define DAC_C1_DACBFMD_SHIFT (1U) 1175 /*! DACBFMD - DAC Buffer Work Mode Select 1176 * 0b00..Normal mode 1177 * 0b01..Reserved 1178 * 0b10..One-Time Scan mode 1179 * 0b11..FIFO mode 1180 */ 1181 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) 1182 #define DAC_C1_DMAEN_MASK (0x80U) 1183 #define DAC_C1_DMAEN_SHIFT (7U) 1184 /*! DMAEN - DMA Enable Select 1185 * 0b0..DMA is disabled. 1186 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The 1187 * interrupts will not be presented on this module at the same time. 1188 */ 1189 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) 1190 /*! @} */ 1191 1192 /*! @name C2 - DAC Control Register 2 */ 1193 /*! @{ */ 1194 #define DAC_C2_DACBFUP_MASK (0x1U) 1195 #define DAC_C2_DACBFUP_SHIFT (0U) 1196 /*! DACBFUP - DAC Buffer Upper Limit 1197 */ 1198 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) 1199 #define DAC_C2_DACBFRP_MASK (0x10U) 1200 #define DAC_C2_DACBFRP_SHIFT (4U) 1201 /*! DACBFRP - DAC Buffer Read Pointer 1202 */ 1203 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) 1204 /*! @} */ 1205 1206 /*! 1207 * @} 1208 */ /* end of group DAC_Register_Masks */ 1209 1210 /* DAC - Peripheral instance base addresses */ 1211 /** Peripheral DAC0 base address */ 1212 #define DAC0_BASE (0x4003F000u) 1213 /** Peripheral DAC0 base pointer */ 1214 #define DAC0 ((DAC_Type *)DAC0_BASE) 1215 /** Array initializer of DAC peripheral base addresses */ 1216 #define DAC_BASE_ADDRS \ 1217 { \ 1218 DAC0_BASE \ 1219 } 1220 /** Array initializer of DAC peripheral base pointers */ 1221 #define DAC_BASE_PTRS \ 1222 { \ 1223 DAC0 \ 1224 } 1225 /** Interrupt vectors for the DAC peripheral type */ 1226 #define DAC_IRQS \ 1227 { \ 1228 DAC0_IRQn \ 1229 } 1230 1231 /*! 1232 * @} 1233 */ /* end of group DAC_Peripheral_Access_Layer */ 1234 1235 /* ---------------------------------------------------------------------------- 1236 -- DMA Peripheral Access Layer 1237 ---------------------------------------------------------------------------- */ 1238 1239 /*! 1240 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 1241 * @{ 1242 */ 1243 1244 /** DMA - Register Layout Typedef */ 1245 typedef struct 1246 { 1247 uint8_t RESERVED_0[256]; 1248 struct 1249 { /* offset: 0x100, array step: 0x10 */ 1250 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 1251 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 1252 union 1253 { /* offset: 0x108, array step: 0x10 */ 1254 struct 1255 { /* offset: 0x108, array step: 0x10 */ 1256 uint8_t RESERVED_0[3]; 1257 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 1258 } DMA_DSR_ACCESS8BIT; 1259 __IO uint32_t 1260 DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 1261 }; 1262 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 1263 } DMA[4]; 1264 } DMA_Type; 1265 1266 /* ---------------------------------------------------------------------------- 1267 -- DMA Register Masks 1268 ---------------------------------------------------------------------------- */ 1269 1270 /*! 1271 * @addtogroup DMA_Register_Masks DMA Register Masks 1272 * @{ 1273 */ 1274 1275 /*! @name SAR - Source Address Register */ 1276 /*! @{ */ 1277 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU) 1278 #define DMA_SAR_SAR_SHIFT (0U) 1279 /*! SAR - SAR 1280 */ 1281 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) 1282 /*! @} */ 1283 1284 /* The count of DMA_SAR */ 1285 #define DMA_SAR_COUNT (4U) 1286 1287 /*! @name DAR - Destination Address Register */ 1288 /*! @{ */ 1289 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU) 1290 #define DMA_DAR_DAR_SHIFT (0U) 1291 /*! DAR - DAR 1292 */ 1293 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) 1294 /*! @} */ 1295 1296 /* The count of DMA_DAR */ 1297 #define DMA_DAR_COUNT (4U) 1298 1299 /* The count of DMA_DSR */ 1300 #define DMA_DSR_COUNT (4U) 1301 1302 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */ 1303 /*! @{ */ 1304 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) 1305 #define DMA_DSR_BCR_BCR_SHIFT (0U) 1306 /*! BCR - BCR 1307 */ 1308 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) 1309 #define DMA_DSR_BCR_DONE_MASK (0x1000000U) 1310 #define DMA_DSR_BCR_DONE_SHIFT (24U) 1311 /*! DONE - Transactions Done 1312 * 0b0..DMA transfer is not yet complete. Writing a 0 has no effect. 1313 * 0b1..DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an 1314 * interrupt service routine to clear the DMA interrupt and error bits. 1315 */ 1316 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) 1317 #define DMA_DSR_BCR_BSY_MASK (0x2000000U) 1318 #define DMA_DSR_BCR_BSY_SHIFT (25U) 1319 /*! BSY - Busy 1320 * 0b0..DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1321 * 0b1..BSY is set the first time the channel is enabled after a transfer is initiated. 1322 */ 1323 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) 1324 #define DMA_DSR_BCR_REQ_MASK (0x4000000U) 1325 #define DMA_DSR_BCR_REQ_SHIFT (26U) 1326 /*! REQ - Request 1327 * 0b0..No request is pending or the channel is currently active. Cleared when the channel is selected. 1328 * 0b1..The DMA channel has a transfer remaining and the channel is not selected. 1329 */ 1330 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) 1331 #define DMA_DSR_BCR_BED_MASK (0x10000000U) 1332 #define DMA_DSR_BCR_BED_SHIFT (28U) 1333 /*! BED - Bus Error on Destination 1334 * 0b0..No bus error occurred. 1335 * 0b1..The DMA channel terminated with a bus error during the write portion of a transfer. 1336 */ 1337 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) 1338 #define DMA_DSR_BCR_BES_MASK (0x20000000U) 1339 #define DMA_DSR_BCR_BES_SHIFT (29U) 1340 /*! BES - Bus Error on Source 1341 * 0b0..No bus error occurred. 1342 * 0b1..The DMA channel terminated with a bus error during the read portion of a transfer. 1343 */ 1344 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) 1345 #define DMA_DSR_BCR_CE_MASK (0x40000000U) 1346 #define DMA_DSR_BCR_CE_SHIFT (30U) 1347 /*! CE - Configuration Error 1348 * 0b0..No configuration error exists. 1349 * 0b1..A configuration error has occurred. 1350 */ 1351 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) 1352 /*! @} */ 1353 1354 /* The count of DMA_DSR_BCR */ 1355 #define DMA_DSR_BCR_COUNT (4U) 1356 1357 /*! @name DCR - DMA Control Register */ 1358 /*! @{ */ 1359 #define DMA_DCR_LCH2_MASK (0x3U) 1360 #define DMA_DCR_LCH2_SHIFT (0U) 1361 /*! LCH2 - Link Channel 2 1362 * 0b00..DMA Channel 0 1363 * 0b01..DMA Channel 1 1364 * 0b10..DMA Channel 2 1365 * 0b11..DMA Channel 3 1366 */ 1367 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) 1368 #define DMA_DCR_LCH1_MASK (0xCU) 1369 #define DMA_DCR_LCH1_SHIFT (2U) 1370 /*! LCH1 - Link Channel 1 1371 * 0b00..DMA Channel 0 1372 * 0b01..DMA Channel 1 1373 * 0b10..DMA Channel 2 1374 * 0b11..DMA Channel 3 1375 */ 1376 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) 1377 #define DMA_DCR_LINKCC_MASK (0x30U) 1378 #define DMA_DCR_LINKCC_SHIFT (4U) 1379 /*! LINKCC - Link Channel Control 1380 * 0b00..No channel-to-channel linking 1381 * 0b01..Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR 1382 * decrements to 0. 0b10..Perform a link to channel LCH1 after each cycle-steal transfer 0b11..Perform a link to channel 1383 * LCH1 after the BCR decrements to 0. 1384 */ 1385 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) 1386 #define DMA_DCR_D_REQ_MASK (0x80U) 1387 #define DMA_DCR_D_REQ_SHIFT (7U) 1388 /*! D_REQ - Disable Request 1389 * 0b0..ERQ bit is not affected. 1390 * 0b1..ERQ bit is cleared when the BCR is exhausted. 1391 */ 1392 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) 1393 #define DMA_DCR_DMOD_MASK (0xF00U) 1394 #define DMA_DCR_DMOD_SHIFT (8U) 1395 /*! DMOD - Destination Address Modulo 1396 * 0b0000..Buffer disabled 1397 * 0b0001..Circular buffer size is 16 bytes 1398 * 0b0010..Circular buffer size is 32 bytes 1399 * 0b0011..Circular buffer size is 64 bytes 1400 * 0b0100..Circular buffer size is 128 bytes 1401 * 0b0101..Circular buffer size is 256 bytes 1402 * 0b0110..Circular buffer size is 512 bytes 1403 * 0b0111..Circular buffer size is 1 KB 1404 * 0b1000..Circular buffer size is 2 KB 1405 * 0b1001..Circular buffer size is 4 KB 1406 * 0b1010..Circular buffer size is 8 KB 1407 * 0b1011..Circular buffer size is 16 KB 1408 * 0b1100..Circular buffer size is 32 KB 1409 * 0b1101..Circular buffer size is 64 KB 1410 * 0b1110..Circular buffer size is 128 KB 1411 * 0b1111..Circular buffer size is 256 KB 1412 */ 1413 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) 1414 #define DMA_DCR_SMOD_MASK (0xF000U) 1415 #define DMA_DCR_SMOD_SHIFT (12U) 1416 /*! SMOD - Source Address Modulo 1417 * 0b0000..Buffer disabled 1418 * 0b0001..Circular buffer size is 16 bytes. 1419 * 0b0010..Circular buffer size is 32 bytes. 1420 * 0b0011..Circular buffer size is 64 bytes. 1421 * 0b0100..Circular buffer size is 128 bytes. 1422 * 0b0101..Circular buffer size is 256 bytes. 1423 * 0b0110..Circular buffer size is 512 bytes. 1424 * 0b0111..Circular buffer size is 1 KB. 1425 * 0b1000..Circular buffer size is 2 KB. 1426 * 0b1001..Circular buffer size is 4 KB. 1427 * 0b1010..Circular buffer size is 8 KB. 1428 * 0b1011..Circular buffer size is 16 KB. 1429 * 0b1100..Circular buffer size is 32 KB. 1430 * 0b1101..Circular buffer size is 64 KB. 1431 * 0b1110..Circular buffer size is 128 KB. 1432 * 0b1111..Circular buffer size is 256 KB. 1433 */ 1434 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) 1435 #define DMA_DCR_START_MASK (0x10000U) 1436 #define DMA_DCR_START_SHIFT (16U) 1437 /*! START - Start Transfer 1438 * 0b0..DMA inactive 1439 * 0b1..The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after 1440 * one module clock and always reads as logic 0. 1441 */ 1442 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) 1443 #define DMA_DCR_DSIZE_MASK (0x60000U) 1444 #define DMA_DCR_DSIZE_SHIFT (17U) 1445 /*! DSIZE - Destination Size 1446 * 0b00..32-bit 1447 * 0b01..8-bit 1448 * 0b10..16-bit 1449 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) 1450 */ 1451 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) 1452 #define DMA_DCR_DINC_MASK (0x80000U) 1453 #define DMA_DCR_DINC_SHIFT (19U) 1454 /*! DINC - Destination Increment 1455 * 0b0..No change to the DAR after a successful transfer. 1456 * 0b1..The DAR increments by 1, 2, 4 depending upon the size of the transfer. 1457 */ 1458 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) 1459 #define DMA_DCR_SSIZE_MASK (0x300000U) 1460 #define DMA_DCR_SSIZE_SHIFT (20U) 1461 /*! SSIZE - Source Size 1462 * 0b00..32-bit 1463 * 0b01..8-bit 1464 * 0b10..16-bit 1465 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) 1466 */ 1467 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) 1468 #define DMA_DCR_SINC_MASK (0x400000U) 1469 #define DMA_DCR_SINC_SHIFT (22U) 1470 /*! SINC - Source Increment 1471 * 0b0..No change to SAR after a successful transfer. 1472 * 0b1..The SAR increments by 1, 2, 4 as determined by the transfer size. 1473 */ 1474 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) 1475 #define DMA_DCR_EADREQ_MASK (0x800000U) 1476 #define DMA_DCR_EADREQ_SHIFT (23U) 1477 /*! EADREQ - Enable asynchronous DMA requests 1478 * 0b0..Disabled 1479 * 0b1..Enabled 1480 */ 1481 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) 1482 #define DMA_DCR_AA_MASK (0x10000000U) 1483 #define DMA_DCR_AA_SHIFT (28U) 1484 /*! AA - Auto-align 1485 * 0b0..Auto-align disabled 1486 * 0b1..If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, 1487 * destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If 1488 * auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 1489 */ 1490 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) 1491 #define DMA_DCR_CS_MASK (0x20000000U) 1492 #define DMA_DCR_CS_SHIFT (29U) 1493 /*! CS - Cycle Steal 1494 * 0b0..DMA continuously makes read/write transfers until the BCR decrements to 0. 1495 * 0b1..Forces a single read/write transfer per request. 1496 */ 1497 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) 1498 #define DMA_DCR_ERQ_MASK (0x40000000U) 1499 #define DMA_DCR_ERQ_SHIFT (30U) 1500 /*! ERQ - Enable Peripheral Request 1501 * 0b0..Peripheral request is ignored. 1502 * 0b1..Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always 1503 * enabled. 1504 */ 1505 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) 1506 #define DMA_DCR_EINT_MASK (0x80000000U) 1507 #define DMA_DCR_EINT_SHIFT (31U) 1508 /*! EINT - Enable Interrupt on Completion of Transfer 1509 * 0b0..No interrupt is generated. 1510 * 0b1..Interrupt signal is enabled. 1511 */ 1512 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) 1513 /*! @} */ 1514 1515 /* The count of DMA_DCR */ 1516 #define DMA_DCR_COUNT (4U) 1517 1518 /*! 1519 * @} 1520 */ /* end of group DMA_Register_Masks */ 1521 1522 /* DMA - Peripheral instance base addresses */ 1523 /** Peripheral DMA base address */ 1524 #define DMA_BASE (0x40008000u) 1525 /** Peripheral DMA base pointer */ 1526 #define DMA0 ((DMA_Type *)DMA_BASE) 1527 /** Array initializer of DMA peripheral base addresses */ 1528 #define DMA_BASE_ADDRS \ 1529 { \ 1530 DMA_BASE \ 1531 } 1532 /** Array initializer of DMA peripheral base pointers */ 1533 #define DMA_BASE_PTRS \ 1534 { \ 1535 DMA0 \ 1536 } 1537 /** Interrupt vectors for the DMA peripheral type */ 1538 #define DMA_CHN_IRQS \ 1539 { \ 1540 { \ 1541 DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn \ 1542 } \ 1543 } 1544 1545 /*! 1546 * @} 1547 */ /* end of group DMA_Peripheral_Access_Layer */ 1548 1549 /* ---------------------------------------------------------------------------- 1550 -- DMAMUX Peripheral Access Layer 1551 ---------------------------------------------------------------------------- */ 1552 1553 /*! 1554 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 1555 * @{ 1556 */ 1557 1558 /** DMAMUX - Register Layout Typedef */ 1559 typedef struct 1560 { 1561 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 1562 } DMAMUX_Type; 1563 1564 /* ---------------------------------------------------------------------------- 1565 -- DMAMUX Register Masks 1566 ---------------------------------------------------------------------------- */ 1567 1568 /*! 1569 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 1570 * @{ 1571 */ 1572 1573 /*! @name CHCFG - Channel Configuration register */ 1574 /*! @{ */ 1575 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 1576 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 1577 /*! SOURCE - DMA Channel Source (Slot) 1578 * 0b000000..Disable_Signal 1579 * 0b000010..LPUART0_Rx_Signal 1580 * 0b000011..LPUART0_Tx_Signal 1581 * 0b000100..LPUART1_Rx_Signal 1582 * 0b000101..LPUART1_Tx_Signal 1583 * 0b000110..UART2_Rx_Signal 1584 * 0b000111..UART2_Tx_Signal 1585 * 0b001010..FlexIO_Channel0_Signal 1586 * 0b001011..FlexIO_Channel1_Signal 1587 * 0b001100..FlexIO_Channel2_Signal 1588 * 0b001101..FlexIO_Channel3_Signal 1589 * 0b010000..SPI0_Rx_Signal 1590 * 0b010001..SPI0_Tx_Signal 1591 * 0b010010..SPI1_Rx_Signal 1592 * 0b010011..SPI1_Tx_Signal 1593 * 0b010110..I2C0_Signal 1594 * 0b010111..I2C1_Signal 1595 * 0b011000..TPM0_Channel0_Signal 1596 * 0b011001..TPM0_Channel1_Signal 1597 * 0b011010..TPM0_Channel2_Signal 1598 * 0b011011..TPM0_Channel3_Signal 1599 * 0b011100..TPM0_Channel4_Signal 1600 * 0b011101..TPM0_Channel5_Signal 1601 * 0b100000..TPM1_Channel0_Signal 1602 * 0b100001..TPM1_Channel1_Signal 1603 * 0b100010..TPM2_Channel0_Signal 1604 * 0b100011..TPM2_Channel1_Signal 1605 * 0b101000..ADC0_Signal 1606 * 0b101010..CMP0_Signal 1607 * 0b101101..DAC0_Signal 1608 * 0b110001..Port_A_Signal 1609 * 0b110011..Port_C_Signal 1610 * 0b110100..Port_D_Signal 1611 * 0b110110..TPM0_Overflow_Signal 1612 * 0b110111..TPM1_Overflow_Signal 1613 * 0b111000..TPM2_Overflow_Signal 1614 * 0b111100..AlwaysOn60_Signal 1615 * 0b111101..AlwaysOn61_Signal 1616 * 0b111110..AlwaysOn62_Signal 1617 * 0b111111..AlwaysOn63_Signal 1618 */ 1619 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 1620 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 1621 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 1622 /*! TRIG - DMA Channel Trigger Enable 1623 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the 1624 * specified source to the DMA channel. (Normal mode) 1625 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. 1626 */ 1627 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 1628 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 1629 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 1630 /*! ENBL - DMA Channel Enable 1631 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has 1632 * separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 1633 * 0b1..DMA channel is enabled 1634 */ 1635 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 1636 /*! @} */ 1637 1638 /* The count of DMAMUX_CHCFG */ 1639 #define DMAMUX_CHCFG_COUNT (4U) 1640 1641 /*! 1642 * @} 1643 */ /* end of group DMAMUX_Register_Masks */ 1644 1645 /* DMAMUX - Peripheral instance base addresses */ 1646 /** Peripheral DMAMUX0 base address */ 1647 #define DMAMUX0_BASE (0x40021000u) 1648 /** Peripheral DMAMUX0 base pointer */ 1649 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 1650 /** Array initializer of DMAMUX peripheral base addresses */ 1651 #define DMAMUX_BASE_ADDRS \ 1652 { \ 1653 DMAMUX0_BASE \ 1654 } 1655 /** Array initializer of DMAMUX peripheral base pointers */ 1656 #define DMAMUX_BASE_PTRS \ 1657 { \ 1658 DMAMUX0 \ 1659 } 1660 1661 /*! 1662 * @} 1663 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 1664 1665 /* ---------------------------------------------------------------------------- 1666 -- FGPIO Peripheral Access Layer 1667 ---------------------------------------------------------------------------- */ 1668 1669 /*! 1670 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 1671 * @{ 1672 */ 1673 1674 /** FGPIO - Register Layout Typedef */ 1675 typedef struct 1676 { 1677 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 1678 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 1679 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 1680 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 1681 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 1682 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 1683 } FGPIO_Type; 1684 1685 /* ---------------------------------------------------------------------------- 1686 -- FGPIO Register Masks 1687 ---------------------------------------------------------------------------- */ 1688 1689 /*! 1690 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 1691 * @{ 1692 */ 1693 1694 /*! @name PDOR - Port Data Output Register */ 1695 /*! @{ */ 1696 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 1697 #define FGPIO_PDOR_PDO_SHIFT (0U) 1698 /*! PDO - Port Data Output 1699 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose 1700 * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for 1701 * general-purpose output. 1702 */ 1703 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 1704 /*! @} */ 1705 1706 /*! @name PSOR - Port Set Output Register */ 1707 /*! @{ */ 1708 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 1709 #define FGPIO_PSOR_PTSO_SHIFT (0U) 1710 /*! PTSO - Port Set Output 1711 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1712 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 1713 */ 1714 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 1715 /*! @} */ 1716 1717 /*! @name PCOR - Port Clear Output Register */ 1718 /*! @{ */ 1719 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 1720 #define FGPIO_PCOR_PTCO_SHIFT (0U) 1721 /*! PTCO - Port Clear Output 1722 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1723 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 1724 */ 1725 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 1726 /*! @} */ 1727 1728 /*! @name PTOR - Port Toggle Output Register */ 1729 /*! @{ */ 1730 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 1731 #define FGPIO_PTOR_PTTO_SHIFT (0U) 1732 /*! PTTO - Port Toggle Output 1733 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1734 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 1735 */ 1736 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 1737 /*! @} */ 1738 1739 /*! @name PDIR - Port Data Input Register */ 1740 /*! @{ */ 1741 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 1742 #define FGPIO_PDIR_PDI_SHIFT (0U) 1743 /*! PDI - Port Data Input 1744 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 1745 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 1746 */ 1747 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 1748 /*! @} */ 1749 1750 /*! @name PDDR - Port Data Direction Register */ 1751 /*! @{ */ 1752 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 1753 #define FGPIO_PDDR_PDD_SHIFT (0U) 1754 /*! PDD - Port Data Direction 1755 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 1756 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 1757 */ 1758 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 1759 /*! @} */ 1760 1761 /*! 1762 * @} 1763 */ /* end of group FGPIO_Register_Masks */ 1764 1765 /* FGPIO - Peripheral instance base addresses */ 1766 /** Peripheral FGPIOA base address */ 1767 #define FGPIOA_BASE (0xF8000000u) 1768 /** Peripheral FGPIOA base pointer */ 1769 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 1770 /** Peripheral FGPIOB base address */ 1771 #define FGPIOB_BASE (0xF8000040u) 1772 /** Peripheral FGPIOB base pointer */ 1773 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 1774 /** Peripheral FGPIOC base address */ 1775 #define FGPIOC_BASE (0xF8000080u) 1776 /** Peripheral FGPIOC base pointer */ 1777 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 1778 /** Peripheral FGPIOD base address */ 1779 #define FGPIOD_BASE (0xF80000C0u) 1780 /** Peripheral FGPIOD base pointer */ 1781 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) 1782 /** Peripheral FGPIOE base address */ 1783 #define FGPIOE_BASE (0xF8000100u) 1784 /** Peripheral FGPIOE base pointer */ 1785 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) 1786 /** Array initializer of FGPIO peripheral base addresses */ 1787 #define FGPIO_BASE_ADDRS \ 1788 { \ 1789 FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE \ 1790 } 1791 /** Array initializer of FGPIO peripheral base pointers */ 1792 #define FGPIO_BASE_PTRS \ 1793 { \ 1794 FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE \ 1795 } 1796 1797 /*! 1798 * @} 1799 */ /* end of group FGPIO_Peripheral_Access_Layer */ 1800 1801 /* ---------------------------------------------------------------------------- 1802 -- FLEXIO Peripheral Access Layer 1803 ---------------------------------------------------------------------------- */ 1804 1805 /*! 1806 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer 1807 * @{ 1808 */ 1809 1810 /** FLEXIO - Register Layout Typedef */ 1811 typedef struct 1812 { 1813 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 1814 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 1815 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ 1816 uint8_t RESERVED_0[4]; 1817 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ 1818 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ 1819 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ 1820 uint8_t RESERVED_1[4]; 1821 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ 1822 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ 1823 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ 1824 uint8_t RESERVED_2[4]; 1825 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ 1826 uint8_t RESERVED_3[76]; 1827 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ 1828 uint8_t RESERVED_4[112]; 1829 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ 1830 uint8_t RESERVED_5[240]; 1831 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ 1832 uint8_t RESERVED_6[112]; 1833 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ 1834 uint8_t RESERVED_7[112]; 1835 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ 1836 uint8_t RESERVED_8[112]; 1837 __IO uint32_t 1838 SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ 1839 uint8_t RESERVED_9[112]; 1840 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ 1841 uint8_t RESERVED_10[112]; 1842 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ 1843 uint8_t RESERVED_11[112]; 1844 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ 1845 } FLEXIO_Type; 1846 1847 /* ---------------------------------------------------------------------------- 1848 -- FLEXIO Register Masks 1849 ---------------------------------------------------------------------------- */ 1850 1851 /*! 1852 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks 1853 * @{ 1854 */ 1855 1856 /*! @name VERID - Version ID Register */ 1857 /*! @{ */ 1858 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) 1859 #define FLEXIO_VERID_FEATURE_SHIFT (0U) 1860 /*! FEATURE - Feature Specification Number 1861 * 0b0000000000000000..Standard features implemented. 1862 * 0b0000000000000001..Supports state, logic and parallel modes. 1863 */ 1864 #define FLEXIO_VERID_FEATURE(x) \ 1865 (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) 1866 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) 1867 #define FLEXIO_VERID_MINOR_SHIFT (16U) 1868 /*! MINOR - Minor Version Number 1869 */ 1870 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) 1871 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) 1872 #define FLEXIO_VERID_MAJOR_SHIFT (24U) 1873 /*! MAJOR - Major Version Number 1874 */ 1875 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) 1876 /*! @} */ 1877 1878 /*! @name PARAM - Parameter Register */ 1879 /*! @{ */ 1880 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) 1881 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) 1882 /*! SHIFTER - Shifter Number 1883 */ 1884 #define FLEXIO_PARAM_SHIFTER(x) \ 1885 (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) 1886 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) 1887 #define FLEXIO_PARAM_TIMER_SHIFT (8U) 1888 /*! TIMER - Timer Number 1889 */ 1890 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) 1891 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) 1892 #define FLEXIO_PARAM_PIN_SHIFT (16U) 1893 /*! PIN - Pin Number 1894 */ 1895 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) 1896 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) 1897 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) 1898 /*! TRIGGER - Trigger Number 1899 */ 1900 #define FLEXIO_PARAM_TRIGGER(x) \ 1901 (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) 1902 /*! @} */ 1903 1904 /*! @name CTRL - FlexIO Control Register */ 1905 /*! @{ */ 1906 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) 1907 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) 1908 /*! FLEXEN - FlexIO Enable 1909 * 0b0..FlexIO module is disabled. 1910 * 0b1..FlexIO module is enabled. 1911 */ 1912 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) 1913 #define FLEXIO_CTRL_SWRST_MASK (0x2U) 1914 #define FLEXIO_CTRL_SWRST_SHIFT (1U) 1915 /*! SWRST - Software Reset 1916 * 0b0..Software reset is disabled 1917 * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. 1918 */ 1919 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) 1920 #define FLEXIO_CTRL_FASTACC_MASK (0x4U) 1921 #define FLEXIO_CTRL_FASTACC_SHIFT (2U) 1922 /*! FASTACC - Fast Access 1923 * 0b0..Configures for normal register accesses to FlexIO 1924 * 0b1..Configures for fast register accesses to FlexIO 1925 */ 1926 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) 1927 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) 1928 #define FLEXIO_CTRL_DBGE_SHIFT (30U) 1929 /*! DBGE - Debug Enable 1930 * 0b0..FlexIO is disabled in debug modes. 1931 * 0b1..FlexIO is enabled in debug modes 1932 */ 1933 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) 1934 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) 1935 #define FLEXIO_CTRL_DOZEN_SHIFT (31U) 1936 /*! DOZEN - Doze Enable 1937 * 0b0..FlexIO enabled in Doze modes. 1938 * 0b1..FlexIO disabled in Doze modes. 1939 */ 1940 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) 1941 /*! @} */ 1942 1943 /*! @name SHIFTSTAT - Shifter Status Register */ 1944 /*! @{ */ 1945 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) 1946 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) 1947 /*! SSF - Shifter Status Flag 1948 * 0b0000..Status flag is clear 1949 * 0b0001..Status flag is set 1950 */ 1951 #define FLEXIO_SHIFTSTAT_SSF(x) \ 1952 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) 1953 /*! @} */ 1954 1955 /*! @name SHIFTERR - Shifter Error Register */ 1956 /*! @{ */ 1957 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) 1958 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) 1959 /*! SEF - Shifter Error Flags 1960 * 0b0000..Shifter Error Flag is clear 1961 * 0b0001..Shifter Error Flag is set 1962 */ 1963 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) 1964 /*! @} */ 1965 1966 /*! @name TIMSTAT - Timer Status Register */ 1967 /*! @{ */ 1968 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) 1969 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) 1970 /*! TSF - Timer Status Flags 1971 * 0b0000..Timer Status Flag is clear 1972 * 0b0001..Timer Status Flag is set 1973 */ 1974 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) 1975 /*! @} */ 1976 1977 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ 1978 /*! @{ */ 1979 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) 1980 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) 1981 /*! SSIE - Shifter Status Interrupt Enable 1982 * 0b0000..Shifter Status Flag interrupt disabled 1983 * 0b0001..Shifter Status Flag interrupt enabled 1984 */ 1985 #define FLEXIO_SHIFTSIEN_SSIE(x) \ 1986 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) 1987 /*! @} */ 1988 1989 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ 1990 /*! @{ */ 1991 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) 1992 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) 1993 /*! SEIE - Shifter Error Interrupt Enable 1994 * 0b0000..Shifter Error Flag interrupt disabled 1995 * 0b0001..Shifter Error Flag interrupt enabled 1996 */ 1997 #define FLEXIO_SHIFTEIEN_SEIE(x) \ 1998 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) 1999 /*! @} */ 2000 2001 /*! @name TIMIEN - Timer Interrupt Enable Register */ 2002 /*! @{ */ 2003 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) 2004 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) 2005 /*! TEIE - Timer Status Interrupt Enable 2006 * 0b0000..Timer Status Flag interrupt is disabled 2007 * 0b0001..Timer Status Flag interrupt is enabled 2008 */ 2009 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) 2010 /*! @} */ 2011 2012 /*! @name SHIFTSDEN - Shifter Status DMA Enable */ 2013 /*! @{ */ 2014 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) 2015 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) 2016 /*! SSDE - Shifter Status DMA Enable 2017 * 0b0000..Shifter Status Flag DMA request is disabled 2018 * 0b0001..Shifter Status Flag DMA request is enabled 2019 */ 2020 #define FLEXIO_SHIFTSDEN_SSDE(x) \ 2021 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) 2022 /*! @} */ 2023 2024 /*! @name SHIFTCTL - Shifter Control N Register */ 2025 /*! @{ */ 2026 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) 2027 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) 2028 /*! SMOD - Shifter Mode 2029 * 0b000..Disabled. 2030 * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 2031 * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 2032 * 0b011..Reserved. 2033 * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 2034 * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 2035 * 0b110..Reserved. 2036 * 0b111..Reserved. 2037 */ 2038 #define FLEXIO_SHIFTCTL_SMOD(x) \ 2039 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) 2040 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) 2041 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) 2042 /*! PINPOL - Shifter Pin Polarity 2043 * 0b0..Pin is active high 2044 * 0b1..Pin is active low 2045 */ 2046 #define FLEXIO_SHIFTCTL_PINPOL(x) \ 2047 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) 2048 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U) 2049 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) 2050 /*! PINSEL - Shifter Pin Select 2051 */ 2052 #define FLEXIO_SHIFTCTL_PINSEL(x) \ 2053 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) 2054 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) 2055 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) 2056 /*! PINCFG - Shifter Pin Configuration 2057 * 0b00..Shifter pin output disabled 2058 * 0b01..Shifter pin open drain or bidirectional output enable 2059 * 0b10..Shifter pin bidirectional output data 2060 * 0b11..Shifter pin output 2061 */ 2062 #define FLEXIO_SHIFTCTL_PINCFG(x) \ 2063 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) 2064 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) 2065 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) 2066 /*! TIMPOL - Timer Polarity 2067 * 0b0..Shift on posedge of Shift clock 2068 * 0b1..Shift on negedge of Shift clock 2069 */ 2070 #define FLEXIO_SHIFTCTL_TIMPOL(x) \ 2071 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) 2072 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) 2073 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) 2074 /*! TIMSEL - Timer Select 2075 */ 2076 #define FLEXIO_SHIFTCTL_TIMSEL(x) \ 2077 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) 2078 /*! @} */ 2079 2080 /* The count of FLEXIO_SHIFTCTL */ 2081 #define FLEXIO_SHIFTCTL_COUNT (4U) 2082 2083 /*! @name SHIFTCFG - Shifter Configuration N Register */ 2084 /*! @{ */ 2085 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) 2086 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) 2087 /*! SSTART - Shifter Start bit 2088 * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 2089 * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 2090 * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag 2091 * if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match 2092 * store sets error flag if start bit is not 1 2093 */ 2094 #define FLEXIO_SHIFTCFG_SSTART(x) \ 2095 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) 2096 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) 2097 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) 2098 /*! SSTOP - Shifter Stop bit 2099 * 0b00..Stop bit disabled for transmitter/receiver/match store 2100 * 0b01..Reserved for transmitter/receiver/match store 2101 * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 2102 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 2103 */ 2104 #define FLEXIO_SHIFTCFG_SSTOP(x) \ 2105 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) 2106 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) 2107 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) 2108 /*! INSRC - Input Source 2109 * 0b0..Pin 2110 * 0b1..Shifter N+1 Output 2111 */ 2112 #define FLEXIO_SHIFTCFG_INSRC(x) \ 2113 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) 2114 /*! @} */ 2115 2116 /* The count of FLEXIO_SHIFTCFG */ 2117 #define FLEXIO_SHIFTCFG_COUNT (4U) 2118 2119 /*! @name SHIFTBUF - Shifter Buffer N Register */ 2120 /*! @{ */ 2121 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) 2122 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) 2123 /*! SHIFTBUF - Shift Buffer 2124 */ 2125 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) \ 2126 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) 2127 /*! @} */ 2128 2129 /* The count of FLEXIO_SHIFTBUF */ 2130 #define FLEXIO_SHIFTBUF_COUNT (4U) 2131 2132 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ 2133 /*! @{ */ 2134 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) 2135 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) 2136 /*! SHIFTBUFBIS - Shift Buffer 2137 */ 2138 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) \ 2139 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) 2140 /*! @} */ 2141 2142 /* The count of FLEXIO_SHIFTBUFBIS */ 2143 #define FLEXIO_SHIFTBUFBIS_COUNT (4U) 2144 2145 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ 2146 /*! @{ */ 2147 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) 2148 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) 2149 /*! SHIFTBUFBYS - Shift Buffer 2150 */ 2151 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) \ 2152 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) 2153 /*! @} */ 2154 2155 /* The count of FLEXIO_SHIFTBUFBYS */ 2156 #define FLEXIO_SHIFTBUFBYS_COUNT (4U) 2157 2158 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ 2159 /*! @{ */ 2160 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) 2161 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) 2162 /*! SHIFTBUFBBS - Shift Buffer 2163 */ 2164 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) \ 2165 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) 2166 /*! @} */ 2167 2168 /* The count of FLEXIO_SHIFTBUFBBS */ 2169 #define FLEXIO_SHIFTBUFBBS_COUNT (4U) 2170 2171 /*! @name TIMCTL - Timer Control N Register */ 2172 /*! @{ */ 2173 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) 2174 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) 2175 /*! TIMOD - Timer Mode 2176 * 0b00..Timer Disabled. 2177 * 0b01..Dual 8-bit counters baud/bit mode. 2178 * 0b10..Dual 8-bit counters PWM mode. 2179 * 0b11..Single 16-bit counter mode. 2180 */ 2181 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) 2182 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) 2183 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) 2184 /*! PINPOL - Timer Pin Polarity 2185 * 0b0..Pin is active high 2186 * 0b1..Pin is active low 2187 */ 2188 #define FLEXIO_TIMCTL_PINPOL(x) \ 2189 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) 2190 #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U) 2191 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) 2192 /*! PINSEL - Timer Pin Select 2193 */ 2194 #define FLEXIO_TIMCTL_PINSEL(x) \ 2195 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) 2196 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) 2197 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) 2198 /*! PINCFG - Timer Pin Configuration 2199 * 0b00..Timer pin output disabled 2200 * 0b01..Timer pin open drain or bidirectional output enable 2201 * 0b10..Timer pin bidirectional output data 2202 * 0b11..Timer pin output 2203 */ 2204 #define FLEXIO_TIMCTL_PINCFG(x) \ 2205 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) 2206 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) 2207 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) 2208 /*! TRGSRC - Trigger Source 2209 * 0b0..External trigger selected 2210 * 0b1..Internal trigger selected 2211 */ 2212 #define FLEXIO_TIMCTL_TRGSRC(x) \ 2213 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) 2214 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) 2215 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) 2216 /*! TRGPOL - Trigger Polarity 2217 * 0b0..Trigger active high 2218 * 0b1..Trigger active low 2219 */ 2220 #define FLEXIO_TIMCTL_TRGPOL(x) \ 2221 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) 2222 #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U) 2223 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) 2224 /*! TRGSEL - Trigger Select 2225 */ 2226 #define FLEXIO_TIMCTL_TRGSEL(x) \ 2227 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) 2228 /*! @} */ 2229 2230 /* The count of FLEXIO_TIMCTL */ 2231 #define FLEXIO_TIMCTL_COUNT (4U) 2232 2233 /*! @name TIMCFG - Timer Configuration N Register */ 2234 /*! @{ */ 2235 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) 2236 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) 2237 /*! TSTART - Timer Start Bit 2238 * 0b0..Start bit disabled 2239 * 0b1..Start bit enabled 2240 */ 2241 #define FLEXIO_TIMCFG_TSTART(x) \ 2242 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) 2243 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) 2244 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) 2245 /*! TSTOP - Timer Stop Bit 2246 * 0b00..Stop bit disabled 2247 * 0b01..Stop bit is enabled on timer compare 2248 * 0b10..Stop bit is enabled on timer disable 2249 * 0b11..Stop bit is enabled on timer compare and timer disable 2250 */ 2251 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) 2252 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) 2253 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) 2254 /*! TIMENA - Timer Enable 2255 * 0b000..Timer always enabled 2256 * 0b001..Timer enabled on Timer N-1 enable 2257 * 0b010..Timer enabled on Trigger high 2258 * 0b011..Timer enabled on Trigger high and Pin high 2259 * 0b100..Timer enabled on Pin rising edge 2260 * 0b101..Timer enabled on Pin rising edge and Trigger high 2261 * 0b110..Timer enabled on Trigger rising edge 2262 * 0b111..Timer enabled on Trigger rising or falling edge 2263 */ 2264 #define FLEXIO_TIMCFG_TIMENA(x) \ 2265 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) 2266 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) 2267 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) 2268 /*! TIMDIS - Timer Disable 2269 * 0b000..Timer never disabled 2270 * 0b001..Timer disabled on Timer N-1 disable 2271 * 0b010..Timer disabled on Timer compare 2272 * 0b011..Timer disabled on Timer compare and Trigger Low 2273 * 0b100..Timer disabled on Pin rising or falling edge 2274 * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 2275 * 0b110..Timer disabled on Trigger falling edge 2276 * 0b111..Reserved 2277 */ 2278 #define FLEXIO_TIMCFG_TIMDIS(x) \ 2279 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) 2280 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) 2281 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) 2282 /*! TIMRST - Timer Reset 2283 * 0b000..Timer never reset 2284 * 0b001..Reserved 2285 * 0b010..Timer reset on Timer Pin equal to Timer Output 2286 * 0b011..Timer reset on Timer Trigger equal to Timer Output 2287 * 0b100..Timer reset on Timer Pin rising edge 2288 * 0b101..Reserved 2289 * 0b110..Timer reset on Trigger rising edge 2290 * 0b111..Timer reset on Trigger rising or falling edge 2291 */ 2292 #define FLEXIO_TIMCFG_TIMRST(x) \ 2293 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) 2294 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) 2295 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) 2296 /*! TIMDEC - Timer Decrement 2297 * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. 2298 * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 2299 * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 2300 * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 2301 */ 2302 #define FLEXIO_TIMCFG_TIMDEC(x) \ 2303 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) 2304 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) 2305 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) 2306 /*! TIMOUT - Timer Output 2307 * 0b00..Timer output is logic one when enabled and is not affected by timer reset 2308 * 0b01..Timer output is logic zero when enabled and is not affected by timer reset 2309 * 0b10..Timer output is logic one when enabled and on timer reset 2310 * 0b11..Timer output is logic zero when enabled and on timer reset 2311 */ 2312 #define FLEXIO_TIMCFG_TIMOUT(x) \ 2313 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) 2314 /*! @} */ 2315 2316 /* The count of FLEXIO_TIMCFG */ 2317 #define FLEXIO_TIMCFG_COUNT (4U) 2318 2319 /*! @name TIMCMP - Timer Compare N Register */ 2320 /*! @{ */ 2321 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) 2322 #define FLEXIO_TIMCMP_CMP_SHIFT (0U) 2323 /*! CMP - Timer Compare Value 2324 */ 2325 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) 2326 /*! @} */ 2327 2328 /* The count of FLEXIO_TIMCMP */ 2329 #define FLEXIO_TIMCMP_COUNT (4U) 2330 2331 /*! 2332 * @} 2333 */ /* end of group FLEXIO_Register_Masks */ 2334 2335 /* FLEXIO - Peripheral instance base addresses */ 2336 /** Peripheral FLEXIO base address */ 2337 #define FLEXIO_BASE (0x4005F000u) 2338 /** Peripheral FLEXIO base pointer */ 2339 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE) 2340 /** Array initializer of FLEXIO peripheral base addresses */ 2341 #define FLEXIO_BASE_ADDRS \ 2342 { \ 2343 FLEXIO_BASE \ 2344 } 2345 /** Array initializer of FLEXIO peripheral base pointers */ 2346 #define FLEXIO_BASE_PTRS \ 2347 { \ 2348 FLEXIO \ 2349 } 2350 /** Interrupt vectors for the FLEXIO peripheral type */ 2351 #define FLEXIO_IRQS \ 2352 { \ 2353 UART2_FLEXIO_IRQn \ 2354 } 2355 2356 /*! 2357 * @} 2358 */ /* end of group FLEXIO_Peripheral_Access_Layer */ 2359 2360 /* ---------------------------------------------------------------------------- 2361 -- FTFA Peripheral Access Layer 2362 ---------------------------------------------------------------------------- */ 2363 2364 /*! 2365 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 2366 * @{ 2367 */ 2368 2369 /** FTFA - Register Layout Typedef */ 2370 typedef struct 2371 { 2372 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 2373 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 2374 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 2375 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 2376 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 2377 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 2378 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 2379 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 2380 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 2381 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 2382 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 2383 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 2384 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 2385 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 2386 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 2387 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 2388 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 2389 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 2390 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 2391 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 2392 } FTFA_Type; 2393 2394 /* ---------------------------------------------------------------------------- 2395 -- FTFA Register Masks 2396 ---------------------------------------------------------------------------- */ 2397 2398 /*! 2399 * @addtogroup FTFA_Register_Masks FTFA Register Masks 2400 * @{ 2401 */ 2402 2403 /*! @name FSTAT - Flash Status Register */ 2404 /*! @{ */ 2405 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 2406 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 2407 /*! MGSTAT0 - Memory Controller Command Completion Status Flag 2408 */ 2409 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 2410 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 2411 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 2412 /*! FPVIOL - Flash Protection Violation Flag 2413 * 0b0..No protection violation detected 2414 * 0b1..Protection violation detected 2415 */ 2416 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 2417 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 2418 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 2419 /*! ACCERR - Flash Access Error Flag 2420 * 0b0..No access error detected 2421 * 0b1..Access error detected 2422 */ 2423 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 2424 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 2425 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 2426 /*! RDCOLERR - Flash Read Collision Error Flag 2427 * 0b0..No collision error detected 2428 * 0b1..Collision error detected 2429 */ 2430 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 2431 #define FTFA_FSTAT_CCIF_MASK (0x80U) 2432 #define FTFA_FSTAT_CCIF_SHIFT (7U) 2433 /*! CCIF - Command Complete Interrupt Flag 2434 * 0b0..Flash command in progress 2435 * 0b1..Flash command has completed 2436 */ 2437 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 2438 /*! @} */ 2439 2440 /*! @name FCNFG - Flash Configuration Register */ 2441 /*! @{ */ 2442 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 2443 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 2444 /*! ERSSUSP - Erase Suspend 2445 * 0b0..No suspend requested 2446 * 0b1..Suspend the current Erase Flash Sector command execution. 2447 */ 2448 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 2449 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 2450 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 2451 /*! ERSAREQ - Erase All Request 2452 * 0b0..No request or request complete 2453 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the 2454 * Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to 2455 * the unsecure state. 2456 */ 2457 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 2458 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 2459 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 2460 /*! RDCOLLIE - Read Collision Error Interrupt Enable 2461 * 0b0..Read collision error interrupt disabled 2462 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read 2463 * collision error is detected (see the description of FSTAT[RDCOLERR]). 2464 */ 2465 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 2466 #define FTFA_FCNFG_CCIE_MASK (0x80U) 2467 #define FTFA_FCNFG_CCIE_SHIFT (7U) 2468 /*! CCIE - Command Complete Interrupt Enable 2469 * 0b0..Command complete interrupt disabled 2470 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 2471 */ 2472 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 2473 /*! @} */ 2474 2475 /*! @name FSEC - Flash Security Register */ 2476 /*! @{ */ 2477 #define FTFA_FSEC_SEC_MASK (0x3U) 2478 #define FTFA_FSEC_SEC_SHIFT (0U) 2479 /*! SEC - Flash Security 2480 * 0b00..MCU security status is secure. 2481 * 0b01..MCU security status is secure. 2482 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) 2483 * 0b11..MCU security status is secure. 2484 */ 2485 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 2486 #define FTFA_FSEC_FSLACC_MASK (0xCU) 2487 #define FTFA_FSEC_FSLACC_SHIFT (2U) 2488 /*! FSLACC - Factory Security Level Access Code 2489 * 0b00..NXP factory access granted 2490 * 0b01..NXP factory access denied 2491 * 0b10..NXP factory access denied 2492 * 0b11..NXP factory access granted 2493 */ 2494 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 2495 #define FTFA_FSEC_MEEN_MASK (0x30U) 2496 #define FTFA_FSEC_MEEN_SHIFT (4U) 2497 /*! MEEN - Mass Erase Enable 2498 * 0b00..Mass erase is enabled 2499 * 0b01..Mass erase is enabled 2500 * 0b10..Mass erase is disabled 2501 * 0b11..Mass erase is enabled 2502 */ 2503 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 2504 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 2505 #define FTFA_FSEC_KEYEN_SHIFT (6U) 2506 /*! KEYEN - Backdoor Key Security Enable 2507 * 0b00..Backdoor key access disabled 2508 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 2509 * 0b10..Backdoor key access enabled 2510 * 0b11..Backdoor key access disabled 2511 */ 2512 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 2513 /*! @} */ 2514 2515 /*! @name FOPT - Flash Option Register */ 2516 /*! @{ */ 2517 #define FTFA_FOPT_OPT_MASK (0xFFU) 2518 #define FTFA_FOPT_OPT_SHIFT (0U) 2519 /*! OPT - Nonvolatile Option 2520 */ 2521 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 2522 /*! @} */ 2523 2524 /*! @name FCCOB3 - Flash Common Command Object Registers */ 2525 /*! @{ */ 2526 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 2527 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 2528 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 2529 /*! @} */ 2530 2531 /*! @name FCCOB2 - Flash Common Command Object Registers */ 2532 /*! @{ */ 2533 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 2534 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 2535 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 2536 /*! @} */ 2537 2538 /*! @name FCCOB1 - Flash Common Command Object Registers */ 2539 /*! @{ */ 2540 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 2541 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 2542 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 2543 /*! @} */ 2544 2545 /*! @name FCCOB0 - Flash Common Command Object Registers */ 2546 /*! @{ */ 2547 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 2548 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 2549 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 2550 /*! @} */ 2551 2552 /*! @name FCCOB7 - Flash Common Command Object Registers */ 2553 /*! @{ */ 2554 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 2555 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 2556 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 2557 /*! @} */ 2558 2559 /*! @name FCCOB6 - Flash Common Command Object Registers */ 2560 /*! @{ */ 2561 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 2562 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 2563 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 2564 /*! @} */ 2565 2566 /*! @name FCCOB5 - Flash Common Command Object Registers */ 2567 /*! @{ */ 2568 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 2569 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 2570 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 2571 /*! @} */ 2572 2573 /*! @name FCCOB4 - Flash Common Command Object Registers */ 2574 /*! @{ */ 2575 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 2576 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 2577 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 2578 /*! @} */ 2579 2580 /*! @name FCCOBB - Flash Common Command Object Registers */ 2581 /*! @{ */ 2582 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 2583 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 2584 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 2585 /*! @} */ 2586 2587 /*! @name FCCOBA - Flash Common Command Object Registers */ 2588 /*! @{ */ 2589 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 2590 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 2591 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 2592 /*! @} */ 2593 2594 /*! @name FCCOB9 - Flash Common Command Object Registers */ 2595 /*! @{ */ 2596 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 2597 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 2598 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 2599 /*! @} */ 2600 2601 /*! @name FCCOB8 - Flash Common Command Object Registers */ 2602 /*! @{ */ 2603 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 2604 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 2605 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 2606 /*! @} */ 2607 2608 /*! @name FPROT3 - Program Flash Protection Registers */ 2609 /*! @{ */ 2610 #define FTFA_FPROT3_PROT_MASK (0xFFU) 2611 #define FTFA_FPROT3_PROT_SHIFT (0U) 2612 /*! PROT - Program Flash Region Protect 2613 * 0b00000000..Program flash region is protected. 2614 * 0b00000001..Program flash region is not protected 2615 */ 2616 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 2617 /*! @} */ 2618 2619 /*! @name FPROT2 - Program Flash Protection Registers */ 2620 /*! @{ */ 2621 #define FTFA_FPROT2_PROT_MASK (0xFFU) 2622 #define FTFA_FPROT2_PROT_SHIFT (0U) 2623 /*! PROT - Program Flash Region Protect 2624 * 0b00000000..Program flash region is protected. 2625 * 0b00000001..Program flash region is not protected 2626 */ 2627 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 2628 /*! @} */ 2629 2630 /*! @name FPROT1 - Program Flash Protection Registers */ 2631 /*! @{ */ 2632 #define FTFA_FPROT1_PROT_MASK (0xFFU) 2633 #define FTFA_FPROT1_PROT_SHIFT (0U) 2634 /*! PROT - Program Flash Region Protect 2635 * 0b00000000..Program flash region is protected. 2636 * 0b00000001..Program flash region is not protected 2637 */ 2638 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 2639 /*! @} */ 2640 2641 /*! @name FPROT0 - Program Flash Protection Registers */ 2642 /*! @{ */ 2643 #define FTFA_FPROT0_PROT_MASK (0xFFU) 2644 #define FTFA_FPROT0_PROT_SHIFT (0U) 2645 /*! PROT - Program Flash Region Protect 2646 * 0b00000000..Program flash region is protected. 2647 * 0b00000001..Program flash region is not protected 2648 */ 2649 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 2650 /*! @} */ 2651 2652 /*! 2653 * @} 2654 */ /* end of group FTFA_Register_Masks */ 2655 2656 /* FTFA - Peripheral instance base addresses */ 2657 /** Peripheral FTFA base address */ 2658 #define FTFA_BASE (0x40020000u) 2659 /** Peripheral FTFA base pointer */ 2660 #define FTFA ((FTFA_Type *)FTFA_BASE) 2661 /** Array initializer of FTFA peripheral base addresses */ 2662 #define FTFA_BASE_ADDRS \ 2663 { \ 2664 FTFA_BASE \ 2665 } 2666 /** Array initializer of FTFA peripheral base pointers */ 2667 #define FTFA_BASE_PTRS \ 2668 { \ 2669 FTFA \ 2670 } 2671 /** Interrupt vectors for the FTFA peripheral type */ 2672 #define FTFA_COMMAND_COMPLETE_IRQS \ 2673 { \ 2674 FTFA_IRQn \ 2675 } 2676 2677 /*! 2678 * @} 2679 */ /* end of group FTFA_Peripheral_Access_Layer */ 2680 2681 /* ---------------------------------------------------------------------------- 2682 -- GPIO Peripheral Access Layer 2683 ---------------------------------------------------------------------------- */ 2684 2685 /*! 2686 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2687 * @{ 2688 */ 2689 2690 /** GPIO - Register Layout Typedef */ 2691 typedef struct 2692 { 2693 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 2694 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 2695 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 2696 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 2697 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 2698 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 2699 } GPIO_Type; 2700 2701 /* ---------------------------------------------------------------------------- 2702 -- GPIO Register Masks 2703 ---------------------------------------------------------------------------- */ 2704 2705 /*! 2706 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2707 * @{ 2708 */ 2709 2710 /*! @name PDOR - Port Data Output Register */ 2711 /*! @{ */ 2712 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 2713 #define GPIO_PDOR_PDO_SHIFT (0U) 2714 /*! PDO - Port Data Output 2715 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose 2716 * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for 2717 * general-purpose output. 2718 */ 2719 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 2720 /*! @} */ 2721 2722 /*! @name PSOR - Port Set Output Register */ 2723 /*! @{ */ 2724 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 2725 #define GPIO_PSOR_PTSO_SHIFT (0U) 2726 /*! PTSO - Port Set Output 2727 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2728 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 2729 */ 2730 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 2731 /*! @} */ 2732 2733 /*! @name PCOR - Port Clear Output Register */ 2734 /*! @{ */ 2735 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 2736 #define GPIO_PCOR_PTCO_SHIFT (0U) 2737 /*! PTCO - Port Clear Output 2738 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2739 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 2740 */ 2741 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 2742 /*! @} */ 2743 2744 /*! @name PTOR - Port Toggle Output Register */ 2745 /*! @{ */ 2746 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 2747 #define GPIO_PTOR_PTTO_SHIFT (0U) 2748 /*! PTTO - Port Toggle Output 2749 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2750 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 2751 */ 2752 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 2753 /*! @} */ 2754 2755 /*! @name PDIR - Port Data Input Register */ 2756 /*! @{ */ 2757 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 2758 #define GPIO_PDIR_PDI_SHIFT (0U) 2759 /*! PDI - Port Data Input 2760 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 2761 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 2762 */ 2763 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 2764 /*! @} */ 2765 2766 /*! @name PDDR - Port Data Direction Register */ 2767 /*! @{ */ 2768 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 2769 #define GPIO_PDDR_PDD_SHIFT (0U) 2770 /*! PDD - Port Data Direction 2771 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 2772 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 2773 */ 2774 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 2775 /*! @} */ 2776 2777 /*! 2778 * @} 2779 */ /* end of group GPIO_Register_Masks */ 2780 2781 /* GPIO - Peripheral instance base addresses */ 2782 /** Peripheral GPIOA base address */ 2783 #define GPIOA_BASE (0x400FF000u) 2784 /** Peripheral GPIOA base pointer */ 2785 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 2786 /** Peripheral GPIOB base address */ 2787 #define GPIOB_BASE (0x400FF040u) 2788 /** Peripheral GPIOB base pointer */ 2789 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 2790 /** Peripheral GPIOC base address */ 2791 #define GPIOC_BASE (0x400FF080u) 2792 /** Peripheral GPIOC base pointer */ 2793 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 2794 /** Peripheral GPIOD base address */ 2795 #define GPIOD_BASE (0x400FF0C0u) 2796 /** Peripheral GPIOD base pointer */ 2797 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 2798 /** Peripheral GPIOE base address */ 2799 #define GPIOE_BASE (0x400FF100u) 2800 /** Peripheral GPIOE base pointer */ 2801 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 2802 /** Array initializer of GPIO peripheral base addresses */ 2803 #define GPIO_BASE_ADDRS \ 2804 { \ 2805 GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE \ 2806 } 2807 /** Array initializer of GPIO peripheral base pointers */ 2808 #define GPIO_BASE_PTRS \ 2809 { \ 2810 GPIOA, GPIOB, GPIOC, GPIOD, GPIOE \ 2811 } 2812 2813 /*! 2814 * @} 2815 */ /* end of group GPIO_Peripheral_Access_Layer */ 2816 2817 /* ---------------------------------------------------------------------------- 2818 -- I2C Peripheral Access Layer 2819 ---------------------------------------------------------------------------- */ 2820 2821 /*! 2822 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 2823 * @{ 2824 */ 2825 2826 /** I2C - Register Layout Typedef */ 2827 typedef struct 2828 { 2829 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 2830 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 2831 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 2832 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 2833 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 2834 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 2835 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ 2836 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 2837 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 2838 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 2839 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 2840 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 2841 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ 2842 } I2C_Type; 2843 2844 /* ---------------------------------------------------------------------------- 2845 -- I2C Register Masks 2846 ---------------------------------------------------------------------------- */ 2847 2848 /*! 2849 * @addtogroup I2C_Register_Masks I2C Register Masks 2850 * @{ 2851 */ 2852 2853 /*! @name A1 - I2C Address Register 1 */ 2854 /*! @{ */ 2855 #define I2C_A1_AD_MASK (0xFEU) 2856 #define I2C_A1_AD_SHIFT (1U) 2857 /*! AD - Address 2858 */ 2859 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 2860 /*! @} */ 2861 2862 /*! @name F - I2C Frequency Divider register */ 2863 /*! @{ */ 2864 #define I2C_F_ICR_MASK (0x3FU) 2865 #define I2C_F_ICR_SHIFT (0U) 2866 /*! ICR - ClockRate 2867 */ 2868 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 2869 #define I2C_F_MULT_MASK (0xC0U) 2870 #define I2C_F_MULT_SHIFT (6U) 2871 /*! MULT - Multiplier Factor 2872 * 0b00..mul = 1 2873 * 0b01..mul = 2 2874 * 0b10..mul = 4 2875 * 0b11..Reserved 2876 */ 2877 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 2878 /*! @} */ 2879 2880 /*! @name C1 - I2C Control Register 1 */ 2881 /*! @{ */ 2882 #define I2C_C1_DMAEN_MASK (0x1U) 2883 #define I2C_C1_DMAEN_SHIFT (0U) 2884 /*! DMAEN - DMA Enable 2885 * 0b0..All DMA signalling disabled. 2886 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data 2887 * byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received 2888 * matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] 2889 * are set. If the direction of transfer is known from master to slave, then it is not required to check 2890 * S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from 2891 * the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be 2892 * used. When FACK = 1, an address or a data byte is transmitted. 2893 */ 2894 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 2895 #define I2C_C1_WUEN_MASK (0x2U) 2896 #define I2C_C1_WUEN_SHIFT (1U) 2897 /*! WUEN - Wakeup Enable 2898 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 2899 * 0b1..Enables the wakeup function in low power mode. 2900 */ 2901 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 2902 #define I2C_C1_RSTA_MASK (0x4U) 2903 #define I2C_C1_RSTA_SHIFT (2U) 2904 /*! RSTA - Repeat START 2905 */ 2906 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 2907 #define I2C_C1_TXAK_MASK (0x8U) 2908 #define I2C_C1_TXAK_SHIFT (3U) 2909 /*! TXAK - Transmit Acknowledge Enable 2910 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the 2911 * current receiving byte (if FACK is set). 2912 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the 2913 * current receiving data byte (if FACK is set). 2914 */ 2915 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 2916 #define I2C_C1_TX_MASK (0x10U) 2917 #define I2C_C1_TX_SHIFT (4U) 2918 /*! TX - Transmit Mode Select 2919 * 0b0..Receive 2920 * 0b1..Transmit 2921 */ 2922 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 2923 #define I2C_C1_MST_MASK (0x20U) 2924 #define I2C_C1_MST_SHIFT (5U) 2925 /*! MST - Master Mode Select 2926 * 0b0..Slave mode 2927 * 0b1..Master mode 2928 */ 2929 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 2930 #define I2C_C1_IICIE_MASK (0x40U) 2931 #define I2C_C1_IICIE_SHIFT (6U) 2932 /*! IICIE - I2C Interrupt Enable 2933 * 0b0..Disabled 2934 * 0b1..Enabled 2935 */ 2936 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 2937 #define I2C_C1_IICEN_MASK (0x80U) 2938 #define I2C_C1_IICEN_SHIFT (7U) 2939 /*! IICEN - I2C Enable 2940 * 0b0..Disabled 2941 * 0b1..Enabled 2942 */ 2943 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 2944 /*! @} */ 2945 2946 /*! @name S - I2C Status register */ 2947 /*! @{ */ 2948 #define I2C_S_RXAK_MASK (0x1U) 2949 #define I2C_S_RXAK_SHIFT (0U) 2950 /*! RXAK - Receive Acknowledge 2951 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 2952 * 0b1..No acknowledge signal detected 2953 */ 2954 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 2955 #define I2C_S_IICIF_MASK (0x2U) 2956 #define I2C_S_IICIF_SHIFT (1U) 2957 /*! IICIF - Interrupt Flag 2958 * 0b0..No interrupt pending 2959 * 0b1..Interrupt pending 2960 */ 2961 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 2962 #define I2C_S_SRW_MASK (0x4U) 2963 #define I2C_S_SRW_SHIFT (2U) 2964 /*! SRW - Slave Read/Write 2965 * 0b0..Slave receive, master writing to slave 2966 * 0b1..Slave transmit, master reading from slave 2967 */ 2968 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 2969 #define I2C_S_RAM_MASK (0x8U) 2970 #define I2C_S_RAM_SHIFT (3U) 2971 /*! RAM - Range Address Match 2972 * 0b0..Not addressed 2973 * 0b1..Addressed as a slave 2974 */ 2975 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 2976 #define I2C_S_ARBL_MASK (0x10U) 2977 #define I2C_S_ARBL_SHIFT (4U) 2978 /*! ARBL - Arbitration Lost 2979 * 0b0..Standard bus operation. 2980 * 0b1..Loss of arbitration. 2981 */ 2982 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 2983 #define I2C_S_BUSY_MASK (0x20U) 2984 #define I2C_S_BUSY_SHIFT (5U) 2985 /*! BUSY - Bus Busy 2986 * 0b0..Bus is idle 2987 * 0b1..Bus is busy 2988 */ 2989 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 2990 #define I2C_S_IAAS_MASK (0x40U) 2991 #define I2C_S_IAAS_SHIFT (6U) 2992 /*! IAAS - Addressed As A Slave 2993 * 0b0..Not addressed 2994 * 0b1..Addressed as a slave 2995 */ 2996 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 2997 #define I2C_S_TCF_MASK (0x80U) 2998 #define I2C_S_TCF_SHIFT (7U) 2999 /*! TCF - Transfer Complete Flag 3000 * 0b0..Transfer in progress 3001 * 0b1..Transfer complete 3002 */ 3003 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 3004 /*! @} */ 3005 3006 /*! @name D - I2C Data I/O register */ 3007 /*! @{ */ 3008 #define I2C_D_DATA_MASK (0xFFU) 3009 #define I2C_D_DATA_SHIFT (0U) 3010 /*! DATA - Data 3011 */ 3012 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 3013 /*! @} */ 3014 3015 /*! @name C2 - I2C Control Register 2 */ 3016 /*! @{ */ 3017 #define I2C_C2_AD_MASK (0x7U) 3018 #define I2C_C2_AD_SHIFT (0U) 3019 /*! AD - Slave Address 3020 */ 3021 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 3022 #define I2C_C2_RMEN_MASK (0x8U) 3023 #define I2C_C2_RMEN_SHIFT (3U) 3024 /*! RMEN - Range Address Matching Enable 3025 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA 3026 * registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of 3027 * values of the A1 and RA registers. 3028 */ 3029 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 3030 #define I2C_C2_SBRC_MASK (0x10U) 3031 #define I2C_C2_SBRC_SHIFT (4U) 3032 /*! SBRC - Slave Baud Rate Control 3033 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 3034 * 0b1..Slave baud rate is independent of the master baud rate 3035 */ 3036 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 3037 #define I2C_C2_HDRS_MASK (0x20U) 3038 #define I2C_C2_HDRS_SHIFT (5U) 3039 /*! HDRS - High Drive Select 3040 * 0b0..Normal drive mode 3041 * 0b1..High drive mode 3042 */ 3043 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 3044 #define I2C_C2_ADEXT_MASK (0x40U) 3045 #define I2C_C2_ADEXT_SHIFT (6U) 3046 /*! ADEXT - Address Extension 3047 * 0b0..7-bit address scheme 3048 * 0b1..10-bit address scheme 3049 */ 3050 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 3051 #define I2C_C2_GCAEN_MASK (0x80U) 3052 #define I2C_C2_GCAEN_SHIFT (7U) 3053 /*! GCAEN - General Call Address Enable 3054 * 0b0..Disabled 3055 * 0b1..Enabled 3056 */ 3057 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 3058 /*! @} */ 3059 3060 /*! @name FLT - I2C Programmable Input Glitch Filter Register */ 3061 /*! @{ */ 3062 #define I2C_FLT_FLT_MASK (0xFU) 3063 #define I2C_FLT_FLT_SHIFT (0U) 3064 /*! FLT - I2C Programmable Filter Factor 3065 * 0b0000..No filter/bypass 3066 */ 3067 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 3068 #define I2C_FLT_STARTF_MASK (0x10U) 3069 #define I2C_FLT_STARTF_SHIFT (4U) 3070 /*! STARTF - I2C Bus Start Detect Flag 3071 * 0b0..No start happens on I2C bus 3072 * 0b1..Start detected on I2C bus 3073 */ 3074 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 3075 #define I2C_FLT_SSIE_MASK (0x20U) 3076 #define I2C_FLT_SSIE_SHIFT (5U) 3077 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 3078 * 0b0..Stop or start detection interrupt is disabled 3079 * 0b1..Stop or start detection interrupt is enabled 3080 */ 3081 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 3082 #define I2C_FLT_STOPF_MASK (0x40U) 3083 #define I2C_FLT_STOPF_SHIFT (6U) 3084 /*! STOPF - I2C Bus Stop Detect Flag 3085 * 0b0..No stop happens on I2C bus 3086 * 0b1..Stop detected on I2C bus 3087 */ 3088 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 3089 #define I2C_FLT_SHEN_MASK (0x80U) 3090 #define I2C_FLT_SHEN_SHIFT (7U) 3091 /*! SHEN - Stop Hold Enable 3092 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 3093 * 0b1..Stop holdoff is enabled. 3094 */ 3095 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 3096 /*! @} */ 3097 3098 /*! @name RA - I2C Range Address register */ 3099 /*! @{ */ 3100 #define I2C_RA_RAD_MASK (0xFEU) 3101 #define I2C_RA_RAD_SHIFT (1U) 3102 /*! RAD - Range Slave Address 3103 */ 3104 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 3105 /*! @} */ 3106 3107 /*! @name SMB - I2C SMBus Control and Status register */ 3108 /*! @{ */ 3109 #define I2C_SMB_SHTF2IE_MASK (0x1U) 3110 #define I2C_SMB_SHTF2IE_SHIFT (0U) 3111 /*! SHTF2IE - SHTF2 Interrupt Enable 3112 * 0b0..SHTF2 interrupt is disabled 3113 * 0b1..SHTF2 interrupt is enabled 3114 */ 3115 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 3116 #define I2C_SMB_SHTF2_MASK (0x2U) 3117 #define I2C_SMB_SHTF2_SHIFT (1U) 3118 /*! SHTF2 - SCL High Timeout Flag 2 3119 * 0b0..No SCL high and SDA low timeout occurs 3120 * 0b1..SCL high and SDA low timeout occurs 3121 */ 3122 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 3123 #define I2C_SMB_SHTF1_MASK (0x4U) 3124 #define I2C_SMB_SHTF1_SHIFT (2U) 3125 /*! SHTF1 - SCL High Timeout Flag 1 3126 * 0b0..No SCL high and SDA high timeout occurs 3127 * 0b1..SCL high and SDA high timeout occurs 3128 */ 3129 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 3130 #define I2C_SMB_SLTF_MASK (0x8U) 3131 #define I2C_SMB_SLTF_SHIFT (3U) 3132 /*! SLTF - SCL Low Timeout Flag 3133 * 0b0..No low timeout occurs 3134 * 0b1..Low timeout occurs 3135 */ 3136 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 3137 #define I2C_SMB_TCKSEL_MASK (0x10U) 3138 #define I2C_SMB_TCKSEL_SHIFT (4U) 3139 /*! TCKSEL - Timeout Counter Clock Select 3140 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 3141 * 0b1..Timeout counter counts at the frequency of the I2C module clock 3142 */ 3143 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 3144 #define I2C_SMB_SIICAEN_MASK (0x20U) 3145 #define I2C_SMB_SIICAEN_SHIFT (5U) 3146 /*! SIICAEN - Second I2C Address Enable 3147 * 0b0..I2C address register 2 matching is disabled 3148 * 0b1..I2C address register 2 matching is enabled 3149 */ 3150 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 3151 #define I2C_SMB_ALERTEN_MASK (0x40U) 3152 #define I2C_SMB_ALERTEN_SHIFT (6U) 3153 /*! ALERTEN - SMBus Alert Response Address Enable 3154 * 0b0..SMBus alert response address matching is disabled 3155 * 0b1..SMBus alert response address matching is enabled 3156 */ 3157 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 3158 #define I2C_SMB_FACK_MASK (0x80U) 3159 #define I2C_SMB_FACK_SHIFT (7U) 3160 /*! FACK - Fast NACK/ACK Enable 3161 * 0b0..An ACK or NACK is sent on the following receiving data byte 3162 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte 3163 * generates a NACK. 3164 */ 3165 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 3166 /*! @} */ 3167 3168 /*! @name A2 - I2C Address Register 2 */ 3169 /*! @{ */ 3170 #define I2C_A2_SAD_MASK (0xFEU) 3171 #define I2C_A2_SAD_SHIFT (1U) 3172 /*! SAD - SMBus Address 3173 */ 3174 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 3175 /*! @} */ 3176 3177 /*! @name SLTH - I2C SCL Low Timeout Register High */ 3178 /*! @{ */ 3179 #define I2C_SLTH_SSLT_MASK (0xFFU) 3180 #define I2C_SLTH_SSLT_SHIFT (0U) 3181 /*! SSLT - SSLT[15:8] 3182 */ 3183 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 3184 /*! @} */ 3185 3186 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 3187 /*! @{ */ 3188 #define I2C_SLTL_SSLT_MASK (0xFFU) 3189 #define I2C_SLTL_SSLT_SHIFT (0U) 3190 /*! SSLT - SSLT[7:0] 3191 */ 3192 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 3193 /*! @} */ 3194 3195 /*! @name S2 - I2C Status register 2 */ 3196 /*! @{ */ 3197 #define I2C_S2_EMPTY_MASK (0x1U) 3198 #define I2C_S2_EMPTY_SHIFT (0U) 3199 /*! EMPTY - Empty flag 3200 * 0b0..Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. 3201 * 0b1..Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. 3202 */ 3203 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) 3204 #define I2C_S2_ERROR_MASK (0x2U) 3205 #define I2C_S2_ERROR_SHIFT (1U) 3206 /*! ERROR - Error flag 3207 * 0b0..The buffer is not full and all write/read operations have no errors. 3208 * 0b1..There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the 3209 * buffer is busy). 3210 */ 3211 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) 3212 /*! @} */ 3213 3214 /*! 3215 * @} 3216 */ /* end of group I2C_Register_Masks */ 3217 3218 /* I2C - Peripheral instance base addresses */ 3219 /** Peripheral I2C0 base address */ 3220 #define I2C0_BASE (0x40066000u) 3221 /** Peripheral I2C0 base pointer */ 3222 #define I2C0 ((I2C_Type *)I2C0_BASE) 3223 /** Peripheral I2C1 base address */ 3224 #define I2C1_BASE (0x40067000u) 3225 /** Peripheral I2C1 base pointer */ 3226 #define I2C1 ((I2C_Type *)I2C1_BASE) 3227 /** Array initializer of I2C peripheral base addresses */ 3228 #define I2C_BASE_ADDRS \ 3229 { \ 3230 I2C0_BASE, I2C1_BASE \ 3231 } 3232 /** Array initializer of I2C peripheral base pointers */ 3233 #define I2C_BASE_PTRS \ 3234 { \ 3235 I2C0, I2C1 \ 3236 } 3237 /** Interrupt vectors for the I2C peripheral type */ 3238 #define I2C_IRQS \ 3239 { \ 3240 I2C0_IRQn, I2C1_IRQn \ 3241 } 3242 3243 /*! 3244 * @} 3245 */ /* end of group I2C_Peripheral_Access_Layer */ 3246 3247 /* ---------------------------------------------------------------------------- 3248 -- LCD Peripheral Access Layer 3249 ---------------------------------------------------------------------------- */ 3250 3251 /*! 3252 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer 3253 * @{ 3254 */ 3255 3256 /** LCD - Register Layout Typedef */ 3257 typedef struct 3258 { 3259 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ 3260 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */ 3261 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */ 3262 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */ 3263 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */ 3264 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */ 3265 union 3266 { /* offset: 0x20 */ 3267 __IO uint8_t 3268 WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */ 3269 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */ 3270 }; 3271 } LCD_Type; 3272 3273 /* ---------------------------------------------------------------------------- 3274 -- LCD Register Masks 3275 ---------------------------------------------------------------------------- */ 3276 3277 /*! 3278 * @addtogroup LCD_Register_Masks LCD Register Masks 3279 * @{ 3280 */ 3281 3282 /*! @name GCR - LCD General Control Register */ 3283 /*! @{ */ 3284 #define LCD_GCR_DUTY_MASK (0x7U) 3285 #define LCD_GCR_DUTY_SHIFT (0U) 3286 /*! DUTY - LCD duty select 3287 * 0b000..Use 1 BP (1/1 duty cycle). 3288 * 0b001..Use 2 BP (1/2 duty cycle). 3289 * 0b010..Use 3 BP (1/3 duty cycle). 3290 * 0b011..Use 4 BP (1/4 duty cycle). (Default) 3291 * 0b100.. 3292 * 0b101.. 3293 * 0b110.. 3294 * 0b111..Use 8 BP (1/8 duty cycle). 3295 */ 3296 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_DUTY_SHIFT)) & LCD_GCR_DUTY_MASK) 3297 #define LCD_GCR_LCLK_MASK (0x38U) 3298 #define LCD_GCR_LCLK_SHIFT (3U) 3299 /*! LCLK - LCD Clock Prescaler 3300 */ 3301 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCLK_SHIFT)) & LCD_GCR_LCLK_MASK) 3302 #define LCD_GCR_SOURCE_MASK (0x40U) 3303 #define LCD_GCR_SOURCE_SHIFT (6U) 3304 /*! SOURCE - LCD Clock Source Select 3305 * 0b0..Selects the default clock as the LCD clock source. 3306 * 0b1..Selects output of the alternate clock source selection (see ALTSOURCE) as the LCD clock source. 3307 */ 3308 #define LCD_GCR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SOURCE_SHIFT)) & LCD_GCR_SOURCE_MASK) 3309 #define LCD_GCR_LCDEN_MASK (0x80U) 3310 #define LCD_GCR_LCDEN_SHIFT (7U) 3311 /*! LCDEN - LCD Driver Enable 3312 * 0b0..All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD 3313 * waveform generation clocks are stopped. V LL3 is connected to V DD internally. All LCD pins, LCD_Pn, 3314 * enabled using the LCD Pin Enable register, output a low value. 3315 * 0b1..LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD 3316 * pins, LCD_Pn, enabled if PAD_SAFE is clearusing the LCD Pin Enable register, output an LCD driver 3317 * waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. 3318 * Charge pump or resistor bias is enabled. 3319 */ 3320 #define LCD_GCR_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDEN_SHIFT)) & LCD_GCR_LCDEN_MASK) 3321 #define LCD_GCR_LCDSTP_MASK (0x100U) 3322 #define LCD_GCR_LCDSTP_SHIFT (8U) 3323 /*! LCDSTP - LCD Stop 3324 * 0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during 3325 * Stop mode. 0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters 3326 * Stop mode. 3327 */ 3328 #define LCD_GCR_LCDSTP(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDSTP_SHIFT)) & LCD_GCR_LCDSTP_MASK) 3329 #define LCD_GCR_LCDDOZE_MASK (0x200U) 3330 #define LCD_GCR_LCDDOZE_SHIFT (9U) 3331 /*! LCDDOZE - LCD Doze enable 3332 * 0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during 3333 * Doze mode. 0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters 3334 * Doze mode. 3335 */ 3336 #define LCD_GCR_LCDDOZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDDOZE_SHIFT)) & LCD_GCR_LCDDOZE_MASK) 3337 #define LCD_GCR_FFR_MASK (0x400U) 3338 #define LCD_GCR_FFR_SHIFT (10U) 3339 /*! FFR - Fast Frame Rate Select 3340 * 0b0..Standard Frame Rate LCD Frame Freq: 23.3 (min) 73.1 (max) 3341 * 0b1..Fast Frame Rate (Standard Frame Rate *2) LCD Frame Freq: 46.6 (min) 146.2 (max) 3342 */ 3343 #define LCD_GCR_FFR(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FFR_SHIFT)) & LCD_GCR_FFR_MASK) 3344 #define LCD_GCR_ALTSOURCE_MASK (0x800U) 3345 #define LCD_GCR_ALTSOURCE_SHIFT (11U) 3346 /*! ALTSOURCE - Selects the alternate clock source 3347 * 0b0..Select Alternate Clock Source 1 (default) 3348 * 0b1..Select Alternate Clock Source 2 3349 */ 3350 #define LCD_GCR_ALTSOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTSOURCE_SHIFT)) & LCD_GCR_ALTSOURCE_MASK) 3351 #define LCD_GCR_ALTDIV_MASK (0x3000U) 3352 #define LCD_GCR_ALTDIV_SHIFT (12U) 3353 /*! ALTDIV - LCD Alternate Clock Divider 3354 * 0b00..Divide factor = 1 (No divide) 3355 * 0b01..Divide factor = 64 3356 * 0b10..Divide factor = 256 3357 * 0b11..Divide factor = 512 3358 */ 3359 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTDIV_SHIFT)) & LCD_GCR_ALTDIV_MASK) 3360 #define LCD_GCR_FDCIEN_MASK (0x4000U) 3361 #define LCD_GCR_FDCIEN_SHIFT (14U) 3362 /*! FDCIEN - LCD Fault Detection Complete Interrupt Enable 3363 * 0b0..No interrupt request is generated by this event. 3364 * 0b1..When a fault is detected and FDCF bit is set, this event causes an interrupt request. 3365 */ 3366 #define LCD_GCR_FDCIEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FDCIEN_SHIFT)) & LCD_GCR_FDCIEN_MASK) 3367 #define LCD_GCR_PADSAFE_MASK (0x8000U) 3368 #define LCD_GCR_PADSAFE_SHIFT (15U) 3369 /*! PADSAFE - Pad Safe State Enable 3370 * 0b0..LCD frontplane and backplane functions enabled according to other LCD control bits 3371 * 0b1..LCD frontplane and backplane functions disabled 3372 */ 3373 #define LCD_GCR_PADSAFE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_PADSAFE_SHIFT)) & LCD_GCR_PADSAFE_MASK) 3374 #define LCD_GCR_VSUPPLY_MASK (0x20000U) 3375 #define LCD_GCR_VSUPPLY_SHIFT (17U) 3376 /*! VSUPPLY - Voltage Supply Control 3377 * 0b0..Drive VLL3 internally from VDD 3378 * 0b1..Drive VLL3 externally from VDD or drive VLL1 internally from vIREG 3379 */ 3380 #define LCD_GCR_VSUPPLY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VSUPPLY_SHIFT)) & LCD_GCR_VSUPPLY_MASK) 3381 #define LCD_GCR_LADJ_MASK (0x300000U) 3382 #define LCD_GCR_LADJ_SHIFT (20U) 3383 /*! LADJ - Load Adjust 3384 */ 3385 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LADJ_SHIFT)) & LCD_GCR_LADJ_MASK) 3386 #define LCD_GCR_CPSEL_MASK (0x800000U) 3387 #define LCD_GCR_CPSEL_SHIFT (23U) 3388 /*! CPSEL - Charge Pump or Resistor Bias Select 3389 * 0b0..LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.) 3390 * 0b1..LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.) 3391 */ 3392 #define LCD_GCR_CPSEL(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_CPSEL_SHIFT)) & LCD_GCR_CPSEL_MASK) 3393 #define LCD_GCR_RVTRIM_MASK (0xF000000U) 3394 #define LCD_GCR_RVTRIM_SHIFT (24U) 3395 /*! RVTRIM - Regulated Voltage Trim 3396 */ 3397 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVTRIM_SHIFT)) & LCD_GCR_RVTRIM_MASK) 3398 #define LCD_GCR_RVEN_MASK (0x80000000U) 3399 #define LCD_GCR_RVEN_SHIFT (31U) 3400 /*! RVEN - Regulated Voltage Enable 3401 * 0b0..Regulated voltage disabled. 3402 * 0b1..Regulated voltage enabled. 3403 */ 3404 #define LCD_GCR_RVEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVEN_SHIFT)) & LCD_GCR_RVEN_MASK) 3405 /*! @} */ 3406 3407 /*! @name AR - LCD Auxiliary Register */ 3408 /*! @{ */ 3409 #define LCD_AR_BRATE_MASK (0x7U) 3410 #define LCD_AR_BRATE_SHIFT (0U) 3411 /*! BRATE - Blink-rate configuration 3412 */ 3413 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BRATE_SHIFT)) & LCD_AR_BRATE_MASK) 3414 #define LCD_AR_BMODE_MASK (0x8U) 3415 #define LCD_AR_BMODE_SHIFT (3U) 3416 /*! BMODE - Blink mode 3417 * 0b0..Display blank during the blink period. 3418 * 0b1..Display alternate display during blink period (Ignored if duty is 5 or greater). 3419 */ 3420 #define LCD_AR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BMODE_SHIFT)) & LCD_AR_BMODE_MASK) 3421 #define LCD_AR_BLANK_MASK (0x20U) 3422 #define LCD_AR_BLANK_SHIFT (5U) 3423 /*! BLANK - Blank display mode 3424 * 0b0..Normal or alternate display mode. 3425 * 0b1..Blank display mode. 3426 */ 3427 #define LCD_AR_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLANK_SHIFT)) & LCD_AR_BLANK_MASK) 3428 #define LCD_AR_ALT_MASK (0x40U) 3429 #define LCD_AR_ALT_SHIFT (6U) 3430 /*! ALT - Alternate display mode 3431 * 0b0..Normal display mode. 3432 * 0b1..Alternate display mode. 3433 */ 3434 #define LCD_AR_ALT(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_ALT_SHIFT)) & LCD_AR_ALT_MASK) 3435 #define LCD_AR_BLINK_MASK (0x80U) 3436 #define LCD_AR_BLINK_SHIFT (7U) 3437 /*! BLINK - Blink command 3438 * 0b0..Disables blinking. 3439 * 0b1..Starts blinking at blinking frequency specified by LCD blink rate calculation. 3440 */ 3441 #define LCD_AR_BLINK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLINK_SHIFT)) & LCD_AR_BLINK_MASK) 3442 /*! @} */ 3443 3444 /*! @name FDCR - LCD Fault Detect Control Register */ 3445 /*! @{ */ 3446 #define LCD_FDCR_FDPINID_MASK (0x3FU) 3447 #define LCD_FDCR_FDPINID_SHIFT (0U) 3448 /*! FDPINID - Fault Detect Pin ID 3449 * 0b000000..Fault detection for LCD_P0 pin. 3450 * 0b000001..Fault detection for LCD_P1 pin. 3451 * 0b111111..Fault detection for LCD_P63 pin. 3452 */ 3453 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPINID_SHIFT)) & LCD_FDCR_FDPINID_MASK) 3454 #define LCD_FDCR_FDBPEN_MASK (0x40U) 3455 #define LCD_FDCR_FDBPEN_SHIFT (6U) 3456 /*! FDBPEN - Fault Detect Back Plane Enable 3457 * 0b0..Type of the selected pin under fault detect test is front plane. 3458 * 0b1..Type of the selected pin under fault detect test is back plane. 3459 */ 3460 #define LCD_FDCR_FDBPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDBPEN_SHIFT)) & LCD_FDCR_FDBPEN_MASK) 3461 #define LCD_FDCR_FDEN_MASK (0x80U) 3462 #define LCD_FDCR_FDEN_SHIFT (7U) 3463 /*! FDEN - Fault Detect Enable 3464 * 0b0..Disable fault detection. 3465 * 0b1..Enable fault detection. 3466 */ 3467 #define LCD_FDCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDEN_SHIFT)) & LCD_FDCR_FDEN_MASK) 3468 #define LCD_FDCR_FDSWW_MASK (0xE00U) 3469 #define LCD_FDCR_FDSWW_SHIFT (9U) 3470 /*! FDSWW - Fault Detect Sample Window Width 3471 * 0b000..Sample window width is 4 sample clock cycles. 3472 * 0b001..Sample window width is 8 sample clock cycles. 3473 * 0b010..Sample window width is 16 sample clock cycles. 3474 * 0b011..Sample window width is 32 sample clock cycles. 3475 * 0b100..Sample window width is 64 sample clock cycles. 3476 * 0b101..Sample window width is 128 sample clock cycles. 3477 * 0b110..Sample window width is 256 sample clock cycles. 3478 * 0b111..Sample window width is 512 sample clock cycles. 3479 */ 3480 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDSWW_SHIFT)) & LCD_FDCR_FDSWW_MASK) 3481 #define LCD_FDCR_FDPRS_MASK (0x7000U) 3482 #define LCD_FDCR_FDPRS_SHIFT (12U) 3483 /*! FDPRS - Fault Detect Clock Prescaler 3484 * 0b000..1/1 bus clock. 3485 * 0b001..1/2 bus clock. 3486 * 0b010..1/4 bus clock. 3487 * 0b011..1/8 bus clock. 3488 * 0b100..1/16 bus clock. 3489 * 0b101..1/32 bus clock. 3490 * 0b110..1/64 bus clock. 3491 * 0b111..1/128 bus clock. 3492 */ 3493 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPRS_SHIFT)) & LCD_FDCR_FDPRS_MASK) 3494 /*! @} */ 3495 3496 /*! @name FDSR - LCD Fault Detect Status Register */ 3497 /*! @{ */ 3498 #define LCD_FDSR_FDCNT_MASK (0xFFU) 3499 #define LCD_FDSR_FDCNT_SHIFT (0U) 3500 /*! FDCNT - Fault Detect Counter 3501 * 0b00000000..No "one" samples. 3502 * 0b00000001..1 "one" samples. 3503 * 0b00000010..2 "one" samples. 3504 * 0b11111110..254 "one" samples. 3505 * 0b11111111..255 or more "one" samples. The FDCNT can overflow. Therefore, FDSWW and FDPRS must be reconfigured for 3506 * proper sampling. 3507 */ 3508 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCNT_SHIFT)) & LCD_FDSR_FDCNT_MASK) 3509 #define LCD_FDSR_FDCF_MASK (0x8000U) 3510 #define LCD_FDSR_FDCF_SHIFT (15U) 3511 /*! FDCF - Fault Detection Complete Flag 3512 * 0b0..Fault detection is not completed. 3513 * 0b1..Fault detection is completed. 3514 */ 3515 #define LCD_FDSR_FDCF(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCF_SHIFT)) & LCD_FDSR_FDCF_MASK) 3516 /*! @} */ 3517 3518 /*! @name PEN - LCD Pin Enable register */ 3519 /*! @{ */ 3520 #define LCD_PEN_PEN_MASK (0xFFFFFFFFU) 3521 #define LCD_PEN_PEN_SHIFT (0U) 3522 /*! PEN - LCD Pin Enable 3523 * 0b00000000000000000000000000000000..LCD operation disabled on LCD_Pn. 3524 * 0b00000000000000000000000000000001..LCD operation enabled on LCD_Pn. 3525 */ 3526 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PEN_SHIFT)) & LCD_PEN_PEN_MASK) 3527 /*! @} */ 3528 3529 /* The count of LCD_PEN */ 3530 #define LCD_PEN_COUNT (2U) 3531 3532 /*! @name BPEN - LCD Back Plane Enable register */ 3533 /*! @{ */ 3534 #define LCD_BPEN_BPEN_MASK (0xFFFFFFFFU) 3535 #define LCD_BPEN_BPEN_SHIFT (0U) 3536 /*! BPEN - Back Plane Enable 3537 * 0b00000000000000000000000000000000..Front plane operation enabled on LCD_Pn. 3538 * 0b00000000000000000000000000000001..Back plane operation enabled on LCD_Pn. 3539 */ 3540 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_BPEN_SHIFT)) & LCD_BPEN_BPEN_MASK) 3541 /*! @} */ 3542 3543 /* The count of LCD_BPEN */ 3544 #define LCD_BPEN_COUNT (2U) 3545 3546 /*! @name WF8B - LCD Waveform Register 0...LCD Waveform Register 63. */ 3547 /*! @{ */ 3548 #define LCD_WF8B_BPALCD0_MASK (0x1U) 3549 #define LCD_WF8B_BPALCD0_SHIFT (0U) 3550 /*! BPALCD0 3551 * 0b0..LCD segment off or LCD backplane inactive for phase A 3552 * 0b1..LCD segment on or LCD backplane active for phase A 3553 */ 3554 #define LCD_WF8B_BPALCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD0_SHIFT)) & LCD_WF8B_BPALCD0_MASK) 3555 #define LCD_WF8B_BPALCD1_MASK (0x1U) 3556 #define LCD_WF8B_BPALCD1_SHIFT (0U) 3557 /*! BPALCD1 3558 * 0b0..LCD segment off or LCD backplane inactive for phase A 3559 * 0b1..LCD segment on or LCD backplane active for phase A 3560 */ 3561 #define LCD_WF8B_BPALCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD1_SHIFT)) & LCD_WF8B_BPALCD1_MASK) 3562 #define LCD_WF8B_BPALCD2_MASK (0x1U) 3563 #define LCD_WF8B_BPALCD2_SHIFT (0U) 3564 /*! BPALCD2 3565 * 0b0..LCD segment off or LCD backplane inactive for phase A 3566 * 0b1..LCD segment on or LCD backplane active for phase A 3567 */ 3568 #define LCD_WF8B_BPALCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD2_SHIFT)) & LCD_WF8B_BPALCD2_MASK) 3569 #define LCD_WF8B_BPALCD3_MASK (0x1U) 3570 #define LCD_WF8B_BPALCD3_SHIFT (0U) 3571 /*! BPALCD3 3572 * 0b0..LCD segment off or LCD backplane inactive for phase A 3573 * 0b1..LCD segment on or LCD backplane active for phase A 3574 */ 3575 #define LCD_WF8B_BPALCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD3_SHIFT)) & LCD_WF8B_BPALCD3_MASK) 3576 #define LCD_WF8B_BPALCD4_MASK (0x1U) 3577 #define LCD_WF8B_BPALCD4_SHIFT (0U) 3578 /*! BPALCD4 3579 * 0b0..LCD segment off or LCD backplane inactive for phase A 3580 * 0b1..LCD segment on or LCD backplane active for phase A 3581 */ 3582 #define LCD_WF8B_BPALCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD4_SHIFT)) & LCD_WF8B_BPALCD4_MASK) 3583 #define LCD_WF8B_BPALCD5_MASK (0x1U) 3584 #define LCD_WF8B_BPALCD5_SHIFT (0U) 3585 /*! BPALCD5 3586 * 0b0..LCD segment off or LCD backplane inactive for phase A 3587 * 0b1..LCD segment on or LCD backplane active for phase A 3588 */ 3589 #define LCD_WF8B_BPALCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD5_SHIFT)) & LCD_WF8B_BPALCD5_MASK) 3590 #define LCD_WF8B_BPALCD6_MASK (0x1U) 3591 #define LCD_WF8B_BPALCD6_SHIFT (0U) 3592 /*! BPALCD6 3593 * 0b0..LCD segment off or LCD backplane inactive for phase A 3594 * 0b1..LCD segment on or LCD backplane active for phase A 3595 */ 3596 #define LCD_WF8B_BPALCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD6_SHIFT)) & LCD_WF8B_BPALCD6_MASK) 3597 #define LCD_WF8B_BPALCD7_MASK (0x1U) 3598 #define LCD_WF8B_BPALCD7_SHIFT (0U) 3599 /*! BPALCD7 3600 * 0b0..LCD segment off or LCD backplane inactive for phase A 3601 * 0b1..LCD segment on or LCD backplane active for phase A 3602 */ 3603 #define LCD_WF8B_BPALCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD7_SHIFT)) & LCD_WF8B_BPALCD7_MASK) 3604 #define LCD_WF8B_BPALCD8_MASK (0x1U) 3605 #define LCD_WF8B_BPALCD8_SHIFT (0U) 3606 /*! BPALCD8 3607 * 0b0..LCD segment off or LCD backplane inactive for phase A 3608 * 0b1..LCD segment on or LCD backplane active for phase A 3609 */ 3610 #define LCD_WF8B_BPALCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD8_SHIFT)) & LCD_WF8B_BPALCD8_MASK) 3611 #define LCD_WF8B_BPALCD9_MASK (0x1U) 3612 #define LCD_WF8B_BPALCD9_SHIFT (0U) 3613 /*! BPALCD9 3614 * 0b0..LCD segment off or LCD backplane inactive for phase A 3615 * 0b1..LCD segment on or LCD backplane active for phase A 3616 */ 3617 #define LCD_WF8B_BPALCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD9_SHIFT)) & LCD_WF8B_BPALCD9_MASK) 3618 #define LCD_WF8B_BPALCD10_MASK (0x1U) 3619 #define LCD_WF8B_BPALCD10_SHIFT (0U) 3620 /*! BPALCD10 3621 * 0b0..LCD segment off or LCD backplane inactive for phase A 3622 * 0b1..LCD segment on or LCD backplane active for phase A 3623 */ 3624 #define LCD_WF8B_BPALCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD10_SHIFT)) & LCD_WF8B_BPALCD10_MASK) 3625 #define LCD_WF8B_BPALCD11_MASK (0x1U) 3626 #define LCD_WF8B_BPALCD11_SHIFT (0U) 3627 /*! BPALCD11 3628 * 0b0..LCD segment off or LCD backplane inactive for phase A 3629 * 0b1..LCD segment on or LCD backplane active for phase A 3630 */ 3631 #define LCD_WF8B_BPALCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD11_SHIFT)) & LCD_WF8B_BPALCD11_MASK) 3632 #define LCD_WF8B_BPALCD12_MASK (0x1U) 3633 #define LCD_WF8B_BPALCD12_SHIFT (0U) 3634 /*! BPALCD12 3635 * 0b0..LCD segment off or LCD backplane inactive for phase A 3636 * 0b1..LCD segment on or LCD backplane active for phase A 3637 */ 3638 #define LCD_WF8B_BPALCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD12_SHIFT)) & LCD_WF8B_BPALCD12_MASK) 3639 #define LCD_WF8B_BPALCD13_MASK (0x1U) 3640 #define LCD_WF8B_BPALCD13_SHIFT (0U) 3641 /*! BPALCD13 3642 * 0b0..LCD segment off or LCD backplane inactive for phase A 3643 * 0b1..LCD segment on or LCD backplane active for phase A 3644 */ 3645 #define LCD_WF8B_BPALCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD13_SHIFT)) & LCD_WF8B_BPALCD13_MASK) 3646 #define LCD_WF8B_BPALCD14_MASK (0x1U) 3647 #define LCD_WF8B_BPALCD14_SHIFT (0U) 3648 /*! BPALCD14 3649 * 0b0..LCD segment off or LCD backplane inactive for phase A 3650 * 0b1..LCD segment on or LCD backplane active for phase A 3651 */ 3652 #define LCD_WF8B_BPALCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD14_SHIFT)) & LCD_WF8B_BPALCD14_MASK) 3653 #define LCD_WF8B_BPALCD15_MASK (0x1U) 3654 #define LCD_WF8B_BPALCD15_SHIFT (0U) 3655 /*! BPALCD15 3656 * 0b0..LCD segment off or LCD backplane inactive for phase A 3657 * 0b1..LCD segment on or LCD backplane active for phase A 3658 */ 3659 #define LCD_WF8B_BPALCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD15_SHIFT)) & LCD_WF8B_BPALCD15_MASK) 3660 #define LCD_WF8B_BPALCD16_MASK (0x1U) 3661 #define LCD_WF8B_BPALCD16_SHIFT (0U) 3662 /*! BPALCD16 3663 * 0b0..LCD segment off or LCD backplane inactive for phase A 3664 * 0b1..LCD segment on or LCD backplane active for phase A 3665 */ 3666 #define LCD_WF8B_BPALCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD16_SHIFT)) & LCD_WF8B_BPALCD16_MASK) 3667 #define LCD_WF8B_BPALCD17_MASK (0x1U) 3668 #define LCD_WF8B_BPALCD17_SHIFT (0U) 3669 /*! BPALCD17 3670 * 0b0..LCD segment off or LCD backplane inactive for phase A 3671 * 0b1..LCD segment on or LCD backplane active for phase A 3672 */ 3673 #define LCD_WF8B_BPALCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD17_SHIFT)) & LCD_WF8B_BPALCD17_MASK) 3674 #define LCD_WF8B_BPALCD18_MASK (0x1U) 3675 #define LCD_WF8B_BPALCD18_SHIFT (0U) 3676 /*! BPALCD18 3677 * 0b0..LCD segment off or LCD backplane inactive for phase A 3678 * 0b1..LCD segment on or LCD backplane active for phase A 3679 */ 3680 #define LCD_WF8B_BPALCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD18_SHIFT)) & LCD_WF8B_BPALCD18_MASK) 3681 #define LCD_WF8B_BPALCD19_MASK (0x1U) 3682 #define LCD_WF8B_BPALCD19_SHIFT (0U) 3683 /*! BPALCD19 3684 * 0b0..LCD segment off or LCD backplane inactive for phase A 3685 * 0b1..LCD segment on or LCD backplane active for phase A 3686 */ 3687 #define LCD_WF8B_BPALCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD19_SHIFT)) & LCD_WF8B_BPALCD19_MASK) 3688 #define LCD_WF8B_BPALCD20_MASK (0x1U) 3689 #define LCD_WF8B_BPALCD20_SHIFT (0U) 3690 /*! BPALCD20 3691 * 0b0..LCD segment off or LCD backplane inactive for phase A 3692 * 0b1..LCD segment on or LCD backplane active for phase A 3693 */ 3694 #define LCD_WF8B_BPALCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD20_SHIFT)) & LCD_WF8B_BPALCD20_MASK) 3695 #define LCD_WF8B_BPALCD21_MASK (0x1U) 3696 #define LCD_WF8B_BPALCD21_SHIFT (0U) 3697 /*! BPALCD21 3698 * 0b0..LCD segment off or LCD backplane inactive for phase A 3699 * 0b1..LCD segment on or LCD backplane active for phase A 3700 */ 3701 #define LCD_WF8B_BPALCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD21_SHIFT)) & LCD_WF8B_BPALCD21_MASK) 3702 #define LCD_WF8B_BPALCD22_MASK (0x1U) 3703 #define LCD_WF8B_BPALCD22_SHIFT (0U) 3704 /*! BPALCD22 3705 * 0b0..LCD segment off or LCD backplane inactive for phase A 3706 * 0b1..LCD segment on or LCD backplane active for phase A 3707 */ 3708 #define LCD_WF8B_BPALCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD22_SHIFT)) & LCD_WF8B_BPALCD22_MASK) 3709 #define LCD_WF8B_BPALCD23_MASK (0x1U) 3710 #define LCD_WF8B_BPALCD23_SHIFT (0U) 3711 /*! BPALCD23 3712 * 0b0..LCD segment off or LCD backplane inactive for phase A 3713 * 0b1..LCD segment on or LCD backplane active for phase A 3714 */ 3715 #define LCD_WF8B_BPALCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD23_SHIFT)) & LCD_WF8B_BPALCD23_MASK) 3716 #define LCD_WF8B_BPALCD24_MASK (0x1U) 3717 #define LCD_WF8B_BPALCD24_SHIFT (0U) 3718 /*! BPALCD24 3719 * 0b0..LCD segment off or LCD backplane inactive for phase A 3720 * 0b1..LCD segment on or LCD backplane active for phase A 3721 */ 3722 #define LCD_WF8B_BPALCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD24_SHIFT)) & LCD_WF8B_BPALCD24_MASK) 3723 #define LCD_WF8B_BPALCD25_MASK (0x1U) 3724 #define LCD_WF8B_BPALCD25_SHIFT (0U) 3725 /*! BPALCD25 3726 * 0b0..LCD segment off or LCD backplane inactive for phase A 3727 * 0b1..LCD segment on or LCD backplane active for phase A 3728 */ 3729 #define LCD_WF8B_BPALCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD25_SHIFT)) & LCD_WF8B_BPALCD25_MASK) 3730 #define LCD_WF8B_BPALCD26_MASK (0x1U) 3731 #define LCD_WF8B_BPALCD26_SHIFT (0U) 3732 /*! BPALCD26 3733 * 0b0..LCD segment off or LCD backplane inactive for phase A 3734 * 0b1..LCD segment on or LCD backplane active for phase A 3735 */ 3736 #define LCD_WF8B_BPALCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD26_SHIFT)) & LCD_WF8B_BPALCD26_MASK) 3737 #define LCD_WF8B_BPALCD27_MASK (0x1U) 3738 #define LCD_WF8B_BPALCD27_SHIFT (0U) 3739 /*! BPALCD27 3740 * 0b0..LCD segment off or LCD backplane inactive for phase A 3741 * 0b1..LCD segment on or LCD backplane active for phase A 3742 */ 3743 #define LCD_WF8B_BPALCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD27_SHIFT)) & LCD_WF8B_BPALCD27_MASK) 3744 #define LCD_WF8B_BPALCD28_MASK (0x1U) 3745 #define LCD_WF8B_BPALCD28_SHIFT (0U) 3746 /*! BPALCD28 3747 * 0b0..LCD segment off or LCD backplane inactive for phase A 3748 * 0b1..LCD segment on or LCD backplane active for phase A 3749 */ 3750 #define LCD_WF8B_BPALCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD28_SHIFT)) & LCD_WF8B_BPALCD28_MASK) 3751 #define LCD_WF8B_BPALCD29_MASK (0x1U) 3752 #define LCD_WF8B_BPALCD29_SHIFT (0U) 3753 /*! BPALCD29 3754 * 0b0..LCD segment off or LCD backplane inactive for phase A 3755 * 0b1..LCD segment on or LCD backplane active for phase A 3756 */ 3757 #define LCD_WF8B_BPALCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD29_SHIFT)) & LCD_WF8B_BPALCD29_MASK) 3758 #define LCD_WF8B_BPALCD30_MASK (0x1U) 3759 #define LCD_WF8B_BPALCD30_SHIFT (0U) 3760 /*! BPALCD30 3761 * 0b0..LCD segment off or LCD backplane inactive for phase A 3762 * 0b1..LCD segment on or LCD backplane active for phase A 3763 */ 3764 #define LCD_WF8B_BPALCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD30_SHIFT)) & LCD_WF8B_BPALCD30_MASK) 3765 #define LCD_WF8B_BPALCD31_MASK (0x1U) 3766 #define LCD_WF8B_BPALCD31_SHIFT (0U) 3767 /*! BPALCD31 3768 * 0b0..LCD segment off or LCD backplane inactive for phase A 3769 * 0b1..LCD segment on or LCD backplane active for phase A 3770 */ 3771 #define LCD_WF8B_BPALCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD31_SHIFT)) & LCD_WF8B_BPALCD31_MASK) 3772 #define LCD_WF8B_BPALCD32_MASK (0x1U) 3773 #define LCD_WF8B_BPALCD32_SHIFT (0U) 3774 /*! BPALCD32 3775 * 0b0..LCD segment off or LCD backplane inactive for phase A 3776 * 0b1..LCD segment on or LCD backplane active for phase A 3777 */ 3778 #define LCD_WF8B_BPALCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD32_SHIFT)) & LCD_WF8B_BPALCD32_MASK) 3779 #define LCD_WF8B_BPALCD33_MASK (0x1U) 3780 #define LCD_WF8B_BPALCD33_SHIFT (0U) 3781 /*! BPALCD33 3782 * 0b0..LCD segment off or LCD backplane inactive for phase A 3783 * 0b1..LCD segment on or LCD backplane active for phase A 3784 */ 3785 #define LCD_WF8B_BPALCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD33_SHIFT)) & LCD_WF8B_BPALCD33_MASK) 3786 #define LCD_WF8B_BPALCD34_MASK (0x1U) 3787 #define LCD_WF8B_BPALCD34_SHIFT (0U) 3788 /*! BPALCD34 3789 * 0b0..LCD segment off or LCD backplane inactive for phase A 3790 * 0b1..LCD segment on or LCD backplane active for phase A 3791 */ 3792 #define LCD_WF8B_BPALCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD34_SHIFT)) & LCD_WF8B_BPALCD34_MASK) 3793 #define LCD_WF8B_BPALCD35_MASK (0x1U) 3794 #define LCD_WF8B_BPALCD35_SHIFT (0U) 3795 /*! BPALCD35 3796 * 0b0..LCD segment off or LCD backplane inactive for phase A 3797 * 0b1..LCD segment on or LCD backplane active for phase A 3798 */ 3799 #define LCD_WF8B_BPALCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD35_SHIFT)) & LCD_WF8B_BPALCD35_MASK) 3800 #define LCD_WF8B_BPALCD36_MASK (0x1U) 3801 #define LCD_WF8B_BPALCD36_SHIFT (0U) 3802 /*! BPALCD36 3803 * 0b0..LCD segment off or LCD backplane inactive for phase A 3804 * 0b1..LCD segment on or LCD backplane active for phase A 3805 */ 3806 #define LCD_WF8B_BPALCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD36_SHIFT)) & LCD_WF8B_BPALCD36_MASK) 3807 #define LCD_WF8B_BPALCD37_MASK (0x1U) 3808 #define LCD_WF8B_BPALCD37_SHIFT (0U) 3809 /*! BPALCD37 3810 * 0b0..LCD segment off or LCD backplane inactive for phase A 3811 * 0b1..LCD segment on or LCD backplane active for phase A 3812 */ 3813 #define LCD_WF8B_BPALCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD37_SHIFT)) & LCD_WF8B_BPALCD37_MASK) 3814 #define LCD_WF8B_BPALCD38_MASK (0x1U) 3815 #define LCD_WF8B_BPALCD38_SHIFT (0U) 3816 /*! BPALCD38 3817 * 0b0..LCD segment off or LCD backplane inactive for phase A 3818 * 0b1..LCD segment on or LCD backplane active for phase A 3819 */ 3820 #define LCD_WF8B_BPALCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD38_SHIFT)) & LCD_WF8B_BPALCD38_MASK) 3821 #define LCD_WF8B_BPALCD39_MASK (0x1U) 3822 #define LCD_WF8B_BPALCD39_SHIFT (0U) 3823 /*! BPALCD39 3824 * 0b0..LCD segment off or LCD backplane inactive for phase A 3825 * 0b1..LCD segment on or LCD backplane active for phase A 3826 */ 3827 #define LCD_WF8B_BPALCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD39_SHIFT)) & LCD_WF8B_BPALCD39_MASK) 3828 #define LCD_WF8B_BPALCD40_MASK (0x1U) 3829 #define LCD_WF8B_BPALCD40_SHIFT (0U) 3830 /*! BPALCD40 3831 * 0b0..LCD segment off or LCD backplane inactive for phase A 3832 * 0b1..LCD segment on or LCD backplane active for phase A 3833 */ 3834 #define LCD_WF8B_BPALCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD40_SHIFT)) & LCD_WF8B_BPALCD40_MASK) 3835 #define LCD_WF8B_BPALCD41_MASK (0x1U) 3836 #define LCD_WF8B_BPALCD41_SHIFT (0U) 3837 /*! BPALCD41 3838 * 0b0..LCD segment off or LCD backplane inactive for phase A 3839 * 0b1..LCD segment on or LCD backplane active for phase A 3840 */ 3841 #define LCD_WF8B_BPALCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD41_SHIFT)) & LCD_WF8B_BPALCD41_MASK) 3842 #define LCD_WF8B_BPALCD42_MASK (0x1U) 3843 #define LCD_WF8B_BPALCD42_SHIFT (0U) 3844 /*! BPALCD42 3845 * 0b0..LCD segment off or LCD backplane inactive for phase A 3846 * 0b1..LCD segment on or LCD backplane active for phase A 3847 */ 3848 #define LCD_WF8B_BPALCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD42_SHIFT)) & LCD_WF8B_BPALCD42_MASK) 3849 #define LCD_WF8B_BPALCD43_MASK (0x1U) 3850 #define LCD_WF8B_BPALCD43_SHIFT (0U) 3851 /*! BPALCD43 3852 * 0b0..LCD segment off or LCD backplane inactive for phase A 3853 * 0b1..LCD segment on or LCD backplane active for phase A 3854 */ 3855 #define LCD_WF8B_BPALCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD43_SHIFT)) & LCD_WF8B_BPALCD43_MASK) 3856 #define LCD_WF8B_BPALCD44_MASK (0x1U) 3857 #define LCD_WF8B_BPALCD44_SHIFT (0U) 3858 /*! BPALCD44 3859 * 0b0..LCD segment off or LCD backplane inactive for phase A 3860 * 0b1..LCD segment on or LCD backplane active for phase A 3861 */ 3862 #define LCD_WF8B_BPALCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD44_SHIFT)) & LCD_WF8B_BPALCD44_MASK) 3863 #define LCD_WF8B_BPALCD45_MASK (0x1U) 3864 #define LCD_WF8B_BPALCD45_SHIFT (0U) 3865 /*! BPALCD45 3866 * 0b0..LCD segment off or LCD backplane inactive for phase A 3867 * 0b1..LCD segment on or LCD backplane active for phase A 3868 */ 3869 #define LCD_WF8B_BPALCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD45_SHIFT)) & LCD_WF8B_BPALCD45_MASK) 3870 #define LCD_WF8B_BPALCD46_MASK (0x1U) 3871 #define LCD_WF8B_BPALCD46_SHIFT (0U) 3872 /*! BPALCD46 3873 * 0b0..LCD segment off or LCD backplane inactive for phase A 3874 * 0b1..LCD segment on or LCD backplane active for phase A 3875 */ 3876 #define LCD_WF8B_BPALCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD46_SHIFT)) & LCD_WF8B_BPALCD46_MASK) 3877 #define LCD_WF8B_BPALCD47_MASK (0x1U) 3878 #define LCD_WF8B_BPALCD47_SHIFT (0U) 3879 /*! BPALCD47 3880 * 0b0..LCD segment off or LCD backplane inactive for phase A 3881 * 0b1..LCD segment on or LCD backplane active for phase A 3882 */ 3883 #define LCD_WF8B_BPALCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD47_SHIFT)) & LCD_WF8B_BPALCD47_MASK) 3884 #define LCD_WF8B_BPALCD48_MASK (0x1U) 3885 #define LCD_WF8B_BPALCD48_SHIFT (0U) 3886 /*! BPALCD48 3887 * 0b0..LCD segment off or LCD backplane inactive for phase A 3888 * 0b1..LCD segment on or LCD backplane active for phase A 3889 */ 3890 #define LCD_WF8B_BPALCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD48_SHIFT)) & LCD_WF8B_BPALCD48_MASK) 3891 #define LCD_WF8B_BPALCD49_MASK (0x1U) 3892 #define LCD_WF8B_BPALCD49_SHIFT (0U) 3893 /*! BPALCD49 3894 * 0b0..LCD segment off or LCD backplane inactive for phase A 3895 * 0b1..LCD segment on or LCD backplane active for phase A 3896 */ 3897 #define LCD_WF8B_BPALCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD49_SHIFT)) & LCD_WF8B_BPALCD49_MASK) 3898 #define LCD_WF8B_BPALCD50_MASK (0x1U) 3899 #define LCD_WF8B_BPALCD50_SHIFT (0U) 3900 /*! BPALCD50 3901 * 0b0..LCD segment off or LCD backplane inactive for phase A 3902 * 0b1..LCD segment on or LCD backplane active for phase A 3903 */ 3904 #define LCD_WF8B_BPALCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD50_SHIFT)) & LCD_WF8B_BPALCD50_MASK) 3905 #define LCD_WF8B_BPALCD51_MASK (0x1U) 3906 #define LCD_WF8B_BPALCD51_SHIFT (0U) 3907 /*! BPALCD51 3908 * 0b0..LCD segment off or LCD backplane inactive for phase A 3909 * 0b1..LCD segment on or LCD backplane active for phase A 3910 */ 3911 #define LCD_WF8B_BPALCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD51_SHIFT)) & LCD_WF8B_BPALCD51_MASK) 3912 #define LCD_WF8B_BPALCD52_MASK (0x1U) 3913 #define LCD_WF8B_BPALCD52_SHIFT (0U) 3914 /*! BPALCD52 3915 * 0b0..LCD segment off or LCD backplane inactive for phase A 3916 * 0b1..LCD segment on or LCD backplane active for phase A 3917 */ 3918 #define LCD_WF8B_BPALCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD52_SHIFT)) & LCD_WF8B_BPALCD52_MASK) 3919 #define LCD_WF8B_BPALCD53_MASK (0x1U) 3920 #define LCD_WF8B_BPALCD53_SHIFT (0U) 3921 /*! BPALCD53 3922 * 0b0..LCD segment off or LCD backplane inactive for phase A 3923 * 0b1..LCD segment on or LCD backplane active for phase A 3924 */ 3925 #define LCD_WF8B_BPALCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD53_SHIFT)) & LCD_WF8B_BPALCD53_MASK) 3926 #define LCD_WF8B_BPALCD54_MASK (0x1U) 3927 #define LCD_WF8B_BPALCD54_SHIFT (0U) 3928 /*! BPALCD54 3929 * 0b0..LCD segment off or LCD backplane inactive for phase A 3930 * 0b1..LCD segment on or LCD backplane active for phase A 3931 */ 3932 #define LCD_WF8B_BPALCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD54_SHIFT)) & LCD_WF8B_BPALCD54_MASK) 3933 #define LCD_WF8B_BPALCD55_MASK (0x1U) 3934 #define LCD_WF8B_BPALCD55_SHIFT (0U) 3935 /*! BPALCD55 3936 * 0b0..LCD segment off or LCD backplane inactive for phase A 3937 * 0b1..LCD segment on or LCD backplane active for phase A 3938 */ 3939 #define LCD_WF8B_BPALCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD55_SHIFT)) & LCD_WF8B_BPALCD55_MASK) 3940 #define LCD_WF8B_BPALCD56_MASK (0x1U) 3941 #define LCD_WF8B_BPALCD56_SHIFT (0U) 3942 /*! BPALCD56 3943 * 0b0..LCD segment off or LCD backplane inactive for phase A 3944 * 0b1..LCD segment on or LCD backplane active for phase A 3945 */ 3946 #define LCD_WF8B_BPALCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD56_SHIFT)) & LCD_WF8B_BPALCD56_MASK) 3947 #define LCD_WF8B_BPALCD57_MASK (0x1U) 3948 #define LCD_WF8B_BPALCD57_SHIFT (0U) 3949 /*! BPALCD57 3950 * 0b0..LCD segment off or LCD backplane inactive for phase A 3951 * 0b1..LCD segment on or LCD backplane active for phase A 3952 */ 3953 #define LCD_WF8B_BPALCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD57_SHIFT)) & LCD_WF8B_BPALCD57_MASK) 3954 #define LCD_WF8B_BPALCD58_MASK (0x1U) 3955 #define LCD_WF8B_BPALCD58_SHIFT (0U) 3956 /*! BPALCD58 3957 * 0b0..LCD segment off or LCD backplane inactive for phase A 3958 * 0b1..LCD segment on or LCD backplane active for phase A 3959 */ 3960 #define LCD_WF8B_BPALCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD58_SHIFT)) & LCD_WF8B_BPALCD58_MASK) 3961 #define LCD_WF8B_BPALCD59_MASK (0x1U) 3962 #define LCD_WF8B_BPALCD59_SHIFT (0U) 3963 /*! BPALCD59 3964 * 0b0..LCD segment off or LCD backplane inactive for phase A 3965 * 0b1..LCD segment on or LCD backplane active for phase A 3966 */ 3967 #define LCD_WF8B_BPALCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD59_SHIFT)) & LCD_WF8B_BPALCD59_MASK) 3968 #define LCD_WF8B_BPALCD60_MASK (0x1U) 3969 #define LCD_WF8B_BPALCD60_SHIFT (0U) 3970 /*! BPALCD60 3971 * 0b0..LCD segment off or LCD backplane inactive for phase A 3972 * 0b1..LCD segment on or LCD backplane active for phase A 3973 */ 3974 #define LCD_WF8B_BPALCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD60_SHIFT)) & LCD_WF8B_BPALCD60_MASK) 3975 #define LCD_WF8B_BPALCD61_MASK (0x1U) 3976 #define LCD_WF8B_BPALCD61_SHIFT (0U) 3977 /*! BPALCD61 3978 * 0b0..LCD segment off or LCD backplane inactive for phase A 3979 * 0b1..LCD segment on or LCD backplane active for phase A 3980 */ 3981 #define LCD_WF8B_BPALCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD61_SHIFT)) & LCD_WF8B_BPALCD61_MASK) 3982 #define LCD_WF8B_BPALCD62_MASK (0x1U) 3983 #define LCD_WF8B_BPALCD62_SHIFT (0U) 3984 /*! BPALCD62 3985 * 0b0..LCD segment off or LCD backplane inactive for phase A 3986 * 0b1..LCD segment on or LCD backplane active for phase A 3987 */ 3988 #define LCD_WF8B_BPALCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD62_SHIFT)) & LCD_WF8B_BPALCD62_MASK) 3989 #define LCD_WF8B_BPALCD63_MASK (0x1U) 3990 #define LCD_WF8B_BPALCD63_SHIFT (0U) 3991 /*! BPALCD63 3992 * 0b0..LCD segment off or LCD backplane inactive for phase A 3993 * 0b1..LCD segment on or LCD backplane active for phase A 3994 */ 3995 #define LCD_WF8B_BPALCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD63_SHIFT)) & LCD_WF8B_BPALCD63_MASK) 3996 #define LCD_WF8B_BPBLCD0_MASK (0x2U) 3997 #define LCD_WF8B_BPBLCD0_SHIFT (1U) 3998 /*! BPBLCD0 3999 * 0b0..LCD segment off or LCD backplane inactive for phase B 4000 * 0b1..LCD segment on or LCD backplane active for phase B 4001 */ 4002 #define LCD_WF8B_BPBLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD0_SHIFT)) & LCD_WF8B_BPBLCD0_MASK) 4003 #define LCD_WF8B_BPBLCD1_MASK (0x2U) 4004 #define LCD_WF8B_BPBLCD1_SHIFT (1U) 4005 /*! BPBLCD1 4006 * 0b0..LCD segment off or LCD backplane inactive for phase B 4007 * 0b1..LCD segment on or LCD backplane active for phase B 4008 */ 4009 #define LCD_WF8B_BPBLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD1_SHIFT)) & LCD_WF8B_BPBLCD1_MASK) 4010 #define LCD_WF8B_BPBLCD2_MASK (0x2U) 4011 #define LCD_WF8B_BPBLCD2_SHIFT (1U) 4012 /*! BPBLCD2 4013 * 0b0..LCD segment off or LCD backplane inactive for phase B 4014 * 0b1..LCD segment on or LCD backplane active for phase B 4015 */ 4016 #define LCD_WF8B_BPBLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD2_SHIFT)) & LCD_WF8B_BPBLCD2_MASK) 4017 #define LCD_WF8B_BPBLCD3_MASK (0x2U) 4018 #define LCD_WF8B_BPBLCD3_SHIFT (1U) 4019 /*! BPBLCD3 4020 * 0b0..LCD segment off or LCD backplane inactive for phase B 4021 * 0b1..LCD segment on or LCD backplane active for phase B 4022 */ 4023 #define LCD_WF8B_BPBLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD3_SHIFT)) & LCD_WF8B_BPBLCD3_MASK) 4024 #define LCD_WF8B_BPBLCD4_MASK (0x2U) 4025 #define LCD_WF8B_BPBLCD4_SHIFT (1U) 4026 /*! BPBLCD4 4027 * 0b0..LCD segment off or LCD backplane inactive for phase B 4028 * 0b1..LCD segment on or LCD backplane active for phase B 4029 */ 4030 #define LCD_WF8B_BPBLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD4_SHIFT)) & LCD_WF8B_BPBLCD4_MASK) 4031 #define LCD_WF8B_BPBLCD5_MASK (0x2U) 4032 #define LCD_WF8B_BPBLCD5_SHIFT (1U) 4033 /*! BPBLCD5 4034 * 0b0..LCD segment off or LCD backplane inactive for phase B 4035 * 0b1..LCD segment on or LCD backplane active for phase B 4036 */ 4037 #define LCD_WF8B_BPBLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD5_SHIFT)) & LCD_WF8B_BPBLCD5_MASK) 4038 #define LCD_WF8B_BPBLCD6_MASK (0x2U) 4039 #define LCD_WF8B_BPBLCD6_SHIFT (1U) 4040 /*! BPBLCD6 4041 * 0b0..LCD segment off or LCD backplane inactive for phase B 4042 * 0b1..LCD segment on or LCD backplane active for phase B 4043 */ 4044 #define LCD_WF8B_BPBLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD6_SHIFT)) & LCD_WF8B_BPBLCD6_MASK) 4045 #define LCD_WF8B_BPBLCD7_MASK (0x2U) 4046 #define LCD_WF8B_BPBLCD7_SHIFT (1U) 4047 /*! BPBLCD7 4048 * 0b0..LCD segment off or LCD backplane inactive for phase B 4049 * 0b1..LCD segment on or LCD backplane active for phase B 4050 */ 4051 #define LCD_WF8B_BPBLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD7_SHIFT)) & LCD_WF8B_BPBLCD7_MASK) 4052 #define LCD_WF8B_BPBLCD8_MASK (0x2U) 4053 #define LCD_WF8B_BPBLCD8_SHIFT (1U) 4054 /*! BPBLCD8 4055 * 0b0..LCD segment off or LCD backplane inactive for phase B 4056 * 0b1..LCD segment on or LCD backplane active for phase B 4057 */ 4058 #define LCD_WF8B_BPBLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD8_SHIFT)) & LCD_WF8B_BPBLCD8_MASK) 4059 #define LCD_WF8B_BPBLCD9_MASK (0x2U) 4060 #define LCD_WF8B_BPBLCD9_SHIFT (1U) 4061 /*! BPBLCD9 4062 * 0b0..LCD segment off or LCD backplane inactive for phase B 4063 * 0b1..LCD segment on or LCD backplane active for phase B 4064 */ 4065 #define LCD_WF8B_BPBLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD9_SHIFT)) & LCD_WF8B_BPBLCD9_MASK) 4066 #define LCD_WF8B_BPBLCD10_MASK (0x2U) 4067 #define LCD_WF8B_BPBLCD10_SHIFT (1U) 4068 /*! BPBLCD10 4069 * 0b0..LCD segment off or LCD backplane inactive for phase B 4070 * 0b1..LCD segment on or LCD backplane active for phase B 4071 */ 4072 #define LCD_WF8B_BPBLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD10_SHIFT)) & LCD_WF8B_BPBLCD10_MASK) 4073 #define LCD_WF8B_BPBLCD11_MASK (0x2U) 4074 #define LCD_WF8B_BPBLCD11_SHIFT (1U) 4075 /*! BPBLCD11 4076 * 0b0..LCD segment off or LCD backplane inactive for phase B 4077 * 0b1..LCD segment on or LCD backplane active for phase B 4078 */ 4079 #define LCD_WF8B_BPBLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD11_SHIFT)) & LCD_WF8B_BPBLCD11_MASK) 4080 #define LCD_WF8B_BPBLCD12_MASK (0x2U) 4081 #define LCD_WF8B_BPBLCD12_SHIFT (1U) 4082 /*! BPBLCD12 4083 * 0b0..LCD segment off or LCD backplane inactive for phase B 4084 * 0b1..LCD segment on or LCD backplane active for phase B 4085 */ 4086 #define LCD_WF8B_BPBLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD12_SHIFT)) & LCD_WF8B_BPBLCD12_MASK) 4087 #define LCD_WF8B_BPBLCD13_MASK (0x2U) 4088 #define LCD_WF8B_BPBLCD13_SHIFT (1U) 4089 /*! BPBLCD13 4090 * 0b0..LCD segment off or LCD backplane inactive for phase B 4091 * 0b1..LCD segment on or LCD backplane active for phase B 4092 */ 4093 #define LCD_WF8B_BPBLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD13_SHIFT)) & LCD_WF8B_BPBLCD13_MASK) 4094 #define LCD_WF8B_BPBLCD14_MASK (0x2U) 4095 #define LCD_WF8B_BPBLCD14_SHIFT (1U) 4096 /*! BPBLCD14 4097 * 0b0..LCD segment off or LCD backplane inactive for phase B 4098 * 0b1..LCD segment on or LCD backplane active for phase B 4099 */ 4100 #define LCD_WF8B_BPBLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD14_SHIFT)) & LCD_WF8B_BPBLCD14_MASK) 4101 #define LCD_WF8B_BPBLCD15_MASK (0x2U) 4102 #define LCD_WF8B_BPBLCD15_SHIFT (1U) 4103 /*! BPBLCD15 4104 * 0b0..LCD segment off or LCD backplane inactive for phase B 4105 * 0b1..LCD segment on or LCD backplane active for phase B 4106 */ 4107 #define LCD_WF8B_BPBLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD15_SHIFT)) & LCD_WF8B_BPBLCD15_MASK) 4108 #define LCD_WF8B_BPBLCD16_MASK (0x2U) 4109 #define LCD_WF8B_BPBLCD16_SHIFT (1U) 4110 /*! BPBLCD16 4111 * 0b0..LCD segment off or LCD backplane inactive for phase B 4112 * 0b1..LCD segment on or LCD backplane active for phase B 4113 */ 4114 #define LCD_WF8B_BPBLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD16_SHIFT)) & LCD_WF8B_BPBLCD16_MASK) 4115 #define LCD_WF8B_BPBLCD17_MASK (0x2U) 4116 #define LCD_WF8B_BPBLCD17_SHIFT (1U) 4117 /*! BPBLCD17 4118 * 0b0..LCD segment off or LCD backplane inactive for phase B 4119 * 0b1..LCD segment on or LCD backplane active for phase B 4120 */ 4121 #define LCD_WF8B_BPBLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD17_SHIFT)) & LCD_WF8B_BPBLCD17_MASK) 4122 #define LCD_WF8B_BPBLCD18_MASK (0x2U) 4123 #define LCD_WF8B_BPBLCD18_SHIFT (1U) 4124 /*! BPBLCD18 4125 * 0b0..LCD segment off or LCD backplane inactive for phase B 4126 * 0b1..LCD segment on or LCD backplane active for phase B 4127 */ 4128 #define LCD_WF8B_BPBLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD18_SHIFT)) & LCD_WF8B_BPBLCD18_MASK) 4129 #define LCD_WF8B_BPBLCD19_MASK (0x2U) 4130 #define LCD_WF8B_BPBLCD19_SHIFT (1U) 4131 /*! BPBLCD19 4132 * 0b0..LCD segment off or LCD backplane inactive for phase B 4133 * 0b1..LCD segment on or LCD backplane active for phase B 4134 */ 4135 #define LCD_WF8B_BPBLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD19_SHIFT)) & LCD_WF8B_BPBLCD19_MASK) 4136 #define LCD_WF8B_BPBLCD20_MASK (0x2U) 4137 #define LCD_WF8B_BPBLCD20_SHIFT (1U) 4138 /*! BPBLCD20 4139 * 0b0..LCD segment off or LCD backplane inactive for phase B 4140 * 0b1..LCD segment on or LCD backplane active for phase B 4141 */ 4142 #define LCD_WF8B_BPBLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD20_SHIFT)) & LCD_WF8B_BPBLCD20_MASK) 4143 #define LCD_WF8B_BPBLCD21_MASK (0x2U) 4144 #define LCD_WF8B_BPBLCD21_SHIFT (1U) 4145 /*! BPBLCD21 4146 * 0b0..LCD segment off or LCD backplane inactive for phase B 4147 * 0b1..LCD segment on or LCD backplane active for phase B 4148 */ 4149 #define LCD_WF8B_BPBLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD21_SHIFT)) & LCD_WF8B_BPBLCD21_MASK) 4150 #define LCD_WF8B_BPBLCD22_MASK (0x2U) 4151 #define LCD_WF8B_BPBLCD22_SHIFT (1U) 4152 /*! BPBLCD22 4153 * 0b0..LCD segment off or LCD backplane inactive for phase B 4154 * 0b1..LCD segment on or LCD backplane active for phase B 4155 */ 4156 #define LCD_WF8B_BPBLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD22_SHIFT)) & LCD_WF8B_BPBLCD22_MASK) 4157 #define LCD_WF8B_BPBLCD23_MASK (0x2U) 4158 #define LCD_WF8B_BPBLCD23_SHIFT (1U) 4159 /*! BPBLCD23 4160 * 0b0..LCD segment off or LCD backplane inactive for phase B 4161 * 0b1..LCD segment on or LCD backplane active for phase B 4162 */ 4163 #define LCD_WF8B_BPBLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD23_SHIFT)) & LCD_WF8B_BPBLCD23_MASK) 4164 #define LCD_WF8B_BPBLCD24_MASK (0x2U) 4165 #define LCD_WF8B_BPBLCD24_SHIFT (1U) 4166 /*! BPBLCD24 4167 * 0b0..LCD segment off or LCD backplane inactive for phase B 4168 * 0b1..LCD segment on or LCD backplane active for phase B 4169 */ 4170 #define LCD_WF8B_BPBLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD24_SHIFT)) & LCD_WF8B_BPBLCD24_MASK) 4171 #define LCD_WF8B_BPBLCD25_MASK (0x2U) 4172 #define LCD_WF8B_BPBLCD25_SHIFT (1U) 4173 /*! BPBLCD25 4174 * 0b0..LCD segment off or LCD backplane inactive for phase B 4175 * 0b1..LCD segment on or LCD backplane active for phase B 4176 */ 4177 #define LCD_WF8B_BPBLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD25_SHIFT)) & LCD_WF8B_BPBLCD25_MASK) 4178 #define LCD_WF8B_BPBLCD26_MASK (0x2U) 4179 #define LCD_WF8B_BPBLCD26_SHIFT (1U) 4180 /*! BPBLCD26 4181 * 0b0..LCD segment off or LCD backplane inactive for phase B 4182 * 0b1..LCD segment on or LCD backplane active for phase B 4183 */ 4184 #define LCD_WF8B_BPBLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD26_SHIFT)) & LCD_WF8B_BPBLCD26_MASK) 4185 #define LCD_WF8B_BPBLCD27_MASK (0x2U) 4186 #define LCD_WF8B_BPBLCD27_SHIFT (1U) 4187 /*! BPBLCD27 4188 * 0b0..LCD segment off or LCD backplane inactive for phase B 4189 * 0b1..LCD segment on or LCD backplane active for phase B 4190 */ 4191 #define LCD_WF8B_BPBLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD27_SHIFT)) & LCD_WF8B_BPBLCD27_MASK) 4192 #define LCD_WF8B_BPBLCD28_MASK (0x2U) 4193 #define LCD_WF8B_BPBLCD28_SHIFT (1U) 4194 /*! BPBLCD28 4195 * 0b0..LCD segment off or LCD backplane inactive for phase B 4196 * 0b1..LCD segment on or LCD backplane active for phase B 4197 */ 4198 #define LCD_WF8B_BPBLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD28_SHIFT)) & LCD_WF8B_BPBLCD28_MASK) 4199 #define LCD_WF8B_BPBLCD29_MASK (0x2U) 4200 #define LCD_WF8B_BPBLCD29_SHIFT (1U) 4201 /*! BPBLCD29 4202 * 0b0..LCD segment off or LCD backplane inactive for phase B 4203 * 0b1..LCD segment on or LCD backplane active for phase B 4204 */ 4205 #define LCD_WF8B_BPBLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD29_SHIFT)) & LCD_WF8B_BPBLCD29_MASK) 4206 #define LCD_WF8B_BPBLCD30_MASK (0x2U) 4207 #define LCD_WF8B_BPBLCD30_SHIFT (1U) 4208 /*! BPBLCD30 4209 * 0b0..LCD segment off or LCD backplane inactive for phase B 4210 * 0b1..LCD segment on or LCD backplane active for phase B 4211 */ 4212 #define LCD_WF8B_BPBLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD30_SHIFT)) & LCD_WF8B_BPBLCD30_MASK) 4213 #define LCD_WF8B_BPBLCD31_MASK (0x2U) 4214 #define LCD_WF8B_BPBLCD31_SHIFT (1U) 4215 /*! BPBLCD31 4216 * 0b0..LCD segment off or LCD backplane inactive for phase B 4217 * 0b1..LCD segment on or LCD backplane active for phase B 4218 */ 4219 #define LCD_WF8B_BPBLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD31_SHIFT)) & LCD_WF8B_BPBLCD31_MASK) 4220 #define LCD_WF8B_BPBLCD32_MASK (0x2U) 4221 #define LCD_WF8B_BPBLCD32_SHIFT (1U) 4222 /*! BPBLCD32 4223 * 0b0..LCD segment off or LCD backplane inactive for phase B 4224 * 0b1..LCD segment on or LCD backplane active for phase B 4225 */ 4226 #define LCD_WF8B_BPBLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD32_SHIFT)) & LCD_WF8B_BPBLCD32_MASK) 4227 #define LCD_WF8B_BPBLCD33_MASK (0x2U) 4228 #define LCD_WF8B_BPBLCD33_SHIFT (1U) 4229 /*! BPBLCD33 4230 * 0b0..LCD segment off or LCD backplane inactive for phase B 4231 * 0b1..LCD segment on or LCD backplane active for phase B 4232 */ 4233 #define LCD_WF8B_BPBLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD33_SHIFT)) & LCD_WF8B_BPBLCD33_MASK) 4234 #define LCD_WF8B_BPBLCD34_MASK (0x2U) 4235 #define LCD_WF8B_BPBLCD34_SHIFT (1U) 4236 /*! BPBLCD34 4237 * 0b0..LCD segment off or LCD backplane inactive for phase B 4238 * 0b1..LCD segment on or LCD backplane active for phase B 4239 */ 4240 #define LCD_WF8B_BPBLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD34_SHIFT)) & LCD_WF8B_BPBLCD34_MASK) 4241 #define LCD_WF8B_BPBLCD35_MASK (0x2U) 4242 #define LCD_WF8B_BPBLCD35_SHIFT (1U) 4243 /*! BPBLCD35 4244 * 0b0..LCD segment off or LCD backplane inactive for phase B 4245 * 0b1..LCD segment on or LCD backplane active for phase B 4246 */ 4247 #define LCD_WF8B_BPBLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD35_SHIFT)) & LCD_WF8B_BPBLCD35_MASK) 4248 #define LCD_WF8B_BPBLCD36_MASK (0x2U) 4249 #define LCD_WF8B_BPBLCD36_SHIFT (1U) 4250 /*! BPBLCD36 4251 * 0b0..LCD segment off or LCD backplane inactive for phase B 4252 * 0b1..LCD segment on or LCD backplane active for phase B 4253 */ 4254 #define LCD_WF8B_BPBLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD36_SHIFT)) & LCD_WF8B_BPBLCD36_MASK) 4255 #define LCD_WF8B_BPBLCD37_MASK (0x2U) 4256 #define LCD_WF8B_BPBLCD37_SHIFT (1U) 4257 /*! BPBLCD37 4258 * 0b0..LCD segment off or LCD backplane inactive for phase B 4259 * 0b1..LCD segment on or LCD backplane active for phase B 4260 */ 4261 #define LCD_WF8B_BPBLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD37_SHIFT)) & LCD_WF8B_BPBLCD37_MASK) 4262 #define LCD_WF8B_BPBLCD38_MASK (0x2U) 4263 #define LCD_WF8B_BPBLCD38_SHIFT (1U) 4264 /*! BPBLCD38 4265 * 0b0..LCD segment off or LCD backplane inactive for phase B 4266 * 0b1..LCD segment on or LCD backplane active for phase B 4267 */ 4268 #define LCD_WF8B_BPBLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD38_SHIFT)) & LCD_WF8B_BPBLCD38_MASK) 4269 #define LCD_WF8B_BPBLCD39_MASK (0x2U) 4270 #define LCD_WF8B_BPBLCD39_SHIFT (1U) 4271 /*! BPBLCD39 4272 * 0b0..LCD segment off or LCD backplane inactive for phase B 4273 * 0b1..LCD segment on or LCD backplane active for phase B 4274 */ 4275 #define LCD_WF8B_BPBLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD39_SHIFT)) & LCD_WF8B_BPBLCD39_MASK) 4276 #define LCD_WF8B_BPBLCD40_MASK (0x2U) 4277 #define LCD_WF8B_BPBLCD40_SHIFT (1U) 4278 /*! BPBLCD40 4279 * 0b0..LCD segment off or LCD backplane inactive for phase B 4280 * 0b1..LCD segment on or LCD backplane active for phase B 4281 */ 4282 #define LCD_WF8B_BPBLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD40_SHIFT)) & LCD_WF8B_BPBLCD40_MASK) 4283 #define LCD_WF8B_BPBLCD41_MASK (0x2U) 4284 #define LCD_WF8B_BPBLCD41_SHIFT (1U) 4285 /*! BPBLCD41 4286 * 0b0..LCD segment off or LCD backplane inactive for phase B 4287 * 0b1..LCD segment on or LCD backplane active for phase B 4288 */ 4289 #define LCD_WF8B_BPBLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD41_SHIFT)) & LCD_WF8B_BPBLCD41_MASK) 4290 #define LCD_WF8B_BPBLCD42_MASK (0x2U) 4291 #define LCD_WF8B_BPBLCD42_SHIFT (1U) 4292 /*! BPBLCD42 4293 * 0b0..LCD segment off or LCD backplane inactive for phase B 4294 * 0b1..LCD segment on or LCD backplane active for phase B 4295 */ 4296 #define LCD_WF8B_BPBLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD42_SHIFT)) & LCD_WF8B_BPBLCD42_MASK) 4297 #define LCD_WF8B_BPBLCD43_MASK (0x2U) 4298 #define LCD_WF8B_BPBLCD43_SHIFT (1U) 4299 /*! BPBLCD43 4300 * 0b0..LCD segment off or LCD backplane inactive for phase B 4301 * 0b1..LCD segment on or LCD backplane active for phase B 4302 */ 4303 #define LCD_WF8B_BPBLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD43_SHIFT)) & LCD_WF8B_BPBLCD43_MASK) 4304 #define LCD_WF8B_BPBLCD44_MASK (0x2U) 4305 #define LCD_WF8B_BPBLCD44_SHIFT (1U) 4306 /*! BPBLCD44 4307 * 0b0..LCD segment off or LCD backplane inactive for phase B 4308 * 0b1..LCD segment on or LCD backplane active for phase B 4309 */ 4310 #define LCD_WF8B_BPBLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD44_SHIFT)) & LCD_WF8B_BPBLCD44_MASK) 4311 #define LCD_WF8B_BPBLCD45_MASK (0x2U) 4312 #define LCD_WF8B_BPBLCD45_SHIFT (1U) 4313 /*! BPBLCD45 4314 * 0b0..LCD segment off or LCD backplane inactive for phase B 4315 * 0b1..LCD segment on or LCD backplane active for phase B 4316 */ 4317 #define LCD_WF8B_BPBLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD45_SHIFT)) & LCD_WF8B_BPBLCD45_MASK) 4318 #define LCD_WF8B_BPBLCD46_MASK (0x2U) 4319 #define LCD_WF8B_BPBLCD46_SHIFT (1U) 4320 /*! BPBLCD46 4321 * 0b0..LCD segment off or LCD backplane inactive for phase B 4322 * 0b1..LCD segment on or LCD backplane active for phase B 4323 */ 4324 #define LCD_WF8B_BPBLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD46_SHIFT)) & LCD_WF8B_BPBLCD46_MASK) 4325 #define LCD_WF8B_BPBLCD47_MASK (0x2U) 4326 #define LCD_WF8B_BPBLCD47_SHIFT (1U) 4327 /*! BPBLCD47 4328 * 0b0..LCD segment off or LCD backplane inactive for phase B 4329 * 0b1..LCD segment on or LCD backplane active for phase B 4330 */ 4331 #define LCD_WF8B_BPBLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD47_SHIFT)) & LCD_WF8B_BPBLCD47_MASK) 4332 #define LCD_WF8B_BPBLCD48_MASK (0x2U) 4333 #define LCD_WF8B_BPBLCD48_SHIFT (1U) 4334 /*! BPBLCD48 4335 * 0b0..LCD segment off or LCD backplane inactive for phase B 4336 * 0b1..LCD segment on or LCD backplane active for phase B 4337 */ 4338 #define LCD_WF8B_BPBLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD48_SHIFT)) & LCD_WF8B_BPBLCD48_MASK) 4339 #define LCD_WF8B_BPBLCD49_MASK (0x2U) 4340 #define LCD_WF8B_BPBLCD49_SHIFT (1U) 4341 /*! BPBLCD49 4342 * 0b0..LCD segment off or LCD backplane inactive for phase B 4343 * 0b1..LCD segment on or LCD backplane active for phase B 4344 */ 4345 #define LCD_WF8B_BPBLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD49_SHIFT)) & LCD_WF8B_BPBLCD49_MASK) 4346 #define LCD_WF8B_BPBLCD50_MASK (0x2U) 4347 #define LCD_WF8B_BPBLCD50_SHIFT (1U) 4348 /*! BPBLCD50 4349 * 0b0..LCD segment off or LCD backplane inactive for phase B 4350 * 0b1..LCD segment on or LCD backplane active for phase B 4351 */ 4352 #define LCD_WF8B_BPBLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD50_SHIFT)) & LCD_WF8B_BPBLCD50_MASK) 4353 #define LCD_WF8B_BPBLCD51_MASK (0x2U) 4354 #define LCD_WF8B_BPBLCD51_SHIFT (1U) 4355 /*! BPBLCD51 4356 * 0b0..LCD segment off or LCD backplane inactive for phase B 4357 * 0b1..LCD segment on or LCD backplane active for phase B 4358 */ 4359 #define LCD_WF8B_BPBLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD51_SHIFT)) & LCD_WF8B_BPBLCD51_MASK) 4360 #define LCD_WF8B_BPBLCD52_MASK (0x2U) 4361 #define LCD_WF8B_BPBLCD52_SHIFT (1U) 4362 /*! BPBLCD52 4363 * 0b0..LCD segment off or LCD backplane inactive for phase B 4364 * 0b1..LCD segment on or LCD backplane active for phase B 4365 */ 4366 #define LCD_WF8B_BPBLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD52_SHIFT)) & LCD_WF8B_BPBLCD52_MASK) 4367 #define LCD_WF8B_BPBLCD53_MASK (0x2U) 4368 #define LCD_WF8B_BPBLCD53_SHIFT (1U) 4369 /*! BPBLCD53 4370 * 0b0..LCD segment off or LCD backplane inactive for phase B 4371 * 0b1..LCD segment on or LCD backplane active for phase B 4372 */ 4373 #define LCD_WF8B_BPBLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD53_SHIFT)) & LCD_WF8B_BPBLCD53_MASK) 4374 #define LCD_WF8B_BPBLCD54_MASK (0x2U) 4375 #define LCD_WF8B_BPBLCD54_SHIFT (1U) 4376 /*! BPBLCD54 4377 * 0b0..LCD segment off or LCD backplane inactive for phase B 4378 * 0b1..LCD segment on or LCD backplane active for phase B 4379 */ 4380 #define LCD_WF8B_BPBLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD54_SHIFT)) & LCD_WF8B_BPBLCD54_MASK) 4381 #define LCD_WF8B_BPBLCD55_MASK (0x2U) 4382 #define LCD_WF8B_BPBLCD55_SHIFT (1U) 4383 /*! BPBLCD55 4384 * 0b0..LCD segment off or LCD backplane inactive for phase B 4385 * 0b1..LCD segment on or LCD backplane active for phase B 4386 */ 4387 #define LCD_WF8B_BPBLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD55_SHIFT)) & LCD_WF8B_BPBLCD55_MASK) 4388 #define LCD_WF8B_BPBLCD56_MASK (0x2U) 4389 #define LCD_WF8B_BPBLCD56_SHIFT (1U) 4390 /*! BPBLCD56 4391 * 0b0..LCD segment off or LCD backplane inactive for phase B 4392 * 0b1..LCD segment on or LCD backplane active for phase B 4393 */ 4394 #define LCD_WF8B_BPBLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD56_SHIFT)) & LCD_WF8B_BPBLCD56_MASK) 4395 #define LCD_WF8B_BPBLCD57_MASK (0x2U) 4396 #define LCD_WF8B_BPBLCD57_SHIFT (1U) 4397 /*! BPBLCD57 4398 * 0b0..LCD segment off or LCD backplane inactive for phase B 4399 * 0b1..LCD segment on or LCD backplane active for phase B 4400 */ 4401 #define LCD_WF8B_BPBLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD57_SHIFT)) & LCD_WF8B_BPBLCD57_MASK) 4402 #define LCD_WF8B_BPBLCD58_MASK (0x2U) 4403 #define LCD_WF8B_BPBLCD58_SHIFT (1U) 4404 /*! BPBLCD58 4405 * 0b0..LCD segment off or LCD backplane inactive for phase B 4406 * 0b1..LCD segment on or LCD backplane active for phase B 4407 */ 4408 #define LCD_WF8B_BPBLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD58_SHIFT)) & LCD_WF8B_BPBLCD58_MASK) 4409 #define LCD_WF8B_BPBLCD59_MASK (0x2U) 4410 #define LCD_WF8B_BPBLCD59_SHIFT (1U) 4411 /*! BPBLCD59 4412 * 0b0..LCD segment off or LCD backplane inactive for phase B 4413 * 0b1..LCD segment on or LCD backplane active for phase B 4414 */ 4415 #define LCD_WF8B_BPBLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD59_SHIFT)) & LCD_WF8B_BPBLCD59_MASK) 4416 #define LCD_WF8B_BPBLCD60_MASK (0x2U) 4417 #define LCD_WF8B_BPBLCD60_SHIFT (1U) 4418 /*! BPBLCD60 4419 * 0b0..LCD segment off or LCD backplane inactive for phase B 4420 * 0b1..LCD segment on or LCD backplane active for phase B 4421 */ 4422 #define LCD_WF8B_BPBLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD60_SHIFT)) & LCD_WF8B_BPBLCD60_MASK) 4423 #define LCD_WF8B_BPBLCD61_MASK (0x2U) 4424 #define LCD_WF8B_BPBLCD61_SHIFT (1U) 4425 /*! BPBLCD61 4426 * 0b0..LCD segment off or LCD backplane inactive for phase B 4427 * 0b1..LCD segment on or LCD backplane active for phase B 4428 */ 4429 #define LCD_WF8B_BPBLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD61_SHIFT)) & LCD_WF8B_BPBLCD61_MASK) 4430 #define LCD_WF8B_BPBLCD62_MASK (0x2U) 4431 #define LCD_WF8B_BPBLCD62_SHIFT (1U) 4432 /*! BPBLCD62 4433 * 0b0..LCD segment off or LCD backplane inactive for phase B 4434 * 0b1..LCD segment on or LCD backplane active for phase B 4435 */ 4436 #define LCD_WF8B_BPBLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD62_SHIFT)) & LCD_WF8B_BPBLCD62_MASK) 4437 #define LCD_WF8B_BPBLCD63_MASK (0x2U) 4438 #define LCD_WF8B_BPBLCD63_SHIFT (1U) 4439 /*! BPBLCD63 4440 * 0b0..LCD segment off or LCD backplane inactive for phase B 4441 * 0b1..LCD segment on or LCD backplane active for phase B 4442 */ 4443 #define LCD_WF8B_BPBLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD63_SHIFT)) & LCD_WF8B_BPBLCD63_MASK) 4444 #define LCD_WF8B_BPCLCD0_MASK (0x4U) 4445 #define LCD_WF8B_BPCLCD0_SHIFT (2U) 4446 /*! BPCLCD0 4447 * 0b0..LCD segment off or LCD backplane inactive for phase C 4448 * 0b1..LCD segment on or LCD backplane active for phase C 4449 */ 4450 #define LCD_WF8B_BPCLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD0_SHIFT)) & LCD_WF8B_BPCLCD0_MASK) 4451 #define LCD_WF8B_BPCLCD1_MASK (0x4U) 4452 #define LCD_WF8B_BPCLCD1_SHIFT (2U) 4453 /*! BPCLCD1 4454 * 0b0..LCD segment off or LCD backplane inactive for phase C 4455 * 0b1..LCD segment on or LCD backplane active for phase C 4456 */ 4457 #define LCD_WF8B_BPCLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD1_SHIFT)) & LCD_WF8B_BPCLCD1_MASK) 4458 #define LCD_WF8B_BPCLCD2_MASK (0x4U) 4459 #define LCD_WF8B_BPCLCD2_SHIFT (2U) 4460 /*! BPCLCD2 4461 * 0b0..LCD segment off or LCD backplane inactive for phase C 4462 * 0b1..LCD segment on or LCD backplane active for phase C 4463 */ 4464 #define LCD_WF8B_BPCLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD2_SHIFT)) & LCD_WF8B_BPCLCD2_MASK) 4465 #define LCD_WF8B_BPCLCD3_MASK (0x4U) 4466 #define LCD_WF8B_BPCLCD3_SHIFT (2U) 4467 /*! BPCLCD3 4468 * 0b0..LCD segment off or LCD backplane inactive for phase C 4469 * 0b1..LCD segment on or LCD backplane active for phase C 4470 */ 4471 #define LCD_WF8B_BPCLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD3_SHIFT)) & LCD_WF8B_BPCLCD3_MASK) 4472 #define LCD_WF8B_BPCLCD4_MASK (0x4U) 4473 #define LCD_WF8B_BPCLCD4_SHIFT (2U) 4474 /*! BPCLCD4 4475 * 0b0..LCD segment off or LCD backplane inactive for phase C 4476 * 0b1..LCD segment on or LCD backplane active for phase C 4477 */ 4478 #define LCD_WF8B_BPCLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD4_SHIFT)) & LCD_WF8B_BPCLCD4_MASK) 4479 #define LCD_WF8B_BPCLCD5_MASK (0x4U) 4480 #define LCD_WF8B_BPCLCD5_SHIFT (2U) 4481 /*! BPCLCD5 4482 * 0b0..LCD segment off or LCD backplane inactive for phase C 4483 * 0b1..LCD segment on or LCD backplane active for phase C 4484 */ 4485 #define LCD_WF8B_BPCLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD5_SHIFT)) & LCD_WF8B_BPCLCD5_MASK) 4486 #define LCD_WF8B_BPCLCD6_MASK (0x4U) 4487 #define LCD_WF8B_BPCLCD6_SHIFT (2U) 4488 /*! BPCLCD6 4489 * 0b0..LCD segment off or LCD backplane inactive for phase C 4490 * 0b1..LCD segment on or LCD backplane active for phase C 4491 */ 4492 #define LCD_WF8B_BPCLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD6_SHIFT)) & LCD_WF8B_BPCLCD6_MASK) 4493 #define LCD_WF8B_BPCLCD7_MASK (0x4U) 4494 #define LCD_WF8B_BPCLCD7_SHIFT (2U) 4495 /*! BPCLCD7 4496 * 0b0..LCD segment off or LCD backplane inactive for phase C 4497 * 0b1..LCD segment on or LCD backplane active for phase C 4498 */ 4499 #define LCD_WF8B_BPCLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD7_SHIFT)) & LCD_WF8B_BPCLCD7_MASK) 4500 #define LCD_WF8B_BPCLCD8_MASK (0x4U) 4501 #define LCD_WF8B_BPCLCD8_SHIFT (2U) 4502 /*! BPCLCD8 4503 * 0b0..LCD segment off or LCD backplane inactive for phase C 4504 * 0b1..LCD segment on or LCD backplane active for phase C 4505 */ 4506 #define LCD_WF8B_BPCLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD8_SHIFT)) & LCD_WF8B_BPCLCD8_MASK) 4507 #define LCD_WF8B_BPCLCD9_MASK (0x4U) 4508 #define LCD_WF8B_BPCLCD9_SHIFT (2U) 4509 /*! BPCLCD9 4510 * 0b0..LCD segment off or LCD backplane inactive for phase C 4511 * 0b1..LCD segment on or LCD backplane active for phase C 4512 */ 4513 #define LCD_WF8B_BPCLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD9_SHIFT)) & LCD_WF8B_BPCLCD9_MASK) 4514 #define LCD_WF8B_BPCLCD10_MASK (0x4U) 4515 #define LCD_WF8B_BPCLCD10_SHIFT (2U) 4516 /*! BPCLCD10 4517 * 0b0..LCD segment off or LCD backplane inactive for phase C 4518 * 0b1..LCD segment on or LCD backplane active for phase C 4519 */ 4520 #define LCD_WF8B_BPCLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD10_SHIFT)) & LCD_WF8B_BPCLCD10_MASK) 4521 #define LCD_WF8B_BPCLCD11_MASK (0x4U) 4522 #define LCD_WF8B_BPCLCD11_SHIFT (2U) 4523 /*! BPCLCD11 4524 * 0b0..LCD segment off or LCD backplane inactive for phase C 4525 * 0b1..LCD segment on or LCD backplane active for phase C 4526 */ 4527 #define LCD_WF8B_BPCLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD11_SHIFT)) & LCD_WF8B_BPCLCD11_MASK) 4528 #define LCD_WF8B_BPCLCD12_MASK (0x4U) 4529 #define LCD_WF8B_BPCLCD12_SHIFT (2U) 4530 /*! BPCLCD12 4531 * 0b0..LCD segment off or LCD backplane inactive for phase C 4532 * 0b1..LCD segment on or LCD backplane active for phase C 4533 */ 4534 #define LCD_WF8B_BPCLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD12_SHIFT)) & LCD_WF8B_BPCLCD12_MASK) 4535 #define LCD_WF8B_BPCLCD13_MASK (0x4U) 4536 #define LCD_WF8B_BPCLCD13_SHIFT (2U) 4537 /*! BPCLCD13 4538 * 0b0..LCD segment off or LCD backplane inactive for phase C 4539 * 0b1..LCD segment on or LCD backplane active for phase C 4540 */ 4541 #define LCD_WF8B_BPCLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD13_SHIFT)) & LCD_WF8B_BPCLCD13_MASK) 4542 #define LCD_WF8B_BPCLCD14_MASK (0x4U) 4543 #define LCD_WF8B_BPCLCD14_SHIFT (2U) 4544 /*! BPCLCD14 4545 * 0b0..LCD segment off or LCD backplane inactive for phase C 4546 * 0b1..LCD segment on or LCD backplane active for phase C 4547 */ 4548 #define LCD_WF8B_BPCLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD14_SHIFT)) & LCD_WF8B_BPCLCD14_MASK) 4549 #define LCD_WF8B_BPCLCD15_MASK (0x4U) 4550 #define LCD_WF8B_BPCLCD15_SHIFT (2U) 4551 /*! BPCLCD15 4552 * 0b0..LCD segment off or LCD backplane inactive for phase C 4553 * 0b1..LCD segment on or LCD backplane active for phase C 4554 */ 4555 #define LCD_WF8B_BPCLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD15_SHIFT)) & LCD_WF8B_BPCLCD15_MASK) 4556 #define LCD_WF8B_BPCLCD16_MASK (0x4U) 4557 #define LCD_WF8B_BPCLCD16_SHIFT (2U) 4558 /*! BPCLCD16 4559 * 0b0..LCD segment off or LCD backplane inactive for phase C 4560 * 0b1..LCD segment on or LCD backplane active for phase C 4561 */ 4562 #define LCD_WF8B_BPCLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD16_SHIFT)) & LCD_WF8B_BPCLCD16_MASK) 4563 #define LCD_WF8B_BPCLCD17_MASK (0x4U) 4564 #define LCD_WF8B_BPCLCD17_SHIFT (2U) 4565 /*! BPCLCD17 4566 * 0b0..LCD segment off or LCD backplane inactive for phase C 4567 * 0b1..LCD segment on or LCD backplane active for phase C 4568 */ 4569 #define LCD_WF8B_BPCLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD17_SHIFT)) & LCD_WF8B_BPCLCD17_MASK) 4570 #define LCD_WF8B_BPCLCD18_MASK (0x4U) 4571 #define LCD_WF8B_BPCLCD18_SHIFT (2U) 4572 /*! BPCLCD18 4573 * 0b0..LCD segment off or LCD backplane inactive for phase C 4574 * 0b1..LCD segment on or LCD backplane active for phase C 4575 */ 4576 #define LCD_WF8B_BPCLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD18_SHIFT)) & LCD_WF8B_BPCLCD18_MASK) 4577 #define LCD_WF8B_BPCLCD19_MASK (0x4U) 4578 #define LCD_WF8B_BPCLCD19_SHIFT (2U) 4579 /*! BPCLCD19 4580 * 0b0..LCD segment off or LCD backplane inactive for phase C 4581 * 0b1..LCD segment on or LCD backplane active for phase C 4582 */ 4583 #define LCD_WF8B_BPCLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD19_SHIFT)) & LCD_WF8B_BPCLCD19_MASK) 4584 #define LCD_WF8B_BPCLCD20_MASK (0x4U) 4585 #define LCD_WF8B_BPCLCD20_SHIFT (2U) 4586 /*! BPCLCD20 4587 * 0b0..LCD segment off or LCD backplane inactive for phase C 4588 * 0b1..LCD segment on or LCD backplane active for phase C 4589 */ 4590 #define LCD_WF8B_BPCLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD20_SHIFT)) & LCD_WF8B_BPCLCD20_MASK) 4591 #define LCD_WF8B_BPCLCD21_MASK (0x4U) 4592 #define LCD_WF8B_BPCLCD21_SHIFT (2U) 4593 /*! BPCLCD21 4594 * 0b0..LCD segment off or LCD backplane inactive for phase C 4595 * 0b1..LCD segment on or LCD backplane active for phase C 4596 */ 4597 #define LCD_WF8B_BPCLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD21_SHIFT)) & LCD_WF8B_BPCLCD21_MASK) 4598 #define LCD_WF8B_BPCLCD22_MASK (0x4U) 4599 #define LCD_WF8B_BPCLCD22_SHIFT (2U) 4600 /*! BPCLCD22 4601 * 0b0..LCD segment off or LCD backplane inactive for phase C 4602 * 0b1..LCD segment on or LCD backplane active for phase C 4603 */ 4604 #define LCD_WF8B_BPCLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD22_SHIFT)) & LCD_WF8B_BPCLCD22_MASK) 4605 #define LCD_WF8B_BPCLCD23_MASK (0x4U) 4606 #define LCD_WF8B_BPCLCD23_SHIFT (2U) 4607 /*! BPCLCD23 4608 * 0b0..LCD segment off or LCD backplane inactive for phase C 4609 * 0b1..LCD segment on or LCD backplane active for phase C 4610 */ 4611 #define LCD_WF8B_BPCLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD23_SHIFT)) & LCD_WF8B_BPCLCD23_MASK) 4612 #define LCD_WF8B_BPCLCD24_MASK (0x4U) 4613 #define LCD_WF8B_BPCLCD24_SHIFT (2U) 4614 /*! BPCLCD24 4615 * 0b0..LCD segment off or LCD backplane inactive for phase C 4616 * 0b1..LCD segment on or LCD backplane active for phase C 4617 */ 4618 #define LCD_WF8B_BPCLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD24_SHIFT)) & LCD_WF8B_BPCLCD24_MASK) 4619 #define LCD_WF8B_BPCLCD25_MASK (0x4U) 4620 #define LCD_WF8B_BPCLCD25_SHIFT (2U) 4621 /*! BPCLCD25 4622 * 0b0..LCD segment off or LCD backplane inactive for phase C 4623 * 0b1..LCD segment on or LCD backplane active for phase C 4624 */ 4625 #define LCD_WF8B_BPCLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD25_SHIFT)) & LCD_WF8B_BPCLCD25_MASK) 4626 #define LCD_WF8B_BPCLCD26_MASK (0x4U) 4627 #define LCD_WF8B_BPCLCD26_SHIFT (2U) 4628 /*! BPCLCD26 4629 * 0b0..LCD segment off or LCD backplane inactive for phase C 4630 * 0b1..LCD segment on or LCD backplane active for phase C 4631 */ 4632 #define LCD_WF8B_BPCLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD26_SHIFT)) & LCD_WF8B_BPCLCD26_MASK) 4633 #define LCD_WF8B_BPCLCD27_MASK (0x4U) 4634 #define LCD_WF8B_BPCLCD27_SHIFT (2U) 4635 /*! BPCLCD27 4636 * 0b0..LCD segment off or LCD backplane inactive for phase C 4637 * 0b1..LCD segment on or LCD backplane active for phase C 4638 */ 4639 #define LCD_WF8B_BPCLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD27_SHIFT)) & LCD_WF8B_BPCLCD27_MASK) 4640 #define LCD_WF8B_BPCLCD28_MASK (0x4U) 4641 #define LCD_WF8B_BPCLCD28_SHIFT (2U) 4642 /*! BPCLCD28 4643 * 0b0..LCD segment off or LCD backplane inactive for phase C 4644 * 0b1..LCD segment on or LCD backplane active for phase C 4645 */ 4646 #define LCD_WF8B_BPCLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD28_SHIFT)) & LCD_WF8B_BPCLCD28_MASK) 4647 #define LCD_WF8B_BPCLCD29_MASK (0x4U) 4648 #define LCD_WF8B_BPCLCD29_SHIFT (2U) 4649 /*! BPCLCD29 4650 * 0b0..LCD segment off or LCD backplane inactive for phase C 4651 * 0b1..LCD segment on or LCD backplane active for phase C 4652 */ 4653 #define LCD_WF8B_BPCLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD29_SHIFT)) & LCD_WF8B_BPCLCD29_MASK) 4654 #define LCD_WF8B_BPCLCD30_MASK (0x4U) 4655 #define LCD_WF8B_BPCLCD30_SHIFT (2U) 4656 /*! BPCLCD30 4657 * 0b0..LCD segment off or LCD backplane inactive for phase C 4658 * 0b1..LCD segment on or LCD backplane active for phase C 4659 */ 4660 #define LCD_WF8B_BPCLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD30_SHIFT)) & LCD_WF8B_BPCLCD30_MASK) 4661 #define LCD_WF8B_BPCLCD31_MASK (0x4U) 4662 #define LCD_WF8B_BPCLCD31_SHIFT (2U) 4663 /*! BPCLCD31 4664 * 0b0..LCD segment off or LCD backplane inactive for phase C 4665 * 0b1..LCD segment on or LCD backplane active for phase C 4666 */ 4667 #define LCD_WF8B_BPCLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD31_SHIFT)) & LCD_WF8B_BPCLCD31_MASK) 4668 #define LCD_WF8B_BPCLCD32_MASK (0x4U) 4669 #define LCD_WF8B_BPCLCD32_SHIFT (2U) 4670 /*! BPCLCD32 4671 * 0b0..LCD segment off or LCD backplane inactive for phase C 4672 * 0b1..LCD segment on or LCD backplane active for phase C 4673 */ 4674 #define LCD_WF8B_BPCLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD32_SHIFT)) & LCD_WF8B_BPCLCD32_MASK) 4675 #define LCD_WF8B_BPCLCD33_MASK (0x4U) 4676 #define LCD_WF8B_BPCLCD33_SHIFT (2U) 4677 /*! BPCLCD33 4678 * 0b0..LCD segment off or LCD backplane inactive for phase C 4679 * 0b1..LCD segment on or LCD backplane active for phase C 4680 */ 4681 #define LCD_WF8B_BPCLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD33_SHIFT)) & LCD_WF8B_BPCLCD33_MASK) 4682 #define LCD_WF8B_BPCLCD34_MASK (0x4U) 4683 #define LCD_WF8B_BPCLCD34_SHIFT (2U) 4684 /*! BPCLCD34 4685 * 0b0..LCD segment off or LCD backplane inactive for phase C 4686 * 0b1..LCD segment on or LCD backplane active for phase C 4687 */ 4688 #define LCD_WF8B_BPCLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD34_SHIFT)) & LCD_WF8B_BPCLCD34_MASK) 4689 #define LCD_WF8B_BPCLCD35_MASK (0x4U) 4690 #define LCD_WF8B_BPCLCD35_SHIFT (2U) 4691 /*! BPCLCD35 4692 * 0b0..LCD segment off or LCD backplane inactive for phase C 4693 * 0b1..LCD segment on or LCD backplane active for phase C 4694 */ 4695 #define LCD_WF8B_BPCLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD35_SHIFT)) & LCD_WF8B_BPCLCD35_MASK) 4696 #define LCD_WF8B_BPCLCD36_MASK (0x4U) 4697 #define LCD_WF8B_BPCLCD36_SHIFT (2U) 4698 /*! BPCLCD36 4699 * 0b0..LCD segment off or LCD backplane inactive for phase C 4700 * 0b1..LCD segment on or LCD backplane active for phase C 4701 */ 4702 #define LCD_WF8B_BPCLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD36_SHIFT)) & LCD_WF8B_BPCLCD36_MASK) 4703 #define LCD_WF8B_BPCLCD37_MASK (0x4U) 4704 #define LCD_WF8B_BPCLCD37_SHIFT (2U) 4705 /*! BPCLCD37 4706 * 0b0..LCD segment off or LCD backplane inactive for phase C 4707 * 0b1..LCD segment on or LCD backplane active for phase C 4708 */ 4709 #define LCD_WF8B_BPCLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD37_SHIFT)) & LCD_WF8B_BPCLCD37_MASK) 4710 #define LCD_WF8B_BPCLCD38_MASK (0x4U) 4711 #define LCD_WF8B_BPCLCD38_SHIFT (2U) 4712 /*! BPCLCD38 4713 * 0b0..LCD segment off or LCD backplane inactive for phase C 4714 * 0b1..LCD segment on or LCD backplane active for phase C 4715 */ 4716 #define LCD_WF8B_BPCLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD38_SHIFT)) & LCD_WF8B_BPCLCD38_MASK) 4717 #define LCD_WF8B_BPCLCD39_MASK (0x4U) 4718 #define LCD_WF8B_BPCLCD39_SHIFT (2U) 4719 /*! BPCLCD39 4720 * 0b0..LCD segment off or LCD backplane inactive for phase C 4721 * 0b1..LCD segment on or LCD backplane active for phase C 4722 */ 4723 #define LCD_WF8B_BPCLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD39_SHIFT)) & LCD_WF8B_BPCLCD39_MASK) 4724 #define LCD_WF8B_BPCLCD40_MASK (0x4U) 4725 #define LCD_WF8B_BPCLCD40_SHIFT (2U) 4726 /*! BPCLCD40 4727 * 0b0..LCD segment off or LCD backplane inactive for phase C 4728 * 0b1..LCD segment on or LCD backplane active for phase C 4729 */ 4730 #define LCD_WF8B_BPCLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD40_SHIFT)) & LCD_WF8B_BPCLCD40_MASK) 4731 #define LCD_WF8B_BPCLCD41_MASK (0x4U) 4732 #define LCD_WF8B_BPCLCD41_SHIFT (2U) 4733 /*! BPCLCD41 4734 * 0b0..LCD segment off or LCD backplane inactive for phase C 4735 * 0b1..LCD segment on or LCD backplane active for phase C 4736 */ 4737 #define LCD_WF8B_BPCLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD41_SHIFT)) & LCD_WF8B_BPCLCD41_MASK) 4738 #define LCD_WF8B_BPCLCD42_MASK (0x4U) 4739 #define LCD_WF8B_BPCLCD42_SHIFT (2U) 4740 /*! BPCLCD42 4741 * 0b0..LCD segment off or LCD backplane inactive for phase C 4742 * 0b1..LCD segment on or LCD backplane active for phase C 4743 */ 4744 #define LCD_WF8B_BPCLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD42_SHIFT)) & LCD_WF8B_BPCLCD42_MASK) 4745 #define LCD_WF8B_BPCLCD43_MASK (0x4U) 4746 #define LCD_WF8B_BPCLCD43_SHIFT (2U) 4747 /*! BPCLCD43 4748 * 0b0..LCD segment off or LCD backplane inactive for phase C 4749 * 0b1..LCD segment on or LCD backplane active for phase C 4750 */ 4751 #define LCD_WF8B_BPCLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD43_SHIFT)) & LCD_WF8B_BPCLCD43_MASK) 4752 #define LCD_WF8B_BPCLCD44_MASK (0x4U) 4753 #define LCD_WF8B_BPCLCD44_SHIFT (2U) 4754 /*! BPCLCD44 4755 * 0b0..LCD segment off or LCD backplane inactive for phase C 4756 * 0b1..LCD segment on or LCD backplane active for phase C 4757 */ 4758 #define LCD_WF8B_BPCLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD44_SHIFT)) & LCD_WF8B_BPCLCD44_MASK) 4759 #define LCD_WF8B_BPCLCD45_MASK (0x4U) 4760 #define LCD_WF8B_BPCLCD45_SHIFT (2U) 4761 /*! BPCLCD45 4762 * 0b0..LCD segment off or LCD backplane inactive for phase C 4763 * 0b1..LCD segment on or LCD backplane active for phase C 4764 */ 4765 #define LCD_WF8B_BPCLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD45_SHIFT)) & LCD_WF8B_BPCLCD45_MASK) 4766 #define LCD_WF8B_BPCLCD46_MASK (0x4U) 4767 #define LCD_WF8B_BPCLCD46_SHIFT (2U) 4768 /*! BPCLCD46 4769 * 0b0..LCD segment off or LCD backplane inactive for phase C 4770 * 0b1..LCD segment on or LCD backplane active for phase C 4771 */ 4772 #define LCD_WF8B_BPCLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD46_SHIFT)) & LCD_WF8B_BPCLCD46_MASK) 4773 #define LCD_WF8B_BPCLCD47_MASK (0x4U) 4774 #define LCD_WF8B_BPCLCD47_SHIFT (2U) 4775 /*! BPCLCD47 4776 * 0b0..LCD segment off or LCD backplane inactive for phase C 4777 * 0b1..LCD segment on or LCD backplane active for phase C 4778 */ 4779 #define LCD_WF8B_BPCLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD47_SHIFT)) & LCD_WF8B_BPCLCD47_MASK) 4780 #define LCD_WF8B_BPCLCD48_MASK (0x4U) 4781 #define LCD_WF8B_BPCLCD48_SHIFT (2U) 4782 /*! BPCLCD48 4783 * 0b0..LCD segment off or LCD backplane inactive for phase C 4784 * 0b1..LCD segment on or LCD backplane active for phase C 4785 */ 4786 #define LCD_WF8B_BPCLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD48_SHIFT)) & LCD_WF8B_BPCLCD48_MASK) 4787 #define LCD_WF8B_BPCLCD49_MASK (0x4U) 4788 #define LCD_WF8B_BPCLCD49_SHIFT (2U) 4789 /*! BPCLCD49 4790 * 0b0..LCD segment off or LCD backplane inactive for phase C 4791 * 0b1..LCD segment on or LCD backplane active for phase C 4792 */ 4793 #define LCD_WF8B_BPCLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD49_SHIFT)) & LCD_WF8B_BPCLCD49_MASK) 4794 #define LCD_WF8B_BPCLCD50_MASK (0x4U) 4795 #define LCD_WF8B_BPCLCD50_SHIFT (2U) 4796 /*! BPCLCD50 4797 * 0b0..LCD segment off or LCD backplane inactive for phase C 4798 * 0b1..LCD segment on or LCD backplane active for phase C 4799 */ 4800 #define LCD_WF8B_BPCLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD50_SHIFT)) & LCD_WF8B_BPCLCD50_MASK) 4801 #define LCD_WF8B_BPCLCD51_MASK (0x4U) 4802 #define LCD_WF8B_BPCLCD51_SHIFT (2U) 4803 /*! BPCLCD51 4804 * 0b0..LCD segment off or LCD backplane inactive for phase C 4805 * 0b1..LCD segment on or LCD backplane active for phase C 4806 */ 4807 #define LCD_WF8B_BPCLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD51_SHIFT)) & LCD_WF8B_BPCLCD51_MASK) 4808 #define LCD_WF8B_BPCLCD52_MASK (0x4U) 4809 #define LCD_WF8B_BPCLCD52_SHIFT (2U) 4810 /*! BPCLCD52 4811 * 0b0..LCD segment off or LCD backplane inactive for phase C 4812 * 0b1..LCD segment on or LCD backplane active for phase C 4813 */ 4814 #define LCD_WF8B_BPCLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD52_SHIFT)) & LCD_WF8B_BPCLCD52_MASK) 4815 #define LCD_WF8B_BPCLCD53_MASK (0x4U) 4816 #define LCD_WF8B_BPCLCD53_SHIFT (2U) 4817 /*! BPCLCD53 4818 * 0b0..LCD segment off or LCD backplane inactive for phase C 4819 * 0b1..LCD segment on or LCD backplane active for phase C 4820 */ 4821 #define LCD_WF8B_BPCLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD53_SHIFT)) & LCD_WF8B_BPCLCD53_MASK) 4822 #define LCD_WF8B_BPCLCD54_MASK (0x4U) 4823 #define LCD_WF8B_BPCLCD54_SHIFT (2U) 4824 /*! BPCLCD54 4825 * 0b0..LCD segment off or LCD backplane inactive for phase C 4826 * 0b1..LCD segment on or LCD backplane active for phase C 4827 */ 4828 #define LCD_WF8B_BPCLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD54_SHIFT)) & LCD_WF8B_BPCLCD54_MASK) 4829 #define LCD_WF8B_BPCLCD55_MASK (0x4U) 4830 #define LCD_WF8B_BPCLCD55_SHIFT (2U) 4831 /*! BPCLCD55 4832 * 0b0..LCD segment off or LCD backplane inactive for phase C 4833 * 0b1..LCD segment on or LCD backplane active for phase C 4834 */ 4835 #define LCD_WF8B_BPCLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD55_SHIFT)) & LCD_WF8B_BPCLCD55_MASK) 4836 #define LCD_WF8B_BPCLCD56_MASK (0x4U) 4837 #define LCD_WF8B_BPCLCD56_SHIFT (2U) 4838 /*! BPCLCD56 4839 * 0b0..LCD segment off or LCD backplane inactive for phase C 4840 * 0b1..LCD segment on or LCD backplane active for phase C 4841 */ 4842 #define LCD_WF8B_BPCLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD56_SHIFT)) & LCD_WF8B_BPCLCD56_MASK) 4843 #define LCD_WF8B_BPCLCD57_MASK (0x4U) 4844 #define LCD_WF8B_BPCLCD57_SHIFT (2U) 4845 /*! BPCLCD57 4846 * 0b0..LCD segment off or LCD backplane inactive for phase C 4847 * 0b1..LCD segment on or LCD backplane active for phase C 4848 */ 4849 #define LCD_WF8B_BPCLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD57_SHIFT)) & LCD_WF8B_BPCLCD57_MASK) 4850 #define LCD_WF8B_BPCLCD58_MASK (0x4U) 4851 #define LCD_WF8B_BPCLCD58_SHIFT (2U) 4852 /*! BPCLCD58 4853 * 0b0..LCD segment off or LCD backplane inactive for phase C 4854 * 0b1..LCD segment on or LCD backplane active for phase C 4855 */ 4856 #define LCD_WF8B_BPCLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD58_SHIFT)) & LCD_WF8B_BPCLCD58_MASK) 4857 #define LCD_WF8B_BPCLCD59_MASK (0x4U) 4858 #define LCD_WF8B_BPCLCD59_SHIFT (2U) 4859 /*! BPCLCD59 4860 * 0b0..LCD segment off or LCD backplane inactive for phase C 4861 * 0b1..LCD segment on or LCD backplane active for phase C 4862 */ 4863 #define LCD_WF8B_BPCLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD59_SHIFT)) & LCD_WF8B_BPCLCD59_MASK) 4864 #define LCD_WF8B_BPCLCD60_MASK (0x4U) 4865 #define LCD_WF8B_BPCLCD60_SHIFT (2U) 4866 /*! BPCLCD60 4867 * 0b0..LCD segment off or LCD backplane inactive for phase C 4868 * 0b1..LCD segment on or LCD backplane active for phase C 4869 */ 4870 #define LCD_WF8B_BPCLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD60_SHIFT)) & LCD_WF8B_BPCLCD60_MASK) 4871 #define LCD_WF8B_BPCLCD61_MASK (0x4U) 4872 #define LCD_WF8B_BPCLCD61_SHIFT (2U) 4873 /*! BPCLCD61 4874 * 0b0..LCD segment off or LCD backplane inactive for phase C 4875 * 0b1..LCD segment on or LCD backplane active for phase C 4876 */ 4877 #define LCD_WF8B_BPCLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD61_SHIFT)) & LCD_WF8B_BPCLCD61_MASK) 4878 #define LCD_WF8B_BPCLCD62_MASK (0x4U) 4879 #define LCD_WF8B_BPCLCD62_SHIFT (2U) 4880 /*! BPCLCD62 4881 * 0b0..LCD segment off or LCD backplane inactive for phase C 4882 * 0b1..LCD segment on or LCD backplane active for phase C 4883 */ 4884 #define LCD_WF8B_BPCLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD62_SHIFT)) & LCD_WF8B_BPCLCD62_MASK) 4885 #define LCD_WF8B_BPCLCD63_MASK (0x4U) 4886 #define LCD_WF8B_BPCLCD63_SHIFT (2U) 4887 /*! BPCLCD63 4888 * 0b0..LCD segment off or LCD backplane inactive for phase C 4889 * 0b1..LCD segment on or LCD backplane active for phase C 4890 */ 4891 #define LCD_WF8B_BPCLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD63_SHIFT)) & LCD_WF8B_BPCLCD63_MASK) 4892 #define LCD_WF8B_BPDLCD0_MASK (0x8U) 4893 #define LCD_WF8B_BPDLCD0_SHIFT (3U) 4894 /*! BPDLCD0 4895 * 0b0..LCD segment off or LCD backplane inactive for phase D 4896 * 0b1..LCD segment on or LCD backplane active for phase D 4897 */ 4898 #define LCD_WF8B_BPDLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD0_SHIFT)) & LCD_WF8B_BPDLCD0_MASK) 4899 #define LCD_WF8B_BPDLCD1_MASK (0x8U) 4900 #define LCD_WF8B_BPDLCD1_SHIFT (3U) 4901 /*! BPDLCD1 4902 * 0b0..LCD segment off or LCD backplane inactive for phase D 4903 * 0b1..LCD segment on or LCD backplane active for phase D 4904 */ 4905 #define LCD_WF8B_BPDLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD1_SHIFT)) & LCD_WF8B_BPDLCD1_MASK) 4906 #define LCD_WF8B_BPDLCD2_MASK (0x8U) 4907 #define LCD_WF8B_BPDLCD2_SHIFT (3U) 4908 /*! BPDLCD2 4909 * 0b0..LCD segment off or LCD backplane inactive for phase D 4910 * 0b1..LCD segment on or LCD backplane active for phase D 4911 */ 4912 #define LCD_WF8B_BPDLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD2_SHIFT)) & LCD_WF8B_BPDLCD2_MASK) 4913 #define LCD_WF8B_BPDLCD3_MASK (0x8U) 4914 #define LCD_WF8B_BPDLCD3_SHIFT (3U) 4915 /*! BPDLCD3 4916 * 0b0..LCD segment off or LCD backplane inactive for phase D 4917 * 0b1..LCD segment on or LCD backplane active for phase D 4918 */ 4919 #define LCD_WF8B_BPDLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD3_SHIFT)) & LCD_WF8B_BPDLCD3_MASK) 4920 #define LCD_WF8B_BPDLCD4_MASK (0x8U) 4921 #define LCD_WF8B_BPDLCD4_SHIFT (3U) 4922 /*! BPDLCD4 4923 * 0b0..LCD segment off or LCD backplane inactive for phase D 4924 * 0b1..LCD segment on or LCD backplane active for phase D 4925 */ 4926 #define LCD_WF8B_BPDLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD4_SHIFT)) & LCD_WF8B_BPDLCD4_MASK) 4927 #define LCD_WF8B_BPDLCD5_MASK (0x8U) 4928 #define LCD_WF8B_BPDLCD5_SHIFT (3U) 4929 /*! BPDLCD5 4930 * 0b0..LCD segment off or LCD backplane inactive for phase D 4931 * 0b1..LCD segment on or LCD backplane active for phase D 4932 */ 4933 #define LCD_WF8B_BPDLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD5_SHIFT)) & LCD_WF8B_BPDLCD5_MASK) 4934 #define LCD_WF8B_BPDLCD6_MASK (0x8U) 4935 #define LCD_WF8B_BPDLCD6_SHIFT (3U) 4936 /*! BPDLCD6 4937 * 0b0..LCD segment off or LCD backplane inactive for phase D 4938 * 0b1..LCD segment on or LCD backplane active for phase D 4939 */ 4940 #define LCD_WF8B_BPDLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD6_SHIFT)) & LCD_WF8B_BPDLCD6_MASK) 4941 #define LCD_WF8B_BPDLCD7_MASK (0x8U) 4942 #define LCD_WF8B_BPDLCD7_SHIFT (3U) 4943 /*! BPDLCD7 4944 * 0b0..LCD segment off or LCD backplane inactive for phase D 4945 * 0b1..LCD segment on or LCD backplane active for phase D 4946 */ 4947 #define LCD_WF8B_BPDLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD7_SHIFT)) & LCD_WF8B_BPDLCD7_MASK) 4948 #define LCD_WF8B_BPDLCD8_MASK (0x8U) 4949 #define LCD_WF8B_BPDLCD8_SHIFT (3U) 4950 /*! BPDLCD8 4951 * 0b0..LCD segment off or LCD backplane inactive for phase D 4952 * 0b1..LCD segment on or LCD backplane active for phase D 4953 */ 4954 #define LCD_WF8B_BPDLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD8_SHIFT)) & LCD_WF8B_BPDLCD8_MASK) 4955 #define LCD_WF8B_BPDLCD9_MASK (0x8U) 4956 #define LCD_WF8B_BPDLCD9_SHIFT (3U) 4957 /*! BPDLCD9 4958 * 0b0..LCD segment off or LCD backplane inactive for phase D 4959 * 0b1..LCD segment on or LCD backplane active for phase D 4960 */ 4961 #define LCD_WF8B_BPDLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD9_SHIFT)) & LCD_WF8B_BPDLCD9_MASK) 4962 #define LCD_WF8B_BPDLCD10_MASK (0x8U) 4963 #define LCD_WF8B_BPDLCD10_SHIFT (3U) 4964 /*! BPDLCD10 4965 * 0b0..LCD segment off or LCD backplane inactive for phase D 4966 * 0b1..LCD segment on or LCD backplane active for phase D 4967 */ 4968 #define LCD_WF8B_BPDLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD10_SHIFT)) & LCD_WF8B_BPDLCD10_MASK) 4969 #define LCD_WF8B_BPDLCD11_MASK (0x8U) 4970 #define LCD_WF8B_BPDLCD11_SHIFT (3U) 4971 /*! BPDLCD11 4972 * 0b0..LCD segment off or LCD backplane inactive for phase D 4973 * 0b1..LCD segment on or LCD backplane active for phase D 4974 */ 4975 #define LCD_WF8B_BPDLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD11_SHIFT)) & LCD_WF8B_BPDLCD11_MASK) 4976 #define LCD_WF8B_BPDLCD12_MASK (0x8U) 4977 #define LCD_WF8B_BPDLCD12_SHIFT (3U) 4978 /*! BPDLCD12 4979 * 0b0..LCD segment off or LCD backplane inactive for phase D 4980 * 0b1..LCD segment on or LCD backplane active for phase D 4981 */ 4982 #define LCD_WF8B_BPDLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD12_SHIFT)) & LCD_WF8B_BPDLCD12_MASK) 4983 #define LCD_WF8B_BPDLCD13_MASK (0x8U) 4984 #define LCD_WF8B_BPDLCD13_SHIFT (3U) 4985 /*! BPDLCD13 4986 * 0b0..LCD segment off or LCD backplane inactive for phase D 4987 * 0b1..LCD segment on or LCD backplane active for phase D 4988 */ 4989 #define LCD_WF8B_BPDLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD13_SHIFT)) & LCD_WF8B_BPDLCD13_MASK) 4990 #define LCD_WF8B_BPDLCD14_MASK (0x8U) 4991 #define LCD_WF8B_BPDLCD14_SHIFT (3U) 4992 /*! BPDLCD14 4993 * 0b0..LCD segment off or LCD backplane inactive for phase D 4994 * 0b1..LCD segment on or LCD backplane active for phase D 4995 */ 4996 #define LCD_WF8B_BPDLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD14_SHIFT)) & LCD_WF8B_BPDLCD14_MASK) 4997 #define LCD_WF8B_BPDLCD15_MASK (0x8U) 4998 #define LCD_WF8B_BPDLCD15_SHIFT (3U) 4999 /*! BPDLCD15 5000 * 0b0..LCD segment off or LCD backplane inactive for phase D 5001 * 0b1..LCD segment on or LCD backplane active for phase D 5002 */ 5003 #define LCD_WF8B_BPDLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD15_SHIFT)) & LCD_WF8B_BPDLCD15_MASK) 5004 #define LCD_WF8B_BPDLCD16_MASK (0x8U) 5005 #define LCD_WF8B_BPDLCD16_SHIFT (3U) 5006 /*! BPDLCD16 5007 * 0b0..LCD segment off or LCD backplane inactive for phase D 5008 * 0b1..LCD segment on or LCD backplane active for phase D 5009 */ 5010 #define LCD_WF8B_BPDLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD16_SHIFT)) & LCD_WF8B_BPDLCD16_MASK) 5011 #define LCD_WF8B_BPDLCD17_MASK (0x8U) 5012 #define LCD_WF8B_BPDLCD17_SHIFT (3U) 5013 /*! BPDLCD17 5014 * 0b0..LCD segment off or LCD backplane inactive for phase D 5015 * 0b1..LCD segment on or LCD backplane active for phase D 5016 */ 5017 #define LCD_WF8B_BPDLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD17_SHIFT)) & LCD_WF8B_BPDLCD17_MASK) 5018 #define LCD_WF8B_BPDLCD18_MASK (0x8U) 5019 #define LCD_WF8B_BPDLCD18_SHIFT (3U) 5020 /*! BPDLCD18 5021 * 0b0..LCD segment off or LCD backplane inactive for phase D 5022 * 0b1..LCD segment on or LCD backplane active for phase D 5023 */ 5024 #define LCD_WF8B_BPDLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD18_SHIFT)) & LCD_WF8B_BPDLCD18_MASK) 5025 #define LCD_WF8B_BPDLCD19_MASK (0x8U) 5026 #define LCD_WF8B_BPDLCD19_SHIFT (3U) 5027 /*! BPDLCD19 5028 * 0b0..LCD segment off or LCD backplane inactive for phase D 5029 * 0b1..LCD segment on or LCD backplane active for phase D 5030 */ 5031 #define LCD_WF8B_BPDLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD19_SHIFT)) & LCD_WF8B_BPDLCD19_MASK) 5032 #define LCD_WF8B_BPDLCD20_MASK (0x8U) 5033 #define LCD_WF8B_BPDLCD20_SHIFT (3U) 5034 /*! BPDLCD20 5035 * 0b0..LCD segment off or LCD backplane inactive for phase D 5036 * 0b1..LCD segment on or LCD backplane active for phase D 5037 */ 5038 #define LCD_WF8B_BPDLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD20_SHIFT)) & LCD_WF8B_BPDLCD20_MASK) 5039 #define LCD_WF8B_BPDLCD21_MASK (0x8U) 5040 #define LCD_WF8B_BPDLCD21_SHIFT (3U) 5041 /*! BPDLCD21 5042 * 0b0..LCD segment off or LCD backplane inactive for phase D 5043 * 0b1..LCD segment on or LCD backplane active for phase D 5044 */ 5045 #define LCD_WF8B_BPDLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD21_SHIFT)) & LCD_WF8B_BPDLCD21_MASK) 5046 #define LCD_WF8B_BPDLCD22_MASK (0x8U) 5047 #define LCD_WF8B_BPDLCD22_SHIFT (3U) 5048 /*! BPDLCD22 5049 * 0b0..LCD segment off or LCD backplane inactive for phase D 5050 * 0b1..LCD segment on or LCD backplane active for phase D 5051 */ 5052 #define LCD_WF8B_BPDLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD22_SHIFT)) & LCD_WF8B_BPDLCD22_MASK) 5053 #define LCD_WF8B_BPDLCD23_MASK (0x8U) 5054 #define LCD_WF8B_BPDLCD23_SHIFT (3U) 5055 /*! BPDLCD23 5056 * 0b0..LCD segment off or LCD backplane inactive for phase D 5057 * 0b1..LCD segment on or LCD backplane active for phase D 5058 */ 5059 #define LCD_WF8B_BPDLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD23_SHIFT)) & LCD_WF8B_BPDLCD23_MASK) 5060 #define LCD_WF8B_BPDLCD24_MASK (0x8U) 5061 #define LCD_WF8B_BPDLCD24_SHIFT (3U) 5062 /*! BPDLCD24 5063 * 0b0..LCD segment off or LCD backplane inactive for phase D 5064 * 0b1..LCD segment on or LCD backplane active for phase D 5065 */ 5066 #define LCD_WF8B_BPDLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD24_SHIFT)) & LCD_WF8B_BPDLCD24_MASK) 5067 #define LCD_WF8B_BPDLCD25_MASK (0x8U) 5068 #define LCD_WF8B_BPDLCD25_SHIFT (3U) 5069 /*! BPDLCD25 5070 * 0b0..LCD segment off or LCD backplane inactive for phase D 5071 * 0b1..LCD segment on or LCD backplane active for phase D 5072 */ 5073 #define LCD_WF8B_BPDLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD25_SHIFT)) & LCD_WF8B_BPDLCD25_MASK) 5074 #define LCD_WF8B_BPDLCD26_MASK (0x8U) 5075 #define LCD_WF8B_BPDLCD26_SHIFT (3U) 5076 /*! BPDLCD26 5077 * 0b0..LCD segment off or LCD backplane inactive for phase D 5078 * 0b1..LCD segment on or LCD backplane active for phase D 5079 */ 5080 #define LCD_WF8B_BPDLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD26_SHIFT)) & LCD_WF8B_BPDLCD26_MASK) 5081 #define LCD_WF8B_BPDLCD27_MASK (0x8U) 5082 #define LCD_WF8B_BPDLCD27_SHIFT (3U) 5083 /*! BPDLCD27 5084 * 0b0..LCD segment off or LCD backplane inactive for phase D 5085 * 0b1..LCD segment on or LCD backplane active for phase D 5086 */ 5087 #define LCD_WF8B_BPDLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD27_SHIFT)) & LCD_WF8B_BPDLCD27_MASK) 5088 #define LCD_WF8B_BPDLCD28_MASK (0x8U) 5089 #define LCD_WF8B_BPDLCD28_SHIFT (3U) 5090 /*! BPDLCD28 5091 * 0b0..LCD segment off or LCD backplane inactive for phase D 5092 * 0b1..LCD segment on or LCD backplane active for phase D 5093 */ 5094 #define LCD_WF8B_BPDLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD28_SHIFT)) & LCD_WF8B_BPDLCD28_MASK) 5095 #define LCD_WF8B_BPDLCD29_MASK (0x8U) 5096 #define LCD_WF8B_BPDLCD29_SHIFT (3U) 5097 /*! BPDLCD29 5098 * 0b0..LCD segment off or LCD backplane inactive for phase D 5099 * 0b1..LCD segment on or LCD backplane active for phase D 5100 */ 5101 #define LCD_WF8B_BPDLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD29_SHIFT)) & LCD_WF8B_BPDLCD29_MASK) 5102 #define LCD_WF8B_BPDLCD30_MASK (0x8U) 5103 #define LCD_WF8B_BPDLCD30_SHIFT (3U) 5104 /*! BPDLCD30 5105 * 0b0..LCD segment off or LCD backplane inactive for phase D 5106 * 0b1..LCD segment on or LCD backplane active for phase D 5107 */ 5108 #define LCD_WF8B_BPDLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD30_SHIFT)) & LCD_WF8B_BPDLCD30_MASK) 5109 #define LCD_WF8B_BPDLCD31_MASK (0x8U) 5110 #define LCD_WF8B_BPDLCD31_SHIFT (3U) 5111 /*! BPDLCD31 5112 * 0b0..LCD segment off or LCD backplane inactive for phase D 5113 * 0b1..LCD segment on or LCD backplane active for phase D 5114 */ 5115 #define LCD_WF8B_BPDLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD31_SHIFT)) & LCD_WF8B_BPDLCD31_MASK) 5116 #define LCD_WF8B_BPDLCD32_MASK (0x8U) 5117 #define LCD_WF8B_BPDLCD32_SHIFT (3U) 5118 /*! BPDLCD32 5119 * 0b0..LCD segment off or LCD backplane inactive for phase D 5120 * 0b1..LCD segment on or LCD backplane active for phase D 5121 */ 5122 #define LCD_WF8B_BPDLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD32_SHIFT)) & LCD_WF8B_BPDLCD32_MASK) 5123 #define LCD_WF8B_BPDLCD33_MASK (0x8U) 5124 #define LCD_WF8B_BPDLCD33_SHIFT (3U) 5125 /*! BPDLCD33 5126 * 0b0..LCD segment off or LCD backplane inactive for phase D 5127 * 0b1..LCD segment on or LCD backplane active for phase D 5128 */ 5129 #define LCD_WF8B_BPDLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD33_SHIFT)) & LCD_WF8B_BPDLCD33_MASK) 5130 #define LCD_WF8B_BPDLCD34_MASK (0x8U) 5131 #define LCD_WF8B_BPDLCD34_SHIFT (3U) 5132 /*! BPDLCD34 5133 * 0b0..LCD segment off or LCD backplane inactive for phase D 5134 * 0b1..LCD segment on or LCD backplane active for phase D 5135 */ 5136 #define LCD_WF8B_BPDLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD34_SHIFT)) & LCD_WF8B_BPDLCD34_MASK) 5137 #define LCD_WF8B_BPDLCD35_MASK (0x8U) 5138 #define LCD_WF8B_BPDLCD35_SHIFT (3U) 5139 /*! BPDLCD35 5140 * 0b0..LCD segment off or LCD backplane inactive for phase D 5141 * 0b1..LCD segment on or LCD backplane active for phase D 5142 */ 5143 #define LCD_WF8B_BPDLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD35_SHIFT)) & LCD_WF8B_BPDLCD35_MASK) 5144 #define LCD_WF8B_BPDLCD36_MASK (0x8U) 5145 #define LCD_WF8B_BPDLCD36_SHIFT (3U) 5146 /*! BPDLCD36 5147 * 0b0..LCD segment off or LCD backplane inactive for phase D 5148 * 0b1..LCD segment on or LCD backplane active for phase D 5149 */ 5150 #define LCD_WF8B_BPDLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD36_SHIFT)) & LCD_WF8B_BPDLCD36_MASK) 5151 #define LCD_WF8B_BPDLCD37_MASK (0x8U) 5152 #define LCD_WF8B_BPDLCD37_SHIFT (3U) 5153 /*! BPDLCD37 5154 * 0b0..LCD segment off or LCD backplane inactive for phase D 5155 * 0b1..LCD segment on or LCD backplane active for phase D 5156 */ 5157 #define LCD_WF8B_BPDLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD37_SHIFT)) & LCD_WF8B_BPDLCD37_MASK) 5158 #define LCD_WF8B_BPDLCD38_MASK (0x8U) 5159 #define LCD_WF8B_BPDLCD38_SHIFT (3U) 5160 /*! BPDLCD38 5161 * 0b0..LCD segment off or LCD backplane inactive for phase D 5162 * 0b1..LCD segment on or LCD backplane active for phase D 5163 */ 5164 #define LCD_WF8B_BPDLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD38_SHIFT)) & LCD_WF8B_BPDLCD38_MASK) 5165 #define LCD_WF8B_BPDLCD39_MASK (0x8U) 5166 #define LCD_WF8B_BPDLCD39_SHIFT (3U) 5167 /*! BPDLCD39 5168 * 0b0..LCD segment off or LCD backplane inactive for phase D 5169 * 0b1..LCD segment on or LCD backplane active for phase D 5170 */ 5171 #define LCD_WF8B_BPDLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD39_SHIFT)) & LCD_WF8B_BPDLCD39_MASK) 5172 #define LCD_WF8B_BPDLCD40_MASK (0x8U) 5173 #define LCD_WF8B_BPDLCD40_SHIFT (3U) 5174 /*! BPDLCD40 5175 * 0b0..LCD segment off or LCD backplane inactive for phase D 5176 * 0b1..LCD segment on or LCD backplane active for phase D 5177 */ 5178 #define LCD_WF8B_BPDLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD40_SHIFT)) & LCD_WF8B_BPDLCD40_MASK) 5179 #define LCD_WF8B_BPDLCD41_MASK (0x8U) 5180 #define LCD_WF8B_BPDLCD41_SHIFT (3U) 5181 /*! BPDLCD41 5182 * 0b0..LCD segment off or LCD backplane inactive for phase D 5183 * 0b1..LCD segment on or LCD backplane active for phase D 5184 */ 5185 #define LCD_WF8B_BPDLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD41_SHIFT)) & LCD_WF8B_BPDLCD41_MASK) 5186 #define LCD_WF8B_BPDLCD42_MASK (0x8U) 5187 #define LCD_WF8B_BPDLCD42_SHIFT (3U) 5188 /*! BPDLCD42 5189 * 0b0..LCD segment off or LCD backplane inactive for phase D 5190 * 0b1..LCD segment on or LCD backplane active for phase D 5191 */ 5192 #define LCD_WF8B_BPDLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD42_SHIFT)) & LCD_WF8B_BPDLCD42_MASK) 5193 #define LCD_WF8B_BPDLCD43_MASK (0x8U) 5194 #define LCD_WF8B_BPDLCD43_SHIFT (3U) 5195 /*! BPDLCD43 5196 * 0b0..LCD segment off or LCD backplane inactive for phase D 5197 * 0b1..LCD segment on or LCD backplane active for phase D 5198 */ 5199 #define LCD_WF8B_BPDLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD43_SHIFT)) & LCD_WF8B_BPDLCD43_MASK) 5200 #define LCD_WF8B_BPDLCD44_MASK (0x8U) 5201 #define LCD_WF8B_BPDLCD44_SHIFT (3U) 5202 /*! BPDLCD44 5203 * 0b0..LCD segment off or LCD backplane inactive for phase D 5204 * 0b1..LCD segment on or LCD backplane active for phase D 5205 */ 5206 #define LCD_WF8B_BPDLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD44_SHIFT)) & LCD_WF8B_BPDLCD44_MASK) 5207 #define LCD_WF8B_BPDLCD45_MASK (0x8U) 5208 #define LCD_WF8B_BPDLCD45_SHIFT (3U) 5209 /*! BPDLCD45 5210 * 0b0..LCD segment off or LCD backplane inactive for phase D 5211 * 0b1..LCD segment on or LCD backplane active for phase D 5212 */ 5213 #define LCD_WF8B_BPDLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD45_SHIFT)) & LCD_WF8B_BPDLCD45_MASK) 5214 #define LCD_WF8B_BPDLCD46_MASK (0x8U) 5215 #define LCD_WF8B_BPDLCD46_SHIFT (3U) 5216 /*! BPDLCD46 5217 * 0b0..LCD segment off or LCD backplane inactive for phase D 5218 * 0b1..LCD segment on or LCD backplane active for phase D 5219 */ 5220 #define LCD_WF8B_BPDLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD46_SHIFT)) & LCD_WF8B_BPDLCD46_MASK) 5221 #define LCD_WF8B_BPDLCD47_MASK (0x8U) 5222 #define LCD_WF8B_BPDLCD47_SHIFT (3U) 5223 /*! BPDLCD47 5224 * 0b0..LCD segment off or LCD backplane inactive for phase D 5225 * 0b1..LCD segment on or LCD backplane active for phase D 5226 */ 5227 #define LCD_WF8B_BPDLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD47_SHIFT)) & LCD_WF8B_BPDLCD47_MASK) 5228 #define LCD_WF8B_BPDLCD48_MASK (0x8U) 5229 #define LCD_WF8B_BPDLCD48_SHIFT (3U) 5230 /*! BPDLCD48 5231 * 0b0..LCD segment off or LCD backplane inactive for phase D 5232 * 0b1..LCD segment on or LCD backplane active for phase D 5233 */ 5234 #define LCD_WF8B_BPDLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD48_SHIFT)) & LCD_WF8B_BPDLCD48_MASK) 5235 #define LCD_WF8B_BPDLCD49_MASK (0x8U) 5236 #define LCD_WF8B_BPDLCD49_SHIFT (3U) 5237 /*! BPDLCD49 5238 * 0b0..LCD segment off or LCD backplane inactive for phase D 5239 * 0b1..LCD segment on or LCD backplane active for phase D 5240 */ 5241 #define LCD_WF8B_BPDLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD49_SHIFT)) & LCD_WF8B_BPDLCD49_MASK) 5242 #define LCD_WF8B_BPDLCD50_MASK (0x8U) 5243 #define LCD_WF8B_BPDLCD50_SHIFT (3U) 5244 /*! BPDLCD50 5245 * 0b0..LCD segment off or LCD backplane inactive for phase D 5246 * 0b1..LCD segment on or LCD backplane active for phase D 5247 */ 5248 #define LCD_WF8B_BPDLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD50_SHIFT)) & LCD_WF8B_BPDLCD50_MASK) 5249 #define LCD_WF8B_BPDLCD51_MASK (0x8U) 5250 #define LCD_WF8B_BPDLCD51_SHIFT (3U) 5251 /*! BPDLCD51 5252 * 0b0..LCD segment off or LCD backplane inactive for phase D 5253 * 0b1..LCD segment on or LCD backplane active for phase D 5254 */ 5255 #define LCD_WF8B_BPDLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD51_SHIFT)) & LCD_WF8B_BPDLCD51_MASK) 5256 #define LCD_WF8B_BPDLCD52_MASK (0x8U) 5257 #define LCD_WF8B_BPDLCD52_SHIFT (3U) 5258 /*! BPDLCD52 5259 * 0b0..LCD segment off or LCD backplane inactive for phase D 5260 * 0b1..LCD segment on or LCD backplane active for phase D 5261 */ 5262 #define LCD_WF8B_BPDLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD52_SHIFT)) & LCD_WF8B_BPDLCD52_MASK) 5263 #define LCD_WF8B_BPDLCD53_MASK (0x8U) 5264 #define LCD_WF8B_BPDLCD53_SHIFT (3U) 5265 /*! BPDLCD53 5266 * 0b0..LCD segment off or LCD backplane inactive for phase D 5267 * 0b1..LCD segment on or LCD backplane active for phase D 5268 */ 5269 #define LCD_WF8B_BPDLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD53_SHIFT)) & LCD_WF8B_BPDLCD53_MASK) 5270 #define LCD_WF8B_BPDLCD54_MASK (0x8U) 5271 #define LCD_WF8B_BPDLCD54_SHIFT (3U) 5272 /*! BPDLCD54 5273 * 0b0..LCD segment off or LCD backplane inactive for phase D 5274 * 0b1..LCD segment on or LCD backplane active for phase D 5275 */ 5276 #define LCD_WF8B_BPDLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD54_SHIFT)) & LCD_WF8B_BPDLCD54_MASK) 5277 #define LCD_WF8B_BPDLCD55_MASK (0x8U) 5278 #define LCD_WF8B_BPDLCD55_SHIFT (3U) 5279 /*! BPDLCD55 5280 * 0b0..LCD segment off or LCD backplane inactive for phase D 5281 * 0b1..LCD segment on or LCD backplane active for phase D 5282 */ 5283 #define LCD_WF8B_BPDLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD55_SHIFT)) & LCD_WF8B_BPDLCD55_MASK) 5284 #define LCD_WF8B_BPDLCD56_MASK (0x8U) 5285 #define LCD_WF8B_BPDLCD56_SHIFT (3U) 5286 /*! BPDLCD56 5287 * 0b0..LCD segment off or LCD backplane inactive for phase D 5288 * 0b1..LCD segment on or LCD backplane active for phase D 5289 */ 5290 #define LCD_WF8B_BPDLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD56_SHIFT)) & LCD_WF8B_BPDLCD56_MASK) 5291 #define LCD_WF8B_BPDLCD57_MASK (0x8U) 5292 #define LCD_WF8B_BPDLCD57_SHIFT (3U) 5293 /*! BPDLCD57 5294 * 0b0..LCD segment off or LCD backplane inactive for phase D 5295 * 0b1..LCD segment on or LCD backplane active for phase D 5296 */ 5297 #define LCD_WF8B_BPDLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD57_SHIFT)) & LCD_WF8B_BPDLCD57_MASK) 5298 #define LCD_WF8B_BPDLCD58_MASK (0x8U) 5299 #define LCD_WF8B_BPDLCD58_SHIFT (3U) 5300 /*! BPDLCD58 5301 * 0b0..LCD segment off or LCD backplane inactive for phase D 5302 * 0b1..LCD segment on or LCD backplane active for phase D 5303 */ 5304 #define LCD_WF8B_BPDLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD58_SHIFT)) & LCD_WF8B_BPDLCD58_MASK) 5305 #define LCD_WF8B_BPDLCD59_MASK (0x8U) 5306 #define LCD_WF8B_BPDLCD59_SHIFT (3U) 5307 /*! BPDLCD59 5308 * 0b0..LCD segment off or LCD backplane inactive for phase D 5309 * 0b1..LCD segment on or LCD backplane active for phase D 5310 */ 5311 #define LCD_WF8B_BPDLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD59_SHIFT)) & LCD_WF8B_BPDLCD59_MASK) 5312 #define LCD_WF8B_BPDLCD60_MASK (0x8U) 5313 #define LCD_WF8B_BPDLCD60_SHIFT (3U) 5314 /*! BPDLCD60 5315 * 0b0..LCD segment off or LCD backplane inactive for phase D 5316 * 0b1..LCD segment on or LCD backplane active for phase D 5317 */ 5318 #define LCD_WF8B_BPDLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD60_SHIFT)) & LCD_WF8B_BPDLCD60_MASK) 5319 #define LCD_WF8B_BPDLCD61_MASK (0x8U) 5320 #define LCD_WF8B_BPDLCD61_SHIFT (3U) 5321 /*! BPDLCD61 5322 * 0b0..LCD segment off or LCD backplane inactive for phase D 5323 * 0b1..LCD segment on or LCD backplane active for phase D 5324 */ 5325 #define LCD_WF8B_BPDLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD61_SHIFT)) & LCD_WF8B_BPDLCD61_MASK) 5326 #define LCD_WF8B_BPDLCD62_MASK (0x8U) 5327 #define LCD_WF8B_BPDLCD62_SHIFT (3U) 5328 /*! BPDLCD62 5329 * 0b0..LCD segment off or LCD backplane inactive for phase D 5330 * 0b1..LCD segment on or LCD backplane active for phase D 5331 */ 5332 #define LCD_WF8B_BPDLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD62_SHIFT)) & LCD_WF8B_BPDLCD62_MASK) 5333 #define LCD_WF8B_BPDLCD63_MASK (0x8U) 5334 #define LCD_WF8B_BPDLCD63_SHIFT (3U) 5335 /*! BPDLCD63 5336 * 0b0..LCD segment off or LCD backplane inactive for phase D 5337 * 0b1..LCD segment on or LCD backplane active for phase D 5338 */ 5339 #define LCD_WF8B_BPDLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD63_SHIFT)) & LCD_WF8B_BPDLCD63_MASK) 5340 #define LCD_WF8B_BPELCD0_MASK (0x10U) 5341 #define LCD_WF8B_BPELCD0_SHIFT (4U) 5342 /*! BPELCD0 5343 * 0b0..LCD segment off or LCD backplane inactive for phase E 5344 * 0b1..LCD segment on or LCD backplane active for phase E 5345 */ 5346 #define LCD_WF8B_BPELCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD0_SHIFT)) & LCD_WF8B_BPELCD0_MASK) 5347 #define LCD_WF8B_BPELCD1_MASK (0x10U) 5348 #define LCD_WF8B_BPELCD1_SHIFT (4U) 5349 /*! BPELCD1 5350 * 0b0..LCD segment off or LCD backplane inactive for phase E 5351 * 0b1..LCD segment on or LCD backplane active for phase E 5352 */ 5353 #define LCD_WF8B_BPELCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD1_SHIFT)) & LCD_WF8B_BPELCD1_MASK) 5354 #define LCD_WF8B_BPELCD2_MASK (0x10U) 5355 #define LCD_WF8B_BPELCD2_SHIFT (4U) 5356 /*! BPELCD2 5357 * 0b0..LCD segment off or LCD backplane inactive for phase E 5358 * 0b1..LCD segment on or LCD backplane active for phase E 5359 */ 5360 #define LCD_WF8B_BPELCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD2_SHIFT)) & LCD_WF8B_BPELCD2_MASK) 5361 #define LCD_WF8B_BPELCD3_MASK (0x10U) 5362 #define LCD_WF8B_BPELCD3_SHIFT (4U) 5363 /*! BPELCD3 5364 * 0b0..LCD segment off or LCD backplane inactive for phase E 5365 * 0b1..LCD segment on or LCD backplane active for phase E 5366 */ 5367 #define LCD_WF8B_BPELCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD3_SHIFT)) & LCD_WF8B_BPELCD3_MASK) 5368 #define LCD_WF8B_BPELCD4_MASK (0x10U) 5369 #define LCD_WF8B_BPELCD4_SHIFT (4U) 5370 /*! BPELCD4 5371 * 0b0..LCD segment off or LCD backplane inactive for phase E 5372 * 0b1..LCD segment on or LCD backplane active for phase E 5373 */ 5374 #define LCD_WF8B_BPELCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD4_SHIFT)) & LCD_WF8B_BPELCD4_MASK) 5375 #define LCD_WF8B_BPELCD5_MASK (0x10U) 5376 #define LCD_WF8B_BPELCD5_SHIFT (4U) 5377 /*! BPELCD5 5378 * 0b0..LCD segment off or LCD backplane inactive for phase E 5379 * 0b1..LCD segment on or LCD backplane active for phase E 5380 */ 5381 #define LCD_WF8B_BPELCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD5_SHIFT)) & LCD_WF8B_BPELCD5_MASK) 5382 #define LCD_WF8B_BPELCD6_MASK (0x10U) 5383 #define LCD_WF8B_BPELCD6_SHIFT (4U) 5384 /*! BPELCD6 5385 * 0b0..LCD segment off or LCD backplane inactive for phase E 5386 * 0b1..LCD segment on or LCD backplane active for phase E 5387 */ 5388 #define LCD_WF8B_BPELCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD6_SHIFT)) & LCD_WF8B_BPELCD6_MASK) 5389 #define LCD_WF8B_BPELCD7_MASK (0x10U) 5390 #define LCD_WF8B_BPELCD7_SHIFT (4U) 5391 /*! BPELCD7 5392 * 0b0..LCD segment off or LCD backplane inactive for phase E 5393 * 0b1..LCD segment on or LCD backplane active for phase E 5394 */ 5395 #define LCD_WF8B_BPELCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD7_SHIFT)) & LCD_WF8B_BPELCD7_MASK) 5396 #define LCD_WF8B_BPELCD8_MASK (0x10U) 5397 #define LCD_WF8B_BPELCD8_SHIFT (4U) 5398 /*! BPELCD8 5399 * 0b0..LCD segment off or LCD backplane inactive for phase E 5400 * 0b1..LCD segment on or LCD backplane active for phase E 5401 */ 5402 #define LCD_WF8B_BPELCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD8_SHIFT)) & LCD_WF8B_BPELCD8_MASK) 5403 #define LCD_WF8B_BPELCD9_MASK (0x10U) 5404 #define LCD_WF8B_BPELCD9_SHIFT (4U) 5405 /*! BPELCD9 5406 * 0b0..LCD segment off or LCD backplane inactive for phase E 5407 * 0b1..LCD segment on or LCD backplane active for phase E 5408 */ 5409 #define LCD_WF8B_BPELCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD9_SHIFT)) & LCD_WF8B_BPELCD9_MASK) 5410 #define LCD_WF8B_BPELCD10_MASK (0x10U) 5411 #define LCD_WF8B_BPELCD10_SHIFT (4U) 5412 /*! BPELCD10 5413 * 0b0..LCD segment off or LCD backplane inactive for phase E 5414 * 0b1..LCD segment on or LCD backplane active for phase E 5415 */ 5416 #define LCD_WF8B_BPELCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD10_SHIFT)) & LCD_WF8B_BPELCD10_MASK) 5417 #define LCD_WF8B_BPELCD11_MASK (0x10U) 5418 #define LCD_WF8B_BPELCD11_SHIFT (4U) 5419 /*! BPELCD11 5420 * 0b0..LCD segment off or LCD backplane inactive for phase E 5421 * 0b1..LCD segment on or LCD backplane active for phase E 5422 */ 5423 #define LCD_WF8B_BPELCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD11_SHIFT)) & LCD_WF8B_BPELCD11_MASK) 5424 #define LCD_WF8B_BPELCD12_MASK (0x10U) 5425 #define LCD_WF8B_BPELCD12_SHIFT (4U) 5426 /*! BPELCD12 5427 * 0b0..LCD segment off or LCD backplane inactive for phase E 5428 * 0b1..LCD segment on or LCD backplane active for phase E 5429 */ 5430 #define LCD_WF8B_BPELCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD12_SHIFT)) & LCD_WF8B_BPELCD12_MASK) 5431 #define LCD_WF8B_BPELCD13_MASK (0x10U) 5432 #define LCD_WF8B_BPELCD13_SHIFT (4U) 5433 /*! BPELCD13 5434 * 0b0..LCD segment off or LCD backplane inactive for phase E 5435 * 0b1..LCD segment on or LCD backplane active for phase E 5436 */ 5437 #define LCD_WF8B_BPELCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD13_SHIFT)) & LCD_WF8B_BPELCD13_MASK) 5438 #define LCD_WF8B_BPELCD14_MASK (0x10U) 5439 #define LCD_WF8B_BPELCD14_SHIFT (4U) 5440 /*! BPELCD14 5441 * 0b0..LCD segment off or LCD backplane inactive for phase E 5442 * 0b1..LCD segment on or LCD backplane active for phase E 5443 */ 5444 #define LCD_WF8B_BPELCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD14_SHIFT)) & LCD_WF8B_BPELCD14_MASK) 5445 #define LCD_WF8B_BPELCD15_MASK (0x10U) 5446 #define LCD_WF8B_BPELCD15_SHIFT (4U) 5447 /*! BPELCD15 5448 * 0b0..LCD segment off or LCD backplane inactive for phase E 5449 * 0b1..LCD segment on or LCD backplane active for phase E 5450 */ 5451 #define LCD_WF8B_BPELCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD15_SHIFT)) & LCD_WF8B_BPELCD15_MASK) 5452 #define LCD_WF8B_BPELCD16_MASK (0x10U) 5453 #define LCD_WF8B_BPELCD16_SHIFT (4U) 5454 /*! BPELCD16 5455 * 0b0..LCD segment off or LCD backplane inactive for phase E 5456 * 0b1..LCD segment on or LCD backplane active for phase E 5457 */ 5458 #define LCD_WF8B_BPELCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD16_SHIFT)) & LCD_WF8B_BPELCD16_MASK) 5459 #define LCD_WF8B_BPELCD17_MASK (0x10U) 5460 #define LCD_WF8B_BPELCD17_SHIFT (4U) 5461 /*! BPELCD17 5462 * 0b0..LCD segment off or LCD backplane inactive for phase E 5463 * 0b1..LCD segment on or LCD backplane active for phase E 5464 */ 5465 #define LCD_WF8B_BPELCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD17_SHIFT)) & LCD_WF8B_BPELCD17_MASK) 5466 #define LCD_WF8B_BPELCD18_MASK (0x10U) 5467 #define LCD_WF8B_BPELCD18_SHIFT (4U) 5468 /*! BPELCD18 5469 * 0b0..LCD segment off or LCD backplane inactive for phase E 5470 * 0b1..LCD segment on or LCD backplane active for phase E 5471 */ 5472 #define LCD_WF8B_BPELCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD18_SHIFT)) & LCD_WF8B_BPELCD18_MASK) 5473 #define LCD_WF8B_BPELCD19_MASK (0x10U) 5474 #define LCD_WF8B_BPELCD19_SHIFT (4U) 5475 /*! BPELCD19 5476 * 0b0..LCD segment off or LCD backplane inactive for phase E 5477 * 0b1..LCD segment on or LCD backplane active for phase E 5478 */ 5479 #define LCD_WF8B_BPELCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD19_SHIFT)) & LCD_WF8B_BPELCD19_MASK) 5480 #define LCD_WF8B_BPELCD20_MASK (0x10U) 5481 #define LCD_WF8B_BPELCD20_SHIFT (4U) 5482 /*! BPELCD20 5483 * 0b0..LCD segment off or LCD backplane inactive for phase E 5484 * 0b1..LCD segment on or LCD backplane active for phase E 5485 */ 5486 #define LCD_WF8B_BPELCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD20_SHIFT)) & LCD_WF8B_BPELCD20_MASK) 5487 #define LCD_WF8B_BPELCD21_MASK (0x10U) 5488 #define LCD_WF8B_BPELCD21_SHIFT (4U) 5489 /*! BPELCD21 5490 * 0b0..LCD segment off or LCD backplane inactive for phase E 5491 * 0b1..LCD segment on or LCD backplane active for phase E 5492 */ 5493 #define LCD_WF8B_BPELCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD21_SHIFT)) & LCD_WF8B_BPELCD21_MASK) 5494 #define LCD_WF8B_BPELCD22_MASK (0x10U) 5495 #define LCD_WF8B_BPELCD22_SHIFT (4U) 5496 /*! BPELCD22 5497 * 0b0..LCD segment off or LCD backplane inactive for phase E 5498 * 0b1..LCD segment on or LCD backplane active for phase E 5499 */ 5500 #define LCD_WF8B_BPELCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD22_SHIFT)) & LCD_WF8B_BPELCD22_MASK) 5501 #define LCD_WF8B_BPELCD23_MASK (0x10U) 5502 #define LCD_WF8B_BPELCD23_SHIFT (4U) 5503 /*! BPELCD23 5504 * 0b0..LCD segment off or LCD backplane inactive for phase E 5505 * 0b1..LCD segment on or LCD backplane active for phase E 5506 */ 5507 #define LCD_WF8B_BPELCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD23_SHIFT)) & LCD_WF8B_BPELCD23_MASK) 5508 #define LCD_WF8B_BPELCD24_MASK (0x10U) 5509 #define LCD_WF8B_BPELCD24_SHIFT (4U) 5510 /*! BPELCD24 5511 * 0b0..LCD segment off or LCD backplane inactive for phase E 5512 * 0b1..LCD segment on or LCD backplane active for phase E 5513 */ 5514 #define LCD_WF8B_BPELCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD24_SHIFT)) & LCD_WF8B_BPELCD24_MASK) 5515 #define LCD_WF8B_BPELCD25_MASK (0x10U) 5516 #define LCD_WF8B_BPELCD25_SHIFT (4U) 5517 /*! BPELCD25 5518 * 0b0..LCD segment off or LCD backplane inactive for phase E 5519 * 0b1..LCD segment on or LCD backplane active for phase E 5520 */ 5521 #define LCD_WF8B_BPELCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD25_SHIFT)) & LCD_WF8B_BPELCD25_MASK) 5522 #define LCD_WF8B_BPELCD26_MASK (0x10U) 5523 #define LCD_WF8B_BPELCD26_SHIFT (4U) 5524 /*! BPELCD26 5525 * 0b0..LCD segment off or LCD backplane inactive for phase E 5526 * 0b1..LCD segment on or LCD backplane active for phase E 5527 */ 5528 #define LCD_WF8B_BPELCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD26_SHIFT)) & LCD_WF8B_BPELCD26_MASK) 5529 #define LCD_WF8B_BPELCD27_MASK (0x10U) 5530 #define LCD_WF8B_BPELCD27_SHIFT (4U) 5531 /*! BPELCD27 5532 * 0b0..LCD segment off or LCD backplane inactive for phase E 5533 * 0b1..LCD segment on or LCD backplane active for phase E 5534 */ 5535 #define LCD_WF8B_BPELCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD27_SHIFT)) & LCD_WF8B_BPELCD27_MASK) 5536 #define LCD_WF8B_BPELCD28_MASK (0x10U) 5537 #define LCD_WF8B_BPELCD28_SHIFT (4U) 5538 /*! BPELCD28 5539 * 0b0..LCD segment off or LCD backplane inactive for phase E 5540 * 0b1..LCD segment on or LCD backplane active for phase E 5541 */ 5542 #define LCD_WF8B_BPELCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD28_SHIFT)) & LCD_WF8B_BPELCD28_MASK) 5543 #define LCD_WF8B_BPELCD29_MASK (0x10U) 5544 #define LCD_WF8B_BPELCD29_SHIFT (4U) 5545 /*! BPELCD29 5546 * 0b0..LCD segment off or LCD backplane inactive for phase E 5547 * 0b1..LCD segment on or LCD backplane active for phase E 5548 */ 5549 #define LCD_WF8B_BPELCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD29_SHIFT)) & LCD_WF8B_BPELCD29_MASK) 5550 #define LCD_WF8B_BPELCD30_MASK (0x10U) 5551 #define LCD_WF8B_BPELCD30_SHIFT (4U) 5552 /*! BPELCD30 5553 * 0b0..LCD segment off or LCD backplane inactive for phase E 5554 * 0b1..LCD segment on or LCD backplane active for phase E 5555 */ 5556 #define LCD_WF8B_BPELCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD30_SHIFT)) & LCD_WF8B_BPELCD30_MASK) 5557 #define LCD_WF8B_BPELCD31_MASK (0x10U) 5558 #define LCD_WF8B_BPELCD31_SHIFT (4U) 5559 /*! BPELCD31 5560 * 0b0..LCD segment off or LCD backplane inactive for phase E 5561 * 0b1..LCD segment on or LCD backplane active for phase E 5562 */ 5563 #define LCD_WF8B_BPELCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD31_SHIFT)) & LCD_WF8B_BPELCD31_MASK) 5564 #define LCD_WF8B_BPELCD32_MASK (0x10U) 5565 #define LCD_WF8B_BPELCD32_SHIFT (4U) 5566 /*! BPELCD32 5567 * 0b0..LCD segment off or LCD backplane inactive for phase E 5568 * 0b1..LCD segment on or LCD backplane active for phase E 5569 */ 5570 #define LCD_WF8B_BPELCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD32_SHIFT)) & LCD_WF8B_BPELCD32_MASK) 5571 #define LCD_WF8B_BPELCD33_MASK (0x10U) 5572 #define LCD_WF8B_BPELCD33_SHIFT (4U) 5573 /*! BPELCD33 5574 * 0b0..LCD segment off or LCD backplane inactive for phase E 5575 * 0b1..LCD segment on or LCD backplane active for phase E 5576 */ 5577 #define LCD_WF8B_BPELCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD33_SHIFT)) & LCD_WF8B_BPELCD33_MASK) 5578 #define LCD_WF8B_BPELCD34_MASK (0x10U) 5579 #define LCD_WF8B_BPELCD34_SHIFT (4U) 5580 /*! BPELCD34 5581 * 0b0..LCD segment off or LCD backplane inactive for phase E 5582 * 0b1..LCD segment on or LCD backplane active for phase E 5583 */ 5584 #define LCD_WF8B_BPELCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD34_SHIFT)) & LCD_WF8B_BPELCD34_MASK) 5585 #define LCD_WF8B_BPELCD35_MASK (0x10U) 5586 #define LCD_WF8B_BPELCD35_SHIFT (4U) 5587 /*! BPELCD35 5588 * 0b0..LCD segment off or LCD backplane inactive for phase E 5589 * 0b1..LCD segment on or LCD backplane active for phase E 5590 */ 5591 #define LCD_WF8B_BPELCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD35_SHIFT)) & LCD_WF8B_BPELCD35_MASK) 5592 #define LCD_WF8B_BPELCD36_MASK (0x10U) 5593 #define LCD_WF8B_BPELCD36_SHIFT (4U) 5594 /*! BPELCD36 5595 * 0b0..LCD segment off or LCD backplane inactive for phase E 5596 * 0b1..LCD segment on or LCD backplane active for phase E 5597 */ 5598 #define LCD_WF8B_BPELCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD36_SHIFT)) & LCD_WF8B_BPELCD36_MASK) 5599 #define LCD_WF8B_BPELCD37_MASK (0x10U) 5600 #define LCD_WF8B_BPELCD37_SHIFT (4U) 5601 /*! BPELCD37 5602 * 0b0..LCD segment off or LCD backplane inactive for phase E 5603 * 0b1..LCD segment on or LCD backplane active for phase E 5604 */ 5605 #define LCD_WF8B_BPELCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD37_SHIFT)) & LCD_WF8B_BPELCD37_MASK) 5606 #define LCD_WF8B_BPELCD38_MASK (0x10U) 5607 #define LCD_WF8B_BPELCD38_SHIFT (4U) 5608 /*! BPELCD38 5609 * 0b0..LCD segment off or LCD backplane inactive for phase E 5610 * 0b1..LCD segment on or LCD backplane active for phase E 5611 */ 5612 #define LCD_WF8B_BPELCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD38_SHIFT)) & LCD_WF8B_BPELCD38_MASK) 5613 #define LCD_WF8B_BPELCD39_MASK (0x10U) 5614 #define LCD_WF8B_BPELCD39_SHIFT (4U) 5615 /*! BPELCD39 5616 * 0b0..LCD segment off or LCD backplane inactive for phase E 5617 * 0b1..LCD segment on or LCD backplane active for phase E 5618 */ 5619 #define LCD_WF8B_BPELCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD39_SHIFT)) & LCD_WF8B_BPELCD39_MASK) 5620 #define LCD_WF8B_BPELCD40_MASK (0x10U) 5621 #define LCD_WF8B_BPELCD40_SHIFT (4U) 5622 /*! BPELCD40 5623 * 0b0..LCD segment off or LCD backplane inactive for phase E 5624 * 0b1..LCD segment on or LCD backplane active for phase E 5625 */ 5626 #define LCD_WF8B_BPELCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD40_SHIFT)) & LCD_WF8B_BPELCD40_MASK) 5627 #define LCD_WF8B_BPELCD41_MASK (0x10U) 5628 #define LCD_WF8B_BPELCD41_SHIFT (4U) 5629 /*! BPELCD41 5630 * 0b0..LCD segment off or LCD backplane inactive for phase E 5631 * 0b1..LCD segment on or LCD backplane active for phase E 5632 */ 5633 #define LCD_WF8B_BPELCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD41_SHIFT)) & LCD_WF8B_BPELCD41_MASK) 5634 #define LCD_WF8B_BPELCD42_MASK (0x10U) 5635 #define LCD_WF8B_BPELCD42_SHIFT (4U) 5636 /*! BPELCD42 5637 * 0b0..LCD segment off or LCD backplane inactive for phase E 5638 * 0b1..LCD segment on or LCD backplane active for phase E 5639 */ 5640 #define LCD_WF8B_BPELCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD42_SHIFT)) & LCD_WF8B_BPELCD42_MASK) 5641 #define LCD_WF8B_BPELCD43_MASK (0x10U) 5642 #define LCD_WF8B_BPELCD43_SHIFT (4U) 5643 /*! BPELCD43 5644 * 0b0..LCD segment off or LCD backplane inactive for phase E 5645 * 0b1..LCD segment on or LCD backplane active for phase E 5646 */ 5647 #define LCD_WF8B_BPELCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD43_SHIFT)) & LCD_WF8B_BPELCD43_MASK) 5648 #define LCD_WF8B_BPELCD44_MASK (0x10U) 5649 #define LCD_WF8B_BPELCD44_SHIFT (4U) 5650 /*! BPELCD44 5651 * 0b0..LCD segment off or LCD backplane inactive for phase E 5652 * 0b1..LCD segment on or LCD backplane active for phase E 5653 */ 5654 #define LCD_WF8B_BPELCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD44_SHIFT)) & LCD_WF8B_BPELCD44_MASK) 5655 #define LCD_WF8B_BPELCD45_MASK (0x10U) 5656 #define LCD_WF8B_BPELCD45_SHIFT (4U) 5657 /*! BPELCD45 5658 * 0b0..LCD segment off or LCD backplane inactive for phase E 5659 * 0b1..LCD segment on or LCD backplane active for phase E 5660 */ 5661 #define LCD_WF8B_BPELCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD45_SHIFT)) & LCD_WF8B_BPELCD45_MASK) 5662 #define LCD_WF8B_BPELCD46_MASK (0x10U) 5663 #define LCD_WF8B_BPELCD46_SHIFT (4U) 5664 /*! BPELCD46 5665 * 0b0..LCD segment off or LCD backplane inactive for phase E 5666 * 0b1..LCD segment on or LCD backplane active for phase E 5667 */ 5668 #define LCD_WF8B_BPELCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD46_SHIFT)) & LCD_WF8B_BPELCD46_MASK) 5669 #define LCD_WF8B_BPELCD47_MASK (0x10U) 5670 #define LCD_WF8B_BPELCD47_SHIFT (4U) 5671 /*! BPELCD47 5672 * 0b0..LCD segment off or LCD backplane inactive for phase E 5673 * 0b1..LCD segment on or LCD backplane active for phase E 5674 */ 5675 #define LCD_WF8B_BPELCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD47_SHIFT)) & LCD_WF8B_BPELCD47_MASK) 5676 #define LCD_WF8B_BPELCD48_MASK (0x10U) 5677 #define LCD_WF8B_BPELCD48_SHIFT (4U) 5678 /*! BPELCD48 5679 * 0b0..LCD segment off or LCD backplane inactive for phase E 5680 * 0b1..LCD segment on or LCD backplane active for phase E 5681 */ 5682 #define LCD_WF8B_BPELCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD48_SHIFT)) & LCD_WF8B_BPELCD48_MASK) 5683 #define LCD_WF8B_BPELCD49_MASK (0x10U) 5684 #define LCD_WF8B_BPELCD49_SHIFT (4U) 5685 /*! BPELCD49 5686 * 0b0..LCD segment off or LCD backplane inactive for phase E 5687 * 0b1..LCD segment on or LCD backplane active for phase E 5688 */ 5689 #define LCD_WF8B_BPELCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD49_SHIFT)) & LCD_WF8B_BPELCD49_MASK) 5690 #define LCD_WF8B_BPELCD50_MASK (0x10U) 5691 #define LCD_WF8B_BPELCD50_SHIFT (4U) 5692 /*! BPELCD50 5693 * 0b0..LCD segment off or LCD backplane inactive for phase E 5694 * 0b1..LCD segment on or LCD backplane active for phase E 5695 */ 5696 #define LCD_WF8B_BPELCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD50_SHIFT)) & LCD_WF8B_BPELCD50_MASK) 5697 #define LCD_WF8B_BPELCD51_MASK (0x10U) 5698 #define LCD_WF8B_BPELCD51_SHIFT (4U) 5699 /*! BPELCD51 5700 * 0b0..LCD segment off or LCD backplane inactive for phase E 5701 * 0b1..LCD segment on or LCD backplane active for phase E 5702 */ 5703 #define LCD_WF8B_BPELCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD51_SHIFT)) & LCD_WF8B_BPELCD51_MASK) 5704 #define LCD_WF8B_BPELCD52_MASK (0x10U) 5705 #define LCD_WF8B_BPELCD52_SHIFT (4U) 5706 /*! BPELCD52 5707 * 0b0..LCD segment off or LCD backplane inactive for phase E 5708 * 0b1..LCD segment on or LCD backplane active for phase E 5709 */ 5710 #define LCD_WF8B_BPELCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD52_SHIFT)) & LCD_WF8B_BPELCD52_MASK) 5711 #define LCD_WF8B_BPELCD53_MASK (0x10U) 5712 #define LCD_WF8B_BPELCD53_SHIFT (4U) 5713 /*! BPELCD53 5714 * 0b0..LCD segment off or LCD backplane inactive for phase E 5715 * 0b1..LCD segment on or LCD backplane active for phase E 5716 */ 5717 #define LCD_WF8B_BPELCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD53_SHIFT)) & LCD_WF8B_BPELCD53_MASK) 5718 #define LCD_WF8B_BPELCD54_MASK (0x10U) 5719 #define LCD_WF8B_BPELCD54_SHIFT (4U) 5720 /*! BPELCD54 5721 * 0b0..LCD segment off or LCD backplane inactive for phase E 5722 * 0b1..LCD segment on or LCD backplane active for phase E 5723 */ 5724 #define LCD_WF8B_BPELCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD54_SHIFT)) & LCD_WF8B_BPELCD54_MASK) 5725 #define LCD_WF8B_BPELCD55_MASK (0x10U) 5726 #define LCD_WF8B_BPELCD55_SHIFT (4U) 5727 /*! BPELCD55 5728 * 0b0..LCD segment off or LCD backplane inactive for phase E 5729 * 0b1..LCD segment on or LCD backplane active for phase E 5730 */ 5731 #define LCD_WF8B_BPELCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD55_SHIFT)) & LCD_WF8B_BPELCD55_MASK) 5732 #define LCD_WF8B_BPELCD56_MASK (0x10U) 5733 #define LCD_WF8B_BPELCD56_SHIFT (4U) 5734 /*! BPELCD56 5735 * 0b0..LCD segment off or LCD backplane inactive for phase E 5736 * 0b1..LCD segment on or LCD backplane active for phase E 5737 */ 5738 #define LCD_WF8B_BPELCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD56_SHIFT)) & LCD_WF8B_BPELCD56_MASK) 5739 #define LCD_WF8B_BPELCD57_MASK (0x10U) 5740 #define LCD_WF8B_BPELCD57_SHIFT (4U) 5741 /*! BPELCD57 5742 * 0b0..LCD segment off or LCD backplane inactive for phase E 5743 * 0b1..LCD segment on or LCD backplane active for phase E 5744 */ 5745 #define LCD_WF8B_BPELCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD57_SHIFT)) & LCD_WF8B_BPELCD57_MASK) 5746 #define LCD_WF8B_BPELCD58_MASK (0x10U) 5747 #define LCD_WF8B_BPELCD58_SHIFT (4U) 5748 /*! BPELCD58 5749 * 0b0..LCD segment off or LCD backplane inactive for phase E 5750 * 0b1..LCD segment on or LCD backplane active for phase E 5751 */ 5752 #define LCD_WF8B_BPELCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD58_SHIFT)) & LCD_WF8B_BPELCD58_MASK) 5753 #define LCD_WF8B_BPELCD59_MASK (0x10U) 5754 #define LCD_WF8B_BPELCD59_SHIFT (4U) 5755 /*! BPELCD59 5756 * 0b0..LCD segment off or LCD backplane inactive for phase E 5757 * 0b1..LCD segment on or LCD backplane active for phase E 5758 */ 5759 #define LCD_WF8B_BPELCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD59_SHIFT)) & LCD_WF8B_BPELCD59_MASK) 5760 #define LCD_WF8B_BPELCD60_MASK (0x10U) 5761 #define LCD_WF8B_BPELCD60_SHIFT (4U) 5762 /*! BPELCD60 5763 * 0b0..LCD segment off or LCD backplane inactive for phase E 5764 * 0b1..LCD segment on or LCD backplane active for phase E 5765 */ 5766 #define LCD_WF8B_BPELCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD60_SHIFT)) & LCD_WF8B_BPELCD60_MASK) 5767 #define LCD_WF8B_BPELCD61_MASK (0x10U) 5768 #define LCD_WF8B_BPELCD61_SHIFT (4U) 5769 /*! BPELCD61 5770 * 0b0..LCD segment off or LCD backplane inactive for phase E 5771 * 0b1..LCD segment on or LCD backplane active for phase E 5772 */ 5773 #define LCD_WF8B_BPELCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD61_SHIFT)) & LCD_WF8B_BPELCD61_MASK) 5774 #define LCD_WF8B_BPELCD62_MASK (0x10U) 5775 #define LCD_WF8B_BPELCD62_SHIFT (4U) 5776 /*! BPELCD62 5777 * 0b0..LCD segment off or LCD backplane inactive for phase E 5778 * 0b1..LCD segment on or LCD backplane active for phase E 5779 */ 5780 #define LCD_WF8B_BPELCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD62_SHIFT)) & LCD_WF8B_BPELCD62_MASK) 5781 #define LCD_WF8B_BPELCD63_MASK (0x10U) 5782 #define LCD_WF8B_BPELCD63_SHIFT (4U) 5783 /*! BPELCD63 5784 * 0b0..LCD segment off or LCD backplane inactive for phase E 5785 * 0b1..LCD segment on or LCD backplane active for phase E 5786 */ 5787 #define LCD_WF8B_BPELCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD63_SHIFT)) & LCD_WF8B_BPELCD63_MASK) 5788 #define LCD_WF8B_BPFLCD0_MASK (0x20U) 5789 #define LCD_WF8B_BPFLCD0_SHIFT (5U) 5790 /*! BPFLCD0 5791 * 0b0..LCD segment off or LCD backplane inactive for phase F 5792 * 0b1..LCD segment on or LCD backplane active for phase F 5793 */ 5794 #define LCD_WF8B_BPFLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD0_SHIFT)) & LCD_WF8B_BPFLCD0_MASK) 5795 #define LCD_WF8B_BPFLCD1_MASK (0x20U) 5796 #define LCD_WF8B_BPFLCD1_SHIFT (5U) 5797 /*! BPFLCD1 5798 * 0b0..LCD segment off or LCD backplane inactive for phase F 5799 * 0b1..LCD segment on or LCD backplane active for phase F 5800 */ 5801 #define LCD_WF8B_BPFLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD1_SHIFT)) & LCD_WF8B_BPFLCD1_MASK) 5802 #define LCD_WF8B_BPFLCD2_MASK (0x20U) 5803 #define LCD_WF8B_BPFLCD2_SHIFT (5U) 5804 /*! BPFLCD2 5805 * 0b0..LCD segment off or LCD backplane inactive for phase F 5806 * 0b1..LCD segment on or LCD backplane active for phase F 5807 */ 5808 #define LCD_WF8B_BPFLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD2_SHIFT)) & LCD_WF8B_BPFLCD2_MASK) 5809 #define LCD_WF8B_BPFLCD3_MASK (0x20U) 5810 #define LCD_WF8B_BPFLCD3_SHIFT (5U) 5811 /*! BPFLCD3 5812 * 0b0..LCD segment off or LCD backplane inactive for phase F 5813 * 0b1..LCD segment on or LCD backplane active for phase F 5814 */ 5815 #define LCD_WF8B_BPFLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD3_SHIFT)) & LCD_WF8B_BPFLCD3_MASK) 5816 #define LCD_WF8B_BPFLCD4_MASK (0x20U) 5817 #define LCD_WF8B_BPFLCD4_SHIFT (5U) 5818 /*! BPFLCD4 5819 * 0b0..LCD segment off or LCD backplane inactive for phase F 5820 * 0b1..LCD segment on or LCD backplane active for phase F 5821 */ 5822 #define LCD_WF8B_BPFLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD4_SHIFT)) & LCD_WF8B_BPFLCD4_MASK) 5823 #define LCD_WF8B_BPFLCD5_MASK (0x20U) 5824 #define LCD_WF8B_BPFLCD5_SHIFT (5U) 5825 /*! BPFLCD5 5826 * 0b0..LCD segment off or LCD backplane inactive for phase F 5827 * 0b1..LCD segment on or LCD backplane active for phase F 5828 */ 5829 #define LCD_WF8B_BPFLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD5_SHIFT)) & LCD_WF8B_BPFLCD5_MASK) 5830 #define LCD_WF8B_BPFLCD6_MASK (0x20U) 5831 #define LCD_WF8B_BPFLCD6_SHIFT (5U) 5832 /*! BPFLCD6 5833 * 0b0..LCD segment off or LCD backplane inactive for phase F 5834 * 0b1..LCD segment on or LCD backplane active for phase F 5835 */ 5836 #define LCD_WF8B_BPFLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD6_SHIFT)) & LCD_WF8B_BPFLCD6_MASK) 5837 #define LCD_WF8B_BPFLCD7_MASK (0x20U) 5838 #define LCD_WF8B_BPFLCD7_SHIFT (5U) 5839 /*! BPFLCD7 5840 * 0b0..LCD segment off or LCD backplane inactive for phase F 5841 * 0b1..LCD segment on or LCD backplane active for phase F 5842 */ 5843 #define LCD_WF8B_BPFLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD7_SHIFT)) & LCD_WF8B_BPFLCD7_MASK) 5844 #define LCD_WF8B_BPFLCD8_MASK (0x20U) 5845 #define LCD_WF8B_BPFLCD8_SHIFT (5U) 5846 /*! BPFLCD8 5847 * 0b0..LCD segment off or LCD backplane inactive for phase F 5848 * 0b1..LCD segment on or LCD backplane active for phase F 5849 */ 5850 #define LCD_WF8B_BPFLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD8_SHIFT)) & LCD_WF8B_BPFLCD8_MASK) 5851 #define LCD_WF8B_BPFLCD9_MASK (0x20U) 5852 #define LCD_WF8B_BPFLCD9_SHIFT (5U) 5853 /*! BPFLCD9 5854 * 0b0..LCD segment off or LCD backplane inactive for phase F 5855 * 0b1..LCD segment on or LCD backplane active for phase F 5856 */ 5857 #define LCD_WF8B_BPFLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD9_SHIFT)) & LCD_WF8B_BPFLCD9_MASK) 5858 #define LCD_WF8B_BPFLCD10_MASK (0x20U) 5859 #define LCD_WF8B_BPFLCD10_SHIFT (5U) 5860 /*! BPFLCD10 5861 * 0b0..LCD segment off or LCD backplane inactive for phase F 5862 * 0b1..LCD segment on or LCD backplane active for phase F 5863 */ 5864 #define LCD_WF8B_BPFLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD10_SHIFT)) & LCD_WF8B_BPFLCD10_MASK) 5865 #define LCD_WF8B_BPFLCD11_MASK (0x20U) 5866 #define LCD_WF8B_BPFLCD11_SHIFT (5U) 5867 /*! BPFLCD11 5868 * 0b0..LCD segment off or LCD backplane inactive for phase F 5869 * 0b1..LCD segment on or LCD backplane active for phase F 5870 */ 5871 #define LCD_WF8B_BPFLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD11_SHIFT)) & LCD_WF8B_BPFLCD11_MASK) 5872 #define LCD_WF8B_BPFLCD12_MASK (0x20U) 5873 #define LCD_WF8B_BPFLCD12_SHIFT (5U) 5874 /*! BPFLCD12 5875 * 0b0..LCD segment off or LCD backplane inactive for phase F 5876 * 0b1..LCD segment on or LCD backplane active for phase F 5877 */ 5878 #define LCD_WF8B_BPFLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD12_SHIFT)) & LCD_WF8B_BPFLCD12_MASK) 5879 #define LCD_WF8B_BPFLCD13_MASK (0x20U) 5880 #define LCD_WF8B_BPFLCD13_SHIFT (5U) 5881 /*! BPFLCD13 5882 * 0b0..LCD segment off or LCD backplane inactive for phase F 5883 * 0b1..LCD segment on or LCD backplane active for phase F 5884 */ 5885 #define LCD_WF8B_BPFLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD13_SHIFT)) & LCD_WF8B_BPFLCD13_MASK) 5886 #define LCD_WF8B_BPFLCD14_MASK (0x20U) 5887 #define LCD_WF8B_BPFLCD14_SHIFT (5U) 5888 /*! BPFLCD14 5889 * 0b0..LCD segment off or LCD backplane inactive for phase F 5890 * 0b1..LCD segment on or LCD backplane active for phase F 5891 */ 5892 #define LCD_WF8B_BPFLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD14_SHIFT)) & LCD_WF8B_BPFLCD14_MASK) 5893 #define LCD_WF8B_BPFLCD15_MASK (0x20U) 5894 #define LCD_WF8B_BPFLCD15_SHIFT (5U) 5895 /*! BPFLCD15 5896 * 0b0..LCD segment off or LCD backplane inactive for phase F 5897 * 0b1..LCD segment on or LCD backplane active for phase F 5898 */ 5899 #define LCD_WF8B_BPFLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD15_SHIFT)) & LCD_WF8B_BPFLCD15_MASK) 5900 #define LCD_WF8B_BPFLCD16_MASK (0x20U) 5901 #define LCD_WF8B_BPFLCD16_SHIFT (5U) 5902 /*! BPFLCD16 5903 * 0b0..LCD segment off or LCD backplane inactive for phase F 5904 * 0b1..LCD segment on or LCD backplane active for phase F 5905 */ 5906 #define LCD_WF8B_BPFLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD16_SHIFT)) & LCD_WF8B_BPFLCD16_MASK) 5907 #define LCD_WF8B_BPFLCD17_MASK (0x20U) 5908 #define LCD_WF8B_BPFLCD17_SHIFT (5U) 5909 /*! BPFLCD17 5910 * 0b0..LCD segment off or LCD backplane inactive for phase F 5911 * 0b1..LCD segment on or LCD backplane active for phase F 5912 */ 5913 #define LCD_WF8B_BPFLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD17_SHIFT)) & LCD_WF8B_BPFLCD17_MASK) 5914 #define LCD_WF8B_BPFLCD18_MASK (0x20U) 5915 #define LCD_WF8B_BPFLCD18_SHIFT (5U) 5916 /*! BPFLCD18 5917 * 0b0..LCD segment off or LCD backplane inactive for phase F 5918 * 0b1..LCD segment on or LCD backplane active for phase F 5919 */ 5920 #define LCD_WF8B_BPFLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD18_SHIFT)) & LCD_WF8B_BPFLCD18_MASK) 5921 #define LCD_WF8B_BPFLCD19_MASK (0x20U) 5922 #define LCD_WF8B_BPFLCD19_SHIFT (5U) 5923 /*! BPFLCD19 5924 * 0b0..LCD segment off or LCD backplane inactive for phase F 5925 * 0b1..LCD segment on or LCD backplane active for phase F 5926 */ 5927 #define LCD_WF8B_BPFLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD19_SHIFT)) & LCD_WF8B_BPFLCD19_MASK) 5928 #define LCD_WF8B_BPFLCD20_MASK (0x20U) 5929 #define LCD_WF8B_BPFLCD20_SHIFT (5U) 5930 /*! BPFLCD20 5931 * 0b0..LCD segment off or LCD backplane inactive for phase F 5932 * 0b1..LCD segment on or LCD backplane active for phase F 5933 */ 5934 #define LCD_WF8B_BPFLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD20_SHIFT)) & LCD_WF8B_BPFLCD20_MASK) 5935 #define LCD_WF8B_BPFLCD21_MASK (0x20U) 5936 #define LCD_WF8B_BPFLCD21_SHIFT (5U) 5937 /*! BPFLCD21 5938 * 0b0..LCD segment off or LCD backplane inactive for phase F 5939 * 0b1..LCD segment on or LCD backplane active for phase F 5940 */ 5941 #define LCD_WF8B_BPFLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD21_SHIFT)) & LCD_WF8B_BPFLCD21_MASK) 5942 #define LCD_WF8B_BPFLCD22_MASK (0x20U) 5943 #define LCD_WF8B_BPFLCD22_SHIFT (5U) 5944 /*! BPFLCD22 5945 * 0b0..LCD segment off or LCD backplane inactive for phase F 5946 * 0b1..LCD segment on or LCD backplane active for phase F 5947 */ 5948 #define LCD_WF8B_BPFLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD22_SHIFT)) & LCD_WF8B_BPFLCD22_MASK) 5949 #define LCD_WF8B_BPFLCD23_MASK (0x20U) 5950 #define LCD_WF8B_BPFLCD23_SHIFT (5U) 5951 /*! BPFLCD23 5952 * 0b0..LCD segment off or LCD backplane inactive for phase F 5953 * 0b1..LCD segment on or LCD backplane active for phase F 5954 */ 5955 #define LCD_WF8B_BPFLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD23_SHIFT)) & LCD_WF8B_BPFLCD23_MASK) 5956 #define LCD_WF8B_BPFLCD24_MASK (0x20U) 5957 #define LCD_WF8B_BPFLCD24_SHIFT (5U) 5958 /*! BPFLCD24 5959 * 0b0..LCD segment off or LCD backplane inactive for phase F 5960 * 0b1..LCD segment on or LCD backplane active for phase F 5961 */ 5962 #define LCD_WF8B_BPFLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD24_SHIFT)) & LCD_WF8B_BPFLCD24_MASK) 5963 #define LCD_WF8B_BPFLCD25_MASK (0x20U) 5964 #define LCD_WF8B_BPFLCD25_SHIFT (5U) 5965 /*! BPFLCD25 5966 * 0b0..LCD segment off or LCD backplane inactive for phase F 5967 * 0b1..LCD segment on or LCD backplane active for phase F 5968 */ 5969 #define LCD_WF8B_BPFLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD25_SHIFT)) & LCD_WF8B_BPFLCD25_MASK) 5970 #define LCD_WF8B_BPFLCD26_MASK (0x20U) 5971 #define LCD_WF8B_BPFLCD26_SHIFT (5U) 5972 /*! BPFLCD26 5973 * 0b0..LCD segment off or LCD backplane inactive for phase F 5974 * 0b1..LCD segment on or LCD backplane active for phase F 5975 */ 5976 #define LCD_WF8B_BPFLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD26_SHIFT)) & LCD_WF8B_BPFLCD26_MASK) 5977 #define LCD_WF8B_BPFLCD27_MASK (0x20U) 5978 #define LCD_WF8B_BPFLCD27_SHIFT (5U) 5979 /*! BPFLCD27 5980 * 0b0..LCD segment off or LCD backplane inactive for phase F 5981 * 0b1..LCD segment on or LCD backplane active for phase F 5982 */ 5983 #define LCD_WF8B_BPFLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD27_SHIFT)) & LCD_WF8B_BPFLCD27_MASK) 5984 #define LCD_WF8B_BPFLCD28_MASK (0x20U) 5985 #define LCD_WF8B_BPFLCD28_SHIFT (5U) 5986 /*! BPFLCD28 5987 * 0b0..LCD segment off or LCD backplane inactive for phase F 5988 * 0b1..LCD segment on or LCD backplane active for phase F 5989 */ 5990 #define LCD_WF8B_BPFLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD28_SHIFT)) & LCD_WF8B_BPFLCD28_MASK) 5991 #define LCD_WF8B_BPFLCD29_MASK (0x20U) 5992 #define LCD_WF8B_BPFLCD29_SHIFT (5U) 5993 /*! BPFLCD29 5994 * 0b0..LCD segment off or LCD backplane inactive for phase F 5995 * 0b1..LCD segment on or LCD backplane active for phase F 5996 */ 5997 #define LCD_WF8B_BPFLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD29_SHIFT)) & LCD_WF8B_BPFLCD29_MASK) 5998 #define LCD_WF8B_BPFLCD30_MASK (0x20U) 5999 #define LCD_WF8B_BPFLCD30_SHIFT (5U) 6000 /*! BPFLCD30 6001 * 0b0..LCD segment off or LCD backplane inactive for phase F 6002 * 0b1..LCD segment on or LCD backplane active for phase F 6003 */ 6004 #define LCD_WF8B_BPFLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD30_SHIFT)) & LCD_WF8B_BPFLCD30_MASK) 6005 #define LCD_WF8B_BPFLCD31_MASK (0x20U) 6006 #define LCD_WF8B_BPFLCD31_SHIFT (5U) 6007 /*! BPFLCD31 6008 * 0b0..LCD segment off or LCD backplane inactive for phase F 6009 * 0b1..LCD segment on or LCD backplane active for phase F 6010 */ 6011 #define LCD_WF8B_BPFLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD31_SHIFT)) & LCD_WF8B_BPFLCD31_MASK) 6012 #define LCD_WF8B_BPFLCD32_MASK (0x20U) 6013 #define LCD_WF8B_BPFLCD32_SHIFT (5U) 6014 /*! BPFLCD32 6015 * 0b0..LCD segment off or LCD backplane inactive for phase F 6016 * 0b1..LCD segment on or LCD backplane active for phase F 6017 */ 6018 #define LCD_WF8B_BPFLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD32_SHIFT)) & LCD_WF8B_BPFLCD32_MASK) 6019 #define LCD_WF8B_BPFLCD33_MASK (0x20U) 6020 #define LCD_WF8B_BPFLCD33_SHIFT (5U) 6021 /*! BPFLCD33 6022 * 0b0..LCD segment off or LCD backplane inactive for phase F 6023 * 0b1..LCD segment on or LCD backplane active for phase F 6024 */ 6025 #define LCD_WF8B_BPFLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD33_SHIFT)) & LCD_WF8B_BPFLCD33_MASK) 6026 #define LCD_WF8B_BPFLCD34_MASK (0x20U) 6027 #define LCD_WF8B_BPFLCD34_SHIFT (5U) 6028 /*! BPFLCD34 6029 * 0b0..LCD segment off or LCD backplane inactive for phase F 6030 * 0b1..LCD segment on or LCD backplane active for phase F 6031 */ 6032 #define LCD_WF8B_BPFLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD34_SHIFT)) & LCD_WF8B_BPFLCD34_MASK) 6033 #define LCD_WF8B_BPFLCD35_MASK (0x20U) 6034 #define LCD_WF8B_BPFLCD35_SHIFT (5U) 6035 /*! BPFLCD35 6036 * 0b0..LCD segment off or LCD backplane inactive for phase F 6037 * 0b1..LCD segment on or LCD backplane active for phase F 6038 */ 6039 #define LCD_WF8B_BPFLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD35_SHIFT)) & LCD_WF8B_BPFLCD35_MASK) 6040 #define LCD_WF8B_BPFLCD36_MASK (0x20U) 6041 #define LCD_WF8B_BPFLCD36_SHIFT (5U) 6042 /*! BPFLCD36 6043 * 0b0..LCD segment off or LCD backplane inactive for phase F 6044 * 0b1..LCD segment on or LCD backplane active for phase F 6045 */ 6046 #define LCD_WF8B_BPFLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD36_SHIFT)) & LCD_WF8B_BPFLCD36_MASK) 6047 #define LCD_WF8B_BPFLCD37_MASK (0x20U) 6048 #define LCD_WF8B_BPFLCD37_SHIFT (5U) 6049 /*! BPFLCD37 6050 * 0b0..LCD segment off or LCD backplane inactive for phase F 6051 * 0b1..LCD segment on or LCD backplane active for phase F 6052 */ 6053 #define LCD_WF8B_BPFLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD37_SHIFT)) & LCD_WF8B_BPFLCD37_MASK) 6054 #define LCD_WF8B_BPFLCD38_MASK (0x20U) 6055 #define LCD_WF8B_BPFLCD38_SHIFT (5U) 6056 /*! BPFLCD38 6057 * 0b0..LCD segment off or LCD backplane inactive for phase F 6058 * 0b1..LCD segment on or LCD backplane active for phase F 6059 */ 6060 #define LCD_WF8B_BPFLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD38_SHIFT)) & LCD_WF8B_BPFLCD38_MASK) 6061 #define LCD_WF8B_BPFLCD39_MASK (0x20U) 6062 #define LCD_WF8B_BPFLCD39_SHIFT (5U) 6063 /*! BPFLCD39 6064 * 0b0..LCD segment off or LCD backplane inactive for phase F 6065 * 0b1..LCD segment on or LCD backplane active for phase F 6066 */ 6067 #define LCD_WF8B_BPFLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD39_SHIFT)) & LCD_WF8B_BPFLCD39_MASK) 6068 #define LCD_WF8B_BPFLCD40_MASK (0x20U) 6069 #define LCD_WF8B_BPFLCD40_SHIFT (5U) 6070 /*! BPFLCD40 6071 * 0b0..LCD segment off or LCD backplane inactive for phase F 6072 * 0b1..LCD segment on or LCD backplane active for phase F 6073 */ 6074 #define LCD_WF8B_BPFLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD40_SHIFT)) & LCD_WF8B_BPFLCD40_MASK) 6075 #define LCD_WF8B_BPFLCD41_MASK (0x20U) 6076 #define LCD_WF8B_BPFLCD41_SHIFT (5U) 6077 /*! BPFLCD41 6078 * 0b0..LCD segment off or LCD backplane inactive for phase F 6079 * 0b1..LCD segment on or LCD backplane active for phase F 6080 */ 6081 #define LCD_WF8B_BPFLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD41_SHIFT)) & LCD_WF8B_BPFLCD41_MASK) 6082 #define LCD_WF8B_BPFLCD42_MASK (0x20U) 6083 #define LCD_WF8B_BPFLCD42_SHIFT (5U) 6084 /*! BPFLCD42 6085 * 0b0..LCD segment off or LCD backplane inactive for phase F 6086 * 0b1..LCD segment on or LCD backplane active for phase F 6087 */ 6088 #define LCD_WF8B_BPFLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD42_SHIFT)) & LCD_WF8B_BPFLCD42_MASK) 6089 #define LCD_WF8B_BPFLCD43_MASK (0x20U) 6090 #define LCD_WF8B_BPFLCD43_SHIFT (5U) 6091 /*! BPFLCD43 6092 * 0b0..LCD segment off or LCD backplane inactive for phase F 6093 * 0b1..LCD segment on or LCD backplane active for phase F 6094 */ 6095 #define LCD_WF8B_BPFLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD43_SHIFT)) & LCD_WF8B_BPFLCD43_MASK) 6096 #define LCD_WF8B_BPFLCD44_MASK (0x20U) 6097 #define LCD_WF8B_BPFLCD44_SHIFT (5U) 6098 /*! BPFLCD44 6099 * 0b0..LCD segment off or LCD backplane inactive for phase F 6100 * 0b1..LCD segment on or LCD backplane active for phase F 6101 */ 6102 #define LCD_WF8B_BPFLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD44_SHIFT)) & LCD_WF8B_BPFLCD44_MASK) 6103 #define LCD_WF8B_BPFLCD45_MASK (0x20U) 6104 #define LCD_WF8B_BPFLCD45_SHIFT (5U) 6105 /*! BPFLCD45 6106 * 0b0..LCD segment off or LCD backplane inactive for phase F 6107 * 0b1..LCD segment on or LCD backplane active for phase F 6108 */ 6109 #define LCD_WF8B_BPFLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD45_SHIFT)) & LCD_WF8B_BPFLCD45_MASK) 6110 #define LCD_WF8B_BPFLCD46_MASK (0x20U) 6111 #define LCD_WF8B_BPFLCD46_SHIFT (5U) 6112 /*! BPFLCD46 6113 * 0b0..LCD segment off or LCD backplane inactive for phase F 6114 * 0b1..LCD segment on or LCD backplane active for phase F 6115 */ 6116 #define LCD_WF8B_BPFLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD46_SHIFT)) & LCD_WF8B_BPFLCD46_MASK) 6117 #define LCD_WF8B_BPFLCD47_MASK (0x20U) 6118 #define LCD_WF8B_BPFLCD47_SHIFT (5U) 6119 /*! BPFLCD47 6120 * 0b0..LCD segment off or LCD backplane inactive for phase F 6121 * 0b1..LCD segment on or LCD backplane active for phase F 6122 */ 6123 #define LCD_WF8B_BPFLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD47_SHIFT)) & LCD_WF8B_BPFLCD47_MASK) 6124 #define LCD_WF8B_BPFLCD48_MASK (0x20U) 6125 #define LCD_WF8B_BPFLCD48_SHIFT (5U) 6126 /*! BPFLCD48 6127 * 0b0..LCD segment off or LCD backplane inactive for phase F 6128 * 0b1..LCD segment on or LCD backplane active for phase F 6129 */ 6130 #define LCD_WF8B_BPFLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD48_SHIFT)) & LCD_WF8B_BPFLCD48_MASK) 6131 #define LCD_WF8B_BPFLCD49_MASK (0x20U) 6132 #define LCD_WF8B_BPFLCD49_SHIFT (5U) 6133 /*! BPFLCD49 6134 * 0b0..LCD segment off or LCD backplane inactive for phase F 6135 * 0b1..LCD segment on or LCD backplane active for phase F 6136 */ 6137 #define LCD_WF8B_BPFLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD49_SHIFT)) & LCD_WF8B_BPFLCD49_MASK) 6138 #define LCD_WF8B_BPFLCD50_MASK (0x20U) 6139 #define LCD_WF8B_BPFLCD50_SHIFT (5U) 6140 /*! BPFLCD50 6141 * 0b0..LCD segment off or LCD backplane inactive for phase F 6142 * 0b1..LCD segment on or LCD backplane active for phase F 6143 */ 6144 #define LCD_WF8B_BPFLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD50_SHIFT)) & LCD_WF8B_BPFLCD50_MASK) 6145 #define LCD_WF8B_BPFLCD51_MASK (0x20U) 6146 #define LCD_WF8B_BPFLCD51_SHIFT (5U) 6147 /*! BPFLCD51 6148 * 0b0..LCD segment off or LCD backplane inactive for phase F 6149 * 0b1..LCD segment on or LCD backplane active for phase F 6150 */ 6151 #define LCD_WF8B_BPFLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD51_SHIFT)) & LCD_WF8B_BPFLCD51_MASK) 6152 #define LCD_WF8B_BPFLCD52_MASK (0x20U) 6153 #define LCD_WF8B_BPFLCD52_SHIFT (5U) 6154 /*! BPFLCD52 6155 * 0b0..LCD segment off or LCD backplane inactive for phase F 6156 * 0b1..LCD segment on or LCD backplane active for phase F 6157 */ 6158 #define LCD_WF8B_BPFLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD52_SHIFT)) & LCD_WF8B_BPFLCD52_MASK) 6159 #define LCD_WF8B_BPFLCD53_MASK (0x20U) 6160 #define LCD_WF8B_BPFLCD53_SHIFT (5U) 6161 /*! BPFLCD53 6162 * 0b0..LCD segment off or LCD backplane inactive for phase F 6163 * 0b1..LCD segment on or LCD backplane active for phase F 6164 */ 6165 #define LCD_WF8B_BPFLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD53_SHIFT)) & LCD_WF8B_BPFLCD53_MASK) 6166 #define LCD_WF8B_BPFLCD54_MASK (0x20U) 6167 #define LCD_WF8B_BPFLCD54_SHIFT (5U) 6168 /*! BPFLCD54 6169 * 0b0..LCD segment off or LCD backplane inactive for phase F 6170 * 0b1..LCD segment on or LCD backplane active for phase F 6171 */ 6172 #define LCD_WF8B_BPFLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD54_SHIFT)) & LCD_WF8B_BPFLCD54_MASK) 6173 #define LCD_WF8B_BPFLCD55_MASK (0x20U) 6174 #define LCD_WF8B_BPFLCD55_SHIFT (5U) 6175 /*! BPFLCD55 6176 * 0b0..LCD segment off or LCD backplane inactive for phase F 6177 * 0b1..LCD segment on or LCD backplane active for phase F 6178 */ 6179 #define LCD_WF8B_BPFLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD55_SHIFT)) & LCD_WF8B_BPFLCD55_MASK) 6180 #define LCD_WF8B_BPFLCD56_MASK (0x20U) 6181 #define LCD_WF8B_BPFLCD56_SHIFT (5U) 6182 /*! BPFLCD56 6183 * 0b0..LCD segment off or LCD backplane inactive for phase F 6184 * 0b1..LCD segment on or LCD backplane active for phase F 6185 */ 6186 #define LCD_WF8B_BPFLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD56_SHIFT)) & LCD_WF8B_BPFLCD56_MASK) 6187 #define LCD_WF8B_BPFLCD57_MASK (0x20U) 6188 #define LCD_WF8B_BPFLCD57_SHIFT (5U) 6189 /*! BPFLCD57 6190 * 0b0..LCD segment off or LCD backplane inactive for phase F 6191 * 0b1..LCD segment on or LCD backplane active for phase F 6192 */ 6193 #define LCD_WF8B_BPFLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD57_SHIFT)) & LCD_WF8B_BPFLCD57_MASK) 6194 #define LCD_WF8B_BPFLCD58_MASK (0x20U) 6195 #define LCD_WF8B_BPFLCD58_SHIFT (5U) 6196 /*! BPFLCD58 6197 * 0b0..LCD segment off or LCD backplane inactive for phase F 6198 * 0b1..LCD segment on or LCD backplane active for phase F 6199 */ 6200 #define LCD_WF8B_BPFLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD58_SHIFT)) & LCD_WF8B_BPFLCD58_MASK) 6201 #define LCD_WF8B_BPFLCD59_MASK (0x20U) 6202 #define LCD_WF8B_BPFLCD59_SHIFT (5U) 6203 /*! BPFLCD59 6204 * 0b0..LCD segment off or LCD backplane inactive for phase F 6205 * 0b1..LCD segment on or LCD backplane active for phase F 6206 */ 6207 #define LCD_WF8B_BPFLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD59_SHIFT)) & LCD_WF8B_BPFLCD59_MASK) 6208 #define LCD_WF8B_BPFLCD60_MASK (0x20U) 6209 #define LCD_WF8B_BPFLCD60_SHIFT (5U) 6210 /*! BPFLCD60 6211 * 0b0..LCD segment off or LCD backplane inactive for phase F 6212 * 0b1..LCD segment on or LCD backplane active for phase F 6213 */ 6214 #define LCD_WF8B_BPFLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD60_SHIFT)) & LCD_WF8B_BPFLCD60_MASK) 6215 #define LCD_WF8B_BPFLCD61_MASK (0x20U) 6216 #define LCD_WF8B_BPFLCD61_SHIFT (5U) 6217 /*! BPFLCD61 6218 * 0b0..LCD segment off or LCD backplane inactive for phase F 6219 * 0b1..LCD segment on or LCD backplane active for phase F 6220 */ 6221 #define LCD_WF8B_BPFLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD61_SHIFT)) & LCD_WF8B_BPFLCD61_MASK) 6222 #define LCD_WF8B_BPFLCD62_MASK (0x20U) 6223 #define LCD_WF8B_BPFLCD62_SHIFT (5U) 6224 /*! BPFLCD62 6225 * 0b0..LCD segment off or LCD backplane inactive for phase F 6226 * 0b1..LCD segment on or LCD backplane active for phase F 6227 */ 6228 #define LCD_WF8B_BPFLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD62_SHIFT)) & LCD_WF8B_BPFLCD62_MASK) 6229 #define LCD_WF8B_BPFLCD63_MASK (0x20U) 6230 #define LCD_WF8B_BPFLCD63_SHIFT (5U) 6231 /*! BPFLCD63 6232 * 0b0..LCD segment off or LCD backplane inactive for phase F 6233 * 0b1..LCD segment on or LCD backplane active for phase F 6234 */ 6235 #define LCD_WF8B_BPFLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD63_SHIFT)) & LCD_WF8B_BPFLCD63_MASK) 6236 #define LCD_WF8B_BPGLCD0_MASK (0x40U) 6237 #define LCD_WF8B_BPGLCD0_SHIFT (6U) 6238 /*! BPGLCD0 6239 * 0b0..LCD segment off or LCD backplane inactive for phase G 6240 * 0b1..LCD segment on or LCD backplane active for phase G 6241 */ 6242 #define LCD_WF8B_BPGLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD0_SHIFT)) & LCD_WF8B_BPGLCD0_MASK) 6243 #define LCD_WF8B_BPGLCD1_MASK (0x40U) 6244 #define LCD_WF8B_BPGLCD1_SHIFT (6U) 6245 /*! BPGLCD1 6246 * 0b0..LCD segment off or LCD backplane inactive for phase G 6247 * 0b1..LCD segment on or LCD backplane active for phase G 6248 */ 6249 #define LCD_WF8B_BPGLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD1_SHIFT)) & LCD_WF8B_BPGLCD1_MASK) 6250 #define LCD_WF8B_BPGLCD2_MASK (0x40U) 6251 #define LCD_WF8B_BPGLCD2_SHIFT (6U) 6252 /*! BPGLCD2 6253 * 0b0..LCD segment off or LCD backplane inactive for phase G 6254 * 0b1..LCD segment on or LCD backplane active for phase G 6255 */ 6256 #define LCD_WF8B_BPGLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD2_SHIFT)) & LCD_WF8B_BPGLCD2_MASK) 6257 #define LCD_WF8B_BPGLCD3_MASK (0x40U) 6258 #define LCD_WF8B_BPGLCD3_SHIFT (6U) 6259 /*! BPGLCD3 6260 * 0b0..LCD segment off or LCD backplane inactive for phase G 6261 * 0b1..LCD segment on or LCD backplane active for phase G 6262 */ 6263 #define LCD_WF8B_BPGLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD3_SHIFT)) & LCD_WF8B_BPGLCD3_MASK) 6264 #define LCD_WF8B_BPGLCD4_MASK (0x40U) 6265 #define LCD_WF8B_BPGLCD4_SHIFT (6U) 6266 /*! BPGLCD4 6267 * 0b0..LCD segment off or LCD backplane inactive for phase G 6268 * 0b1..LCD segment on or LCD backplane active for phase G 6269 */ 6270 #define LCD_WF8B_BPGLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD4_SHIFT)) & LCD_WF8B_BPGLCD4_MASK) 6271 #define LCD_WF8B_BPGLCD5_MASK (0x40U) 6272 #define LCD_WF8B_BPGLCD5_SHIFT (6U) 6273 /*! BPGLCD5 6274 * 0b0..LCD segment off or LCD backplane inactive for phase G 6275 * 0b1..LCD segment on or LCD backplane active for phase G 6276 */ 6277 #define LCD_WF8B_BPGLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD5_SHIFT)) & LCD_WF8B_BPGLCD5_MASK) 6278 #define LCD_WF8B_BPGLCD6_MASK (0x40U) 6279 #define LCD_WF8B_BPGLCD6_SHIFT (6U) 6280 /*! BPGLCD6 6281 * 0b0..LCD segment off or LCD backplane inactive for phase G 6282 * 0b1..LCD segment on or LCD backplane active for phase G 6283 */ 6284 #define LCD_WF8B_BPGLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD6_SHIFT)) & LCD_WF8B_BPGLCD6_MASK) 6285 #define LCD_WF8B_BPGLCD7_MASK (0x40U) 6286 #define LCD_WF8B_BPGLCD7_SHIFT (6U) 6287 /*! BPGLCD7 6288 * 0b0..LCD segment off or LCD backplane inactive for phase G 6289 * 0b1..LCD segment on or LCD backplane active for phase G 6290 */ 6291 #define LCD_WF8B_BPGLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD7_SHIFT)) & LCD_WF8B_BPGLCD7_MASK) 6292 #define LCD_WF8B_BPGLCD8_MASK (0x40U) 6293 #define LCD_WF8B_BPGLCD8_SHIFT (6U) 6294 /*! BPGLCD8 6295 * 0b0..LCD segment off or LCD backplane inactive for phase G 6296 * 0b1..LCD segment on or LCD backplane active for phase G 6297 */ 6298 #define LCD_WF8B_BPGLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD8_SHIFT)) & LCD_WF8B_BPGLCD8_MASK) 6299 #define LCD_WF8B_BPGLCD9_MASK (0x40U) 6300 #define LCD_WF8B_BPGLCD9_SHIFT (6U) 6301 /*! BPGLCD9 6302 * 0b0..LCD segment off or LCD backplane inactive for phase G 6303 * 0b1..LCD segment on or LCD backplane active for phase G 6304 */ 6305 #define LCD_WF8B_BPGLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD9_SHIFT)) & LCD_WF8B_BPGLCD9_MASK) 6306 #define LCD_WF8B_BPGLCD10_MASK (0x40U) 6307 #define LCD_WF8B_BPGLCD10_SHIFT (6U) 6308 /*! BPGLCD10 6309 * 0b0..LCD segment off or LCD backplane inactive for phase G 6310 * 0b1..LCD segment on or LCD backplane active for phase G 6311 */ 6312 #define LCD_WF8B_BPGLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD10_SHIFT)) & LCD_WF8B_BPGLCD10_MASK) 6313 #define LCD_WF8B_BPGLCD11_MASK (0x40U) 6314 #define LCD_WF8B_BPGLCD11_SHIFT (6U) 6315 /*! BPGLCD11 6316 * 0b0..LCD segment off or LCD backplane inactive for phase G 6317 * 0b1..LCD segment on or LCD backplane active for phase G 6318 */ 6319 #define LCD_WF8B_BPGLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD11_SHIFT)) & LCD_WF8B_BPGLCD11_MASK) 6320 #define LCD_WF8B_BPGLCD12_MASK (0x40U) 6321 #define LCD_WF8B_BPGLCD12_SHIFT (6U) 6322 /*! BPGLCD12 6323 * 0b0..LCD segment off or LCD backplane inactive for phase G 6324 * 0b1..LCD segment on or LCD backplane active for phase G 6325 */ 6326 #define LCD_WF8B_BPGLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD12_SHIFT)) & LCD_WF8B_BPGLCD12_MASK) 6327 #define LCD_WF8B_BPGLCD13_MASK (0x40U) 6328 #define LCD_WF8B_BPGLCD13_SHIFT (6U) 6329 /*! BPGLCD13 6330 * 0b0..LCD segment off or LCD backplane inactive for phase G 6331 * 0b1..LCD segment on or LCD backplane active for phase G 6332 */ 6333 #define LCD_WF8B_BPGLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD13_SHIFT)) & LCD_WF8B_BPGLCD13_MASK) 6334 #define LCD_WF8B_BPGLCD14_MASK (0x40U) 6335 #define LCD_WF8B_BPGLCD14_SHIFT (6U) 6336 /*! BPGLCD14 6337 * 0b0..LCD segment off or LCD backplane inactive for phase G 6338 * 0b1..LCD segment on or LCD backplane active for phase G 6339 */ 6340 #define LCD_WF8B_BPGLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD14_SHIFT)) & LCD_WF8B_BPGLCD14_MASK) 6341 #define LCD_WF8B_BPGLCD15_MASK (0x40U) 6342 #define LCD_WF8B_BPGLCD15_SHIFT (6U) 6343 /*! BPGLCD15 6344 * 0b0..LCD segment off or LCD backplane inactive for phase G 6345 * 0b1..LCD segment on or LCD backplane active for phase G 6346 */ 6347 #define LCD_WF8B_BPGLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD15_SHIFT)) & LCD_WF8B_BPGLCD15_MASK) 6348 #define LCD_WF8B_BPGLCD16_MASK (0x40U) 6349 #define LCD_WF8B_BPGLCD16_SHIFT (6U) 6350 /*! BPGLCD16 6351 * 0b0..LCD segment off or LCD backplane inactive for phase G 6352 * 0b1..LCD segment on or LCD backplane active for phase G 6353 */ 6354 #define LCD_WF8B_BPGLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD16_SHIFT)) & LCD_WF8B_BPGLCD16_MASK) 6355 #define LCD_WF8B_BPGLCD17_MASK (0x40U) 6356 #define LCD_WF8B_BPGLCD17_SHIFT (6U) 6357 /*! BPGLCD17 6358 * 0b0..LCD segment off or LCD backplane inactive for phase G 6359 * 0b1..LCD segment on or LCD backplane active for phase G 6360 */ 6361 #define LCD_WF8B_BPGLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD17_SHIFT)) & LCD_WF8B_BPGLCD17_MASK) 6362 #define LCD_WF8B_BPGLCD18_MASK (0x40U) 6363 #define LCD_WF8B_BPGLCD18_SHIFT (6U) 6364 /*! BPGLCD18 6365 * 0b0..LCD segment off or LCD backplane inactive for phase G 6366 * 0b1..LCD segment on or LCD backplane active for phase G 6367 */ 6368 #define LCD_WF8B_BPGLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD18_SHIFT)) & LCD_WF8B_BPGLCD18_MASK) 6369 #define LCD_WF8B_BPGLCD19_MASK (0x40U) 6370 #define LCD_WF8B_BPGLCD19_SHIFT (6U) 6371 /*! BPGLCD19 6372 * 0b0..LCD segment off or LCD backplane inactive for phase G 6373 * 0b1..LCD segment on or LCD backplane active for phase G 6374 */ 6375 #define LCD_WF8B_BPGLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD19_SHIFT)) & LCD_WF8B_BPGLCD19_MASK) 6376 #define LCD_WF8B_BPGLCD20_MASK (0x40U) 6377 #define LCD_WF8B_BPGLCD20_SHIFT (6U) 6378 /*! BPGLCD20 6379 * 0b0..LCD segment off or LCD backplane inactive for phase G 6380 * 0b1..LCD segment on or LCD backplane active for phase G 6381 */ 6382 #define LCD_WF8B_BPGLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD20_SHIFT)) & LCD_WF8B_BPGLCD20_MASK) 6383 #define LCD_WF8B_BPGLCD21_MASK (0x40U) 6384 #define LCD_WF8B_BPGLCD21_SHIFT (6U) 6385 /*! BPGLCD21 6386 * 0b0..LCD segment off or LCD backplane inactive for phase G 6387 * 0b1..LCD segment on or LCD backplane active for phase G 6388 */ 6389 #define LCD_WF8B_BPGLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD21_SHIFT)) & LCD_WF8B_BPGLCD21_MASK) 6390 #define LCD_WF8B_BPGLCD22_MASK (0x40U) 6391 #define LCD_WF8B_BPGLCD22_SHIFT (6U) 6392 /*! BPGLCD22 6393 * 0b0..LCD segment off or LCD backplane inactive for phase G 6394 * 0b1..LCD segment on or LCD backplane active for phase G 6395 */ 6396 #define LCD_WF8B_BPGLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD22_SHIFT)) & LCD_WF8B_BPGLCD22_MASK) 6397 #define LCD_WF8B_BPGLCD23_MASK (0x40U) 6398 #define LCD_WF8B_BPGLCD23_SHIFT (6U) 6399 /*! BPGLCD23 6400 * 0b0..LCD segment off or LCD backplane inactive for phase G 6401 * 0b1..LCD segment on or LCD backplane active for phase G 6402 */ 6403 #define LCD_WF8B_BPGLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD23_SHIFT)) & LCD_WF8B_BPGLCD23_MASK) 6404 #define LCD_WF8B_BPGLCD24_MASK (0x40U) 6405 #define LCD_WF8B_BPGLCD24_SHIFT (6U) 6406 /*! BPGLCD24 6407 * 0b0..LCD segment off or LCD backplane inactive for phase G 6408 * 0b1..LCD segment on or LCD backplane active for phase G 6409 */ 6410 #define LCD_WF8B_BPGLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD24_SHIFT)) & LCD_WF8B_BPGLCD24_MASK) 6411 #define LCD_WF8B_BPGLCD25_MASK (0x40U) 6412 #define LCD_WF8B_BPGLCD25_SHIFT (6U) 6413 /*! BPGLCD25 6414 * 0b0..LCD segment off or LCD backplane inactive for phase G 6415 * 0b1..LCD segment on or LCD backplane active for phase G 6416 */ 6417 #define LCD_WF8B_BPGLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD25_SHIFT)) & LCD_WF8B_BPGLCD25_MASK) 6418 #define LCD_WF8B_BPGLCD26_MASK (0x40U) 6419 #define LCD_WF8B_BPGLCD26_SHIFT (6U) 6420 /*! BPGLCD26 6421 * 0b0..LCD segment off or LCD backplane inactive for phase G 6422 * 0b1..LCD segment on or LCD backplane active for phase G 6423 */ 6424 #define LCD_WF8B_BPGLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD26_SHIFT)) & LCD_WF8B_BPGLCD26_MASK) 6425 #define LCD_WF8B_BPGLCD27_MASK (0x40U) 6426 #define LCD_WF8B_BPGLCD27_SHIFT (6U) 6427 /*! BPGLCD27 6428 * 0b0..LCD segment off or LCD backplane inactive for phase G 6429 * 0b1..LCD segment on or LCD backplane active for phase G 6430 */ 6431 #define LCD_WF8B_BPGLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD27_SHIFT)) & LCD_WF8B_BPGLCD27_MASK) 6432 #define LCD_WF8B_BPGLCD28_MASK (0x40U) 6433 #define LCD_WF8B_BPGLCD28_SHIFT (6U) 6434 /*! BPGLCD28 6435 * 0b0..LCD segment off or LCD backplane inactive for phase G 6436 * 0b1..LCD segment on or LCD backplane active for phase G 6437 */ 6438 #define LCD_WF8B_BPGLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD28_SHIFT)) & LCD_WF8B_BPGLCD28_MASK) 6439 #define LCD_WF8B_BPGLCD29_MASK (0x40U) 6440 #define LCD_WF8B_BPGLCD29_SHIFT (6U) 6441 /*! BPGLCD29 6442 * 0b0..LCD segment off or LCD backplane inactive for phase G 6443 * 0b1..LCD segment on or LCD backplane active for phase G 6444 */ 6445 #define LCD_WF8B_BPGLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD29_SHIFT)) & LCD_WF8B_BPGLCD29_MASK) 6446 #define LCD_WF8B_BPGLCD30_MASK (0x40U) 6447 #define LCD_WF8B_BPGLCD30_SHIFT (6U) 6448 /*! BPGLCD30 6449 * 0b0..LCD segment off or LCD backplane inactive for phase G 6450 * 0b1..LCD segment on or LCD backplane active for phase G 6451 */ 6452 #define LCD_WF8B_BPGLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD30_SHIFT)) & LCD_WF8B_BPGLCD30_MASK) 6453 #define LCD_WF8B_BPGLCD31_MASK (0x40U) 6454 #define LCD_WF8B_BPGLCD31_SHIFT (6U) 6455 /*! BPGLCD31 6456 * 0b0..LCD segment off or LCD backplane inactive for phase G 6457 * 0b1..LCD segment on or LCD backplane active for phase G 6458 */ 6459 #define LCD_WF8B_BPGLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD31_SHIFT)) & LCD_WF8B_BPGLCD31_MASK) 6460 #define LCD_WF8B_BPGLCD32_MASK (0x40U) 6461 #define LCD_WF8B_BPGLCD32_SHIFT (6U) 6462 /*! BPGLCD32 6463 * 0b0..LCD segment off or LCD backplane inactive for phase G 6464 * 0b1..LCD segment on or LCD backplane active for phase G 6465 */ 6466 #define LCD_WF8B_BPGLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD32_SHIFT)) & LCD_WF8B_BPGLCD32_MASK) 6467 #define LCD_WF8B_BPGLCD33_MASK (0x40U) 6468 #define LCD_WF8B_BPGLCD33_SHIFT (6U) 6469 /*! BPGLCD33 6470 * 0b0..LCD segment off or LCD backplane inactive for phase G 6471 * 0b1..LCD segment on or LCD backplane active for phase G 6472 */ 6473 #define LCD_WF8B_BPGLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD33_SHIFT)) & LCD_WF8B_BPGLCD33_MASK) 6474 #define LCD_WF8B_BPGLCD34_MASK (0x40U) 6475 #define LCD_WF8B_BPGLCD34_SHIFT (6U) 6476 /*! BPGLCD34 6477 * 0b0..LCD segment off or LCD backplane inactive for phase G 6478 * 0b1..LCD segment on or LCD backplane active for phase G 6479 */ 6480 #define LCD_WF8B_BPGLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD34_SHIFT)) & LCD_WF8B_BPGLCD34_MASK) 6481 #define LCD_WF8B_BPGLCD35_MASK (0x40U) 6482 #define LCD_WF8B_BPGLCD35_SHIFT (6U) 6483 /*! BPGLCD35 6484 * 0b0..LCD segment off or LCD backplane inactive for phase G 6485 * 0b1..LCD segment on or LCD backplane active for phase G 6486 */ 6487 #define LCD_WF8B_BPGLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD35_SHIFT)) & LCD_WF8B_BPGLCD35_MASK) 6488 #define LCD_WF8B_BPGLCD36_MASK (0x40U) 6489 #define LCD_WF8B_BPGLCD36_SHIFT (6U) 6490 /*! BPGLCD36 6491 * 0b0..LCD segment off or LCD backplane inactive for phase G 6492 * 0b1..LCD segment on or LCD backplane active for phase G 6493 */ 6494 #define LCD_WF8B_BPGLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD36_SHIFT)) & LCD_WF8B_BPGLCD36_MASK) 6495 #define LCD_WF8B_BPGLCD37_MASK (0x40U) 6496 #define LCD_WF8B_BPGLCD37_SHIFT (6U) 6497 /*! BPGLCD37 6498 * 0b0..LCD segment off or LCD backplane inactive for phase G 6499 * 0b1..LCD segment on or LCD backplane active for phase G 6500 */ 6501 #define LCD_WF8B_BPGLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD37_SHIFT)) & LCD_WF8B_BPGLCD37_MASK) 6502 #define LCD_WF8B_BPGLCD38_MASK (0x40U) 6503 #define LCD_WF8B_BPGLCD38_SHIFT (6U) 6504 /*! BPGLCD38 6505 * 0b0..LCD segment off or LCD backplane inactive for phase G 6506 * 0b1..LCD segment on or LCD backplane active for phase G 6507 */ 6508 #define LCD_WF8B_BPGLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD38_SHIFT)) & LCD_WF8B_BPGLCD38_MASK) 6509 #define LCD_WF8B_BPGLCD39_MASK (0x40U) 6510 #define LCD_WF8B_BPGLCD39_SHIFT (6U) 6511 /*! BPGLCD39 6512 * 0b0..LCD segment off or LCD backplane inactive for phase G 6513 * 0b1..LCD segment on or LCD backplane active for phase G 6514 */ 6515 #define LCD_WF8B_BPGLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD39_SHIFT)) & LCD_WF8B_BPGLCD39_MASK) 6516 #define LCD_WF8B_BPGLCD40_MASK (0x40U) 6517 #define LCD_WF8B_BPGLCD40_SHIFT (6U) 6518 /*! BPGLCD40 6519 * 0b0..LCD segment off or LCD backplane inactive for phase G 6520 * 0b1..LCD segment on or LCD backplane active for phase G 6521 */ 6522 #define LCD_WF8B_BPGLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD40_SHIFT)) & LCD_WF8B_BPGLCD40_MASK) 6523 #define LCD_WF8B_BPGLCD41_MASK (0x40U) 6524 #define LCD_WF8B_BPGLCD41_SHIFT (6U) 6525 /*! BPGLCD41 6526 * 0b0..LCD segment off or LCD backplane inactive for phase G 6527 * 0b1..LCD segment on or LCD backplane active for phase G 6528 */ 6529 #define LCD_WF8B_BPGLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD41_SHIFT)) & LCD_WF8B_BPGLCD41_MASK) 6530 #define LCD_WF8B_BPGLCD42_MASK (0x40U) 6531 #define LCD_WF8B_BPGLCD42_SHIFT (6U) 6532 /*! BPGLCD42 6533 * 0b0..LCD segment off or LCD backplane inactive for phase G 6534 * 0b1..LCD segment on or LCD backplane active for phase G 6535 */ 6536 #define LCD_WF8B_BPGLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD42_SHIFT)) & LCD_WF8B_BPGLCD42_MASK) 6537 #define LCD_WF8B_BPGLCD43_MASK (0x40U) 6538 #define LCD_WF8B_BPGLCD43_SHIFT (6U) 6539 /*! BPGLCD43 6540 * 0b0..LCD segment off or LCD backplane inactive for phase G 6541 * 0b1..LCD segment on or LCD backplane active for phase G 6542 */ 6543 #define LCD_WF8B_BPGLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD43_SHIFT)) & LCD_WF8B_BPGLCD43_MASK) 6544 #define LCD_WF8B_BPGLCD44_MASK (0x40U) 6545 #define LCD_WF8B_BPGLCD44_SHIFT (6U) 6546 /*! BPGLCD44 6547 * 0b0..LCD segment off or LCD backplane inactive for phase G 6548 * 0b1..LCD segment on or LCD backplane active for phase G 6549 */ 6550 #define LCD_WF8B_BPGLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD44_SHIFT)) & LCD_WF8B_BPGLCD44_MASK) 6551 #define LCD_WF8B_BPGLCD45_MASK (0x40U) 6552 #define LCD_WF8B_BPGLCD45_SHIFT (6U) 6553 /*! BPGLCD45 6554 * 0b0..LCD segment off or LCD backplane inactive for phase G 6555 * 0b1..LCD segment on or LCD backplane active for phase G 6556 */ 6557 #define LCD_WF8B_BPGLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD45_SHIFT)) & LCD_WF8B_BPGLCD45_MASK) 6558 #define LCD_WF8B_BPGLCD46_MASK (0x40U) 6559 #define LCD_WF8B_BPGLCD46_SHIFT (6U) 6560 /*! BPGLCD46 6561 * 0b0..LCD segment off or LCD backplane inactive for phase G 6562 * 0b1..LCD segment on or LCD backplane active for phase G 6563 */ 6564 #define LCD_WF8B_BPGLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD46_SHIFT)) & LCD_WF8B_BPGLCD46_MASK) 6565 #define LCD_WF8B_BPGLCD47_MASK (0x40U) 6566 #define LCD_WF8B_BPGLCD47_SHIFT (6U) 6567 /*! BPGLCD47 6568 * 0b0..LCD segment off or LCD backplane inactive for phase G 6569 * 0b1..LCD segment on or LCD backplane active for phase G 6570 */ 6571 #define LCD_WF8B_BPGLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD47_SHIFT)) & LCD_WF8B_BPGLCD47_MASK) 6572 #define LCD_WF8B_BPGLCD48_MASK (0x40U) 6573 #define LCD_WF8B_BPGLCD48_SHIFT (6U) 6574 /*! BPGLCD48 6575 * 0b0..LCD segment off or LCD backplane inactive for phase G 6576 * 0b1..LCD segment on or LCD backplane active for phase G 6577 */ 6578 #define LCD_WF8B_BPGLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD48_SHIFT)) & LCD_WF8B_BPGLCD48_MASK) 6579 #define LCD_WF8B_BPGLCD49_MASK (0x40U) 6580 #define LCD_WF8B_BPGLCD49_SHIFT (6U) 6581 /*! BPGLCD49 6582 * 0b0..LCD segment off or LCD backplane inactive for phase G 6583 * 0b1..LCD segment on or LCD backplane active for phase G 6584 */ 6585 #define LCD_WF8B_BPGLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD49_SHIFT)) & LCD_WF8B_BPGLCD49_MASK) 6586 #define LCD_WF8B_BPGLCD50_MASK (0x40U) 6587 #define LCD_WF8B_BPGLCD50_SHIFT (6U) 6588 /*! BPGLCD50 6589 * 0b0..LCD segment off or LCD backplane inactive for phase G 6590 * 0b1..LCD segment on or LCD backplane active for phase G 6591 */ 6592 #define LCD_WF8B_BPGLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD50_SHIFT)) & LCD_WF8B_BPGLCD50_MASK) 6593 #define LCD_WF8B_BPGLCD51_MASK (0x40U) 6594 #define LCD_WF8B_BPGLCD51_SHIFT (6U) 6595 /*! BPGLCD51 6596 * 0b0..LCD segment off or LCD backplane inactive for phase G 6597 * 0b1..LCD segment on or LCD backplane active for phase G 6598 */ 6599 #define LCD_WF8B_BPGLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD51_SHIFT)) & LCD_WF8B_BPGLCD51_MASK) 6600 #define LCD_WF8B_BPGLCD52_MASK (0x40U) 6601 #define LCD_WF8B_BPGLCD52_SHIFT (6U) 6602 /*! BPGLCD52 6603 * 0b0..LCD segment off or LCD backplane inactive for phase G 6604 * 0b1..LCD segment on or LCD backplane active for phase G 6605 */ 6606 #define LCD_WF8B_BPGLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD52_SHIFT)) & LCD_WF8B_BPGLCD52_MASK) 6607 #define LCD_WF8B_BPGLCD53_MASK (0x40U) 6608 #define LCD_WF8B_BPGLCD53_SHIFT (6U) 6609 /*! BPGLCD53 6610 * 0b0..LCD segment off or LCD backplane inactive for phase G 6611 * 0b1..LCD segment on or LCD backplane active for phase G 6612 */ 6613 #define LCD_WF8B_BPGLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD53_SHIFT)) & LCD_WF8B_BPGLCD53_MASK) 6614 #define LCD_WF8B_BPGLCD54_MASK (0x40U) 6615 #define LCD_WF8B_BPGLCD54_SHIFT (6U) 6616 /*! BPGLCD54 6617 * 0b0..LCD segment off or LCD backplane inactive for phase G 6618 * 0b1..LCD segment on or LCD backplane active for phase G 6619 */ 6620 #define LCD_WF8B_BPGLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD54_SHIFT)) & LCD_WF8B_BPGLCD54_MASK) 6621 #define LCD_WF8B_BPGLCD55_MASK (0x40U) 6622 #define LCD_WF8B_BPGLCD55_SHIFT (6U) 6623 /*! BPGLCD55 6624 * 0b0..LCD segment off or LCD backplane inactive for phase G 6625 * 0b1..LCD segment on or LCD backplane active for phase G 6626 */ 6627 #define LCD_WF8B_BPGLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD55_SHIFT)) & LCD_WF8B_BPGLCD55_MASK) 6628 #define LCD_WF8B_BPGLCD56_MASK (0x40U) 6629 #define LCD_WF8B_BPGLCD56_SHIFT (6U) 6630 /*! BPGLCD56 6631 * 0b0..LCD segment off or LCD backplane inactive for phase G 6632 * 0b1..LCD segment on or LCD backplane active for phase G 6633 */ 6634 #define LCD_WF8B_BPGLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD56_SHIFT)) & LCD_WF8B_BPGLCD56_MASK) 6635 #define LCD_WF8B_BPGLCD57_MASK (0x40U) 6636 #define LCD_WF8B_BPGLCD57_SHIFT (6U) 6637 /*! BPGLCD57 6638 * 0b0..LCD segment off or LCD backplane inactive for phase G 6639 * 0b1..LCD segment on or LCD backplane active for phase G 6640 */ 6641 #define LCD_WF8B_BPGLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD57_SHIFT)) & LCD_WF8B_BPGLCD57_MASK) 6642 #define LCD_WF8B_BPGLCD58_MASK (0x40U) 6643 #define LCD_WF8B_BPGLCD58_SHIFT (6U) 6644 /*! BPGLCD58 6645 * 0b0..LCD segment off or LCD backplane inactive for phase G 6646 * 0b1..LCD segment on or LCD backplane active for phase G 6647 */ 6648 #define LCD_WF8B_BPGLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD58_SHIFT)) & LCD_WF8B_BPGLCD58_MASK) 6649 #define LCD_WF8B_BPGLCD59_MASK (0x40U) 6650 #define LCD_WF8B_BPGLCD59_SHIFT (6U) 6651 /*! BPGLCD59 6652 * 0b0..LCD segment off or LCD backplane inactive for phase G 6653 * 0b1..LCD segment on or LCD backplane active for phase G 6654 */ 6655 #define LCD_WF8B_BPGLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD59_SHIFT)) & LCD_WF8B_BPGLCD59_MASK) 6656 #define LCD_WF8B_BPGLCD60_MASK (0x40U) 6657 #define LCD_WF8B_BPGLCD60_SHIFT (6U) 6658 /*! BPGLCD60 6659 * 0b0..LCD segment off or LCD backplane inactive for phase G 6660 * 0b1..LCD segment on or LCD backplane active for phase G 6661 */ 6662 #define LCD_WF8B_BPGLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD60_SHIFT)) & LCD_WF8B_BPGLCD60_MASK) 6663 #define LCD_WF8B_BPGLCD61_MASK (0x40U) 6664 #define LCD_WF8B_BPGLCD61_SHIFT (6U) 6665 /*! BPGLCD61 6666 * 0b0..LCD segment off or LCD backplane inactive for phase G 6667 * 0b1..LCD segment on or LCD backplane active for phase G 6668 */ 6669 #define LCD_WF8B_BPGLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD61_SHIFT)) & LCD_WF8B_BPGLCD61_MASK) 6670 #define LCD_WF8B_BPGLCD62_MASK (0x40U) 6671 #define LCD_WF8B_BPGLCD62_SHIFT (6U) 6672 /*! BPGLCD62 6673 * 0b0..LCD segment off or LCD backplane inactive for phase G 6674 * 0b1..LCD segment on or LCD backplane active for phase G 6675 */ 6676 #define LCD_WF8B_BPGLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD62_SHIFT)) & LCD_WF8B_BPGLCD62_MASK) 6677 #define LCD_WF8B_BPGLCD63_MASK (0x40U) 6678 #define LCD_WF8B_BPGLCD63_SHIFT (6U) 6679 /*! BPGLCD63 6680 * 0b0..LCD segment off or LCD backplane inactive for phase G 6681 * 0b1..LCD segment on or LCD backplane active for phase G 6682 */ 6683 #define LCD_WF8B_BPGLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD63_SHIFT)) & LCD_WF8B_BPGLCD63_MASK) 6684 #define LCD_WF8B_BPHLCD0_MASK (0x80U) 6685 #define LCD_WF8B_BPHLCD0_SHIFT (7U) 6686 /*! BPHLCD0 6687 * 0b0..LCD segment off or LCD backplane inactive for phase H 6688 * 0b1..LCD segment on or LCD backplane active for phase H 6689 */ 6690 #define LCD_WF8B_BPHLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD0_SHIFT)) & LCD_WF8B_BPHLCD0_MASK) 6691 #define LCD_WF8B_BPHLCD1_MASK (0x80U) 6692 #define LCD_WF8B_BPHLCD1_SHIFT (7U) 6693 /*! BPHLCD1 6694 * 0b0..LCD segment off or LCD backplane inactive for phase H 6695 * 0b1..LCD segment on or LCD backplane active for phase H 6696 */ 6697 #define LCD_WF8B_BPHLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD1_SHIFT)) & LCD_WF8B_BPHLCD1_MASK) 6698 #define LCD_WF8B_BPHLCD2_MASK (0x80U) 6699 #define LCD_WF8B_BPHLCD2_SHIFT (7U) 6700 /*! BPHLCD2 6701 * 0b0..LCD segment off or LCD backplane inactive for phase H 6702 * 0b1..LCD segment on or LCD backplane active for phase H 6703 */ 6704 #define LCD_WF8B_BPHLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD2_SHIFT)) & LCD_WF8B_BPHLCD2_MASK) 6705 #define LCD_WF8B_BPHLCD3_MASK (0x80U) 6706 #define LCD_WF8B_BPHLCD3_SHIFT (7U) 6707 /*! BPHLCD3 6708 * 0b0..LCD segment off or LCD backplane inactive for phase H 6709 * 0b1..LCD segment on or LCD backplane active for phase H 6710 */ 6711 #define LCD_WF8B_BPHLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD3_SHIFT)) & LCD_WF8B_BPHLCD3_MASK) 6712 #define LCD_WF8B_BPHLCD4_MASK (0x80U) 6713 #define LCD_WF8B_BPHLCD4_SHIFT (7U) 6714 /*! BPHLCD4 6715 * 0b0..LCD segment off or LCD backplane inactive for phase H 6716 * 0b1..LCD segment on or LCD backplane active for phase H 6717 */ 6718 #define LCD_WF8B_BPHLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD4_SHIFT)) & LCD_WF8B_BPHLCD4_MASK) 6719 #define LCD_WF8B_BPHLCD5_MASK (0x80U) 6720 #define LCD_WF8B_BPHLCD5_SHIFT (7U) 6721 /*! BPHLCD5 6722 * 0b0..LCD segment off or LCD backplane inactive for phase H 6723 * 0b1..LCD segment on or LCD backplane active for phase H 6724 */ 6725 #define LCD_WF8B_BPHLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD5_SHIFT)) & LCD_WF8B_BPHLCD5_MASK) 6726 #define LCD_WF8B_BPHLCD6_MASK (0x80U) 6727 #define LCD_WF8B_BPHLCD6_SHIFT (7U) 6728 /*! BPHLCD6 6729 * 0b0..LCD segment off or LCD backplane inactive for phase H 6730 * 0b1..LCD segment on or LCD backplane active for phase H 6731 */ 6732 #define LCD_WF8B_BPHLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD6_SHIFT)) & LCD_WF8B_BPHLCD6_MASK) 6733 #define LCD_WF8B_BPHLCD7_MASK (0x80U) 6734 #define LCD_WF8B_BPHLCD7_SHIFT (7U) 6735 /*! BPHLCD7 6736 * 0b0..LCD segment off or LCD backplane inactive for phase H 6737 * 0b1..LCD segment on or LCD backplane active for phase H 6738 */ 6739 #define LCD_WF8B_BPHLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD7_SHIFT)) & LCD_WF8B_BPHLCD7_MASK) 6740 #define LCD_WF8B_BPHLCD8_MASK (0x80U) 6741 #define LCD_WF8B_BPHLCD8_SHIFT (7U) 6742 /*! BPHLCD8 6743 * 0b0..LCD segment off or LCD backplane inactive for phase H 6744 * 0b1..LCD segment on or LCD backplane active for phase H 6745 */ 6746 #define LCD_WF8B_BPHLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD8_SHIFT)) & LCD_WF8B_BPHLCD8_MASK) 6747 #define LCD_WF8B_BPHLCD9_MASK (0x80U) 6748 #define LCD_WF8B_BPHLCD9_SHIFT (7U) 6749 /*! BPHLCD9 6750 * 0b0..LCD segment off or LCD backplane inactive for phase H 6751 * 0b1..LCD segment on or LCD backplane active for phase H 6752 */ 6753 #define LCD_WF8B_BPHLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD9_SHIFT)) & LCD_WF8B_BPHLCD9_MASK) 6754 #define LCD_WF8B_BPHLCD10_MASK (0x80U) 6755 #define LCD_WF8B_BPHLCD10_SHIFT (7U) 6756 /*! BPHLCD10 6757 * 0b0..LCD segment off or LCD backplane inactive for phase H 6758 * 0b1..LCD segment on or LCD backplane active for phase H 6759 */ 6760 #define LCD_WF8B_BPHLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD10_SHIFT)) & LCD_WF8B_BPHLCD10_MASK) 6761 #define LCD_WF8B_BPHLCD11_MASK (0x80U) 6762 #define LCD_WF8B_BPHLCD11_SHIFT (7U) 6763 /*! BPHLCD11 6764 * 0b0..LCD segment off or LCD backplane inactive for phase H 6765 * 0b1..LCD segment on or LCD backplane active for phase H 6766 */ 6767 #define LCD_WF8B_BPHLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD11_SHIFT)) & LCD_WF8B_BPHLCD11_MASK) 6768 #define LCD_WF8B_BPHLCD12_MASK (0x80U) 6769 #define LCD_WF8B_BPHLCD12_SHIFT (7U) 6770 /*! BPHLCD12 6771 * 0b0..LCD segment off or LCD backplane inactive for phase H 6772 * 0b1..LCD segment on or LCD backplane active for phase H 6773 */ 6774 #define LCD_WF8B_BPHLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD12_SHIFT)) & LCD_WF8B_BPHLCD12_MASK) 6775 #define LCD_WF8B_BPHLCD13_MASK (0x80U) 6776 #define LCD_WF8B_BPHLCD13_SHIFT (7U) 6777 /*! BPHLCD13 6778 * 0b0..LCD segment off or LCD backplane inactive for phase H 6779 * 0b1..LCD segment on or LCD backplane active for phase H 6780 */ 6781 #define LCD_WF8B_BPHLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD13_SHIFT)) & LCD_WF8B_BPHLCD13_MASK) 6782 #define LCD_WF8B_BPHLCD14_MASK (0x80U) 6783 #define LCD_WF8B_BPHLCD14_SHIFT (7U) 6784 /*! BPHLCD14 6785 * 0b0..LCD segment off or LCD backplane inactive for phase H 6786 * 0b1..LCD segment on or LCD backplane active for phase H 6787 */ 6788 #define LCD_WF8B_BPHLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD14_SHIFT)) & LCD_WF8B_BPHLCD14_MASK) 6789 #define LCD_WF8B_BPHLCD15_MASK (0x80U) 6790 #define LCD_WF8B_BPHLCD15_SHIFT (7U) 6791 /*! BPHLCD15 6792 * 0b0..LCD segment off or LCD backplane inactive for phase H 6793 * 0b1..LCD segment on or LCD backplane active for phase H 6794 */ 6795 #define LCD_WF8B_BPHLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD15_SHIFT)) & LCD_WF8B_BPHLCD15_MASK) 6796 #define LCD_WF8B_BPHLCD16_MASK (0x80U) 6797 #define LCD_WF8B_BPHLCD16_SHIFT (7U) 6798 /*! BPHLCD16 6799 * 0b0..LCD segment off or LCD backplane inactive for phase H 6800 * 0b1..LCD segment on or LCD backplane active for phase H 6801 */ 6802 #define LCD_WF8B_BPHLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD16_SHIFT)) & LCD_WF8B_BPHLCD16_MASK) 6803 #define LCD_WF8B_BPHLCD17_MASK (0x80U) 6804 #define LCD_WF8B_BPHLCD17_SHIFT (7U) 6805 /*! BPHLCD17 6806 * 0b0..LCD segment off or LCD backplane inactive for phase H 6807 * 0b1..LCD segment on or LCD backplane active for phase H 6808 */ 6809 #define LCD_WF8B_BPHLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD17_SHIFT)) & LCD_WF8B_BPHLCD17_MASK) 6810 #define LCD_WF8B_BPHLCD18_MASK (0x80U) 6811 #define LCD_WF8B_BPHLCD18_SHIFT (7U) 6812 /*! BPHLCD18 6813 * 0b0..LCD segment off or LCD backplane inactive for phase H 6814 * 0b1..LCD segment on or LCD backplane active for phase H 6815 */ 6816 #define LCD_WF8B_BPHLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD18_SHIFT)) & LCD_WF8B_BPHLCD18_MASK) 6817 #define LCD_WF8B_BPHLCD19_MASK (0x80U) 6818 #define LCD_WF8B_BPHLCD19_SHIFT (7U) 6819 /*! BPHLCD19 6820 * 0b0..LCD segment off or LCD backplane inactive for phase H 6821 * 0b1..LCD segment on or LCD backplane active for phase H 6822 */ 6823 #define LCD_WF8B_BPHLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD19_SHIFT)) & LCD_WF8B_BPHLCD19_MASK) 6824 #define LCD_WF8B_BPHLCD20_MASK (0x80U) 6825 #define LCD_WF8B_BPHLCD20_SHIFT (7U) 6826 /*! BPHLCD20 6827 * 0b0..LCD segment off or LCD backplane inactive for phase H 6828 * 0b1..LCD segment on or LCD backplane active for phase H 6829 */ 6830 #define LCD_WF8B_BPHLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD20_SHIFT)) & LCD_WF8B_BPHLCD20_MASK) 6831 #define LCD_WF8B_BPHLCD21_MASK (0x80U) 6832 #define LCD_WF8B_BPHLCD21_SHIFT (7U) 6833 /*! BPHLCD21 6834 * 0b0..LCD segment off or LCD backplane inactive for phase H 6835 * 0b1..LCD segment on or LCD backplane active for phase H 6836 */ 6837 #define LCD_WF8B_BPHLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD21_SHIFT)) & LCD_WF8B_BPHLCD21_MASK) 6838 #define LCD_WF8B_BPHLCD22_MASK (0x80U) 6839 #define LCD_WF8B_BPHLCD22_SHIFT (7U) 6840 /*! BPHLCD22 6841 * 0b0..LCD segment off or LCD backplane inactive for phase H 6842 * 0b1..LCD segment on or LCD backplane active for phase H 6843 */ 6844 #define LCD_WF8B_BPHLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD22_SHIFT)) & LCD_WF8B_BPHLCD22_MASK) 6845 #define LCD_WF8B_BPHLCD23_MASK (0x80U) 6846 #define LCD_WF8B_BPHLCD23_SHIFT (7U) 6847 /*! BPHLCD23 6848 * 0b0..LCD segment off or LCD backplane inactive for phase H 6849 * 0b1..LCD segment on or LCD backplane active for phase H 6850 */ 6851 #define LCD_WF8B_BPHLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD23_SHIFT)) & LCD_WF8B_BPHLCD23_MASK) 6852 #define LCD_WF8B_BPHLCD24_MASK (0x80U) 6853 #define LCD_WF8B_BPHLCD24_SHIFT (7U) 6854 /*! BPHLCD24 6855 * 0b0..LCD segment off or LCD backplane inactive for phase H 6856 * 0b1..LCD segment on or LCD backplane active for phase H 6857 */ 6858 #define LCD_WF8B_BPHLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD24_SHIFT)) & LCD_WF8B_BPHLCD24_MASK) 6859 #define LCD_WF8B_BPHLCD25_MASK (0x80U) 6860 #define LCD_WF8B_BPHLCD25_SHIFT (7U) 6861 /*! BPHLCD25 6862 * 0b0..LCD segment off or LCD backplane inactive for phase H 6863 * 0b1..LCD segment on or LCD backplane active for phase H 6864 */ 6865 #define LCD_WF8B_BPHLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD25_SHIFT)) & LCD_WF8B_BPHLCD25_MASK) 6866 #define LCD_WF8B_BPHLCD26_MASK (0x80U) 6867 #define LCD_WF8B_BPHLCD26_SHIFT (7U) 6868 /*! BPHLCD26 6869 * 0b0..LCD segment off or LCD backplane inactive for phase H 6870 * 0b1..LCD segment on or LCD backplane active for phase H 6871 */ 6872 #define LCD_WF8B_BPHLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD26_SHIFT)) & LCD_WF8B_BPHLCD26_MASK) 6873 #define LCD_WF8B_BPHLCD27_MASK (0x80U) 6874 #define LCD_WF8B_BPHLCD27_SHIFT (7U) 6875 /*! BPHLCD27 6876 * 0b0..LCD segment off or LCD backplane inactive for phase H 6877 * 0b1..LCD segment on or LCD backplane active for phase H 6878 */ 6879 #define LCD_WF8B_BPHLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD27_SHIFT)) & LCD_WF8B_BPHLCD27_MASK) 6880 #define LCD_WF8B_BPHLCD28_MASK (0x80U) 6881 #define LCD_WF8B_BPHLCD28_SHIFT (7U) 6882 /*! BPHLCD28 6883 * 0b0..LCD segment off or LCD backplane inactive for phase H 6884 * 0b1..LCD segment on or LCD backplane active for phase H 6885 */ 6886 #define LCD_WF8B_BPHLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD28_SHIFT)) & LCD_WF8B_BPHLCD28_MASK) 6887 #define LCD_WF8B_BPHLCD29_MASK (0x80U) 6888 #define LCD_WF8B_BPHLCD29_SHIFT (7U) 6889 /*! BPHLCD29 6890 * 0b0..LCD segment off or LCD backplane inactive for phase H 6891 * 0b1..LCD segment on or LCD backplane active for phase H 6892 */ 6893 #define LCD_WF8B_BPHLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD29_SHIFT)) & LCD_WF8B_BPHLCD29_MASK) 6894 #define LCD_WF8B_BPHLCD30_MASK (0x80U) 6895 #define LCD_WF8B_BPHLCD30_SHIFT (7U) 6896 /*! BPHLCD30 6897 * 0b0..LCD segment off or LCD backplane inactive for phase H 6898 * 0b1..LCD segment on or LCD backplane active for phase H 6899 */ 6900 #define LCD_WF8B_BPHLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD30_SHIFT)) & LCD_WF8B_BPHLCD30_MASK) 6901 #define LCD_WF8B_BPHLCD31_MASK (0x80U) 6902 #define LCD_WF8B_BPHLCD31_SHIFT (7U) 6903 /*! BPHLCD31 6904 * 0b0..LCD segment off or LCD backplane inactive for phase H 6905 * 0b1..LCD segment on or LCD backplane active for phase H 6906 */ 6907 #define LCD_WF8B_BPHLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD31_SHIFT)) & LCD_WF8B_BPHLCD31_MASK) 6908 #define LCD_WF8B_BPHLCD32_MASK (0x80U) 6909 #define LCD_WF8B_BPHLCD32_SHIFT (7U) 6910 /*! BPHLCD32 6911 * 0b0..LCD segment off or LCD backplane inactive for phase H 6912 * 0b1..LCD segment on or LCD backplane active for phase H 6913 */ 6914 #define LCD_WF8B_BPHLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD32_SHIFT)) & LCD_WF8B_BPHLCD32_MASK) 6915 #define LCD_WF8B_BPHLCD33_MASK (0x80U) 6916 #define LCD_WF8B_BPHLCD33_SHIFT (7U) 6917 /*! BPHLCD33 6918 * 0b0..LCD segment off or LCD backplane inactive for phase H 6919 * 0b1..LCD segment on or LCD backplane active for phase H 6920 */ 6921 #define LCD_WF8B_BPHLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD33_SHIFT)) & LCD_WF8B_BPHLCD33_MASK) 6922 #define LCD_WF8B_BPHLCD34_MASK (0x80U) 6923 #define LCD_WF8B_BPHLCD34_SHIFT (7U) 6924 /*! BPHLCD34 6925 * 0b0..LCD segment off or LCD backplane inactive for phase H 6926 * 0b1..LCD segment on or LCD backplane active for phase H 6927 */ 6928 #define LCD_WF8B_BPHLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD34_SHIFT)) & LCD_WF8B_BPHLCD34_MASK) 6929 #define LCD_WF8B_BPHLCD35_MASK (0x80U) 6930 #define LCD_WF8B_BPHLCD35_SHIFT (7U) 6931 /*! BPHLCD35 6932 * 0b0..LCD segment off or LCD backplane inactive for phase H 6933 * 0b1..LCD segment on or LCD backplane active for phase H 6934 */ 6935 #define LCD_WF8B_BPHLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD35_SHIFT)) & LCD_WF8B_BPHLCD35_MASK) 6936 #define LCD_WF8B_BPHLCD36_MASK (0x80U) 6937 #define LCD_WF8B_BPHLCD36_SHIFT (7U) 6938 /*! BPHLCD36 6939 * 0b0..LCD segment off or LCD backplane inactive for phase H 6940 * 0b1..LCD segment on or LCD backplane active for phase H 6941 */ 6942 #define LCD_WF8B_BPHLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD36_SHIFT)) & LCD_WF8B_BPHLCD36_MASK) 6943 #define LCD_WF8B_BPHLCD37_MASK (0x80U) 6944 #define LCD_WF8B_BPHLCD37_SHIFT (7U) 6945 /*! BPHLCD37 6946 * 0b0..LCD segment off or LCD backplane inactive for phase H 6947 * 0b1..LCD segment on or LCD backplane active for phase H 6948 */ 6949 #define LCD_WF8B_BPHLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD37_SHIFT)) & LCD_WF8B_BPHLCD37_MASK) 6950 #define LCD_WF8B_BPHLCD38_MASK (0x80U) 6951 #define LCD_WF8B_BPHLCD38_SHIFT (7U) 6952 /*! BPHLCD38 6953 * 0b0..LCD segment off or LCD backplane inactive for phase H 6954 * 0b1..LCD segment on or LCD backplane active for phase H 6955 */ 6956 #define LCD_WF8B_BPHLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD38_SHIFT)) & LCD_WF8B_BPHLCD38_MASK) 6957 #define LCD_WF8B_BPHLCD39_MASK (0x80U) 6958 #define LCD_WF8B_BPHLCD39_SHIFT (7U) 6959 /*! BPHLCD39 6960 * 0b0..LCD segment off or LCD backplane inactive for phase H 6961 * 0b1..LCD segment on or LCD backplane active for phase H 6962 */ 6963 #define LCD_WF8B_BPHLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD39_SHIFT)) & LCD_WF8B_BPHLCD39_MASK) 6964 #define LCD_WF8B_BPHLCD40_MASK (0x80U) 6965 #define LCD_WF8B_BPHLCD40_SHIFT (7U) 6966 /*! BPHLCD40 6967 * 0b0..LCD segment off or LCD backplane inactive for phase H 6968 * 0b1..LCD segment on or LCD backplane active for phase H 6969 */ 6970 #define LCD_WF8B_BPHLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD40_SHIFT)) & LCD_WF8B_BPHLCD40_MASK) 6971 #define LCD_WF8B_BPHLCD41_MASK (0x80U) 6972 #define LCD_WF8B_BPHLCD41_SHIFT (7U) 6973 /*! BPHLCD41 6974 * 0b0..LCD segment off or LCD backplane inactive for phase H 6975 * 0b1..LCD segment on or LCD backplane active for phase H 6976 */ 6977 #define LCD_WF8B_BPHLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD41_SHIFT)) & LCD_WF8B_BPHLCD41_MASK) 6978 #define LCD_WF8B_BPHLCD42_MASK (0x80U) 6979 #define LCD_WF8B_BPHLCD42_SHIFT (7U) 6980 /*! BPHLCD42 6981 * 0b0..LCD segment off or LCD backplane inactive for phase H 6982 * 0b1..LCD segment on or LCD backplane active for phase H 6983 */ 6984 #define LCD_WF8B_BPHLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD42_SHIFT)) & LCD_WF8B_BPHLCD42_MASK) 6985 #define LCD_WF8B_BPHLCD43_MASK (0x80U) 6986 #define LCD_WF8B_BPHLCD43_SHIFT (7U) 6987 /*! BPHLCD43 6988 * 0b0..LCD segment off or LCD backplane inactive for phase H 6989 * 0b1..LCD segment on or LCD backplane active for phase H 6990 */ 6991 #define LCD_WF8B_BPHLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD43_SHIFT)) & LCD_WF8B_BPHLCD43_MASK) 6992 #define LCD_WF8B_BPHLCD44_MASK (0x80U) 6993 #define LCD_WF8B_BPHLCD44_SHIFT (7U) 6994 /*! BPHLCD44 6995 * 0b0..LCD segment off or LCD backplane inactive for phase H 6996 * 0b1..LCD segment on or LCD backplane active for phase H 6997 */ 6998 #define LCD_WF8B_BPHLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD44_SHIFT)) & LCD_WF8B_BPHLCD44_MASK) 6999 #define LCD_WF8B_BPHLCD45_MASK (0x80U) 7000 #define LCD_WF8B_BPHLCD45_SHIFT (7U) 7001 /*! BPHLCD45 7002 * 0b0..LCD segment off or LCD backplane inactive for phase H 7003 * 0b1..LCD segment on or LCD backplane active for phase H 7004 */ 7005 #define LCD_WF8B_BPHLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD45_SHIFT)) & LCD_WF8B_BPHLCD45_MASK) 7006 #define LCD_WF8B_BPHLCD46_MASK (0x80U) 7007 #define LCD_WF8B_BPHLCD46_SHIFT (7U) 7008 /*! BPHLCD46 7009 * 0b0..LCD segment off or LCD backplane inactive for phase H 7010 * 0b1..LCD segment on or LCD backplane active for phase H 7011 */ 7012 #define LCD_WF8B_BPHLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD46_SHIFT)) & LCD_WF8B_BPHLCD46_MASK) 7013 #define LCD_WF8B_BPHLCD47_MASK (0x80U) 7014 #define LCD_WF8B_BPHLCD47_SHIFT (7U) 7015 /*! BPHLCD47 7016 * 0b0..LCD segment off or LCD backplane inactive for phase H 7017 * 0b1..LCD segment on or LCD backplane active for phase H 7018 */ 7019 #define LCD_WF8B_BPHLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD47_SHIFT)) & LCD_WF8B_BPHLCD47_MASK) 7020 #define LCD_WF8B_BPHLCD48_MASK (0x80U) 7021 #define LCD_WF8B_BPHLCD48_SHIFT (7U) 7022 /*! BPHLCD48 7023 * 0b0..LCD segment off or LCD backplane inactive for phase H 7024 * 0b1..LCD segment on or LCD backplane active for phase H 7025 */ 7026 #define LCD_WF8B_BPHLCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD48_SHIFT)) & LCD_WF8B_BPHLCD48_MASK) 7027 #define LCD_WF8B_BPHLCD49_MASK (0x80U) 7028 #define LCD_WF8B_BPHLCD49_SHIFT (7U) 7029 /*! BPHLCD49 7030 * 0b0..LCD segment off or LCD backplane inactive for phase H 7031 * 0b1..LCD segment on or LCD backplane active for phase H 7032 */ 7033 #define LCD_WF8B_BPHLCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD49_SHIFT)) & LCD_WF8B_BPHLCD49_MASK) 7034 #define LCD_WF8B_BPHLCD50_MASK (0x80U) 7035 #define LCD_WF8B_BPHLCD50_SHIFT (7U) 7036 /*! BPHLCD50 7037 * 0b0..LCD segment off or LCD backplane inactive for phase H 7038 * 0b1..LCD segment on or LCD backplane active for phase H 7039 */ 7040 #define LCD_WF8B_BPHLCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD50_SHIFT)) & LCD_WF8B_BPHLCD50_MASK) 7041 #define LCD_WF8B_BPHLCD51_MASK (0x80U) 7042 #define LCD_WF8B_BPHLCD51_SHIFT (7U) 7043 /*! BPHLCD51 7044 * 0b0..LCD segment off or LCD backplane inactive for phase H 7045 * 0b1..LCD segment on or LCD backplane active for phase H 7046 */ 7047 #define LCD_WF8B_BPHLCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD51_SHIFT)) & LCD_WF8B_BPHLCD51_MASK) 7048 #define LCD_WF8B_BPHLCD52_MASK (0x80U) 7049 #define LCD_WF8B_BPHLCD52_SHIFT (7U) 7050 /*! BPHLCD52 7051 * 0b0..LCD segment off or LCD backplane inactive for phase H 7052 * 0b1..LCD segment on or LCD backplane active for phase H 7053 */ 7054 #define LCD_WF8B_BPHLCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD52_SHIFT)) & LCD_WF8B_BPHLCD52_MASK) 7055 #define LCD_WF8B_BPHLCD53_MASK (0x80U) 7056 #define LCD_WF8B_BPHLCD53_SHIFT (7U) 7057 /*! BPHLCD53 7058 * 0b0..LCD segment off or LCD backplane inactive for phase H 7059 * 0b1..LCD segment on or LCD backplane active for phase H 7060 */ 7061 #define LCD_WF8B_BPHLCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD53_SHIFT)) & LCD_WF8B_BPHLCD53_MASK) 7062 #define LCD_WF8B_BPHLCD54_MASK (0x80U) 7063 #define LCD_WF8B_BPHLCD54_SHIFT (7U) 7064 /*! BPHLCD54 7065 * 0b0..LCD segment off or LCD backplane inactive for phase H 7066 * 0b1..LCD segment on or LCD backplane active for phase H 7067 */ 7068 #define LCD_WF8B_BPHLCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD54_SHIFT)) & LCD_WF8B_BPHLCD54_MASK) 7069 #define LCD_WF8B_BPHLCD55_MASK (0x80U) 7070 #define LCD_WF8B_BPHLCD55_SHIFT (7U) 7071 /*! BPHLCD55 7072 * 0b0..LCD segment off or LCD backplane inactive for phase H 7073 * 0b1..LCD segment on or LCD backplane active for phase H 7074 */ 7075 #define LCD_WF8B_BPHLCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD55_SHIFT)) & LCD_WF8B_BPHLCD55_MASK) 7076 #define LCD_WF8B_BPHLCD56_MASK (0x80U) 7077 #define LCD_WF8B_BPHLCD56_SHIFT (7U) 7078 /*! BPHLCD56 7079 * 0b0..LCD segment off or LCD backplane inactive for phase H 7080 * 0b1..LCD segment on or LCD backplane active for phase H 7081 */ 7082 #define LCD_WF8B_BPHLCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD56_SHIFT)) & LCD_WF8B_BPHLCD56_MASK) 7083 #define LCD_WF8B_BPHLCD57_MASK (0x80U) 7084 #define LCD_WF8B_BPHLCD57_SHIFT (7U) 7085 /*! BPHLCD57 7086 * 0b0..LCD segment off or LCD backplane inactive for phase H 7087 * 0b1..LCD segment on or LCD backplane active for phase H 7088 */ 7089 #define LCD_WF8B_BPHLCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD57_SHIFT)) & LCD_WF8B_BPHLCD57_MASK) 7090 #define LCD_WF8B_BPHLCD58_MASK (0x80U) 7091 #define LCD_WF8B_BPHLCD58_SHIFT (7U) 7092 /*! BPHLCD58 7093 * 0b0..LCD segment off or LCD backplane inactive for phase H 7094 * 0b1..LCD segment on or LCD backplane active for phase H 7095 */ 7096 #define LCD_WF8B_BPHLCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD58_SHIFT)) & LCD_WF8B_BPHLCD58_MASK) 7097 #define LCD_WF8B_BPHLCD59_MASK (0x80U) 7098 #define LCD_WF8B_BPHLCD59_SHIFT (7U) 7099 /*! BPHLCD59 7100 * 0b0..LCD segment off or LCD backplane inactive for phase H 7101 * 0b1..LCD segment on or LCD backplane active for phase H 7102 */ 7103 #define LCD_WF8B_BPHLCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD59_SHIFT)) & LCD_WF8B_BPHLCD59_MASK) 7104 #define LCD_WF8B_BPHLCD60_MASK (0x80U) 7105 #define LCD_WF8B_BPHLCD60_SHIFT (7U) 7106 /*! BPHLCD60 7107 * 0b0..LCD segment off or LCD backplane inactive for phase H 7108 * 0b1..LCD segment on or LCD backplane active for phase H 7109 */ 7110 #define LCD_WF8B_BPHLCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD60_SHIFT)) & LCD_WF8B_BPHLCD60_MASK) 7111 #define LCD_WF8B_BPHLCD61_MASK (0x80U) 7112 #define LCD_WF8B_BPHLCD61_SHIFT (7U) 7113 /*! BPHLCD61 7114 * 0b0..LCD segment off or LCD backplane inactive for phase H 7115 * 0b1..LCD segment on or LCD backplane active for phase H 7116 */ 7117 #define LCD_WF8B_BPHLCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD61_SHIFT)) & LCD_WF8B_BPHLCD61_MASK) 7118 #define LCD_WF8B_BPHLCD62_MASK (0x80U) 7119 #define LCD_WF8B_BPHLCD62_SHIFT (7U) 7120 /*! BPHLCD62 7121 * 0b0..LCD segment off or LCD backplane inactive for phase H 7122 * 0b1..LCD segment on or LCD backplane active for phase H 7123 */ 7124 #define LCD_WF8B_BPHLCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD62_SHIFT)) & LCD_WF8B_BPHLCD62_MASK) 7125 #define LCD_WF8B_BPHLCD63_MASK (0x80U) 7126 #define LCD_WF8B_BPHLCD63_SHIFT (7U) 7127 /*! BPHLCD63 7128 * 0b0..LCD segment off or LCD backplane inactive for phase H 7129 * 0b1..LCD segment on or LCD backplane active for phase H 7130 */ 7131 #define LCD_WF8B_BPHLCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD63_SHIFT)) & LCD_WF8B_BPHLCD63_MASK) 7132 /*! @} */ 7133 7134 /* The count of LCD_WF8B */ 7135 #define LCD_WF8B_COUNT (64U) 7136 7137 /*! @name WF - LCD Waveform register */ 7138 /*! @{ */ 7139 #define LCD_WF_WF0_MASK (0xFFU) 7140 #define LCD_WF_WF0_SHIFT (0U) 7141 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF0_SHIFT)) & LCD_WF_WF0_MASK) 7142 #define LCD_WF_WF4_MASK (0xFFU) 7143 #define LCD_WF_WF4_SHIFT (0U) 7144 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF4_SHIFT)) & LCD_WF_WF4_MASK) 7145 #define LCD_WF_WF8_MASK (0xFFU) 7146 #define LCD_WF_WF8_SHIFT (0U) 7147 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF8_SHIFT)) & LCD_WF_WF8_MASK) 7148 #define LCD_WF_WF12_MASK (0xFFU) 7149 #define LCD_WF_WF12_SHIFT (0U) 7150 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF12_SHIFT)) & LCD_WF_WF12_MASK) 7151 #define LCD_WF_WF16_MASK (0xFFU) 7152 #define LCD_WF_WF16_SHIFT (0U) 7153 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF16_SHIFT)) & LCD_WF_WF16_MASK) 7154 #define LCD_WF_WF20_MASK (0xFFU) 7155 #define LCD_WF_WF20_SHIFT (0U) 7156 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF20_SHIFT)) & LCD_WF_WF20_MASK) 7157 #define LCD_WF_WF24_MASK (0xFFU) 7158 #define LCD_WF_WF24_SHIFT (0U) 7159 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF24_SHIFT)) & LCD_WF_WF24_MASK) 7160 #define LCD_WF_WF28_MASK (0xFFU) 7161 #define LCD_WF_WF28_SHIFT (0U) 7162 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF28_SHIFT)) & LCD_WF_WF28_MASK) 7163 #define LCD_WF_WF32_MASK (0xFFU) 7164 #define LCD_WF_WF32_SHIFT (0U) 7165 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF32_SHIFT)) & LCD_WF_WF32_MASK) 7166 #define LCD_WF_WF36_MASK (0xFFU) 7167 #define LCD_WF_WF36_SHIFT (0U) 7168 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF36_SHIFT)) & LCD_WF_WF36_MASK) 7169 #define LCD_WF_WF40_MASK (0xFFU) 7170 #define LCD_WF_WF40_SHIFT (0U) 7171 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF40_SHIFT)) & LCD_WF_WF40_MASK) 7172 #define LCD_WF_WF44_MASK (0xFFU) 7173 #define LCD_WF_WF44_SHIFT (0U) 7174 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF44_SHIFT)) & LCD_WF_WF44_MASK) 7175 #define LCD_WF_WF48_MASK (0xFFU) 7176 #define LCD_WF_WF48_SHIFT (0U) 7177 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF48_SHIFT)) & LCD_WF_WF48_MASK) 7178 #define LCD_WF_WF52_MASK (0xFFU) 7179 #define LCD_WF_WF52_SHIFT (0U) 7180 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF52_SHIFT)) & LCD_WF_WF52_MASK) 7181 #define LCD_WF_WF56_MASK (0xFFU) 7182 #define LCD_WF_WF56_SHIFT (0U) 7183 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF56_SHIFT)) & LCD_WF_WF56_MASK) 7184 #define LCD_WF_WF60_MASK (0xFFU) 7185 #define LCD_WF_WF60_SHIFT (0U) 7186 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF60_SHIFT)) & LCD_WF_WF60_MASK) 7187 #define LCD_WF_WF1_MASK (0xFF00U) 7188 #define LCD_WF_WF1_SHIFT (8U) 7189 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF1_SHIFT)) & LCD_WF_WF1_MASK) 7190 #define LCD_WF_WF5_MASK (0xFF00U) 7191 #define LCD_WF_WF5_SHIFT (8U) 7192 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF5_SHIFT)) & LCD_WF_WF5_MASK) 7193 #define LCD_WF_WF9_MASK (0xFF00U) 7194 #define LCD_WF_WF9_SHIFT (8U) 7195 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF9_SHIFT)) & LCD_WF_WF9_MASK) 7196 #define LCD_WF_WF13_MASK (0xFF00U) 7197 #define LCD_WF_WF13_SHIFT (8U) 7198 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF13_SHIFT)) & LCD_WF_WF13_MASK) 7199 #define LCD_WF_WF17_MASK (0xFF00U) 7200 #define LCD_WF_WF17_SHIFT (8U) 7201 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF17_SHIFT)) & LCD_WF_WF17_MASK) 7202 #define LCD_WF_WF21_MASK (0xFF00U) 7203 #define LCD_WF_WF21_SHIFT (8U) 7204 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF21_SHIFT)) & LCD_WF_WF21_MASK) 7205 #define LCD_WF_WF25_MASK (0xFF00U) 7206 #define LCD_WF_WF25_SHIFT (8U) 7207 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF25_SHIFT)) & LCD_WF_WF25_MASK) 7208 #define LCD_WF_WF29_MASK (0xFF00U) 7209 #define LCD_WF_WF29_SHIFT (8U) 7210 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF29_SHIFT)) & LCD_WF_WF29_MASK) 7211 #define LCD_WF_WF33_MASK (0xFF00U) 7212 #define LCD_WF_WF33_SHIFT (8U) 7213 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF33_SHIFT)) & LCD_WF_WF33_MASK) 7214 #define LCD_WF_WF37_MASK (0xFF00U) 7215 #define LCD_WF_WF37_SHIFT (8U) 7216 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF37_SHIFT)) & LCD_WF_WF37_MASK) 7217 #define LCD_WF_WF41_MASK (0xFF00U) 7218 #define LCD_WF_WF41_SHIFT (8U) 7219 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF41_SHIFT)) & LCD_WF_WF41_MASK) 7220 #define LCD_WF_WF45_MASK (0xFF00U) 7221 #define LCD_WF_WF45_SHIFT (8U) 7222 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF45_SHIFT)) & LCD_WF_WF45_MASK) 7223 #define LCD_WF_WF49_MASK (0xFF00U) 7224 #define LCD_WF_WF49_SHIFT (8U) 7225 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF49_SHIFT)) & LCD_WF_WF49_MASK) 7226 #define LCD_WF_WF53_MASK (0xFF00U) 7227 #define LCD_WF_WF53_SHIFT (8U) 7228 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF53_SHIFT)) & LCD_WF_WF53_MASK) 7229 #define LCD_WF_WF57_MASK (0xFF00U) 7230 #define LCD_WF_WF57_SHIFT (8U) 7231 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF57_SHIFT)) & LCD_WF_WF57_MASK) 7232 #define LCD_WF_WF61_MASK (0xFF00U) 7233 #define LCD_WF_WF61_SHIFT (8U) 7234 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF61_SHIFT)) & LCD_WF_WF61_MASK) 7235 #define LCD_WF_WF2_MASK (0xFF0000U) 7236 #define LCD_WF_WF2_SHIFT (16U) 7237 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF2_SHIFT)) & LCD_WF_WF2_MASK) 7238 #define LCD_WF_WF6_MASK (0xFF0000U) 7239 #define LCD_WF_WF6_SHIFT (16U) 7240 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF6_SHIFT)) & LCD_WF_WF6_MASK) 7241 #define LCD_WF_WF10_MASK (0xFF0000U) 7242 #define LCD_WF_WF10_SHIFT (16U) 7243 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF10_SHIFT)) & LCD_WF_WF10_MASK) 7244 #define LCD_WF_WF14_MASK (0xFF0000U) 7245 #define LCD_WF_WF14_SHIFT (16U) 7246 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF14_SHIFT)) & LCD_WF_WF14_MASK) 7247 #define LCD_WF_WF18_MASK (0xFF0000U) 7248 #define LCD_WF_WF18_SHIFT (16U) 7249 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF18_SHIFT)) & LCD_WF_WF18_MASK) 7250 #define LCD_WF_WF22_MASK (0xFF0000U) 7251 #define LCD_WF_WF22_SHIFT (16U) 7252 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF22_SHIFT)) & LCD_WF_WF22_MASK) 7253 #define LCD_WF_WF26_MASK (0xFF0000U) 7254 #define LCD_WF_WF26_SHIFT (16U) 7255 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF26_SHIFT)) & LCD_WF_WF26_MASK) 7256 #define LCD_WF_WF30_MASK (0xFF0000U) 7257 #define LCD_WF_WF30_SHIFT (16U) 7258 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF30_SHIFT)) & LCD_WF_WF30_MASK) 7259 #define LCD_WF_WF34_MASK (0xFF0000U) 7260 #define LCD_WF_WF34_SHIFT (16U) 7261 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF34_SHIFT)) & LCD_WF_WF34_MASK) 7262 #define LCD_WF_WF38_MASK (0xFF0000U) 7263 #define LCD_WF_WF38_SHIFT (16U) 7264 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF38_SHIFT)) & LCD_WF_WF38_MASK) 7265 #define LCD_WF_WF42_MASK (0xFF0000U) 7266 #define LCD_WF_WF42_SHIFT (16U) 7267 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF42_SHIFT)) & LCD_WF_WF42_MASK) 7268 #define LCD_WF_WF46_MASK (0xFF0000U) 7269 #define LCD_WF_WF46_SHIFT (16U) 7270 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF46_SHIFT)) & LCD_WF_WF46_MASK) 7271 #define LCD_WF_WF50_MASK (0xFF0000U) 7272 #define LCD_WF_WF50_SHIFT (16U) 7273 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF50_SHIFT)) & LCD_WF_WF50_MASK) 7274 #define LCD_WF_WF54_MASK (0xFF0000U) 7275 #define LCD_WF_WF54_SHIFT (16U) 7276 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF54_SHIFT)) & LCD_WF_WF54_MASK) 7277 #define LCD_WF_WF58_MASK (0xFF0000U) 7278 #define LCD_WF_WF58_SHIFT (16U) 7279 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF58_SHIFT)) & LCD_WF_WF58_MASK) 7280 #define LCD_WF_WF62_MASK (0xFF0000U) 7281 #define LCD_WF_WF62_SHIFT (16U) 7282 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF62_SHIFT)) & LCD_WF_WF62_MASK) 7283 #define LCD_WF_WF3_MASK (0xFF000000U) 7284 #define LCD_WF_WF3_SHIFT (24U) 7285 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF3_SHIFT)) & LCD_WF_WF3_MASK) 7286 #define LCD_WF_WF7_MASK (0xFF000000U) 7287 #define LCD_WF_WF7_SHIFT (24U) 7288 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF7_SHIFT)) & LCD_WF_WF7_MASK) 7289 #define LCD_WF_WF11_MASK (0xFF000000U) 7290 #define LCD_WF_WF11_SHIFT (24U) 7291 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF11_SHIFT)) & LCD_WF_WF11_MASK) 7292 #define LCD_WF_WF15_MASK (0xFF000000U) 7293 #define LCD_WF_WF15_SHIFT (24U) 7294 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF15_SHIFT)) & LCD_WF_WF15_MASK) 7295 #define LCD_WF_WF19_MASK (0xFF000000U) 7296 #define LCD_WF_WF19_SHIFT (24U) 7297 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF19_SHIFT)) & LCD_WF_WF19_MASK) 7298 #define LCD_WF_WF23_MASK (0xFF000000U) 7299 #define LCD_WF_WF23_SHIFT (24U) 7300 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF23_SHIFT)) & LCD_WF_WF23_MASK) 7301 #define LCD_WF_WF27_MASK (0xFF000000U) 7302 #define LCD_WF_WF27_SHIFT (24U) 7303 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF27_SHIFT)) & LCD_WF_WF27_MASK) 7304 #define LCD_WF_WF31_MASK (0xFF000000U) 7305 #define LCD_WF_WF31_SHIFT (24U) 7306 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF31_SHIFT)) & LCD_WF_WF31_MASK) 7307 #define LCD_WF_WF35_MASK (0xFF000000U) 7308 #define LCD_WF_WF35_SHIFT (24U) 7309 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF35_SHIFT)) & LCD_WF_WF35_MASK) 7310 #define LCD_WF_WF39_MASK (0xFF000000U) 7311 #define LCD_WF_WF39_SHIFT (24U) 7312 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF39_SHIFT)) & LCD_WF_WF39_MASK) 7313 #define LCD_WF_WF43_MASK (0xFF000000U) 7314 #define LCD_WF_WF43_SHIFT (24U) 7315 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF43_SHIFT)) & LCD_WF_WF43_MASK) 7316 #define LCD_WF_WF47_MASK (0xFF000000U) 7317 #define LCD_WF_WF47_SHIFT (24U) 7318 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF47_SHIFT)) & LCD_WF_WF47_MASK) 7319 #define LCD_WF_WF51_MASK (0xFF000000U) 7320 #define LCD_WF_WF51_SHIFT (24U) 7321 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF51_SHIFT)) & LCD_WF_WF51_MASK) 7322 #define LCD_WF_WF55_MASK (0xFF000000U) 7323 #define LCD_WF_WF55_SHIFT (24U) 7324 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF55_SHIFT)) & LCD_WF_WF55_MASK) 7325 #define LCD_WF_WF59_MASK (0xFF000000U) 7326 #define LCD_WF_WF59_SHIFT (24U) 7327 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF59_SHIFT)) & LCD_WF_WF59_MASK) 7328 #define LCD_WF_WF63_MASK (0xFF000000U) 7329 #define LCD_WF_WF63_SHIFT (24U) 7330 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF63_SHIFT)) & LCD_WF_WF63_MASK) 7331 /*! @} */ 7332 7333 /* The count of LCD_WF */ 7334 #define LCD_WF_COUNT (16U) 7335 7336 /*! 7337 * @} 7338 */ /* end of group LCD_Register_Masks */ 7339 7340 /* LCD - Peripheral instance base addresses */ 7341 /** Peripheral LCD base address */ 7342 #define LCD_BASE (0x40053000u) 7343 /** Peripheral LCD base pointer */ 7344 #define LCD ((LCD_Type *)LCD_BASE) 7345 /** Array initializer of LCD peripheral base addresses */ 7346 #define LCD_BASE_ADDRS \ 7347 { \ 7348 LCD_BASE \ 7349 } 7350 /** Array initializer of LCD peripheral base pointers */ 7351 #define LCD_BASE_PTRS \ 7352 { \ 7353 LCD \ 7354 } 7355 /** Interrupt vectors for the LCD peripheral type */ 7356 #define LCD_LCD_IRQS \ 7357 { \ 7358 LCD_IRQn \ 7359 } 7360 7361 /*! 7362 * @} 7363 */ /* end of group LCD_Peripheral_Access_Layer */ 7364 7365 /* ---------------------------------------------------------------------------- 7366 -- LLWU Peripheral Access Layer 7367 ---------------------------------------------------------------------------- */ 7368 7369 /*! 7370 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 7371 * @{ 7372 */ 7373 7374 /** LLWU - Register Layout Typedef */ 7375 typedef struct 7376 { 7377 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 7378 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 7379 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 7380 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 7381 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 7382 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 7383 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 7384 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 7385 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 7386 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 7387 } LLWU_Type; 7388 7389 /* ---------------------------------------------------------------------------- 7390 -- LLWU Register Masks 7391 ---------------------------------------------------------------------------- */ 7392 7393 /*! 7394 * @addtogroup LLWU_Register_Masks LLWU Register Masks 7395 * @{ 7396 */ 7397 7398 /*! @name PE1 - LLWU Pin Enable 1 register */ 7399 /*! @{ */ 7400 #define LLWU_PE1_WUPE0_MASK (0x3U) 7401 #define LLWU_PE1_WUPE0_SHIFT (0U) 7402 /*! WUPE0 - Wakeup Pin Enable For LLWU_P0 7403 * 0b00..External input pin disabled as wakeup input 7404 * 0b01..External input pin enabled with rising edge detection 7405 * 0b10..External input pin enabled with falling edge detection 7406 * 0b11..External input pin enabled with any change detection 7407 */ 7408 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 7409 #define LLWU_PE1_WUPE1_MASK (0xCU) 7410 #define LLWU_PE1_WUPE1_SHIFT (2U) 7411 /*! WUPE1 - Wakeup Pin Enable For LLWU_P1 7412 * 0b00..External input pin disabled as wakeup input 7413 * 0b01..External input pin enabled with rising edge detection 7414 * 0b10..External input pin enabled with falling edge detection 7415 * 0b11..External input pin enabled with any change detection 7416 */ 7417 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 7418 #define LLWU_PE1_WUPE2_MASK (0x30U) 7419 #define LLWU_PE1_WUPE2_SHIFT (4U) 7420 /*! WUPE2 - Wakeup Pin Enable For LLWU_P2 7421 * 0b00..External input pin disabled as wakeup input 7422 * 0b01..External input pin enabled with rising edge detection 7423 * 0b10..External input pin enabled with falling edge detection 7424 * 0b11..External input pin enabled with any change detection 7425 */ 7426 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 7427 #define LLWU_PE1_WUPE3_MASK (0xC0U) 7428 #define LLWU_PE1_WUPE3_SHIFT (6U) 7429 /*! WUPE3 - Wakeup Pin Enable For LLWU_P3 7430 * 0b00..External input pin disabled as wakeup input 7431 * 0b01..External input pin enabled with rising edge detection 7432 * 0b10..External input pin enabled with falling edge detection 7433 * 0b11..External input pin enabled with any change detection 7434 */ 7435 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 7436 /*! @} */ 7437 7438 /*! @name PE2 - LLWU Pin Enable 2 register */ 7439 /*! @{ */ 7440 #define LLWU_PE2_WUPE4_MASK (0x3U) 7441 #define LLWU_PE2_WUPE4_SHIFT (0U) 7442 /*! WUPE4 - Wakeup Pin Enable For LLWU_P4 7443 * 0b00..External input pin disabled as wakeup input 7444 * 0b01..External input pin enabled with rising edge detection 7445 * 0b10..External input pin enabled with falling edge detection 7446 * 0b11..External input pin enabled with any change detection 7447 */ 7448 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 7449 #define LLWU_PE2_WUPE5_MASK (0xCU) 7450 #define LLWU_PE2_WUPE5_SHIFT (2U) 7451 /*! WUPE5 - Wakeup Pin Enable For LLWU_P5 7452 * 0b00..External input pin disabled as wakeup input 7453 * 0b01..External input pin enabled with rising edge detection 7454 * 0b10..External input pin enabled with falling edge detection 7455 * 0b11..External input pin enabled with any change detection 7456 */ 7457 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 7458 #define LLWU_PE2_WUPE6_MASK (0x30U) 7459 #define LLWU_PE2_WUPE6_SHIFT (4U) 7460 /*! WUPE6 - Wakeup Pin Enable For LLWU_P6 7461 * 0b00..External input pin disabled as wakeup input 7462 * 0b01..External input pin enabled with rising edge detection 7463 * 0b10..External input pin enabled with falling edge detection 7464 * 0b11..External input pin enabled with any change detection 7465 */ 7466 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 7467 #define LLWU_PE2_WUPE7_MASK (0xC0U) 7468 #define LLWU_PE2_WUPE7_SHIFT (6U) 7469 /*! WUPE7 - Wakeup Pin Enable For LLWU_P7 7470 * 0b00..External input pin disabled as wakeup input 7471 * 0b01..External input pin enabled with rising edge detection 7472 * 0b10..External input pin enabled with falling edge detection 7473 * 0b11..External input pin enabled with any change detection 7474 */ 7475 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 7476 /*! @} */ 7477 7478 /*! @name PE3 - LLWU Pin Enable 3 register */ 7479 /*! @{ */ 7480 #define LLWU_PE3_WUPE8_MASK (0x3U) 7481 #define LLWU_PE3_WUPE8_SHIFT (0U) 7482 /*! WUPE8 - Wakeup Pin Enable For LLWU_P8 7483 * 0b00..External input pin disabled as wakeup input 7484 * 0b01..External input pin enabled with rising edge detection 7485 * 0b10..External input pin enabled with falling edge detection 7486 * 0b11..External input pin enabled with any change detection 7487 */ 7488 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 7489 #define LLWU_PE3_WUPE9_MASK (0xCU) 7490 #define LLWU_PE3_WUPE9_SHIFT (2U) 7491 /*! WUPE9 - Wakeup Pin Enable For LLWU_P9 7492 * 0b00..External input pin disabled as wakeup input 7493 * 0b01..External input pin enabled with rising edge detection 7494 * 0b10..External input pin enabled with falling edge detection 7495 * 0b11..External input pin enabled with any change detection 7496 */ 7497 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 7498 #define LLWU_PE3_WUPE10_MASK (0x30U) 7499 #define LLWU_PE3_WUPE10_SHIFT (4U) 7500 /*! WUPE10 - Wakeup Pin Enable For LLWU_P10 7501 * 0b00..External input pin disabled as wakeup input 7502 * 0b01..External input pin enabled with rising edge detection 7503 * 0b10..External input pin enabled with falling edge detection 7504 * 0b11..External input pin enabled with any change detection 7505 */ 7506 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 7507 #define LLWU_PE3_WUPE11_MASK (0xC0U) 7508 #define LLWU_PE3_WUPE11_SHIFT (6U) 7509 /*! WUPE11 - Wakeup Pin Enable For LLWU_P11 7510 * 0b00..External input pin disabled as wakeup input 7511 * 0b01..External input pin enabled with rising edge detection 7512 * 0b10..External input pin enabled with falling edge detection 7513 * 0b11..External input pin enabled with any change detection 7514 */ 7515 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 7516 /*! @} */ 7517 7518 /*! @name PE4 - LLWU Pin Enable 4 register */ 7519 /*! @{ */ 7520 #define LLWU_PE4_WUPE12_MASK (0x3U) 7521 #define LLWU_PE4_WUPE12_SHIFT (0U) 7522 /*! WUPE12 - Wakeup Pin Enable For LLWU_P12 7523 * 0b00..External input pin disabled as wakeup input 7524 * 0b01..External input pin enabled with rising edge detection 7525 * 0b10..External input pin enabled with falling edge detection 7526 * 0b11..External input pin enabled with any change detection 7527 */ 7528 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 7529 #define LLWU_PE4_WUPE13_MASK (0xCU) 7530 #define LLWU_PE4_WUPE13_SHIFT (2U) 7531 /*! WUPE13 - Wakeup Pin Enable For LLWU_P13 7532 * 0b00..External input pin disabled as wakeup input 7533 * 0b01..External input pin enabled with rising edge detection 7534 * 0b10..External input pin enabled with falling edge detection 7535 * 0b11..External input pin enabled with any change detection 7536 */ 7537 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 7538 #define LLWU_PE4_WUPE14_MASK (0x30U) 7539 #define LLWU_PE4_WUPE14_SHIFT (4U) 7540 /*! WUPE14 - Wakeup Pin Enable For LLWU_P14 7541 * 0b00..External input pin disabled as wakeup input 7542 * 0b01..External input pin enabled with rising edge detection 7543 * 0b10..External input pin enabled with falling edge detection 7544 * 0b11..External input pin enabled with any change detection 7545 */ 7546 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 7547 #define LLWU_PE4_WUPE15_MASK (0xC0U) 7548 #define LLWU_PE4_WUPE15_SHIFT (6U) 7549 /*! WUPE15 - Wakeup Pin Enable For LLWU_P15 7550 * 0b00..External input pin disabled as wakeup input 7551 * 0b01..External input pin enabled with rising edge detection 7552 * 0b10..External input pin enabled with falling edge detection 7553 * 0b11..External input pin enabled with any change detection 7554 */ 7555 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 7556 /*! @} */ 7557 7558 /*! @name ME - LLWU Module Enable register */ 7559 /*! @{ */ 7560 #define LLWU_ME_WUME0_MASK (0x1U) 7561 #define LLWU_ME_WUME0_SHIFT (0U) 7562 /*! WUME0 - Wakeup Module Enable For Module 0 7563 * 0b0..Internal module flag not used as wakeup source 7564 * 0b1..Internal module flag used as wakeup source 7565 */ 7566 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 7567 #define LLWU_ME_WUME1_MASK (0x2U) 7568 #define LLWU_ME_WUME1_SHIFT (1U) 7569 /*! WUME1 - Wakeup Module Enable for Module 1 7570 * 0b0..Internal module flag not used as wakeup source 7571 * 0b1..Internal module flag used as wakeup source 7572 */ 7573 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 7574 #define LLWU_ME_WUME2_MASK (0x4U) 7575 #define LLWU_ME_WUME2_SHIFT (2U) 7576 /*! WUME2 - Wakeup Module Enable For Module 2 7577 * 0b0..Internal module flag not used as wakeup source 7578 * 0b1..Internal module flag used as wakeup source 7579 */ 7580 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 7581 #define LLWU_ME_WUME3_MASK (0x8U) 7582 #define LLWU_ME_WUME3_SHIFT (3U) 7583 /*! WUME3 - Wakeup Module Enable For Module 3 7584 * 0b0..Internal module flag not used as wakeup source 7585 * 0b1..Internal module flag used as wakeup source 7586 */ 7587 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 7588 #define LLWU_ME_WUME4_MASK (0x10U) 7589 #define LLWU_ME_WUME4_SHIFT (4U) 7590 /*! WUME4 - Wakeup Module Enable For Module 4 7591 * 0b0..Internal module flag not used as wakeup source 7592 * 0b1..Internal module flag used as wakeup source 7593 */ 7594 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 7595 #define LLWU_ME_WUME5_MASK (0x20U) 7596 #define LLWU_ME_WUME5_SHIFT (5U) 7597 /*! WUME5 - Wakeup Module Enable For Module 5 7598 * 0b0..Internal module flag not used as wakeup source 7599 * 0b1..Internal module flag used as wakeup source 7600 */ 7601 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 7602 #define LLWU_ME_WUME6_MASK (0x40U) 7603 #define LLWU_ME_WUME6_SHIFT (6U) 7604 /*! WUME6 - Wakeup Module Enable For Module 6 7605 * 0b0..Internal module flag not used as wakeup source 7606 * 0b1..Internal module flag used as wakeup source 7607 */ 7608 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 7609 #define LLWU_ME_WUME7_MASK (0x80U) 7610 #define LLWU_ME_WUME7_SHIFT (7U) 7611 /*! WUME7 - Wakeup Module Enable For Module 7 7612 * 0b0..Internal module flag not used as wakeup source 7613 * 0b1..Internal module flag used as wakeup source 7614 */ 7615 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 7616 /*! @} */ 7617 7618 /*! @name F1 - LLWU Flag 1 register */ 7619 /*! @{ */ 7620 #define LLWU_F1_WUF0_MASK (0x1U) 7621 #define LLWU_F1_WUF0_SHIFT (0U) 7622 /*! WUF0 - Wakeup Flag For LLWU_P0 7623 * 0b0..LLWU_P0 input was not a wakeup source 7624 * 0b1..LLWU_P0 input was a wakeup source 7625 */ 7626 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) 7627 #define LLWU_F1_WUF1_MASK (0x2U) 7628 #define LLWU_F1_WUF1_SHIFT (1U) 7629 /*! WUF1 - Wakeup Flag For LLWU_P1 7630 * 0b0..LLWU_P1 input was not a wakeup source 7631 * 0b1..LLWU_P1 input was a wakeup source 7632 */ 7633 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) 7634 #define LLWU_F1_WUF2_MASK (0x4U) 7635 #define LLWU_F1_WUF2_SHIFT (2U) 7636 /*! WUF2 - Wakeup Flag For LLWU_P2 7637 * 0b0..LLWU_P2 input was not a wakeup source 7638 * 0b1..LLWU_P2 input was a wakeup source 7639 */ 7640 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) 7641 #define LLWU_F1_WUF3_MASK (0x8U) 7642 #define LLWU_F1_WUF3_SHIFT (3U) 7643 /*! WUF3 - Wakeup Flag For LLWU_P3 7644 * 0b0..LLWU_P3 input was not a wake-up source 7645 * 0b1..LLWU_P3 input was a wake-up source 7646 */ 7647 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) 7648 #define LLWU_F1_WUF4_MASK (0x10U) 7649 #define LLWU_F1_WUF4_SHIFT (4U) 7650 /*! WUF4 - Wakeup Flag For LLWU_P4 7651 * 0b0..LLWU_P4 input was not a wakeup source 7652 * 0b1..LLWU_P4 input was a wakeup source 7653 */ 7654 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) 7655 #define LLWU_F1_WUF5_MASK (0x20U) 7656 #define LLWU_F1_WUF5_SHIFT (5U) 7657 /*! WUF5 - Wakeup Flag For LLWU_P5 7658 * 0b0..LLWU_P5 input was not a wakeup source 7659 * 0b1..LLWU_P5 input was a wakeup source 7660 */ 7661 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) 7662 #define LLWU_F1_WUF6_MASK (0x40U) 7663 #define LLWU_F1_WUF6_SHIFT (6U) 7664 /*! WUF6 - Wakeup Flag For LLWU_P6 7665 * 0b0..LLWU_P6 input was not a wakeup source 7666 * 0b1..LLWU_P6 input was a wakeup source 7667 */ 7668 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) 7669 #define LLWU_F1_WUF7_MASK (0x80U) 7670 #define LLWU_F1_WUF7_SHIFT (7U) 7671 /*! WUF7 - Wakeup Flag For LLWU_P7 7672 * 0b0..LLWU_P7 input was not a wakeup source 7673 * 0b1..LLWU_P7 input was a wakeup source 7674 */ 7675 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) 7676 /*! @} */ 7677 7678 /*! @name F2 - LLWU Flag 2 register */ 7679 /*! @{ */ 7680 #define LLWU_F2_WUF8_MASK (0x1U) 7681 #define LLWU_F2_WUF8_SHIFT (0U) 7682 /*! WUF8 - Wakeup Flag For LLWU_P8 7683 * 0b0..LLWU_P8 input was not a wakeup source 7684 * 0b1..LLWU_P8 input was a wakeup source 7685 */ 7686 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) 7687 #define LLWU_F2_WUF9_MASK (0x2U) 7688 #define LLWU_F2_WUF9_SHIFT (1U) 7689 /*! WUF9 - Wakeup Flag For LLWU_P9 7690 * 0b0..LLWU_P9 input was not a wakeup source 7691 * 0b1..LLWU_P9 input was a wakeup source 7692 */ 7693 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) 7694 #define LLWU_F2_WUF10_MASK (0x4U) 7695 #define LLWU_F2_WUF10_SHIFT (2U) 7696 /*! WUF10 - Wakeup Flag For LLWU_P10 7697 * 0b0..LLWU_P10 input was not a wakeup source 7698 * 0b1..LLWU_P10 input was a wakeup source 7699 */ 7700 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) 7701 #define LLWU_F2_WUF11_MASK (0x8U) 7702 #define LLWU_F2_WUF11_SHIFT (3U) 7703 /*! WUF11 - Wakeup Flag For LLWU_P11 7704 * 0b0..LLWU_P11 input was not a wakeup source 7705 * 0b1..LLWU_P11 input was a wakeup source 7706 */ 7707 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) 7708 #define LLWU_F2_WUF12_MASK (0x10U) 7709 #define LLWU_F2_WUF12_SHIFT (4U) 7710 /*! WUF12 - Wakeup Flag For LLWU_P12 7711 * 0b0..LLWU_P12 input was not a wakeup source 7712 * 0b1..LLWU_P12 input was a wakeup source 7713 */ 7714 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) 7715 #define LLWU_F2_WUF13_MASK (0x20U) 7716 #define LLWU_F2_WUF13_SHIFT (5U) 7717 /*! WUF13 - Wakeup Flag For LLWU_P13 7718 * 0b0..LLWU_P13 input was not a wakeup source 7719 * 0b1..LLWU_P13 input was a wakeup source 7720 */ 7721 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) 7722 #define LLWU_F2_WUF14_MASK (0x40U) 7723 #define LLWU_F2_WUF14_SHIFT (6U) 7724 /*! WUF14 - Wakeup Flag For LLWU_P14 7725 * 0b0..LLWU_P14 input was not a wakeup source 7726 * 0b1..LLWU_P14 input was a wakeup source 7727 */ 7728 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) 7729 #define LLWU_F2_WUF15_MASK (0x80U) 7730 #define LLWU_F2_WUF15_SHIFT (7U) 7731 /*! WUF15 - Wakeup Flag For LLWU_P15 7732 * 0b0..LLWU_P15 input was not a wakeup source 7733 * 0b1..LLWU_P15 input was a wakeup source 7734 */ 7735 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) 7736 /*! @} */ 7737 7738 /*! @name F3 - LLWU Flag 3 register */ 7739 /*! @{ */ 7740 #define LLWU_F3_MWUF0_MASK (0x1U) 7741 #define LLWU_F3_MWUF0_SHIFT (0U) 7742 /*! MWUF0 - Wakeup flag For module 0 7743 * 0b0..Module 0 input was not a wakeup source 7744 * 0b1..Module 0 input was a wakeup source 7745 */ 7746 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) 7747 #define LLWU_F3_MWUF1_MASK (0x2U) 7748 #define LLWU_F3_MWUF1_SHIFT (1U) 7749 /*! MWUF1 - Wakeup flag For module 1 7750 * 0b0..Module 1 input was not a wakeup source 7751 * 0b1..Module 1 input was a wakeup source 7752 */ 7753 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) 7754 #define LLWU_F3_MWUF2_MASK (0x4U) 7755 #define LLWU_F3_MWUF2_SHIFT (2U) 7756 /*! MWUF2 - Wakeup flag For module 2 7757 * 0b0..Module 2 input was not a wakeup source 7758 * 0b1..Module 2 input was a wakeup source 7759 */ 7760 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) 7761 #define LLWU_F3_MWUF3_MASK (0x8U) 7762 #define LLWU_F3_MWUF3_SHIFT (3U) 7763 /*! MWUF3 - Wakeup flag For module 3 7764 * 0b0..Module 3 input was not a wakeup source 7765 * 0b1..Module 3 input was a wakeup source 7766 */ 7767 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) 7768 #define LLWU_F3_MWUF4_MASK (0x10U) 7769 #define LLWU_F3_MWUF4_SHIFT (4U) 7770 /*! MWUF4 - Wakeup flag For module 4 7771 * 0b0..Module 4 input was not a wakeup source 7772 * 0b1..Module 4 input was a wakeup source 7773 */ 7774 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) 7775 #define LLWU_F3_MWUF5_MASK (0x20U) 7776 #define LLWU_F3_MWUF5_SHIFT (5U) 7777 /*! MWUF5 - Wakeup flag For module 5 7778 * 0b0..Module 5 input was not a wakeup source 7779 * 0b1..Module 5 input was a wakeup source 7780 */ 7781 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) 7782 #define LLWU_F3_MWUF6_MASK (0x40U) 7783 #define LLWU_F3_MWUF6_SHIFT (6U) 7784 /*! MWUF6 - Wakeup flag For module 6 7785 * 0b0..Module 6 input was not a wakeup source 7786 * 0b1..Module 6 input was a wakeup source 7787 */ 7788 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) 7789 #define LLWU_F3_MWUF7_MASK (0x80U) 7790 #define LLWU_F3_MWUF7_SHIFT (7U) 7791 /*! MWUF7 - Wakeup flag For module 7 7792 * 0b0..Module 7 input was not a wakeup source 7793 * 0b1..Module 7 input was a wakeup source 7794 */ 7795 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) 7796 /*! @} */ 7797 7798 /*! @name FILT1 - LLWU Pin Filter 1 register */ 7799 /*! @{ */ 7800 #define LLWU_FILT1_FILTSEL_MASK (0xFU) 7801 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 7802 /*! FILTSEL - Filter Pin Select 7803 * 0b0000..Select LLWU_P0 for filter 7804 * 0b1111..Select LLWU_P15 for filter 7805 */ 7806 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 7807 #define LLWU_FILT1_FILTE_MASK (0x60U) 7808 #define LLWU_FILT1_FILTE_SHIFT (5U) 7809 /*! FILTE - Digital Filter On External Pin 7810 * 0b00..Filter disabled 7811 * 0b01..Filter posedge detect enabled 7812 * 0b10..Filter negedge detect enabled 7813 * 0b11..Filter any edge detect enabled 7814 */ 7815 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 7816 #define LLWU_FILT1_FILTF_MASK (0x80U) 7817 #define LLWU_FILT1_FILTF_SHIFT (7U) 7818 /*! FILTF - Filter Detect Flag 7819 * 0b0..Pin Filter 1 was not a wakeup source 7820 * 0b1..Pin Filter 1 was a wakeup source 7821 */ 7822 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 7823 /*! @} */ 7824 7825 /*! @name FILT2 - LLWU Pin Filter 2 register */ 7826 /*! @{ */ 7827 #define LLWU_FILT2_FILTSEL_MASK (0xFU) 7828 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 7829 /*! FILTSEL - Filter Pin Select 7830 * 0b0000..Select LLWU_P0 for filter 7831 * 0b1111..Select LLWU_P15 for filter 7832 */ 7833 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 7834 #define LLWU_FILT2_FILTE_MASK (0x60U) 7835 #define LLWU_FILT2_FILTE_SHIFT (5U) 7836 /*! FILTE - Digital Filter On External Pin 7837 * 0b00..Filter disabled 7838 * 0b01..Filter posedge detect enabled 7839 * 0b10..Filter negedge detect enabled 7840 * 0b11..Filter any edge detect enabled 7841 */ 7842 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 7843 #define LLWU_FILT2_FILTF_MASK (0x80U) 7844 #define LLWU_FILT2_FILTF_SHIFT (7U) 7845 /*! FILTF - Filter Detect Flag 7846 * 0b0..Pin Filter 2 was not a wakeup source 7847 * 0b1..Pin Filter 2 was a wakeup source 7848 */ 7849 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 7850 /*! @} */ 7851 7852 /*! 7853 * @} 7854 */ /* end of group LLWU_Register_Masks */ 7855 7856 /* LLWU - Peripheral instance base addresses */ 7857 /** Peripheral LLWU base address */ 7858 #define LLWU_BASE (0x4007C000u) 7859 /** Peripheral LLWU base pointer */ 7860 #define LLWU ((LLWU_Type *)LLWU_BASE) 7861 /** Array initializer of LLWU peripheral base addresses */ 7862 #define LLWU_BASE_ADDRS \ 7863 { \ 7864 LLWU_BASE \ 7865 } 7866 /** Array initializer of LLWU peripheral base pointers */ 7867 #define LLWU_BASE_PTRS \ 7868 { \ 7869 LLWU \ 7870 } 7871 /** Interrupt vectors for the LLWU peripheral type */ 7872 #define LLWU_IRQS \ 7873 { \ 7874 LLWU_IRQn \ 7875 } 7876 7877 /*! 7878 * @} 7879 */ /* end of group LLWU_Peripheral_Access_Layer */ 7880 7881 /* ---------------------------------------------------------------------------- 7882 -- LPTMR Peripheral Access Layer 7883 ---------------------------------------------------------------------------- */ 7884 7885 /*! 7886 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 7887 * @{ 7888 */ 7889 7890 /** LPTMR - Register Layout Typedef */ 7891 typedef struct 7892 { 7893 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 7894 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 7895 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 7896 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 7897 } LPTMR_Type; 7898 7899 /* ---------------------------------------------------------------------------- 7900 -- LPTMR Register Masks 7901 ---------------------------------------------------------------------------- */ 7902 7903 /*! 7904 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 7905 * @{ 7906 */ 7907 7908 /*! @name CSR - Low Power Timer Control Status Register */ 7909 /*! @{ */ 7910 #define LPTMR_CSR_TEN_MASK (0x1U) 7911 #define LPTMR_CSR_TEN_SHIFT (0U) 7912 /*! TEN - Timer Enable 7913 * 0b0..LPTMR is disabled and internal logic is reset. 7914 * 0b1..LPTMR is enabled. 7915 */ 7916 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 7917 #define LPTMR_CSR_TMS_MASK (0x2U) 7918 #define LPTMR_CSR_TMS_SHIFT (1U) 7919 /*! TMS - Timer Mode Select 7920 * 0b0..Time Counter mode. 7921 * 0b1..Pulse Counter mode. 7922 */ 7923 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 7924 #define LPTMR_CSR_TFC_MASK (0x4U) 7925 #define LPTMR_CSR_TFC_SHIFT (2U) 7926 /*! TFC - Timer Free-Running Counter 7927 * 0b0..CNR is reset whenever TCF is set. 7928 * 0b1..CNR is reset on overflow. 7929 */ 7930 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 7931 #define LPTMR_CSR_TPP_MASK (0x8U) 7932 #define LPTMR_CSR_TPP_SHIFT (3U) 7933 /*! TPP - Timer Pin Polarity 7934 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 7935 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 7936 */ 7937 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 7938 #define LPTMR_CSR_TPS_MASK (0x30U) 7939 #define LPTMR_CSR_TPS_SHIFT (4U) 7940 /*! TPS - Timer Pin Select 7941 * 0b00..Pulse counter input 0 is selected. 7942 * 0b01..Pulse counter input 1 is selected. 7943 * 0b10..Pulse counter input 2 is selected. 7944 * 0b11..Pulse counter input 3 is selected. 7945 */ 7946 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 7947 #define LPTMR_CSR_TIE_MASK (0x40U) 7948 #define LPTMR_CSR_TIE_SHIFT (6U) 7949 /*! TIE - Timer Interrupt Enable 7950 * 0b0..Timer interrupt disabled. 7951 * 0b1..Timer interrupt enabled. 7952 */ 7953 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 7954 #define LPTMR_CSR_TCF_MASK (0x80U) 7955 #define LPTMR_CSR_TCF_SHIFT (7U) 7956 /*! TCF - Timer Compare Flag 7957 * 0b0..The value of CNR is not equal to CMR and increments. 7958 * 0b1..The value of CNR is equal to CMR and increments. 7959 */ 7960 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 7961 /*! @} */ 7962 7963 /*! @name PSR - Low Power Timer Prescale Register */ 7964 /*! @{ */ 7965 #define LPTMR_PSR_PCS_MASK (0x3U) 7966 #define LPTMR_PSR_PCS_SHIFT (0U) 7967 /*! PCS - Prescaler Clock Select 7968 * 0b00..Prescaler/glitch filter clock 0 selected. 7969 * 0b01..Prescaler/glitch filter clock 1 selected. 7970 * 0b10..Prescaler/glitch filter clock 2 selected. 7971 * 0b11..Prescaler/glitch filter clock 3 selected. 7972 */ 7973 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 7974 #define LPTMR_PSR_PBYP_MASK (0x4U) 7975 #define LPTMR_PSR_PBYP_SHIFT (2U) 7976 /*! PBYP - Prescaler Bypass 7977 * 0b0..Prescaler/glitch filter is enabled. 7978 * 0b1..Prescaler/glitch filter is bypassed. 7979 */ 7980 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 7981 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 7982 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 7983 /*! PRESCALE - Prescale Value 7984 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 7985 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising 7986 * clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 7987 * rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin 7988 * after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on 7989 * input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes 7990 * change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter 7991 * recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256; 7992 * glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler 7993 * clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides 7994 * the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 7995 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 7996 * rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input 7997 * pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes 7998 * change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch 7999 * filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by 8000 * 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the 8001 * prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. 8002 */ 8003 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 8004 /*! @} */ 8005 8006 /*! @name CMR - Low Power Timer Compare Register */ 8007 /*! @{ */ 8008 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 8009 #define LPTMR_CMR_COMPARE_SHIFT (0U) 8010 /*! COMPARE - Compare Value 8011 */ 8012 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 8013 /*! @} */ 8014 8015 /*! @name CNR - Low Power Timer Counter Register */ 8016 /*! @{ */ 8017 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 8018 #define LPTMR_CNR_COUNTER_SHIFT (0U) 8019 /*! COUNTER - Counter Value 8020 */ 8021 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 8022 /*! @} */ 8023 8024 /*! 8025 * @} 8026 */ /* end of group LPTMR_Register_Masks */ 8027 8028 /* LPTMR - Peripheral instance base addresses */ 8029 /** Peripheral LPTMR0 base address */ 8030 #define LPTMR0_BASE (0x40040000u) 8031 /** Peripheral LPTMR0 base pointer */ 8032 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 8033 /** Array initializer of LPTMR peripheral base addresses */ 8034 #define LPTMR_BASE_ADDRS \ 8035 { \ 8036 LPTMR0_BASE \ 8037 } 8038 /** Array initializer of LPTMR peripheral base pointers */ 8039 #define LPTMR_BASE_PTRS \ 8040 { \ 8041 LPTMR0 \ 8042 } 8043 /** Interrupt vectors for the LPTMR peripheral type */ 8044 #define LPTMR_IRQS \ 8045 { \ 8046 LPTMR0_IRQn \ 8047 } 8048 8049 /*! 8050 * @} 8051 */ /* end of group LPTMR_Peripheral_Access_Layer */ 8052 8053 /* ---------------------------------------------------------------------------- 8054 -- LPUART Peripheral Access Layer 8055 ---------------------------------------------------------------------------- */ 8056 8057 /*! 8058 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer 8059 * @{ 8060 */ 8061 8062 /** LPUART - Register Layout Typedef */ 8063 typedef struct 8064 { 8065 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ 8066 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ 8067 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ 8068 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ 8069 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ 8070 } LPUART_Type; 8071 8072 /* ---------------------------------------------------------------------------- 8073 -- LPUART Register Masks 8074 ---------------------------------------------------------------------------- */ 8075 8076 /*! 8077 * @addtogroup LPUART_Register_Masks LPUART Register Masks 8078 * @{ 8079 */ 8080 8081 /*! @name BAUD - LPUART Baud Rate Register */ 8082 /*! @{ */ 8083 #define LPUART_BAUD_SBR_MASK (0x1FFFU) 8084 #define LPUART_BAUD_SBR_SHIFT (0U) 8085 /*! SBR - Baud Rate Modulo Divisor. 8086 */ 8087 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) 8088 #define LPUART_BAUD_SBNS_MASK (0x2000U) 8089 #define LPUART_BAUD_SBNS_SHIFT (13U) 8090 /*! SBNS - Stop Bit Number Select 8091 * 0b0..One stop bit. 8092 * 0b1..Two stop bits. 8093 */ 8094 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) 8095 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) 8096 #define LPUART_BAUD_RXEDGIE_SHIFT (14U) 8097 /*! RXEDGIE - RX Input Active Edge Interrupt Enable 8098 * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). 8099 * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. 8100 */ 8101 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) 8102 #define LPUART_BAUD_LBKDIE_MASK (0x8000U) 8103 #define LPUART_BAUD_LBKDIE_SHIFT (15U) 8104 /*! LBKDIE - LIN Break Detect Interrupt Enable 8105 * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 8106 * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. 8107 */ 8108 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) 8109 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) 8110 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) 8111 /*! RESYNCDIS - Resynchronization Disable 8112 * 0b0..Resynchronization during received data word is supported 8113 * 0b1..Resynchronization during received data word is disabled 8114 */ 8115 #define LPUART_BAUD_RESYNCDIS(x) \ 8116 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) 8117 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) 8118 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) 8119 /*! BOTHEDGE - Both Edge Sampling 8120 * 0b0..Receiver samples input data using the rising edge of the baud rate clock. 8121 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. 8122 */ 8123 #define LPUART_BAUD_BOTHEDGE(x) \ 8124 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) 8125 #define LPUART_BAUD_MATCFG_MASK (0xC0000U) 8126 #define LPUART_BAUD_MATCFG_SHIFT (18U) 8127 /*! MATCFG - Match Configuration 8128 * 0b00..Address Match Wakeup 8129 * 0b01..Idle Match Wakeup 8130 * 0b10..Match On and Match Off 8131 * 0b11..Enables RWU on Data Match and Match On/Off 8132 */ 8133 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) 8134 #define LPUART_BAUD_RDMAE_MASK (0x200000U) 8135 #define LPUART_BAUD_RDMAE_SHIFT (21U) 8136 /*! RDMAE - Receiver Full DMA Enable 8137 * 0b0..DMA request disabled. 8138 * 0b1..DMA request enabled. 8139 */ 8140 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) 8141 #define LPUART_BAUD_TDMAE_MASK (0x800000U) 8142 #define LPUART_BAUD_TDMAE_SHIFT (23U) 8143 /*! TDMAE - Transmitter DMA Enable 8144 * 0b0..DMA request disabled. 8145 * 0b1..DMA request enabled. 8146 */ 8147 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) 8148 #define LPUART_BAUD_OSR_MASK (0x1F000000U) 8149 #define LPUART_BAUD_OSR_SHIFT (24U) 8150 /*! OSR - Oversampling Ratio 8151 */ 8152 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) 8153 #define LPUART_BAUD_M10_MASK (0x20000000U) 8154 #define LPUART_BAUD_M10_SHIFT (29U) 8155 /*! M10 - 10-bit Mode select 8156 * 0b0..Receiver and transmitter use 8-bit or 9-bit data characters. 8157 * 0b1..Receiver and transmitter use 10-bit data characters. 8158 */ 8159 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) 8160 #define LPUART_BAUD_MAEN2_MASK (0x40000000U) 8161 #define LPUART_BAUD_MAEN2_SHIFT (30U) 8162 /*! MAEN2 - Match Address Mode Enable 2 8163 * 0b0..Normal operation. 8164 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. 8165 */ 8166 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) 8167 #define LPUART_BAUD_MAEN1_MASK (0x80000000U) 8168 #define LPUART_BAUD_MAEN1_SHIFT (31U) 8169 /*! MAEN1 - Match Address Mode Enable 1 8170 * 0b0..Normal operation. 8171 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. 8172 */ 8173 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) 8174 /*! @} */ 8175 8176 /*! @name STAT - LPUART Status Register */ 8177 /*! @{ */ 8178 #define LPUART_STAT_MA2F_MASK (0x4000U) 8179 #define LPUART_STAT_MA2F_SHIFT (14U) 8180 /*! MA2F - Match 2 Flag 8181 * 0b0..Received data is not equal to MA2 8182 * 0b1..Received data is equal to MA2 8183 */ 8184 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) 8185 #define LPUART_STAT_MA1F_MASK (0x8000U) 8186 #define LPUART_STAT_MA1F_SHIFT (15U) 8187 /*! MA1F - Match 1 Flag 8188 * 0b0..Received data is not equal to MA1 8189 * 0b1..Received data is equal to MA1 8190 */ 8191 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) 8192 #define LPUART_STAT_PF_MASK (0x10000U) 8193 #define LPUART_STAT_PF_SHIFT (16U) 8194 /*! PF - Parity Error Flag 8195 * 0b0..No parity error. 8196 * 0b1..Parity error. 8197 */ 8198 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) 8199 #define LPUART_STAT_FE_MASK (0x20000U) 8200 #define LPUART_STAT_FE_SHIFT (17U) 8201 /*! FE - Framing Error Flag 8202 * 0b0..No framing error detected. This does not guarantee the framing is correct. 8203 * 0b1..Framing error. 8204 */ 8205 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) 8206 #define LPUART_STAT_NF_MASK (0x40000U) 8207 #define LPUART_STAT_NF_SHIFT (18U) 8208 /*! NF - Noise Flag 8209 * 0b0..No noise detected. 8210 * 0b1..Noise detected in the received character in LPUART_DATA. 8211 */ 8212 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) 8213 #define LPUART_STAT_OR_MASK (0x80000U) 8214 #define LPUART_STAT_OR_SHIFT (19U) 8215 /*! OR - Receiver Overrun Flag 8216 * 0b0..No overrun. 8217 * 0b1..Receive overrun (new LPUART data lost). 8218 */ 8219 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) 8220 #define LPUART_STAT_IDLE_MASK (0x100000U) 8221 #define LPUART_STAT_IDLE_SHIFT (20U) 8222 /*! IDLE - Idle Line Flag 8223 * 0b0..No idle line detected. 8224 * 0b1..Idle line was detected. 8225 */ 8226 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) 8227 #define LPUART_STAT_RDRF_MASK (0x200000U) 8228 #define LPUART_STAT_RDRF_SHIFT (21U) 8229 /*! RDRF - Receive Data Register Full Flag 8230 * 0b0..Receive data buffer empty. 8231 * 0b1..Receive data buffer full. 8232 */ 8233 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) 8234 #define LPUART_STAT_TC_MASK (0x400000U) 8235 #define LPUART_STAT_TC_SHIFT (22U) 8236 /*! TC - Transmission Complete Flag 8237 * 0b0..Transmitter active (sending data, a preamble, or a break). 8238 * 0b1..Transmitter idle (transmission activity complete). 8239 */ 8240 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) 8241 #define LPUART_STAT_TDRE_MASK (0x800000U) 8242 #define LPUART_STAT_TDRE_SHIFT (23U) 8243 /*! TDRE - Transmit Data Register Empty Flag 8244 * 0b0..Transmit data buffer full. 8245 * 0b1..Transmit data buffer empty. 8246 */ 8247 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) 8248 #define LPUART_STAT_RAF_MASK (0x1000000U) 8249 #define LPUART_STAT_RAF_SHIFT (24U) 8250 /*! RAF - Receiver Active Flag 8251 * 0b0..LPUART receiver idle waiting for a start bit. 8252 * 0b1..LPUART receiver active (LPUART_RX input not idle). 8253 */ 8254 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) 8255 #define LPUART_STAT_LBKDE_MASK (0x2000000U) 8256 #define LPUART_STAT_LBKDE_SHIFT (25U) 8257 /*! LBKDE - LIN Break Detection Enable 8258 * 0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 8259 * 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). 8260 * 0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M 8261 * = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). 8262 */ 8263 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) 8264 #define LPUART_STAT_BRK13_MASK (0x4000000U) 8265 #define LPUART_STAT_BRK13_SHIFT (26U) 8266 /*! BRK13 - Break Character Generation Length 8267 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 8268 * or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). 8269 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 8270 * or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). 8271 */ 8272 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) 8273 #define LPUART_STAT_RWUID_MASK (0x8000000U) 8274 #define LPUART_STAT_RWUID_SHIFT (27U) 8275 /*! RWUID - Receive Wake Up Idle Detect 8276 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle 8277 * character. During address match wakeup, the IDLE bit does not get set when an address does not match. 8278 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During 8279 * address match wakeup, the IDLE bit does get set when an address does not match. 8280 */ 8281 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) 8282 #define LPUART_STAT_RXINV_MASK (0x10000000U) 8283 #define LPUART_STAT_RXINV_SHIFT (28U) 8284 /*! RXINV - Receive Data Inversion 8285 * 0b0..Receive data not inverted. 8286 * 0b1..Receive data inverted. 8287 */ 8288 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) 8289 #define LPUART_STAT_MSBF_MASK (0x20000000U) 8290 #define LPUART_STAT_MSBF_SHIFT (29U) 8291 /*! MSBF - MSB First 8292 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received 8293 * after the start bit is identified as bit0. 8294 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on 8295 * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is 8296 * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 8297 */ 8298 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) 8299 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) 8300 #define LPUART_STAT_RXEDGIF_SHIFT (30U) 8301 /*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag 8302 * 0b0..No active edge on the receive pin has occurred. 8303 * 0b1..An active edge on the receive pin has occurred. 8304 */ 8305 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) 8306 #define LPUART_STAT_LBKDIF_MASK (0x80000000U) 8307 #define LPUART_STAT_LBKDIF_SHIFT (31U) 8308 /*! LBKDIF - LIN Break Detect Interrupt Flag 8309 * 0b0..No LIN break character has been detected. 8310 * 0b1..LIN break character has been detected. 8311 */ 8312 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) 8313 /*! @} */ 8314 8315 /*! @name CTRL - LPUART Control Register */ 8316 /*! @{ */ 8317 #define LPUART_CTRL_PT_MASK (0x1U) 8318 #define LPUART_CTRL_PT_SHIFT (0U) 8319 /*! PT - Parity Type 8320 * 0b0..Even parity. 8321 * 0b1..Odd parity. 8322 */ 8323 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) 8324 #define LPUART_CTRL_PE_MASK (0x2U) 8325 #define LPUART_CTRL_PE_SHIFT (1U) 8326 /*! PE - Parity Enable 8327 * 0b0..No hardware parity generation or checking. 8328 * 0b1..Parity enabled. 8329 */ 8330 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) 8331 #define LPUART_CTRL_ILT_MASK (0x4U) 8332 #define LPUART_CTRL_ILT_SHIFT (2U) 8333 /*! ILT - Idle Line Type Select 8334 * 0b0..Idle character bit count starts after start bit. 8335 * 0b1..Idle character bit count starts after stop bit. 8336 */ 8337 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) 8338 #define LPUART_CTRL_WAKE_MASK (0x8U) 8339 #define LPUART_CTRL_WAKE_SHIFT (3U) 8340 /*! WAKE - Receiver Wakeup Method Select 8341 * 0b0..Configures RWU for idle-line wakeup. 8342 * 0b1..Configures RWU with address-mark wakeup. 8343 */ 8344 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) 8345 #define LPUART_CTRL_M_MASK (0x10U) 8346 #define LPUART_CTRL_M_SHIFT (4U) 8347 /*! M - 9-Bit or 8-Bit Mode Select 8348 * 0b0..Receiver and transmitter use 8-bit data characters. 8349 * 0b1..Receiver and transmitter use 9-bit data characters. 8350 */ 8351 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) 8352 #define LPUART_CTRL_RSRC_MASK (0x20U) 8353 #define LPUART_CTRL_RSRC_SHIFT (5U) 8354 /*! RSRC - Receiver Source Select 8355 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the 8356 * LPUART_RX pin. 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and 8357 * receiver input. 8358 */ 8359 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) 8360 #define LPUART_CTRL_DOZEEN_MASK (0x40U) 8361 #define LPUART_CTRL_DOZEEN_SHIFT (6U) 8362 /*! DOZEEN - Doze Enable 8363 * 0b0..LPUART is enabled in Doze mode. 8364 * 0b1..LPUART is disabled in Doze mode. 8365 */ 8366 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) 8367 #define LPUART_CTRL_LOOPS_MASK (0x80U) 8368 #define LPUART_CTRL_LOOPS_SHIFT (7U) 8369 /*! LOOPS - Loop Mode Select 8370 * 0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins. 8371 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC 8372 * bit). 8373 */ 8374 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) 8375 #define LPUART_CTRL_IDLECFG_MASK (0x700U) 8376 #define LPUART_CTRL_IDLECFG_SHIFT (8U) 8377 /*! IDLECFG - Idle Configuration 8378 * 0b000..1 idle character 8379 * 0b001..2 idle characters 8380 * 0b010..4 idle characters 8381 * 0b011..8 idle characters 8382 * 0b100..16 idle characters 8383 * 0b101..32 idle characters 8384 * 0b110..64 idle characters 8385 * 0b111..128 idle characters 8386 */ 8387 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) 8388 #define LPUART_CTRL_MA2IE_MASK (0x4000U) 8389 #define LPUART_CTRL_MA2IE_SHIFT (14U) 8390 /*! MA2IE - Match 2 Interrupt Enable 8391 * 0b0..MA2F interrupt disabled 8392 * 0b1..MA2F interrupt enabled 8393 */ 8394 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) 8395 #define LPUART_CTRL_MA1IE_MASK (0x8000U) 8396 #define LPUART_CTRL_MA1IE_SHIFT (15U) 8397 /*! MA1IE - Match 1 Interrupt Enable 8398 * 0b0..MA1F interrupt disabled 8399 * 0b1..MA1F interrupt enabled 8400 */ 8401 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) 8402 #define LPUART_CTRL_SBK_MASK (0x10000U) 8403 #define LPUART_CTRL_SBK_SHIFT (16U) 8404 /*! SBK - Send Break 8405 * 0b0..Normal transmitter operation. 8406 * 0b1..Queue break character(s) to be sent. 8407 */ 8408 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) 8409 #define LPUART_CTRL_RWU_MASK (0x20000U) 8410 #define LPUART_CTRL_RWU_SHIFT (17U) 8411 /*! RWU - Receiver Wakeup Control 8412 * 0b0..Normal receiver operation. 8413 * 0b1..LPUART receiver in standby waiting for wakeup condition. 8414 */ 8415 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) 8416 #define LPUART_CTRL_RE_MASK (0x40000U) 8417 #define LPUART_CTRL_RE_SHIFT (18U) 8418 /*! RE - Receiver Enable 8419 * 0b0..Receiver disabled. 8420 * 0b1..Receiver enabled. 8421 */ 8422 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) 8423 #define LPUART_CTRL_TE_MASK (0x80000U) 8424 #define LPUART_CTRL_TE_SHIFT (19U) 8425 /*! TE - Transmitter Enable 8426 * 0b0..Transmitter disabled. 8427 * 0b1..Transmitter enabled. 8428 */ 8429 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) 8430 #define LPUART_CTRL_ILIE_MASK (0x100000U) 8431 #define LPUART_CTRL_ILIE_SHIFT (20U) 8432 /*! ILIE - Idle Line Interrupt Enable 8433 * 0b0..Hardware interrupts from IDLE disabled; use polling. 8434 * 0b1..Hardware interrupt requested when IDLE flag is 1. 8435 */ 8436 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) 8437 #define LPUART_CTRL_RIE_MASK (0x200000U) 8438 #define LPUART_CTRL_RIE_SHIFT (21U) 8439 /*! RIE - Receiver Interrupt Enable 8440 * 0b0..Hardware interrupts from RDRF disabled; use polling. 8441 * 0b1..Hardware interrupt requested when RDRF flag is 1. 8442 */ 8443 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) 8444 #define LPUART_CTRL_TCIE_MASK (0x400000U) 8445 #define LPUART_CTRL_TCIE_SHIFT (22U) 8446 /*! TCIE - Transmission Complete Interrupt Enable for 8447 * 0b0..Hardware interrupts from TC disabled; use polling. 8448 * 0b1..Hardware interrupt requested when TC flag is 1. 8449 */ 8450 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) 8451 #define LPUART_CTRL_TIE_MASK (0x800000U) 8452 #define LPUART_CTRL_TIE_SHIFT (23U) 8453 /*! TIE - Transmit Interrupt Enable 8454 * 0b0..Hardware interrupts from TDRE disabled; use polling. 8455 * 0b1..Hardware interrupt requested when TDRE flag is 1. 8456 */ 8457 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) 8458 #define LPUART_CTRL_PEIE_MASK (0x1000000U) 8459 #define LPUART_CTRL_PEIE_SHIFT (24U) 8460 /*! PEIE - Parity Error Interrupt Enable 8461 * 0b0..PF interrupts disabled; use polling). 8462 * 0b1..Hardware interrupt requested when PF is set. 8463 */ 8464 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) 8465 #define LPUART_CTRL_FEIE_MASK (0x2000000U) 8466 #define LPUART_CTRL_FEIE_SHIFT (25U) 8467 /*! FEIE - Framing Error Interrupt Enable 8468 * 0b0..FE interrupts disabled; use polling. 8469 * 0b1..Hardware interrupt requested when FE is set. 8470 */ 8471 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) 8472 #define LPUART_CTRL_NEIE_MASK (0x4000000U) 8473 #define LPUART_CTRL_NEIE_SHIFT (26U) 8474 /*! NEIE - Noise Error Interrupt Enable 8475 * 0b0..NF interrupts disabled; use polling. 8476 * 0b1..Hardware interrupt requested when NF is set. 8477 */ 8478 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) 8479 #define LPUART_CTRL_ORIE_MASK (0x8000000U) 8480 #define LPUART_CTRL_ORIE_SHIFT (27U) 8481 /*! ORIE - Overrun Interrupt Enable 8482 * 0b0..OR interrupts disabled; use polling. 8483 * 0b1..Hardware interrupt requested when OR is set. 8484 */ 8485 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) 8486 #define LPUART_CTRL_TXINV_MASK (0x10000000U) 8487 #define LPUART_CTRL_TXINV_SHIFT (28U) 8488 /*! TXINV - Transmit Data Inversion 8489 * 0b0..Transmit data not inverted. 8490 * 0b1..Transmit data inverted. 8491 */ 8492 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) 8493 #define LPUART_CTRL_TXDIR_MASK (0x20000000U) 8494 #define LPUART_CTRL_TXDIR_SHIFT (29U) 8495 /*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode 8496 * 0b0..LPUART_TX pin is an input in single-wire mode. 8497 * 0b1..LPUART_TX pin is an output in single-wire mode. 8498 */ 8499 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) 8500 #define LPUART_CTRL_R9T8_MASK (0x40000000U) 8501 #define LPUART_CTRL_R9T8_SHIFT (30U) 8502 /*! R9T8 - Receive Bit 9 / Transmit Bit 8 8503 */ 8504 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) 8505 #define LPUART_CTRL_R8T9_MASK (0x80000000U) 8506 #define LPUART_CTRL_R8T9_SHIFT (31U) 8507 /*! R8T9 - Receive Bit 8 / Transmit Bit 9 8508 */ 8509 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) 8510 /*! @} */ 8511 8512 /*! @name DATA - LPUART Data Register */ 8513 /*! @{ */ 8514 #define LPUART_DATA_R0T0_MASK (0x1U) 8515 #define LPUART_DATA_R0T0_SHIFT (0U) 8516 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) 8517 #define LPUART_DATA_R1T1_MASK (0x2U) 8518 #define LPUART_DATA_R1T1_SHIFT (1U) 8519 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) 8520 #define LPUART_DATA_R2T2_MASK (0x4U) 8521 #define LPUART_DATA_R2T2_SHIFT (2U) 8522 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) 8523 #define LPUART_DATA_R3T3_MASK (0x8U) 8524 #define LPUART_DATA_R3T3_SHIFT (3U) 8525 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) 8526 #define LPUART_DATA_R4T4_MASK (0x10U) 8527 #define LPUART_DATA_R4T4_SHIFT (4U) 8528 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) 8529 #define LPUART_DATA_R5T5_MASK (0x20U) 8530 #define LPUART_DATA_R5T5_SHIFT (5U) 8531 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) 8532 #define LPUART_DATA_R6T6_MASK (0x40U) 8533 #define LPUART_DATA_R6T6_SHIFT (6U) 8534 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) 8535 #define LPUART_DATA_R7T7_MASK (0x80U) 8536 #define LPUART_DATA_R7T7_SHIFT (7U) 8537 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) 8538 #define LPUART_DATA_R8T8_MASK (0x100U) 8539 #define LPUART_DATA_R8T8_SHIFT (8U) 8540 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) 8541 #define LPUART_DATA_R9T9_MASK (0x200U) 8542 #define LPUART_DATA_R9T9_SHIFT (9U) 8543 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) 8544 #define LPUART_DATA_IDLINE_MASK (0x800U) 8545 #define LPUART_DATA_IDLINE_SHIFT (11U) 8546 /*! IDLINE - Idle Line 8547 * 0b0..Receiver was not idle before receiving this character. 8548 * 0b1..Receiver was idle before receiving this character. 8549 */ 8550 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) 8551 #define LPUART_DATA_RXEMPT_MASK (0x1000U) 8552 #define LPUART_DATA_RXEMPT_SHIFT (12U) 8553 /*! RXEMPT - Receive Buffer Empty 8554 * 0b0..Receive buffer contains valid data. 8555 * 0b1..Receive buffer is empty, data returned on read is not valid. 8556 */ 8557 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) 8558 #define LPUART_DATA_FRETSC_MASK (0x2000U) 8559 #define LPUART_DATA_FRETSC_SHIFT (13U) 8560 /*! FRETSC - Frame Error / Transmit Special Character 8561 * 0b0..The dataword was received without a frame error on read, transmit a normal character on write. 8562 * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit. 8563 */ 8564 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) 8565 #define LPUART_DATA_PARITYE_MASK (0x4000U) 8566 #define LPUART_DATA_PARITYE_SHIFT (14U) 8567 /*! PARITYE 8568 * 0b0..The dataword was received without a parity error. 8569 * 0b1..The dataword was received with a parity error. 8570 */ 8571 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) 8572 #define LPUART_DATA_NOISY_MASK (0x8000U) 8573 #define LPUART_DATA_NOISY_SHIFT (15U) 8574 /*! NOISY 8575 * 0b0..The dataword was received without noise. 8576 * 0b1..The data was received with noise. 8577 */ 8578 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) 8579 /*! @} */ 8580 8581 /*! @name MATCH - LPUART Match Address Register */ 8582 /*! @{ */ 8583 #define LPUART_MATCH_MA1_MASK (0x3FFU) 8584 #define LPUART_MATCH_MA1_SHIFT (0U) 8585 /*! MA1 - Match Address 1 8586 */ 8587 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) 8588 #define LPUART_MATCH_MA2_MASK (0x3FF0000U) 8589 #define LPUART_MATCH_MA2_SHIFT (16U) 8590 /*! MA2 - Match Address 2 8591 */ 8592 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) 8593 /*! @} */ 8594 8595 /*! 8596 * @} 8597 */ /* end of group LPUART_Register_Masks */ 8598 8599 /* LPUART - Peripheral instance base addresses */ 8600 /** Peripheral LPUART0 base address */ 8601 #define LPUART0_BASE (0x40054000u) 8602 /** Peripheral LPUART0 base pointer */ 8603 #define LPUART0 ((LPUART_Type *)LPUART0_BASE) 8604 /** Peripheral LPUART1 base address */ 8605 #define LPUART1_BASE (0x40055000u) 8606 /** Peripheral LPUART1 base pointer */ 8607 #define LPUART1 ((LPUART_Type *)LPUART1_BASE) 8608 /** Array initializer of LPUART peripheral base addresses */ 8609 #define LPUART_BASE_ADDRS \ 8610 { \ 8611 LPUART0_BASE, LPUART1_BASE \ 8612 } 8613 /** Array initializer of LPUART peripheral base pointers */ 8614 #define LPUART_BASE_PTRS \ 8615 { \ 8616 LPUART0, LPUART1 \ 8617 } 8618 /** Interrupt vectors for the LPUART peripheral type */ 8619 #define LPUART_RX_TX_IRQS \ 8620 { \ 8621 LPUART0_IRQn, LPUART1_IRQn \ 8622 } 8623 #define LPUART_ERR_IRQS \ 8624 { \ 8625 LPUART0_IRQn, LPUART1_IRQn \ 8626 } 8627 8628 /*! 8629 * @} 8630 */ /* end of group LPUART_Peripheral_Access_Layer */ 8631 8632 /* ---------------------------------------------------------------------------- 8633 -- MCG Peripheral Access Layer 8634 ---------------------------------------------------------------------------- */ 8635 8636 /*! 8637 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 8638 * @{ 8639 */ 8640 8641 /** MCG - Register Layout Typedef */ 8642 typedef struct 8643 { 8644 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */ 8645 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */ 8646 uint8_t RESERVED_0[4]; 8647 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ 8648 uint8_t RESERVED_1[1]; 8649 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 8650 uint8_t RESERVED_2[15]; 8651 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */ 8652 } MCG_Type; 8653 8654 /* ---------------------------------------------------------------------------- 8655 -- MCG Register Masks 8656 ---------------------------------------------------------------------------- */ 8657 8658 /*! 8659 * @addtogroup MCG_Register_Masks MCG Register Masks 8660 * @{ 8661 */ 8662 8663 /*! @name C1 - MCG Control Register 1 */ 8664 /*! @{ */ 8665 #define MCG_C1_IREFSTEN_MASK (0x1U) 8666 #define MCG_C1_IREFSTEN_SHIFT (0U) 8667 /*! IREFSTEN - Internal Reference Stop Enable 8668 * 0b0..LIRC is disabled in Stop mode. 8669 * 0b1..LIRC is enabled in Stop mode, if IRCLKEN is set. 8670 */ 8671 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 8672 #define MCG_C1_IRCLKEN_MASK (0x2U) 8673 #define MCG_C1_IRCLKEN_SHIFT (1U) 8674 /*! IRCLKEN - Internal Reference Clock Enable 8675 * 0b0..LIRC is disabled. 8676 * 0b1..LIRC is enabled. 8677 */ 8678 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 8679 #define MCG_C1_CLKS_MASK (0xC0U) 8680 #define MCG_C1_CLKS_SHIFT (6U) 8681 /*! CLKS - Clock Source Select 8682 * 0b00..Selects HIRC clock as the main clock source. This is HIRC mode. 8683 * 0b01..Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode. 8684 * 0b10..Selects external clock as the main clock source. This is EXT mode. 8685 * 0b11..Reserved. Writing 11 takes no effect. 8686 */ 8687 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 8688 /*! @} */ 8689 8690 /*! @name C2 - MCG Control Register 2 */ 8691 /*! @{ */ 8692 #define MCG_C2_IRCS_MASK (0x1U) 8693 #define MCG_C2_IRCS_SHIFT (0U) 8694 /*! IRCS - Low-frequency Internal Reference Clock Select 8695 * 0b0..LIRC is in 2 MHz mode. 8696 * 0b1..LIRC is in 8 MHz mode. 8697 */ 8698 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 8699 #define MCG_C2_EREFS0_MASK (0x4U) 8700 #define MCG_C2_EREFS0_SHIFT (2U) 8701 /*! EREFS0 - External Clock Source Select 8702 * 0b0..External clock requested. 8703 * 0b1..Oscillator requested. 8704 */ 8705 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) 8706 #define MCG_C2_HGO0_MASK (0x8U) 8707 #define MCG_C2_HGO0_SHIFT (3U) 8708 /*! HGO0 - Crystal Oscillator Operation Mode Select 8709 * 0b0..Configure crystal oscillator for low-power operation. 8710 * 0b1..Configure crystal oscillator for high-gain operation. 8711 */ 8712 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) 8713 #define MCG_C2_RANGE0_MASK (0x30U) 8714 #define MCG_C2_RANGE0_SHIFT (4U) 8715 /*! RANGE0 - External Clock Source Frequency Range Select 8716 * 0b00..Low frequency range selected for the crystal oscillator or the external clock source. 8717 * 0b01..High frequency range selected for the crystal oscillator or the external clock source. 8718 * 0b10..Very high frequency range selected for the crystal oscillator or the external clock source. 8719 * 0b11..Very high frequency range selected for the crystal oscillator or the external clock source. Same effect as 10. 8720 */ 8721 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) 8722 /*! @} */ 8723 8724 /*! @name S - MCG Status Register */ 8725 /*! @{ */ 8726 #define MCG_S_OSCINIT0_MASK (0x2U) 8727 #define MCG_S_OSCINIT0_SHIFT (1U) 8728 /*! OSCINIT0 - OSC Initialization Status 8729 * 0b0..OSC is not ready. 8730 * 0b1..OSC clock is ready. 8731 */ 8732 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 8733 #define MCG_S_CLKST_MASK (0xCU) 8734 #define MCG_S_CLKST_SHIFT (2U) 8735 /*! CLKST - Clock Mode Status 8736 * 0b00..HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode. 8737 * 0b01..LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode. 8738 * 0b10..External clock is selected as the main clock source, and MCG_Lite works at EXT mode. 8739 * 0b11..Reserved. 8740 */ 8741 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 8742 /*! @} */ 8743 8744 /*! @name SC - MCG Status and Control Register */ 8745 /*! @{ */ 8746 #define MCG_SC_FCRDIV_MASK (0xEU) 8747 #define MCG_SC_FCRDIV_SHIFT (1U) 8748 /*! FCRDIV - Low-frequency Internal Reference Clock Divider 8749 * 0b000..Division factor is 1. 8750 * 0b001..Division factor is 2. 8751 * 0b010..Division factor is 4. 8752 * 0b011..Division factor is 8. 8753 * 0b100..Division factor is 16. 8754 * 0b101..Division factor is 32. 8755 * 0b110..Division factor is 64. 8756 * 0b111..Division factor is 128. 8757 */ 8758 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 8759 /*! @} */ 8760 8761 /*! @name MC - MCG Miscellaneous Control Register */ 8762 /*! @{ */ 8763 #define MCG_MC_LIRC_DIV2_MASK (0x7U) 8764 #define MCG_MC_LIRC_DIV2_SHIFT (0U) 8765 /*! LIRC_DIV2 - Second Low-frequency Internal Reference Clock Divider 8766 * 0b000..Division factor is 1. 8767 * 0b001..Division factor is 2. 8768 * 0b010..Division factor is 4. 8769 * 0b011..Division factor is 8. 8770 * 0b100..Division factor is 16. 8771 * 0b101..Division factor is 32. 8772 * 0b110..Division factor is 64. 8773 * 0b111..Division factor is 128. 8774 */ 8775 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK) 8776 #define MCG_MC_HIRCEN_MASK (0x80U) 8777 #define MCG_MC_HIRCEN_SHIFT (7U) 8778 /*! HIRCEN - High-frequency IRC Enable 8779 * 0b0..HIRC source is not enabled. 8780 * 0b1..HIRC source is enabled. 8781 */ 8782 #define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK) 8783 /*! @} */ 8784 8785 /*! 8786 * @} 8787 */ /* end of group MCG_Register_Masks */ 8788 8789 /* MCG - Peripheral instance base addresses */ 8790 /** Peripheral MCG base address */ 8791 #define MCG_BASE (0x40064000u) 8792 /** Peripheral MCG base pointer */ 8793 #define MCG ((MCG_Type *)MCG_BASE) 8794 /** Array initializer of MCG peripheral base addresses */ 8795 #define MCG_BASE_ADDRS \ 8796 { \ 8797 MCG_BASE \ 8798 } 8799 /** Array initializer of MCG peripheral base pointers */ 8800 #define MCG_BASE_PTRS \ 8801 { \ 8802 MCG \ 8803 } 8804 8805 /*! 8806 * @} 8807 */ /* end of group MCG_Peripheral_Access_Layer */ 8808 8809 /* ---------------------------------------------------------------------------- 8810 -- MCM Peripheral Access Layer 8811 ---------------------------------------------------------------------------- */ 8812 8813 /*! 8814 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 8815 * @{ 8816 */ 8817 8818 /** MCM - Register Layout Typedef */ 8819 typedef struct 8820 { 8821 uint8_t RESERVED_0[8]; 8822 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 8823 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 8824 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 8825 uint8_t RESERVED_1[48]; 8826 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 8827 } MCM_Type; 8828 8829 /* ---------------------------------------------------------------------------- 8830 -- MCM Register Masks 8831 ---------------------------------------------------------------------------- */ 8832 8833 /*! 8834 * @addtogroup MCM_Register_Masks MCM Register Masks 8835 * @{ 8836 */ 8837 8838 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 8839 /*! @{ */ 8840 #define MCM_PLASC_ASC_MASK (0xFFU) 8841 #define MCM_PLASC_ASC_SHIFT (0U) 8842 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the 8843 * crossbar switch's slave input port. 8844 * 0b00000000..A bus slave connection to AXBS input port n is absent. 8845 * 0b00000001..A bus slave connection to AXBS input port n is present. 8846 */ 8847 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 8848 /*! @} */ 8849 8850 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 8851 /*! @{ */ 8852 #define MCM_PLAMC_AMC_MASK (0xFFU) 8853 #define MCM_PLAMC_AMC_SHIFT (0U) 8854 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 8855 * 0b00000000..A bus master connection to AXBS input port n is absent 8856 * 0b00000001..A bus master connection to AXBS input port n is present 8857 */ 8858 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 8859 /*! @} */ 8860 8861 /*! @name PLACR - Platform Control Register */ 8862 /*! @{ */ 8863 #define MCM_PLACR_ARB_MASK (0x200U) 8864 #define MCM_PLACR_ARB_SHIFT (9U) 8865 /*! ARB - Arbitration select 8866 * 0b0..Fixed-priority arbitration for the crossbar masters 8867 * 0b1..Round-robin arbitration for the crossbar masters 8868 */ 8869 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 8870 #define MCM_PLACR_CFCC_MASK (0x400U) 8871 #define MCM_PLACR_CFCC_SHIFT (10U) 8872 /*! CFCC - Clear Flash Controller Cache 8873 */ 8874 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 8875 #define MCM_PLACR_DFCDA_MASK (0x800U) 8876 #define MCM_PLACR_DFCDA_SHIFT (11U) 8877 /*! DFCDA - Disable Flash Controller Data Caching 8878 * 0b0..Enable flash controller data caching 8879 * 0b1..Disable flash controller data caching. 8880 */ 8881 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 8882 #define MCM_PLACR_DFCIC_MASK (0x1000U) 8883 #define MCM_PLACR_DFCIC_SHIFT (12U) 8884 /*! DFCIC - Disable Flash Controller Instruction Caching 8885 * 0b0..Enable flash controller instruction caching. 8886 * 0b1..Disable flash controller instruction caching. 8887 */ 8888 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 8889 #define MCM_PLACR_DFCC_MASK (0x2000U) 8890 #define MCM_PLACR_DFCC_SHIFT (13U) 8891 /*! DFCC - Disable Flash Controller Cache 8892 * 0b0..Enable flash controller cache. 8893 * 0b1..Disable flash controller cache. 8894 */ 8895 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 8896 #define MCM_PLACR_EFDS_MASK (0x4000U) 8897 #define MCM_PLACR_EFDS_SHIFT (14U) 8898 /*! EFDS - Enable Flash Data Speculation 8899 * 0b0..Disable flash data speculation. 8900 * 0b1..Enable flash data speculation. 8901 */ 8902 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 8903 #define MCM_PLACR_DFCS_MASK (0x8000U) 8904 #define MCM_PLACR_DFCS_SHIFT (15U) 8905 /*! DFCS - Disable Flash Controller Speculation 8906 * 0b0..Enable flash controller speculation. 8907 * 0b1..Disable flash controller speculation. 8908 */ 8909 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 8910 #define MCM_PLACR_ESFC_MASK (0x10000U) 8911 #define MCM_PLACR_ESFC_SHIFT (16U) 8912 /*! ESFC - Enable Stalling Flash Controller 8913 * 0b0..Disable stalling flash controller when flash is busy. 8914 * 0b1..Enable stalling flash controller when flash is busy. 8915 */ 8916 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 8917 /*! @} */ 8918 8919 /*! @name CPO - Compute Operation Control Register */ 8920 /*! @{ */ 8921 #define MCM_CPO_CPOREQ_MASK (0x1U) 8922 #define MCM_CPO_CPOREQ_SHIFT (0U) 8923 /*! CPOREQ - Compute Operation Request 8924 * 0b0..Request is cleared. 8925 * 0b1..Request Compute Operation. 8926 */ 8927 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 8928 #define MCM_CPO_CPOACK_MASK (0x2U) 8929 #define MCM_CPO_CPOACK_SHIFT (1U) 8930 /*! CPOACK - Compute Operation Acknowledge 8931 * 0b0..Compute operation entry has not completed or compute operation exit has completed. 8932 * 0b1..Compute operation entry has completed or compute operation exit has not completed. 8933 */ 8934 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 8935 #define MCM_CPO_CPOWOI_MASK (0x4U) 8936 #define MCM_CPO_CPOWOI_SHIFT (2U) 8937 /*! CPOWOI - Compute Operation Wake-up on Interrupt 8938 * 0b0..No effect. 8939 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 8940 */ 8941 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 8942 /*! @} */ 8943 8944 /*! 8945 * @} 8946 */ /* end of group MCM_Register_Masks */ 8947 8948 /* MCM - Peripheral instance base addresses */ 8949 /** Peripheral MCM base address */ 8950 #define MCM_BASE (0xF0003000u) 8951 /** Peripheral MCM base pointer */ 8952 #define MCM ((MCM_Type *)MCM_BASE) 8953 /** Array initializer of MCM peripheral base addresses */ 8954 #define MCM_BASE_ADDRS \ 8955 { \ 8956 MCM_BASE \ 8957 } 8958 /** Array initializer of MCM peripheral base pointers */ 8959 #define MCM_BASE_PTRS \ 8960 { \ 8961 MCM \ 8962 } 8963 8964 /*! 8965 * @} 8966 */ /* end of group MCM_Peripheral_Access_Layer */ 8967 8968 /* ---------------------------------------------------------------------------- 8969 -- MTB Peripheral Access Layer 8970 ---------------------------------------------------------------------------- */ 8971 8972 /*! 8973 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 8974 * @{ 8975 */ 8976 8977 /** MTB - Register Layout Typedef */ 8978 typedef struct 8979 { 8980 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 8981 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 8982 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 8983 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 8984 uint8_t RESERVED_0[3824]; 8985 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 8986 uint8_t RESERVED_1[156]; 8987 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 8988 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 8989 uint8_t RESERVED_2[8]; 8990 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 8991 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 8992 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 8993 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 8994 uint8_t RESERVED_3[8]; 8995 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 8996 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 8997 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 8998 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 8999 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 9000 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 9001 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 9002 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 9003 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 9004 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 9005 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 9006 } MTB_Type; 9007 9008 /* ---------------------------------------------------------------------------- 9009 -- MTB Register Masks 9010 ---------------------------------------------------------------------------- */ 9011 9012 /*! 9013 * @addtogroup MTB_Register_Masks MTB Register Masks 9014 * @{ 9015 */ 9016 9017 /*! @name POSITION - MTB Position Register */ 9018 /*! @{ */ 9019 #define MTB_POSITION_WRAP_MASK (0x4U) 9020 #define MTB_POSITION_WRAP_SHIFT (2U) 9021 /*! WRAP - WRAP 9022 */ 9023 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 9024 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 9025 #define MTB_POSITION_POINTER_SHIFT (3U) 9026 /*! POINTER - Trace Packet Address Pointer[28:0] 9027 */ 9028 #define MTB_POSITION_POINTER(x) \ 9029 (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 9030 /*! @} */ 9031 9032 /*! @name MASTER - MTB Master Register */ 9033 /*! @{ */ 9034 #define MTB_MASTER_MASK_MASK (0x1FU) 9035 #define MTB_MASTER_MASK_SHIFT (0U) 9036 /*! MASK - Mask 9037 */ 9038 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 9039 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 9040 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 9041 /*! TSTARTEN - Trace Start Input Enable 9042 */ 9043 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 9044 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 9045 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 9046 /*! TSTOPEN - Trace Stop Input Enable 9047 */ 9048 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 9049 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 9050 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 9051 /*! SFRWPRIV - Special Function Register Write Privilege 9052 */ 9053 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 9054 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 9055 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 9056 /*! RAMPRIV - RAM Privilege 9057 */ 9058 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 9059 #define MTB_MASTER_HALTREQ_MASK (0x200U) 9060 #define MTB_MASTER_HALTREQ_SHIFT (9U) 9061 /*! HALTREQ - Halt Request 9062 */ 9063 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 9064 #define MTB_MASTER_EN_MASK (0x80000000U) 9065 #define MTB_MASTER_EN_SHIFT (31U) 9066 /*! EN - Main Trace Enable 9067 */ 9068 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 9069 /*! @} */ 9070 9071 /*! @name FLOW - MTB Flow Register */ 9072 /*! @{ */ 9073 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 9074 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 9075 /*! AUTOSTOP - AUTOSTOP 9076 */ 9077 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 9078 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 9079 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 9080 /*! AUTOHALT - AUTOHALT 9081 */ 9082 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 9083 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 9084 #define MTB_FLOW_WATERMARK_SHIFT (3U) 9085 /*! WATERMARK - WATERMARK[28:0] 9086 */ 9087 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 9088 /*! @} */ 9089 9090 /*! @name BASE - MTB Base Register */ 9091 /*! @{ */ 9092 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 9093 #define MTB_BASE_BASEADDR_SHIFT (0U) 9094 /*! BASEADDR - BASEADDR 9095 */ 9096 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 9097 /*! @} */ 9098 9099 /*! @name MODECTRL - Integration Mode Control Register */ 9100 /*! @{ */ 9101 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 9102 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 9103 /*! MODECTRL - MODECTRL 9104 */ 9105 #define MTB_MODECTRL_MODECTRL(x) \ 9106 (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 9107 /*! @} */ 9108 9109 /*! @name TAGSET - Claim TAG Set Register */ 9110 /*! @{ */ 9111 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 9112 #define MTB_TAGSET_TAGSET_SHIFT (0U) 9113 /*! TAGSET - TAGSET 9114 */ 9115 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 9116 /*! @} */ 9117 9118 /*! @name TAGCLEAR - Claim TAG Clear Register */ 9119 /*! @{ */ 9120 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 9121 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 9122 /*! TAGCLEAR - TAGCLEAR 9123 */ 9124 #define MTB_TAGCLEAR_TAGCLEAR(x) \ 9125 (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 9126 /*! @} */ 9127 9128 /*! @name LOCKACCESS - Lock Access Register */ 9129 /*! @{ */ 9130 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 9131 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 9132 #define MTB_LOCKACCESS_LOCKACCESS(x) \ 9133 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 9134 /*! @} */ 9135 9136 /*! @name LOCKSTAT - Lock Status Register */ 9137 /*! @{ */ 9138 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 9139 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 9140 /*! LOCKSTAT - LOCKSTAT 9141 */ 9142 #define MTB_LOCKSTAT_LOCKSTAT(x) \ 9143 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 9144 /*! @} */ 9145 9146 /*! @name AUTHSTAT - Authentication Status Register */ 9147 /*! @{ */ 9148 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 9149 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 9150 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 9151 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 9152 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 9153 /*! BIT2 - BIT2 9154 */ 9155 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 9156 /*! @} */ 9157 9158 /*! @name DEVICEARCH - Device Architecture Register */ 9159 /*! @{ */ 9160 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 9161 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 9162 /*! DEVICEARCH - DEVICEARCH 9163 */ 9164 #define MTB_DEVICEARCH_DEVICEARCH(x) \ 9165 (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 9166 /*! @} */ 9167 9168 /*! @name DEVICECFG - Device Configuration Register */ 9169 /*! @{ */ 9170 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 9171 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 9172 /*! DEVICECFG - DEVICECFG 9173 */ 9174 #define MTB_DEVICECFG_DEVICECFG(x) \ 9175 (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 9176 /*! @} */ 9177 9178 /*! @name DEVICETYPID - Device Type Identifier Register */ 9179 /*! @{ */ 9180 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 9181 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 9182 /*! DEVICETYPID - DEVICETYPID 9183 */ 9184 #define MTB_DEVICETYPID_DEVICETYPID(x) \ 9185 (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 9186 /*! @} */ 9187 9188 /*! @name PERIPHID4 - Peripheral ID Register */ 9189 /*! @{ */ 9190 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 9191 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 9192 /*! PERIPHID - PERIPHID 9193 */ 9194 #define MTB_PERIPHID4_PERIPHID(x) \ 9195 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 9196 /*! @} */ 9197 9198 /*! @name PERIPHID5 - Peripheral ID Register */ 9199 /*! @{ */ 9200 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 9201 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 9202 /*! PERIPHID - PERIPHID 9203 */ 9204 #define MTB_PERIPHID5_PERIPHID(x) \ 9205 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 9206 /*! @} */ 9207 9208 /*! @name PERIPHID6 - Peripheral ID Register */ 9209 /*! @{ */ 9210 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 9211 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 9212 /*! PERIPHID - PERIPHID 9213 */ 9214 #define MTB_PERIPHID6_PERIPHID(x) \ 9215 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 9216 /*! @} */ 9217 9218 /*! @name PERIPHID7 - Peripheral ID Register */ 9219 /*! @{ */ 9220 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 9221 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 9222 /*! PERIPHID - PERIPHID 9223 */ 9224 #define MTB_PERIPHID7_PERIPHID(x) \ 9225 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 9226 /*! @} */ 9227 9228 /*! @name PERIPHID0 - Peripheral ID Register */ 9229 /*! @{ */ 9230 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 9231 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 9232 /*! PERIPHID - PERIPHID 9233 */ 9234 #define MTB_PERIPHID0_PERIPHID(x) \ 9235 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 9236 /*! @} */ 9237 9238 /*! @name PERIPHID1 - Peripheral ID Register */ 9239 /*! @{ */ 9240 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 9241 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 9242 /*! PERIPHID - PERIPHID 9243 */ 9244 #define MTB_PERIPHID1_PERIPHID(x) \ 9245 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 9246 /*! @} */ 9247 9248 /*! @name PERIPHID2 - Peripheral ID Register */ 9249 /*! @{ */ 9250 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 9251 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 9252 /*! PERIPHID - PERIPHID 9253 */ 9254 #define MTB_PERIPHID2_PERIPHID(x) \ 9255 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 9256 /*! @} */ 9257 9258 /*! @name PERIPHID3 - Peripheral ID Register */ 9259 /*! @{ */ 9260 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 9261 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 9262 /*! PERIPHID - PERIPHID 9263 */ 9264 #define MTB_PERIPHID3_PERIPHID(x) \ 9265 (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 9266 /*! @} */ 9267 9268 /*! @name COMPID - Component ID Register */ 9269 /*! @{ */ 9270 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 9271 #define MTB_COMPID_COMPID_SHIFT (0U) 9272 /*! COMPID - Component ID 9273 */ 9274 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 9275 /*! @} */ 9276 9277 /* The count of MTB_COMPID */ 9278 #define MTB_COMPID_COUNT (4U) 9279 9280 /*! 9281 * @} 9282 */ /* end of group MTB_Register_Masks */ 9283 9284 /* MTB - Peripheral instance base addresses */ 9285 /** Peripheral MTB base address */ 9286 #define MTB_BASE (0xF0000000u) 9287 /** Peripheral MTB base pointer */ 9288 #define MTB ((MTB_Type *)MTB_BASE) 9289 /** Array initializer of MTB peripheral base addresses */ 9290 #define MTB_BASE_ADDRS \ 9291 { \ 9292 MTB_BASE \ 9293 } 9294 /** Array initializer of MTB peripheral base pointers */ 9295 #define MTB_BASE_PTRS \ 9296 { \ 9297 MTB \ 9298 } 9299 9300 /*! 9301 * @} 9302 */ /* end of group MTB_Peripheral_Access_Layer */ 9303 9304 /* ---------------------------------------------------------------------------- 9305 -- MTBDWT Peripheral Access Layer 9306 ---------------------------------------------------------------------------- */ 9307 9308 /*! 9309 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 9310 * @{ 9311 */ 9312 9313 /** MTBDWT - Register Layout Typedef */ 9314 typedef struct 9315 { 9316 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 9317 uint8_t RESERVED_0[28]; 9318 struct 9319 { /* offset: 0x20, array step: 0x10 */ 9320 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 9321 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 9322 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array 9323 offset: 0x28, array step: 0x10 */ 9324 uint8_t RESERVED_0[4]; 9325 } COMPARATOR[2]; 9326 uint8_t RESERVED_1[448]; 9327 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 9328 uint8_t RESERVED_2[3524]; 9329 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 9330 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 9331 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 9332 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 9333 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 9334 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 9335 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 9336 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 9337 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 9338 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 9339 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 9340 } MTBDWT_Type; 9341 9342 /* ---------------------------------------------------------------------------- 9343 -- MTBDWT Register Masks 9344 ---------------------------------------------------------------------------- */ 9345 9346 /*! 9347 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 9348 * @{ 9349 */ 9350 9351 /*! @name CTRL - MTB DWT Control Register */ 9352 /*! @{ */ 9353 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 9354 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 9355 /*! DWTCFGCTRL - DWT configuration controls 9356 */ 9357 #define MTBDWT_CTRL_DWTCFGCTRL(x) \ 9358 (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 9359 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 9360 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 9361 /*! NUMCMP - Number of comparators 9362 */ 9363 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 9364 /*! @} */ 9365 9366 /*! @name COMP - MTB_DWT Comparator Register */ 9367 /*! @{ */ 9368 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 9369 #define MTBDWT_COMP_COMP_SHIFT (0U) 9370 /*! COMP - Reference value for comparison 9371 */ 9372 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 9373 /*! @} */ 9374 9375 /* The count of MTBDWT_COMP */ 9376 #define MTBDWT_COMP_COUNT (2U) 9377 9378 /*! @name MASK - MTB_DWT Comparator Mask Register */ 9379 /*! @{ */ 9380 #define MTBDWT_MASK_MASK_MASK (0x1FU) 9381 #define MTBDWT_MASK_MASK_SHIFT (0U) 9382 /*! MASK - MASK 9383 */ 9384 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 9385 /*! @} */ 9386 9387 /* The count of MTBDWT_MASK */ 9388 #define MTBDWT_MASK_COUNT (2U) 9389 9390 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 9391 /*! @{ */ 9392 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 9393 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 9394 /*! FUNCTION - Function 9395 * 0b0000..Disabled. 9396 * 0b0100..Instruction fetch. 9397 * 0b0101..Data operand read. 9398 * 0b0110..Data operand write. 9399 * 0b0111..Data operand (read + write). 9400 */ 9401 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 9402 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 9403 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 9404 /*! DATAVMATCH - Data Value Match 9405 * 0b0..Perform address comparison. 9406 * 0b1..Perform data value comparison. 9407 */ 9408 #define MTBDWT_FCT_DATAVMATCH(x) \ 9409 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 9410 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 9411 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 9412 /*! DATAVSIZE - Data Value Size 9413 * 0b00..Byte. 9414 * 0b01..Halfword. 9415 * 0b10..Word. 9416 * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. 9417 */ 9418 #define MTBDWT_FCT_DATAVSIZE(x) \ 9419 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 9420 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 9421 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 9422 /*! DATAVADDR0 - Data Value Address 0 9423 */ 9424 #define MTBDWT_FCT_DATAVADDR0(x) \ 9425 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 9426 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 9427 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 9428 /*! MATCHED - Comparator match 9429 * 0b0..No match. 9430 * 0b1..Match occurred. 9431 */ 9432 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 9433 /*! @} */ 9434 9435 /* The count of MTBDWT_FCT */ 9436 #define MTBDWT_FCT_COUNT (2U) 9437 9438 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 9439 /*! @{ */ 9440 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 9441 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 9442 /*! ACOMP0 - Action based on Comparator 0 match 9443 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. 9444 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. 9445 */ 9446 #define MTBDWT_TBCTRL_ACOMP0(x) \ 9447 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 9448 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 9449 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 9450 /*! ACOMP1 - Action based on Comparator 1 match 9451 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. 9452 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. 9453 */ 9454 #define MTBDWT_TBCTRL_ACOMP1(x) \ 9455 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 9456 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 9457 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 9458 /*! NUMCOMP - Number of Comparators 9459 */ 9460 #define MTBDWT_TBCTRL_NUMCOMP(x) \ 9461 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 9462 /*! @} */ 9463 9464 /*! @name DEVICECFG - Device Configuration Register */ 9465 /*! @{ */ 9466 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 9467 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 9468 /*! DEVICECFG - DEVICECFG 9469 */ 9470 #define MTBDWT_DEVICECFG_DEVICECFG(x) \ 9471 (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 9472 /*! @} */ 9473 9474 /*! @name DEVICETYPID - Device Type Identifier Register */ 9475 /*! @{ */ 9476 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 9477 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 9478 /*! DEVICETYPID - DEVICETYPID 9479 */ 9480 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) \ 9481 (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 9482 /*! @} */ 9483 9484 /*! @name PERIPHID4 - Peripheral ID Register */ 9485 /*! @{ */ 9486 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 9487 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 9488 /*! PERIPHID - PERIPHID 9489 */ 9490 #define MTBDWT_PERIPHID4_PERIPHID(x) \ 9491 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 9492 /*! @} */ 9493 9494 /*! @name PERIPHID5 - Peripheral ID Register */ 9495 /*! @{ */ 9496 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 9497 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 9498 /*! PERIPHID - PERIPHID 9499 */ 9500 #define MTBDWT_PERIPHID5_PERIPHID(x) \ 9501 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 9502 /*! @} */ 9503 9504 /*! @name PERIPHID6 - Peripheral ID Register */ 9505 /*! @{ */ 9506 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 9507 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 9508 /*! PERIPHID - PERIPHID 9509 */ 9510 #define MTBDWT_PERIPHID6_PERIPHID(x) \ 9511 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 9512 /*! @} */ 9513 9514 /*! @name PERIPHID7 - Peripheral ID Register */ 9515 /*! @{ */ 9516 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 9517 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 9518 /*! PERIPHID - PERIPHID 9519 */ 9520 #define MTBDWT_PERIPHID7_PERIPHID(x) \ 9521 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 9522 /*! @} */ 9523 9524 /*! @name PERIPHID0 - Peripheral ID Register */ 9525 /*! @{ */ 9526 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 9527 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 9528 /*! PERIPHID - PERIPHID 9529 */ 9530 #define MTBDWT_PERIPHID0_PERIPHID(x) \ 9531 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 9532 /*! @} */ 9533 9534 /*! @name PERIPHID1 - Peripheral ID Register */ 9535 /*! @{ */ 9536 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 9537 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 9538 /*! PERIPHID - PERIPHID 9539 */ 9540 #define MTBDWT_PERIPHID1_PERIPHID(x) \ 9541 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 9542 /*! @} */ 9543 9544 /*! @name PERIPHID2 - Peripheral ID Register */ 9545 /*! @{ */ 9546 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 9547 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 9548 /*! PERIPHID - PERIPHID 9549 */ 9550 #define MTBDWT_PERIPHID2_PERIPHID(x) \ 9551 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 9552 /*! @} */ 9553 9554 /*! @name PERIPHID3 - Peripheral ID Register */ 9555 /*! @{ */ 9556 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 9557 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 9558 /*! PERIPHID - PERIPHID 9559 */ 9560 #define MTBDWT_PERIPHID3_PERIPHID(x) \ 9561 (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 9562 /*! @} */ 9563 9564 /*! @name COMPID - Component ID Register */ 9565 /*! @{ */ 9566 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 9567 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 9568 /*! COMPID - Component ID 9569 */ 9570 #define MTBDWT_COMPID_COMPID(x) \ 9571 (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 9572 /*! @} */ 9573 9574 /* The count of MTBDWT_COMPID */ 9575 #define MTBDWT_COMPID_COUNT (4U) 9576 9577 /*! 9578 * @} 9579 */ /* end of group MTBDWT_Register_Masks */ 9580 9581 /* MTBDWT - Peripheral instance base addresses */ 9582 /** Peripheral MTBDWT base address */ 9583 #define MTBDWT_BASE (0xF0001000u) 9584 /** Peripheral MTBDWT base pointer */ 9585 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 9586 /** Array initializer of MTBDWT peripheral base addresses */ 9587 #define MTBDWT_BASE_ADDRS \ 9588 { \ 9589 MTBDWT_BASE \ 9590 } 9591 /** Array initializer of MTBDWT peripheral base pointers */ 9592 #define MTBDWT_BASE_PTRS \ 9593 { \ 9594 MTBDWT \ 9595 } 9596 9597 /*! 9598 * @} 9599 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 9600 9601 /* ---------------------------------------------------------------------------- 9602 -- NV Peripheral Access Layer 9603 ---------------------------------------------------------------------------- */ 9604 9605 /*! 9606 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 9607 * @{ 9608 */ 9609 9610 /** NV - Register Layout Typedef */ 9611 typedef struct 9612 { 9613 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 9614 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 9615 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 9616 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 9617 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 9618 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 9619 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 9620 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 9621 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 9622 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 9623 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 9624 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 9625 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 9626 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 9627 } NV_Type; 9628 9629 /* ---------------------------------------------------------------------------- 9630 -- NV Register Masks 9631 ---------------------------------------------------------------------------- */ 9632 9633 /*! 9634 * @addtogroup NV_Register_Masks NV Register Masks 9635 * @{ 9636 */ 9637 9638 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 9639 /*! @{ */ 9640 #define NV_BACKKEY3_KEY_MASK (0xFFU) 9641 #define NV_BACKKEY3_KEY_SHIFT (0U) 9642 /*! KEY - Backdoor Comparison Key. 9643 */ 9644 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 9645 /*! @} */ 9646 9647 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 9648 /*! @{ */ 9649 #define NV_BACKKEY2_KEY_MASK (0xFFU) 9650 #define NV_BACKKEY2_KEY_SHIFT (0U) 9651 /*! KEY - Backdoor Comparison Key. 9652 */ 9653 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 9654 /*! @} */ 9655 9656 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 9657 /*! @{ */ 9658 #define NV_BACKKEY1_KEY_MASK (0xFFU) 9659 #define NV_BACKKEY1_KEY_SHIFT (0U) 9660 /*! KEY - Backdoor Comparison Key. 9661 */ 9662 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 9663 /*! @} */ 9664 9665 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 9666 /*! @{ */ 9667 #define NV_BACKKEY0_KEY_MASK (0xFFU) 9668 #define NV_BACKKEY0_KEY_SHIFT (0U) 9669 /*! KEY - Backdoor Comparison Key. 9670 */ 9671 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 9672 /*! @} */ 9673 9674 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 9675 /*! @{ */ 9676 #define NV_BACKKEY7_KEY_MASK (0xFFU) 9677 #define NV_BACKKEY7_KEY_SHIFT (0U) 9678 /*! KEY - Backdoor Comparison Key. 9679 */ 9680 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 9681 /*! @} */ 9682 9683 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 9684 /*! @{ */ 9685 #define NV_BACKKEY6_KEY_MASK (0xFFU) 9686 #define NV_BACKKEY6_KEY_SHIFT (0U) 9687 /*! KEY - Backdoor Comparison Key. 9688 */ 9689 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 9690 /*! @} */ 9691 9692 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 9693 /*! @{ */ 9694 #define NV_BACKKEY5_KEY_MASK (0xFFU) 9695 #define NV_BACKKEY5_KEY_SHIFT (0U) 9696 /*! KEY - Backdoor Comparison Key. 9697 */ 9698 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 9699 /*! @} */ 9700 9701 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 9702 /*! @{ */ 9703 #define NV_BACKKEY4_KEY_MASK (0xFFU) 9704 #define NV_BACKKEY4_KEY_SHIFT (0U) 9705 /*! KEY - Backdoor Comparison Key. 9706 */ 9707 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 9708 /*! @} */ 9709 9710 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 9711 /*! @{ */ 9712 #define NV_FPROT3_PROT_MASK (0xFFU) 9713 #define NV_FPROT3_PROT_SHIFT (0U) 9714 /*! PROT - P-Flash Region Protect 9715 */ 9716 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 9717 /*! @} */ 9718 9719 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 9720 /*! @{ */ 9721 #define NV_FPROT2_PROT_MASK (0xFFU) 9722 #define NV_FPROT2_PROT_SHIFT (0U) 9723 /*! PROT - P-Flash Region Protect 9724 */ 9725 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 9726 /*! @} */ 9727 9728 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 9729 /*! @{ */ 9730 #define NV_FPROT1_PROT_MASK (0xFFU) 9731 #define NV_FPROT1_PROT_SHIFT (0U) 9732 /*! PROT - P-Flash Region Protect 9733 */ 9734 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 9735 /*! @} */ 9736 9737 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 9738 /*! @{ */ 9739 #define NV_FPROT0_PROT_MASK (0xFFU) 9740 #define NV_FPROT0_PROT_SHIFT (0U) 9741 /*! PROT - P-Flash Region Protect 9742 */ 9743 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 9744 /*! @} */ 9745 9746 /*! @name FSEC - Non-volatile Flash Security Register */ 9747 /*! @{ */ 9748 #define NV_FSEC_SEC_MASK (0x3U) 9749 #define NV_FSEC_SEC_SHIFT (0U) 9750 /*! SEC - Flash Security 9751 * 0b10..MCU security status is unsecure 9752 * 0b11..MCU security status is secure 9753 */ 9754 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 9755 #define NV_FSEC_FSLACC_MASK (0xCU) 9756 #define NV_FSEC_FSLACC_SHIFT (2U) 9757 /*! FSLACC - Freescale Failure Analysis Access Code 9758 * 0b10..Freescale factory access denied 9759 * 0b11..Freescale factory access granted 9760 */ 9761 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 9762 #define NV_FSEC_MEEN_MASK (0x30U) 9763 #define NV_FSEC_MEEN_SHIFT (4U) 9764 /*! MEEN 9765 * 0b10..Mass erase is disabled 9766 * 0b11..Mass erase is enabled 9767 */ 9768 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 9769 #define NV_FSEC_KEYEN_MASK (0xC0U) 9770 #define NV_FSEC_KEYEN_SHIFT (6U) 9771 /*! KEYEN - Backdoor Key Security Enable 9772 * 0b10..Backdoor key access enabled 9773 * 0b11..Backdoor key access disabled 9774 */ 9775 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 9776 /*! @} */ 9777 9778 /*! @name FOPT - Non-volatile Flash Option Register */ 9779 /*! @{ */ 9780 #define NV_FOPT_LPBOOT0_MASK (0x1U) 9781 #define NV_FOPT_LPBOOT0_SHIFT (0U) 9782 /*! LPBOOT0 9783 * 0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when 9784 * LPBOOT1=1. 0b1..Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when 9785 * LPBOOT1=1. 9786 */ 9787 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) 9788 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) 9789 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) 9790 /*! BOOTPIN_OPT 9791 * 0b0..Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI 9792 * pin 0b1..Boot source configured by FOPT (BOOTSRC_SEL) bits 9793 */ 9794 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) 9795 #define NV_FOPT_NMI_DIS_MASK (0x4U) 9796 #define NV_FOPT_NMI_DIS_SHIFT (2U) 9797 /*! NMI_DIS 9798 * 0b0..NMI interrupts are always blocked 9799 * 0b1..NMI_b pin/interrupts reset default to enabled 9800 */ 9801 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 9802 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) 9803 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) 9804 /*! RESET_PIN_CFG 9805 * 0b0..RESET pin is disabled following a POR and cannot be enabled as reset function 9806 * 0b1..RESET_b pin is dedicated 9807 */ 9808 #define NV_FOPT_RESET_PIN_CFG(x) \ 9809 (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) 9810 #define NV_FOPT_LPBOOT1_MASK (0x10U) 9811 #define NV_FOPT_LPBOOT1_SHIFT (4U) 9812 /*! LPBOOT1 9813 * 0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when 9814 * LPBOOT0=1. 0b1..Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when 9815 * LPBOOT0=1. 9816 */ 9817 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) 9818 #define NV_FOPT_FAST_INIT_MASK (0x20U) 9819 #define NV_FOPT_FAST_INIT_SHIFT (5U) 9820 /*! FAST_INIT 9821 * 0b0..Slower initialization 9822 * 0b1..Fast Initialization 9823 */ 9824 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) 9825 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) 9826 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) 9827 /*! BOOTSRC_SEL - Boot source selection 9828 * 0b00..Boot from Flash 9829 * 0b10..Boot from ROM 9830 * 0b11..Boot from ROM 9831 */ 9832 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) 9833 /*! @} */ 9834 9835 /*! 9836 * @} 9837 */ /* end of group NV_Register_Masks */ 9838 9839 /* NV - Peripheral instance base addresses */ 9840 /** Peripheral FTFA_FlashConfig base address */ 9841 #define FTFA_FlashConfig_BASE (0x400u) 9842 /** Peripheral FTFA_FlashConfig base pointer */ 9843 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 9844 /** Array initializer of NV peripheral base addresses */ 9845 #define NV_BASE_ADDRS \ 9846 { \ 9847 FTFA_FlashConfig_BASE \ 9848 } 9849 /** Array initializer of NV peripheral base pointers */ 9850 #define NV_BASE_PTRS \ 9851 { \ 9852 FTFA_FlashConfig \ 9853 } 9854 9855 /*! 9856 * @} 9857 */ /* end of group NV_Peripheral_Access_Layer */ 9858 9859 /* ---------------------------------------------------------------------------- 9860 -- OSC Peripheral Access Layer 9861 ---------------------------------------------------------------------------- */ 9862 9863 /*! 9864 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 9865 * @{ 9866 */ 9867 9868 /** OSC - Register Layout Typedef */ 9869 typedef struct 9870 { 9871 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 9872 } OSC_Type; 9873 9874 /* ---------------------------------------------------------------------------- 9875 -- OSC Register Masks 9876 ---------------------------------------------------------------------------- */ 9877 9878 /*! 9879 * @addtogroup OSC_Register_Masks OSC Register Masks 9880 * @{ 9881 */ 9882 9883 /*! @name CR - OSC Control Register */ 9884 /*! @{ */ 9885 #define OSC_CR_SC16P_MASK (0x1U) 9886 #define OSC_CR_SC16P_SHIFT (0U) 9887 /*! SC16P - Oscillator 16 pF Capacitor Load Configure 9888 * 0b0..Disable the selection. 9889 * 0b1..Add 16 pF capacitor to the oscillator load. 9890 */ 9891 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 9892 #define OSC_CR_SC8P_MASK (0x2U) 9893 #define OSC_CR_SC8P_SHIFT (1U) 9894 /*! SC8P - Oscillator 8 pF Capacitor Load Configure 9895 * 0b0..Disable the selection. 9896 * 0b1..Add 8 pF capacitor to the oscillator load. 9897 */ 9898 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 9899 #define OSC_CR_SC4P_MASK (0x4U) 9900 #define OSC_CR_SC4P_SHIFT (2U) 9901 /*! SC4P - Oscillator 4 pF Capacitor Load Configure 9902 * 0b0..Disable the selection. 9903 * 0b1..Add 4 pF capacitor to the oscillator load. 9904 */ 9905 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 9906 #define OSC_CR_SC2P_MASK (0x8U) 9907 #define OSC_CR_SC2P_SHIFT (3U) 9908 /*! SC2P - Oscillator 2 pF Capacitor Load Configure 9909 * 0b0..Disable the selection. 9910 * 0b1..Add 2 pF capacitor to the oscillator load. 9911 */ 9912 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 9913 #define OSC_CR_EREFSTEN_MASK (0x20U) 9914 #define OSC_CR_EREFSTEN_SHIFT (5U) 9915 /*! EREFSTEN - External Reference Stop Enable 9916 * 0b0..External reference clock is disabled in Stop mode. 9917 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. 9918 */ 9919 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 9920 #define OSC_CR_ERCLKEN_MASK (0x80U) 9921 #define OSC_CR_ERCLKEN_SHIFT (7U) 9922 /*! ERCLKEN - External Reference Enable 9923 * 0b0..External reference clock is inactive. 9924 * 0b1..External reference clock is enabled. 9925 */ 9926 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 9927 /*! @} */ 9928 9929 /*! 9930 * @} 9931 */ /* end of group OSC_Register_Masks */ 9932 9933 /* OSC - Peripheral instance base addresses */ 9934 /** Peripheral OSC0 base address */ 9935 #define OSC0_BASE (0x40065000u) 9936 /** Peripheral OSC0 base pointer */ 9937 #define OSC0 ((OSC_Type *)OSC0_BASE) 9938 /** Array initializer of OSC peripheral base addresses */ 9939 #define OSC_BASE_ADDRS \ 9940 { \ 9941 OSC0_BASE \ 9942 } 9943 /** Array initializer of OSC peripheral base pointers */ 9944 #define OSC_BASE_PTRS \ 9945 { \ 9946 OSC0 \ 9947 } 9948 9949 /*! 9950 * @} 9951 */ /* end of group OSC_Peripheral_Access_Layer */ 9952 9953 /* ---------------------------------------------------------------------------- 9954 -- PIT Peripheral Access Layer 9955 ---------------------------------------------------------------------------- */ 9956 9957 /*! 9958 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 9959 * @{ 9960 */ 9961 9962 /** PIT - Register Layout Typedef */ 9963 typedef struct 9964 { 9965 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 9966 uint8_t RESERVED_0[220]; 9967 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 9968 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 9969 uint8_t RESERVED_1[24]; 9970 struct 9971 { /* offset: 0x100, array step: 0x10 */ 9972 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 9973 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 9974 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 9975 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 9976 } CHANNEL[2]; 9977 } PIT_Type; 9978 9979 /* ---------------------------------------------------------------------------- 9980 -- PIT Register Masks 9981 ---------------------------------------------------------------------------- */ 9982 9983 /*! 9984 * @addtogroup PIT_Register_Masks PIT Register Masks 9985 * @{ 9986 */ 9987 9988 /*! @name MCR - PIT Module Control Register */ 9989 /*! @{ */ 9990 #define PIT_MCR_FRZ_MASK (0x1U) 9991 #define PIT_MCR_FRZ_SHIFT (0U) 9992 /*! FRZ - Freeze 9993 * 0b0..Timers continue to run in Debug mode. 9994 * 0b1..Timers are stopped in Debug mode. 9995 */ 9996 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 9997 #define PIT_MCR_MDIS_MASK (0x2U) 9998 #define PIT_MCR_MDIS_SHIFT (1U) 9999 /*! MDIS - Module Disable - (PIT section) 10000 * 0b0..Clock for standard PIT timers is enabled. 10001 * 0b1..Clock for standard PIT timers is disabled. 10002 */ 10003 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 10004 /*! @} */ 10005 10006 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ 10007 /*! @{ */ 10008 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) 10009 #define PIT_LTMR64H_LTH_SHIFT (0U) 10010 /*! LTH - Life Timer value 10011 */ 10012 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) 10013 /*! @} */ 10014 10015 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ 10016 /*! @{ */ 10017 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) 10018 #define PIT_LTMR64L_LTL_SHIFT (0U) 10019 /*! LTL - Life Timer value 10020 */ 10021 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) 10022 /*! @} */ 10023 10024 /*! @name LDVAL - Timer Load Value Register */ 10025 /*! @{ */ 10026 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 10027 #define PIT_LDVAL_TSV_SHIFT (0U) 10028 /*! TSV - Timer Start Value 10029 */ 10030 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 10031 /*! @} */ 10032 10033 /* The count of PIT_LDVAL */ 10034 #define PIT_LDVAL_COUNT (2U) 10035 10036 /*! @name CVAL - Current Timer Value Register */ 10037 /*! @{ */ 10038 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 10039 #define PIT_CVAL_TVL_SHIFT (0U) 10040 /*! TVL - Current Timer Value 10041 */ 10042 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 10043 /*! @} */ 10044 10045 /* The count of PIT_CVAL */ 10046 #define PIT_CVAL_COUNT (2U) 10047 10048 /*! @name TCTRL - Timer Control Register */ 10049 /*! @{ */ 10050 #define PIT_TCTRL_TEN_MASK (0x1U) 10051 #define PIT_TCTRL_TEN_SHIFT (0U) 10052 /*! TEN - Timer Enable 10053 * 0b0..Timer n is disabled. 10054 * 0b1..Timer n is enabled. 10055 */ 10056 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 10057 #define PIT_TCTRL_TIE_MASK (0x2U) 10058 #define PIT_TCTRL_TIE_SHIFT (1U) 10059 /*! TIE - Timer Interrupt Enable 10060 * 0b0..Interrupt requests from Timer n are disabled. 10061 * 0b1..Interrupt will be requested whenever TIF is set. 10062 */ 10063 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 10064 #define PIT_TCTRL_CHN_MASK (0x4U) 10065 #define PIT_TCTRL_CHN_SHIFT (2U) 10066 /*! CHN - Chain Mode 10067 * 0b0..Timer is not chained. 10068 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to 10069 * Timer 1. 10070 */ 10071 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 10072 /*! @} */ 10073 10074 /* The count of PIT_TCTRL */ 10075 #define PIT_TCTRL_COUNT (2U) 10076 10077 /*! @name TFLG - Timer Flag Register */ 10078 /*! @{ */ 10079 #define PIT_TFLG_TIF_MASK (0x1U) 10080 #define PIT_TFLG_TIF_SHIFT (0U) 10081 /*! TIF - Timer Interrupt Flag 10082 * 0b0..Timeout has not yet occurred. 10083 * 0b1..Timeout has occurred. 10084 */ 10085 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 10086 /*! @} */ 10087 10088 /* The count of PIT_TFLG */ 10089 #define PIT_TFLG_COUNT (2U) 10090 10091 /*! 10092 * @} 10093 */ /* end of group PIT_Register_Masks */ 10094 10095 /* PIT - Peripheral instance base addresses */ 10096 /** Peripheral PIT base address */ 10097 #define PIT_BASE (0x40037000u) 10098 /** Peripheral PIT base pointer */ 10099 #define PIT ((PIT_Type *)PIT_BASE) 10100 /** Array initializer of PIT peripheral base addresses */ 10101 #define PIT_BASE_ADDRS \ 10102 { \ 10103 PIT_BASE \ 10104 } 10105 /** Array initializer of PIT peripheral base pointers */ 10106 #define PIT_BASE_PTRS \ 10107 { \ 10108 PIT \ 10109 } 10110 /** Interrupt vectors for the PIT peripheral type */ 10111 #define PIT_IRQS \ 10112 { \ 10113 { \ 10114 PIT_IRQn, PIT_IRQn \ 10115 } \ 10116 } 10117 10118 /*! 10119 * @} 10120 */ /* end of group PIT_Peripheral_Access_Layer */ 10121 10122 /* ---------------------------------------------------------------------------- 10123 -- PMC Peripheral Access Layer 10124 ---------------------------------------------------------------------------- */ 10125 10126 /*! 10127 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 10128 * @{ 10129 */ 10130 10131 /** PMC - Register Layout Typedef */ 10132 typedef struct 10133 { 10134 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 10135 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 10136 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 10137 } PMC_Type; 10138 10139 /* ---------------------------------------------------------------------------- 10140 -- PMC Register Masks 10141 ---------------------------------------------------------------------------- */ 10142 10143 /*! 10144 * @addtogroup PMC_Register_Masks PMC Register Masks 10145 * @{ 10146 */ 10147 10148 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ 10149 /*! @{ */ 10150 #define PMC_LVDSC1_LVDV_MASK (0x3U) 10151 #define PMC_LVDSC1_LVDV_SHIFT (0U) 10152 /*! LVDV - Low-Voltage Detect Voltage Select 10153 * 0b00..Low trip point selected (V LVD = V LVDL ) 10154 * 0b01..High trip point selected (V LVD = V LVDH ) 10155 * 0b10..Reserved 10156 * 0b11..Reserved 10157 */ 10158 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 10159 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 10160 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 10161 /*! LVDRE - Low-Voltage Detect Reset Enable 10162 * 0b0..LVDF does not generate hardware resets 10163 * 0b1..Force an MCU reset when LVDF = 1 10164 */ 10165 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 10166 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 10167 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 10168 /*! LVDIE - Low-Voltage Detect Interrupt Enable 10169 * 0b0..Hardware interrupt disabled (use polling) 10170 * 0b1..Request a hardware interrupt when LVDF = 1 10171 */ 10172 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 10173 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 10174 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 10175 /*! LVDACK - Low-Voltage Detect Acknowledge 10176 */ 10177 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 10178 #define PMC_LVDSC1_LVDF_MASK (0x80U) 10179 #define PMC_LVDSC1_LVDF_SHIFT (7U) 10180 /*! LVDF - Low-Voltage Detect Flag 10181 * 0b0..Low-voltage event not detected 10182 * 0b1..Low-voltage event detected 10183 */ 10184 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 10185 /*! @} */ 10186 10187 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ 10188 /*! @{ */ 10189 #define PMC_LVDSC2_LVWV_MASK (0x3U) 10190 #define PMC_LVDSC2_LVWV_SHIFT (0U) 10191 /*! LVWV - Low-Voltage Warning Voltage Select 10192 * 0b00..Low trip point selected (VLVW = VLVW1) 10193 * 0b01..Mid 1 trip point selected (VLVW = VLVW2) 10194 * 0b10..Mid 2 trip point selected (VLVW = VLVW3) 10195 * 0b11..High trip point selected (VLVW = VLVW4) 10196 */ 10197 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 10198 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 10199 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 10200 /*! LVWIE - Low-Voltage Warning Interrupt Enable 10201 * 0b0..Hardware interrupt disabled (use polling) 10202 * 0b1..Request a hardware interrupt when LVWF = 1 10203 */ 10204 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 10205 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 10206 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 10207 /*! LVWACK - Low-Voltage Warning Acknowledge 10208 */ 10209 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 10210 #define PMC_LVDSC2_LVWF_MASK (0x80U) 10211 #define PMC_LVDSC2_LVWF_SHIFT (7U) 10212 /*! LVWF - Low-Voltage Warning Flag 10213 * 0b0..Low-voltage warning event not detected 10214 * 0b1..Low-voltage warning event detected 10215 */ 10216 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 10217 /*! @} */ 10218 10219 /*! @name REGSC - Regulator Status And Control register */ 10220 /*! @{ */ 10221 #define PMC_REGSC_BGBE_MASK (0x1U) 10222 #define PMC_REGSC_BGBE_SHIFT (0U) 10223 /*! BGBE - Bandgap Buffer Enable 10224 * 0b0..Bandgap buffer not enabled 10225 * 0b1..Bandgap buffer enabled 10226 */ 10227 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 10228 #define PMC_REGSC_REGONS_MASK (0x4U) 10229 #define PMC_REGSC_REGONS_SHIFT (2U) 10230 /*! REGONS - Regulator In Run Regulation Status 10231 * 0b0..Regulator is in stop regulation or in transition to/from it 10232 * 0b1..Regulator is in run regulation 10233 */ 10234 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 10235 #define PMC_REGSC_ACKISO_MASK (0x8U) 10236 #define PMC_REGSC_ACKISO_SHIFT (3U) 10237 /*! ACKISO - Acknowledge Isolation 10238 * 0b0..Peripherals and I/O pads are in normal run state. 10239 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state. 10240 */ 10241 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 10242 #define PMC_REGSC_BGEN_MASK (0x10U) 10243 #define PMC_REGSC_BGEN_SHIFT (4U) 10244 /*! BGEN - Bandgap Enable In VLPx Operation 10245 * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. 10246 * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. 10247 */ 10248 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) 10249 /*! @} */ 10250 10251 /*! 10252 * @} 10253 */ /* end of group PMC_Register_Masks */ 10254 10255 /* PMC - Peripheral instance base addresses */ 10256 /** Peripheral PMC base address */ 10257 #define PMC_BASE (0x4007D000u) 10258 /** Peripheral PMC base pointer */ 10259 #define PMC ((PMC_Type *)PMC_BASE) 10260 /** Array initializer of PMC peripheral base addresses */ 10261 #define PMC_BASE_ADDRS \ 10262 { \ 10263 PMC_BASE \ 10264 } 10265 /** Array initializer of PMC peripheral base pointers */ 10266 #define PMC_BASE_PTRS \ 10267 { \ 10268 PMC \ 10269 } 10270 /** Interrupt vectors for the PMC peripheral type */ 10271 #define PMC_IRQS \ 10272 { \ 10273 PMC_IRQn \ 10274 } 10275 10276 /*! 10277 * @} 10278 */ /* end of group PMC_Peripheral_Access_Layer */ 10279 10280 /* ---------------------------------------------------------------------------- 10281 -- PORT Peripheral Access Layer 10282 ---------------------------------------------------------------------------- */ 10283 10284 /*! 10285 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 10286 * @{ 10287 */ 10288 10289 /** PORT - Register Layout Typedef */ 10290 typedef struct 10291 { 10292 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 10293 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 10294 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 10295 uint8_t RESERVED_0[24]; 10296 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 10297 } PORT_Type; 10298 10299 /* ---------------------------------------------------------------------------- 10300 -- PORT Register Masks 10301 ---------------------------------------------------------------------------- */ 10302 10303 /*! 10304 * @addtogroup PORT_Register_Masks PORT Register Masks 10305 * @{ 10306 */ 10307 10308 /*! @name PCR - Pin Control Register n */ 10309 /*! @{ */ 10310 #define PORT_PCR_PS_MASK (0x1U) 10311 #define PORT_PCR_PS_SHIFT (0U) 10312 /*! PS - Pull Select 10313 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 10314 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 10315 */ 10316 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 10317 #define PORT_PCR_PE_MASK (0x2U) 10318 #define PORT_PCR_PE_SHIFT (1U) 10319 /*! PE - Pull Enable 10320 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 10321 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital 10322 * input. 10323 */ 10324 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 10325 #define PORT_PCR_SRE_MASK (0x4U) 10326 #define PORT_PCR_SRE_SHIFT (2U) 10327 /*! SRE - Slew Rate Enable 10328 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 10329 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 10330 */ 10331 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 10332 #define PORT_PCR_PFE_MASK (0x10U) 10333 #define PORT_PCR_PFE_SHIFT (4U) 10334 /*! PFE - Passive Filter Enable 10335 * 0b0..Passive input filter is disabled on the corresponding pin. 10336 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. 10337 * Refer to the device data sheet for filter characteristics. 10338 */ 10339 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 10340 #define PORT_PCR_DSE_MASK (0x40U) 10341 #define PORT_PCR_DSE_SHIFT (6U) 10342 /*! DSE - Drive Strength Enable 10343 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 10344 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 10345 */ 10346 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 10347 #define PORT_PCR_MUX_MASK (0x700U) 10348 #define PORT_PCR_MUX_SHIFT (8U) 10349 /*! MUX - Pin Mux Control 10350 * 0b000..Pin disabled (Alternative 0) (analog). 10351 * 0b001..Alternative 1 (GPIO). 10352 * 0b010..Alternative 2 (chip-specific). 10353 * 0b011..Alternative 3 (chip-specific). 10354 * 0b100..Alternative 4 (chip-specific). 10355 * 0b101..Alternative 5 (chip-specific). 10356 * 0b110..Alternative 6 (chip-specific). 10357 * 0b111..Alternative 7 (chip-specific). 10358 */ 10359 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 10360 #define PORT_PCR_IRQC_MASK (0xF0000U) 10361 #define PORT_PCR_IRQC_SHIFT (16U) 10362 /*! IRQC - Interrupt Configuration 10363 * 0b0000..Interrupt Status Flag (ISF) is disabled. 10364 * 0b0001..ISF flag and DMA request on rising edge. 10365 * 0b0010..ISF flag and DMA request on falling edge. 10366 * 0b0011..ISF flag and DMA request on either edge. 10367 * 0b0100..Reserved. 10368 * 0b0101..Reserved. 10369 * 0b0110..Reserved. 10370 * 0b0111..Reserved. 10371 * 0b1000..ISF flag and Interrupt when logic 0. 10372 * 0b1001..ISF flag and Interrupt on rising-edge. 10373 * 0b1010..ISF flag and Interrupt on falling-edge. 10374 * 0b1011..ISF flag and Interrupt on either edge. 10375 * 0b1100..ISF flag and Interrupt when logic 1. 10376 * 0b1101..Reserved. 10377 * 0b1110..Reserved. 10378 * 0b1111..Reserved. 10379 */ 10380 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 10381 #define PORT_PCR_ISF_MASK (0x1000000U) 10382 #define PORT_PCR_ISF_SHIFT (24U) 10383 /*! ISF - Interrupt Status Flag 10384 * 0b0..Configured interrupt is not detected. 10385 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the 10386 * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, 10387 * the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt 10388 * and the pin remains asserted, then the flag is set again immediately after it is cleared. 10389 */ 10390 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 10391 /*! @} */ 10392 10393 /* The count of PORT_PCR */ 10394 #define PORT_PCR_COUNT (32U) 10395 10396 /*! @name GPCLR - Global Pin Control Low Register */ 10397 /*! @{ */ 10398 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 10399 #define PORT_GPCLR_GPWD_SHIFT (0U) 10400 /*! GPWD - Global Pin Write Data 10401 */ 10402 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 10403 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 10404 #define PORT_GPCLR_GPWE_SHIFT (16U) 10405 /*! GPWE - Global Pin Write Enable 10406 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 10407 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 10408 */ 10409 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 10410 /*! @} */ 10411 10412 /*! @name GPCHR - Global Pin Control High Register */ 10413 /*! @{ */ 10414 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 10415 #define PORT_GPCHR_GPWD_SHIFT (0U) 10416 /*! GPWD - Global Pin Write Data 10417 */ 10418 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 10419 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 10420 #define PORT_GPCHR_GPWE_SHIFT (16U) 10421 /*! GPWE - Global Pin Write Enable 10422 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 10423 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 10424 */ 10425 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 10426 /*! @} */ 10427 10428 /*! @name ISFR - Interrupt Status Flag Register */ 10429 /*! @{ */ 10430 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 10431 #define PORT_ISFR_ISF_SHIFT (0U) 10432 /*! ISF - Interrupt Status Flag 10433 * 0b00000000000000000000000000000000..Configured interrupt is not detected. 10434 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a 10435 * DMA request, then the corresponding flag will be cleared automatically at 10436 * the completion of the requested DMA transfer. Otherwise, the flag remains set 10437 * until a logic 1 is written to the flag. If the pin is configured for a 10438 * level sensitive interrupt and the pin remains asserted, then the flag is set 10439 * again immediately after it is cleared. 10440 */ 10441 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 10442 /*! @} */ 10443 10444 /*! 10445 * @} 10446 */ /* end of group PORT_Register_Masks */ 10447 10448 /* PORT - Peripheral instance base addresses */ 10449 /** Peripheral PORTA base address */ 10450 #define PORTA_BASE (0x40049000u) 10451 /** Peripheral PORTA base pointer */ 10452 #define PORTA ((PORT_Type *)PORTA_BASE) 10453 /** Peripheral PORTB base address */ 10454 #define PORTB_BASE (0x4004A000u) 10455 /** Peripheral PORTB base pointer */ 10456 #define PORTB ((PORT_Type *)PORTB_BASE) 10457 /** Peripheral PORTC base address */ 10458 #define PORTC_BASE (0x4004B000u) 10459 /** Peripheral PORTC base pointer */ 10460 #define PORTC ((PORT_Type *)PORTC_BASE) 10461 /** Peripheral PORTD base address */ 10462 #define PORTD_BASE (0x4004C000u) 10463 /** Peripheral PORTD base pointer */ 10464 #define PORTD ((PORT_Type *)PORTD_BASE) 10465 /** Peripheral PORTE base address */ 10466 #define PORTE_BASE (0x4004D000u) 10467 /** Peripheral PORTE base pointer */ 10468 #define PORTE ((PORT_Type *)PORTE_BASE) 10469 /** Array initializer of PORT peripheral base addresses */ 10470 #define PORT_BASE_ADDRS \ 10471 { \ 10472 PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE \ 10473 } 10474 /** Array initializer of PORT peripheral base pointers */ 10475 #define PORT_BASE_PTRS \ 10476 { \ 10477 PORTA, PORTB, PORTC, PORTD, PORTE \ 10478 } 10479 /** Interrupt vectors for the PORT peripheral type */ 10480 #define PORT_IRQS \ 10481 { \ 10482 PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn \ 10483 } 10484 10485 /*! 10486 * @} 10487 */ /* end of group PORT_Peripheral_Access_Layer */ 10488 10489 /* ---------------------------------------------------------------------------- 10490 -- RCM Peripheral Access Layer 10491 ---------------------------------------------------------------------------- */ 10492 10493 /*! 10494 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 10495 * @{ 10496 */ 10497 10498 /** RCM - Register Layout Typedef */ 10499 typedef struct 10500 { 10501 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 10502 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 10503 uint8_t RESERVED_0[2]; 10504 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 10505 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 10506 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ 10507 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ 10508 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ 10509 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ 10510 } RCM_Type; 10511 10512 /* ---------------------------------------------------------------------------- 10513 -- RCM Register Masks 10514 ---------------------------------------------------------------------------- */ 10515 10516 /*! 10517 * @addtogroup RCM_Register_Masks RCM Register Masks 10518 * @{ 10519 */ 10520 10521 /*! @name SRS0 - System Reset Status Register 0 */ 10522 /*! @{ */ 10523 #define RCM_SRS0_WAKEUP_MASK (0x1U) 10524 #define RCM_SRS0_WAKEUP_SHIFT (0U) 10525 /*! WAKEUP - Low Leakage Wakeup Reset 10526 * 0b0..Reset not caused by LLWU module wakeup source 10527 * 0b1..Reset caused by LLWU module wakeup source 10528 */ 10529 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 10530 #define RCM_SRS0_LVD_MASK (0x2U) 10531 #define RCM_SRS0_LVD_SHIFT (1U) 10532 /*! LVD - Low-Voltage Detect Reset 10533 * 0b0..Reset not caused by LVD trip or POR 10534 * 0b1..Reset caused by LVD trip or POR 10535 */ 10536 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 10537 #define RCM_SRS0_WDOG_MASK (0x20U) 10538 #define RCM_SRS0_WDOG_SHIFT (5U) 10539 /*! WDOG - Watchdog 10540 * 0b0..Reset not caused by watchdog timeout 10541 * 0b1..Reset caused by watchdog timeout 10542 */ 10543 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 10544 #define RCM_SRS0_PIN_MASK (0x40U) 10545 #define RCM_SRS0_PIN_SHIFT (6U) 10546 /*! PIN - External Reset Pin 10547 * 0b0..Reset not caused by external reset pin 10548 * 0b1..Reset caused by external reset pin 10549 */ 10550 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 10551 #define RCM_SRS0_POR_MASK (0x80U) 10552 #define RCM_SRS0_POR_SHIFT (7U) 10553 /*! POR - Power-On Reset 10554 * 0b0..Reset not caused by POR 10555 * 0b1..Reset caused by POR 10556 */ 10557 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 10558 /*! @} */ 10559 10560 /*! @name SRS1 - System Reset Status Register 1 */ 10561 /*! @{ */ 10562 #define RCM_SRS1_LOCKUP_MASK (0x2U) 10563 #define RCM_SRS1_LOCKUP_SHIFT (1U) 10564 /*! LOCKUP - Core Lockup 10565 * 0b0..Reset not caused by core LOCKUP event 10566 * 0b1..Reset caused by core LOCKUP event 10567 */ 10568 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 10569 #define RCM_SRS1_SW_MASK (0x4U) 10570 #define RCM_SRS1_SW_SHIFT (2U) 10571 /*! SW - Software 10572 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 10573 * 0b1..Reset caused by software setting of SYSRESETREQ bit 10574 */ 10575 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 10576 #define RCM_SRS1_MDM_AP_MASK (0x8U) 10577 #define RCM_SRS1_MDM_AP_SHIFT (3U) 10578 /*! MDM_AP - MDM-AP System Reset Request 10579 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit 10580 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit 10581 */ 10582 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 10583 #define RCM_SRS1_SACKERR_MASK (0x20U) 10584 #define RCM_SRS1_SACKERR_SHIFT (5U) 10585 /*! SACKERR - Stop Mode Acknowledge Error Reset 10586 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 10587 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 10588 */ 10589 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 10590 /*! @} */ 10591 10592 /*! @name RPFC - Reset Pin Filter Control register */ 10593 /*! @{ */ 10594 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 10595 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 10596 /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes 10597 * 0b00..All filtering disabled 10598 * 0b01..Bus clock filter enabled for normal operation 10599 * 0b10..LPO clock filter enabled for normal operation 10600 * 0b11..Reserved 10601 */ 10602 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 10603 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 10604 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 10605 /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode 10606 * 0b0..All filtering disabled 10607 * 0b1..LPO clock filter enabled 10608 */ 10609 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 10610 /*! @} */ 10611 10612 /*! @name RPFW - Reset Pin Filter Width register */ 10613 /*! @{ */ 10614 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 10615 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 10616 /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select 10617 * 0b00000..Bus clock filter count is 1 10618 * 0b00001..Bus clock filter count is 2 10619 * 0b00010..Bus clock filter count is 3 10620 * 0b00011..Bus clock filter count is 4 10621 * 0b00100..Bus clock filter count is 5 10622 * 0b00101..Bus clock filter count is 6 10623 * 0b00110..Bus clock filter count is 7 10624 * 0b00111..Bus clock filter count is 8 10625 * 0b01000..Bus clock filter count is 9 10626 * 0b01001..Bus clock filter count is 10 10627 * 0b01010..Bus clock filter count is 11 10628 * 0b01011..Bus clock filter count is 12 10629 * 0b01100..Bus clock filter count is 13 10630 * 0b01101..Bus clock filter count is 14 10631 * 0b01110..Bus clock filter count is 15 10632 * 0b01111..Bus clock filter count is 16 10633 * 0b10000..Bus clock filter count is 17 10634 * 0b10001..Bus clock filter count is 18 10635 * 0b10010..Bus clock filter count is 19 10636 * 0b10011..Bus clock filter count is 20 10637 * 0b10100..Bus clock filter count is 21 10638 * 0b10101..Bus clock filter count is 22 10639 * 0b10110..Bus clock filter count is 23 10640 * 0b10111..Bus clock filter count is 24 10641 * 0b11000..Bus clock filter count is 25 10642 * 0b11001..Bus clock filter count is 26 10643 * 0b11010..Bus clock filter count is 27 10644 * 0b11011..Bus clock filter count is 28 10645 * 0b11100..Bus clock filter count is 29 10646 * 0b11101..Bus clock filter count is 30 10647 * 0b11110..Bus clock filter count is 31 10648 * 0b11111..Bus clock filter count is 32 10649 */ 10650 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 10651 /*! @} */ 10652 10653 /*! @name FM - Force Mode Register */ 10654 /*! @{ */ 10655 #define RCM_FM_FORCEROM_MASK (0x6U) 10656 #define RCM_FM_FORCEROM_SHIFT (1U) 10657 /*! FORCEROM - Force ROM Boot 10658 * 0b00..No effect 10659 * 0b01..Force boot from ROM with RCM_MR[1] set. 10660 * 0b10..Force boot from ROM with RCM_MR[2] set. 10661 * 0b11..Force boot from ROM with RCM_MR[2:1] set. 10662 */ 10663 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) 10664 /*! @} */ 10665 10666 /*! @name MR - Mode Register */ 10667 /*! @{ */ 10668 #define RCM_MR_BOOTROM_MASK (0x6U) 10669 #define RCM_MR_BOOTROM_SHIFT (1U) 10670 /*! BOOTROM - Boot ROM Configuration 10671 * 0b00..Boot from Flash 10672 * 0b01..Boot from ROM due to BOOTCFG0 pin assertion 10673 * 0b10..Boot form ROM due to FOPT[7] configuration 10674 * 0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration 10675 */ 10676 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) 10677 /*! @} */ 10678 10679 /*! @name SSRS0 - Sticky System Reset Status Register 0 */ 10680 /*! @{ */ 10681 #define RCM_SSRS0_SWAKEUP_MASK (0x1U) 10682 #define RCM_SSRS0_SWAKEUP_SHIFT (0U) 10683 /*! SWAKEUP - Sticky Low Leakage Wakeup Reset 10684 * 0b0..Reset not caused by LLWU module wakeup source 10685 * 0b1..Reset caused by LLWU module wakeup source 10686 */ 10687 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) 10688 #define RCM_SSRS0_SLVD_MASK (0x2U) 10689 #define RCM_SSRS0_SLVD_SHIFT (1U) 10690 /*! SLVD - Sticky Low-Voltage Detect Reset 10691 * 0b0..Reset not caused by LVD trip or POR 10692 * 0b1..Reset caused by LVD trip or POR 10693 */ 10694 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) 10695 #define RCM_SSRS0_SWDOG_MASK (0x20U) 10696 #define RCM_SSRS0_SWDOG_SHIFT (5U) 10697 /*! SWDOG - Sticky Watchdog 10698 * 0b0..Reset not caused by watchdog timeout 10699 * 0b1..Reset caused by watchdog timeout 10700 */ 10701 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) 10702 #define RCM_SSRS0_SPIN_MASK (0x40U) 10703 #define RCM_SSRS0_SPIN_SHIFT (6U) 10704 /*! SPIN - Sticky External Reset Pin 10705 * 0b0..Reset not caused by external reset pin 10706 * 0b1..Reset caused by external reset pin 10707 */ 10708 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) 10709 #define RCM_SSRS0_SPOR_MASK (0x80U) 10710 #define RCM_SSRS0_SPOR_SHIFT (7U) 10711 /*! SPOR - Sticky Power-On Reset 10712 * 0b0..Reset not caused by POR 10713 * 0b1..Reset caused by POR 10714 */ 10715 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) 10716 /*! @} */ 10717 10718 /*! @name SSRS1 - Sticky System Reset Status Register 1 */ 10719 /*! @{ */ 10720 #define RCM_SSRS1_SLOCKUP_MASK (0x2U) 10721 #define RCM_SSRS1_SLOCKUP_SHIFT (1U) 10722 /*! SLOCKUP - Sticky Core Lockup 10723 * 0b0..Reset not caused by core LOCKUP event 10724 * 0b1..Reset caused by core LOCKUP event 10725 */ 10726 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) 10727 #define RCM_SSRS1_SSW_MASK (0x4U) 10728 #define RCM_SSRS1_SSW_SHIFT (2U) 10729 /*! SSW - Sticky Software 10730 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 10731 * 0b1..Reset caused by software setting of SYSRESETREQ bit 10732 */ 10733 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) 10734 #define RCM_SSRS1_SMDM_AP_MASK (0x8U) 10735 #define RCM_SSRS1_SMDM_AP_SHIFT (3U) 10736 /*! SMDM_AP - Sticky MDM-AP System Reset Request 10737 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit 10738 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit 10739 */ 10740 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) 10741 #define RCM_SSRS1_SSACKERR_MASK (0x20U) 10742 #define RCM_SSRS1_SSACKERR_SHIFT (5U) 10743 /*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset 10744 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 10745 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 10746 */ 10747 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) 10748 /*! @} */ 10749 10750 /*! 10751 * @} 10752 */ /* end of group RCM_Register_Masks */ 10753 10754 /* RCM - Peripheral instance base addresses */ 10755 /** Peripheral RCM base address */ 10756 #define RCM_BASE (0x4007F000u) 10757 /** Peripheral RCM base pointer */ 10758 #define RCM ((RCM_Type *)RCM_BASE) 10759 /** Array initializer of RCM peripheral base addresses */ 10760 #define RCM_BASE_ADDRS \ 10761 { \ 10762 RCM_BASE \ 10763 } 10764 /** Array initializer of RCM peripheral base pointers */ 10765 #define RCM_BASE_PTRS \ 10766 { \ 10767 RCM \ 10768 } 10769 10770 /*! 10771 * @} 10772 */ /* end of group RCM_Peripheral_Access_Layer */ 10773 10774 /* ---------------------------------------------------------------------------- 10775 -- RFSYS Peripheral Access Layer 10776 ---------------------------------------------------------------------------- */ 10777 10778 /*! 10779 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer 10780 * @{ 10781 */ 10782 10783 /** RFSYS - Register Layout Typedef */ 10784 typedef struct 10785 { 10786 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ 10787 } RFSYS_Type; 10788 10789 /* ---------------------------------------------------------------------------- 10790 -- RFSYS Register Masks 10791 ---------------------------------------------------------------------------- */ 10792 10793 /*! 10794 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks 10795 * @{ 10796 */ 10797 10798 /*! @name REG - Register file register */ 10799 /*! @{ */ 10800 #define RFSYS_REG_LL_MASK (0xFFU) 10801 #define RFSYS_REG_LL_SHIFT (0U) 10802 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) 10803 #define RFSYS_REG_LH_MASK (0xFF00U) 10804 #define RFSYS_REG_LH_SHIFT (8U) 10805 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) 10806 #define RFSYS_REG_HL_MASK (0xFF0000U) 10807 #define RFSYS_REG_HL_SHIFT (16U) 10808 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) 10809 #define RFSYS_REG_HH_MASK (0xFF000000U) 10810 #define RFSYS_REG_HH_SHIFT (24U) 10811 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) 10812 /*! @} */ 10813 10814 /* The count of RFSYS_REG */ 10815 #define RFSYS_REG_COUNT (8U) 10816 10817 /*! 10818 * @} 10819 */ /* end of group RFSYS_Register_Masks */ 10820 10821 /* RFSYS - Peripheral instance base addresses */ 10822 /** Peripheral RFSYS base address */ 10823 #define RFSYS_BASE (0x40041000u) 10824 /** Peripheral RFSYS base pointer */ 10825 #define RFSYS ((RFSYS_Type *)RFSYS_BASE) 10826 /** Array initializer of RFSYS peripheral base addresses */ 10827 #define RFSYS_BASE_ADDRS \ 10828 { \ 10829 RFSYS_BASE \ 10830 } 10831 /** Array initializer of RFSYS peripheral base pointers */ 10832 #define RFSYS_BASE_PTRS \ 10833 { \ 10834 RFSYS \ 10835 } 10836 10837 /*! 10838 * @} 10839 */ /* end of group RFSYS_Peripheral_Access_Layer */ 10840 10841 /* ---------------------------------------------------------------------------- 10842 -- ROM Peripheral Access Layer 10843 ---------------------------------------------------------------------------- */ 10844 10845 /*! 10846 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 10847 * @{ 10848 */ 10849 10850 /** ROM - Register Layout Typedef */ 10851 typedef struct 10852 { 10853 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 10854 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 10855 uint8_t RESERVED_0[4028]; 10856 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 10857 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 10858 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 10859 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 10860 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 10861 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 10862 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 10863 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 10864 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 10865 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 10866 } ROM_Type; 10867 10868 /* ---------------------------------------------------------------------------- 10869 -- ROM Register Masks 10870 ---------------------------------------------------------------------------- */ 10871 10872 /*! 10873 * @addtogroup ROM_Register_Masks ROM Register Masks 10874 * @{ 10875 */ 10876 10877 /*! @name ENTRY - Entry */ 10878 /*! @{ */ 10879 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 10880 #define ROM_ENTRY_ENTRY_SHIFT (0U) 10881 /*! ENTRY - ENTRY 10882 */ 10883 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 10884 /*! @} */ 10885 10886 /* The count of ROM_ENTRY */ 10887 #define ROM_ENTRY_COUNT (3U) 10888 10889 /*! @name TABLEMARK - End of Table Marker Register */ 10890 /*! @{ */ 10891 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 10892 #define ROM_TABLEMARK_MARK_SHIFT (0U) 10893 /*! MARK - MARK 10894 */ 10895 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 10896 /*! @} */ 10897 10898 /*! @name SYSACCESS - System Access Register */ 10899 /*! @{ */ 10900 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 10901 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 10902 /*! SYSACCESS - SYSACCESS 10903 */ 10904 #define ROM_SYSACCESS_SYSACCESS(x) \ 10905 (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 10906 /*! @} */ 10907 10908 /*! @name PERIPHID4 - Peripheral ID Register */ 10909 /*! @{ */ 10910 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 10911 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 10912 /*! PERIPHID - PERIPHID 10913 */ 10914 #define ROM_PERIPHID4_PERIPHID(x) \ 10915 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 10916 /*! @} */ 10917 10918 /*! @name PERIPHID5 - Peripheral ID Register */ 10919 /*! @{ */ 10920 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 10921 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 10922 /*! PERIPHID - PERIPHID 10923 */ 10924 #define ROM_PERIPHID5_PERIPHID(x) \ 10925 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 10926 /*! @} */ 10927 10928 /*! @name PERIPHID6 - Peripheral ID Register */ 10929 /*! @{ */ 10930 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 10931 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 10932 /*! PERIPHID - PERIPHID 10933 */ 10934 #define ROM_PERIPHID6_PERIPHID(x) \ 10935 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 10936 /*! @} */ 10937 10938 /*! @name PERIPHID7 - Peripheral ID Register */ 10939 /*! @{ */ 10940 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 10941 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 10942 /*! PERIPHID - PERIPHID 10943 */ 10944 #define ROM_PERIPHID7_PERIPHID(x) \ 10945 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 10946 /*! @} */ 10947 10948 /*! @name PERIPHID0 - Peripheral ID Register */ 10949 /*! @{ */ 10950 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 10951 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 10952 /*! PERIPHID - PERIPHID 10953 */ 10954 #define ROM_PERIPHID0_PERIPHID(x) \ 10955 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 10956 /*! @} */ 10957 10958 /*! @name PERIPHID1 - Peripheral ID Register */ 10959 /*! @{ */ 10960 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 10961 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 10962 /*! PERIPHID - PERIPHID 10963 */ 10964 #define ROM_PERIPHID1_PERIPHID(x) \ 10965 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 10966 /*! @} */ 10967 10968 /*! @name PERIPHID2 - Peripheral ID Register */ 10969 /*! @{ */ 10970 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 10971 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 10972 /*! PERIPHID - PERIPHID 10973 */ 10974 #define ROM_PERIPHID2_PERIPHID(x) \ 10975 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 10976 /*! @} */ 10977 10978 /*! @name PERIPHID3 - Peripheral ID Register */ 10979 /*! @{ */ 10980 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 10981 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 10982 /*! PERIPHID - PERIPHID 10983 */ 10984 #define ROM_PERIPHID3_PERIPHID(x) \ 10985 (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 10986 /*! @} */ 10987 10988 /*! @name COMPID - Component ID Register */ 10989 /*! @{ */ 10990 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 10991 #define ROM_COMPID_COMPID_SHIFT (0U) 10992 /*! COMPID - Component ID 10993 */ 10994 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 10995 /*! @} */ 10996 10997 /* The count of ROM_COMPID */ 10998 #define ROM_COMPID_COUNT (4U) 10999 11000 /*! 11001 * @} 11002 */ /* end of group ROM_Register_Masks */ 11003 11004 /* ROM - Peripheral instance base addresses */ 11005 /** Peripheral ROM base address */ 11006 #define ROM_BASE (0xF0002000u) 11007 /** Peripheral ROM base pointer */ 11008 #define ROM ((ROM_Type *)ROM_BASE) 11009 /** Array initializer of ROM peripheral base addresses */ 11010 #define ROM_BASE_ADDRS \ 11011 { \ 11012 ROM_BASE \ 11013 } 11014 /** Array initializer of ROM peripheral base pointers */ 11015 #define ROM_BASE_PTRS \ 11016 { \ 11017 ROM \ 11018 } 11019 11020 /*! 11021 * @} 11022 */ /* end of group ROM_Peripheral_Access_Layer */ 11023 11024 /* ---------------------------------------------------------------------------- 11025 -- RTC Peripheral Access Layer 11026 ---------------------------------------------------------------------------- */ 11027 11028 /*! 11029 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 11030 * @{ 11031 */ 11032 11033 /** RTC - Register Layout Typedef */ 11034 typedef struct 11035 { 11036 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 11037 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 11038 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 11039 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 11040 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 11041 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 11042 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 11043 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 11044 } RTC_Type; 11045 11046 /* ---------------------------------------------------------------------------- 11047 -- RTC Register Masks 11048 ---------------------------------------------------------------------------- */ 11049 11050 /*! 11051 * @addtogroup RTC_Register_Masks RTC Register Masks 11052 * @{ 11053 */ 11054 11055 /*! @name TSR - RTC Time Seconds Register */ 11056 /*! @{ */ 11057 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) 11058 #define RTC_TSR_TSR_SHIFT (0U) 11059 /*! TSR - Time Seconds Register 11060 */ 11061 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) 11062 /*! @} */ 11063 11064 /*! @name TPR - RTC Time Prescaler Register */ 11065 /*! @{ */ 11066 #define RTC_TPR_TPR_MASK (0xFFFFU) 11067 #define RTC_TPR_TPR_SHIFT (0U) 11068 /*! TPR - Time Prescaler Register 11069 */ 11070 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) 11071 /*! @} */ 11072 11073 /*! @name TAR - RTC Time Alarm Register */ 11074 /*! @{ */ 11075 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) 11076 #define RTC_TAR_TAR_SHIFT (0U) 11077 /*! TAR - Time Alarm Register 11078 */ 11079 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) 11080 /*! @} */ 11081 11082 /*! @name TCR - RTC Time Compensation Register */ 11083 /*! @{ */ 11084 #define RTC_TCR_TCR_MASK (0xFFU) 11085 #define RTC_TCR_TCR_SHIFT (0U) 11086 /*! TCR - Time Compensation Register 11087 * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 11088 * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 11089 * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 11090 * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 11091 * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. 11092 */ 11093 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) 11094 #define RTC_TCR_CIR_MASK (0xFF00U) 11095 #define RTC_TCR_CIR_SHIFT (8U) 11096 /*! CIR - Compensation Interval Register 11097 */ 11098 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) 11099 #define RTC_TCR_TCV_MASK (0xFF0000U) 11100 #define RTC_TCR_TCV_SHIFT (16U) 11101 /*! TCV - Time Compensation Value 11102 */ 11103 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) 11104 #define RTC_TCR_CIC_MASK (0xFF000000U) 11105 #define RTC_TCR_CIC_SHIFT (24U) 11106 /*! CIC - Compensation Interval Counter 11107 */ 11108 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) 11109 /*! @} */ 11110 11111 /*! @name CR - RTC Control Register */ 11112 /*! @{ */ 11113 #define RTC_CR_SWR_MASK (0x1U) 11114 #define RTC_CR_SWR_SHIFT (0U) 11115 /*! SWR - Software Reset 11116 * 0b0..No effect. 11117 * 0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly 11118 * clearing it. 11119 */ 11120 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) 11121 #define RTC_CR_WPE_MASK (0x2U) 11122 #define RTC_CR_WPE_SHIFT (1U) 11123 /*! WPE - Wakeup Pin Enable 11124 * 0b0..Wakeup pin is disabled. 11125 * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. 11126 */ 11127 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) 11128 #define RTC_CR_SUP_MASK (0x4U) 11129 #define RTC_CR_SUP_SHIFT (2U) 11130 /*! SUP - Supervisor Access 11131 * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 11132 * 0b1..Non-supervisor mode write accesses are supported. 11133 */ 11134 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) 11135 #define RTC_CR_UM_MASK (0x8U) 11136 #define RTC_CR_UM_SHIFT (3U) 11137 /*! UM - Update Mode 11138 * 0b0..Registers cannot be written when locked. 11139 * 0b1..Registers can be written when locked under limited conditions. 11140 */ 11141 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) 11142 #define RTC_CR_WPS_MASK (0x10U) 11143 #define RTC_CR_WPS_SHIFT (4U) 11144 /*! WPS - Wakeup Pin Select 11145 * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 11146 * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is 11147 * output to other peripherals. 11148 */ 11149 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) 11150 #define RTC_CR_OSCE_MASK (0x100U) 11151 #define RTC_CR_OSCE_SHIFT (8U) 11152 /*! OSCE - Oscillator Enable 11153 * 0b0..32.768 kHz oscillator is disabled. 11154 * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before 11155 * enabling the time counter to allow the 32.768 kHz clock time to stabilize. 11156 */ 11157 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) 11158 #define RTC_CR_CLKO_MASK (0x200U) 11159 #define RTC_CR_CLKO_SHIFT (9U) 11160 /*! CLKO - Clock Output 11161 * 0b0..The 32 kHz clock is output to other peripherals. 11162 * 0b1..The 32 kHz clock is not output to other peripherals. 11163 */ 11164 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) 11165 #define RTC_CR_SC16P_MASK (0x400U) 11166 #define RTC_CR_SC16P_SHIFT (10U) 11167 /*! SC16P - Oscillator 16pF Load Configure 11168 * 0b0..Disable the load. 11169 * 0b1..Enable the additional load. 11170 */ 11171 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) 11172 #define RTC_CR_SC8P_MASK (0x800U) 11173 #define RTC_CR_SC8P_SHIFT (11U) 11174 /*! SC8P - Oscillator 8pF Load Configure 11175 * 0b0..Disable the load. 11176 * 0b1..Enable the additional load. 11177 */ 11178 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) 11179 #define RTC_CR_SC4P_MASK (0x1000U) 11180 #define RTC_CR_SC4P_SHIFT (12U) 11181 /*! SC4P - Oscillator 4pF Load Configure 11182 * 0b0..Disable the load. 11183 * 0b1..Enable the additional load. 11184 */ 11185 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) 11186 #define RTC_CR_SC2P_MASK (0x2000U) 11187 #define RTC_CR_SC2P_SHIFT (13U) 11188 /*! SC2P - Oscillator 2pF Load Configure 11189 * 0b0..Disable the load. 11190 * 0b1..Enable the additional load. 11191 */ 11192 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) 11193 /*! @} */ 11194 11195 /*! @name SR - RTC Status Register */ 11196 /*! @{ */ 11197 #define RTC_SR_TIF_MASK (0x1U) 11198 #define RTC_SR_TIF_SHIFT (0U) 11199 /*! TIF - Time Invalid Flag 11200 * 0b0..Time is valid. 11201 * 0b1..Time is invalid and time counter is read as zero. 11202 */ 11203 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) 11204 #define RTC_SR_TOF_MASK (0x2U) 11205 #define RTC_SR_TOF_SHIFT (1U) 11206 /*! TOF - Time Overflow Flag 11207 * 0b0..Time overflow has not occurred. 11208 * 0b1..Time overflow has occurred and time counter is read as zero. 11209 */ 11210 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) 11211 #define RTC_SR_TAF_MASK (0x4U) 11212 #define RTC_SR_TAF_SHIFT (2U) 11213 /*! TAF - Time Alarm Flag 11214 * 0b0..Time alarm has not occurred. 11215 * 0b1..Time alarm has occurred. 11216 */ 11217 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) 11218 #define RTC_SR_TCE_MASK (0x10U) 11219 #define RTC_SR_TCE_SHIFT (4U) 11220 /*! TCE - Time Counter Enable 11221 * 0b0..Time counter is disabled. 11222 * 0b1..Time counter is enabled. 11223 */ 11224 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) 11225 /*! @} */ 11226 11227 /*! @name LR - RTC Lock Register */ 11228 /*! @{ */ 11229 #define RTC_LR_TCL_MASK (0x8U) 11230 #define RTC_LR_TCL_SHIFT (3U) 11231 /*! TCL - Time Compensation Lock 11232 * 0b0..Time Compensation Register is locked and writes are ignored. 11233 * 0b1..Time Compensation Register is not locked and writes complete as normal. 11234 */ 11235 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) 11236 #define RTC_LR_CRL_MASK (0x10U) 11237 #define RTC_LR_CRL_SHIFT (4U) 11238 /*! CRL - Control Register Lock 11239 * 0b0..Control Register is locked and writes are ignored. 11240 * 0b1..Control Register is not locked and writes complete as normal. 11241 */ 11242 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) 11243 #define RTC_LR_SRL_MASK (0x20U) 11244 #define RTC_LR_SRL_SHIFT (5U) 11245 /*! SRL - Status Register Lock 11246 * 0b0..Status Register is locked and writes are ignored. 11247 * 0b1..Status Register is not locked and writes complete as normal. 11248 */ 11249 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) 11250 #define RTC_LR_LRL_MASK (0x40U) 11251 #define RTC_LR_LRL_SHIFT (6U) 11252 /*! LRL - Lock Register Lock 11253 * 0b0..Lock Register is locked and writes are ignored. 11254 * 0b1..Lock Register is not locked and writes complete as normal. 11255 */ 11256 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) 11257 /*! @} */ 11258 11259 /*! @name IER - RTC Interrupt Enable Register */ 11260 /*! @{ */ 11261 #define RTC_IER_TIIE_MASK (0x1U) 11262 #define RTC_IER_TIIE_SHIFT (0U) 11263 /*! TIIE - Time Invalid Interrupt Enable 11264 * 0b0..Time invalid flag does not generate an interrupt. 11265 * 0b1..Time invalid flag does generate an interrupt. 11266 */ 11267 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) 11268 #define RTC_IER_TOIE_MASK (0x2U) 11269 #define RTC_IER_TOIE_SHIFT (1U) 11270 /*! TOIE - Time Overflow Interrupt Enable 11271 * 0b0..Time overflow flag does not generate an interrupt. 11272 * 0b1..Time overflow flag does generate an interrupt. 11273 */ 11274 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) 11275 #define RTC_IER_TAIE_MASK (0x4U) 11276 #define RTC_IER_TAIE_SHIFT (2U) 11277 /*! TAIE - Time Alarm Interrupt Enable 11278 * 0b0..Time alarm flag does not generate an interrupt. 11279 * 0b1..Time alarm flag does generate an interrupt. 11280 */ 11281 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) 11282 #define RTC_IER_TSIE_MASK (0x10U) 11283 #define RTC_IER_TSIE_SHIFT (4U) 11284 /*! TSIE - Time Seconds Interrupt Enable 11285 * 0b0..Seconds interrupt is disabled. 11286 * 0b1..Seconds interrupt is enabled. 11287 */ 11288 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) 11289 #define RTC_IER_WPON_MASK (0x80U) 11290 #define RTC_IER_WPON_SHIFT (7U) 11291 /*! WPON - Wakeup Pin On 11292 * 0b0..No effect. 11293 * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert. 11294 */ 11295 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) 11296 /*! @} */ 11297 11298 /*! 11299 * @} 11300 */ /* end of group RTC_Register_Masks */ 11301 11302 /* RTC - Peripheral instance base addresses */ 11303 /** Peripheral RTC base address */ 11304 #define RTC_BASE (0x4003D000u) 11305 /** Peripheral RTC base pointer */ 11306 #define RTC ((RTC_Type *)RTC_BASE) 11307 /** Array initializer of RTC peripheral base addresses */ 11308 #define RTC_BASE_ADDRS \ 11309 { \ 11310 RTC_BASE \ 11311 } 11312 /** Array initializer of RTC peripheral base pointers */ 11313 #define RTC_BASE_PTRS \ 11314 { \ 11315 RTC \ 11316 } 11317 /** Interrupt vectors for the RTC peripheral type */ 11318 #define RTC_IRQS \ 11319 { \ 11320 RTC_IRQn \ 11321 } 11322 #define RTC_SECONDS_IRQS \ 11323 { \ 11324 RTC_Seconds_IRQn \ 11325 } 11326 11327 /*! 11328 * @} 11329 */ /* end of group RTC_Peripheral_Access_Layer */ 11330 11331 /* ---------------------------------------------------------------------------- 11332 -- SIM Peripheral Access Layer 11333 ---------------------------------------------------------------------------- */ 11334 11335 /*! 11336 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 11337 * @{ 11338 */ 11339 11340 /** SIM - Register Layout Typedef */ 11341 typedef struct 11342 { 11343 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 11344 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 11345 uint8_t RESERVED_0[4092]; 11346 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 11347 uint8_t RESERVED_1[4]; 11348 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 11349 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 11350 uint8_t RESERVED_2[4]; 11351 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 11352 uint8_t RESERVED_3[8]; 11353 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 11354 uint8_t RESERVED_4[12]; 11355 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 11356 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 11357 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 11358 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 11359 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 11360 uint8_t RESERVED_5[4]; 11361 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 11362 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 11363 uint8_t RESERVED_6[4]; 11364 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 11365 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 11366 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 11367 uint8_t RESERVED_7[156]; 11368 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 11369 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ 11370 } SIM_Type; 11371 11372 /* ---------------------------------------------------------------------------- 11373 -- SIM Register Masks 11374 ---------------------------------------------------------------------------- */ 11375 11376 /*! 11377 * @addtogroup SIM_Register_Masks SIM Register Masks 11378 * @{ 11379 */ 11380 11381 /*! @name SOPT1 - System Options Register 1 */ 11382 /*! @{ */ 11383 #define SIM_SOPT1_OSC32KOUT_MASK (0x30000U) 11384 #define SIM_SOPT1_OSC32KOUT_SHIFT (16U) 11385 /*! OSC32KOUT - 32K oscillator clock output 11386 * 0b00..ERCLK32K is not output. 11387 * 0b01..ERCLK32K is output on PTE0. 11388 * 0b10..ERCLK32K is output on PTE26. 11389 * 0b11..Reserved. 11390 */ 11391 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK) 11392 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 11393 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 11394 /*! OSC32KSEL - 32K Oscillator Clock Select 11395 * 0b00..System oscillator (OSC32KCLK) 11396 * 0b01..Reserved 11397 * 0b10..RTC_CLKIN 11398 * 0b11..LPO 1kHz 11399 */ 11400 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 11401 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) 11402 #define SIM_SOPT1_USBVSTBY_SHIFT (29U) 11403 /*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes 11404 * 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. 11405 * 0b1..USB voltage regulator in standby during VLPR and VLPW modes. 11406 */ 11407 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) 11408 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) 11409 #define SIM_SOPT1_USBSSTBY_SHIFT (30U) 11410 /*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 11411 * 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 11412 * 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. 11413 */ 11414 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) 11415 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) 11416 #define SIM_SOPT1_USBREGEN_SHIFT (31U) 11417 /*! USBREGEN - USB voltage regulator enable 11418 * 0b0..USB voltage regulator is disabled. 11419 * 0b1..USB voltage regulator is enabled. 11420 */ 11421 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) 11422 /*! @} */ 11423 11424 /*! @name SOPT1CFG - SOPT1 Configuration Register */ 11425 /*! @{ */ 11426 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) 11427 #define SIM_SOPT1CFG_URWE_SHIFT (24U) 11428 /*! URWE - USB voltage regulator enable write enable 11429 * 0b0..SOPT1 USBREGEN cannot be written. 11430 * 0b1..SOPT1 USBREGEN can be written. 11431 */ 11432 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) 11433 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) 11434 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) 11435 /*! UVSWE - USB voltage regulator VLP standby write enable 11436 * 0b0..SOPT1 USBVSTB cannot be written. 11437 * 0b1..SOPT1 USBVSTB can be written. 11438 */ 11439 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) 11440 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) 11441 #define SIM_SOPT1CFG_USSWE_SHIFT (26U) 11442 /*! USSWE - USB voltage regulator stop standby write enable 11443 * 0b0..SOPT1 USBSSTB cannot be written. 11444 * 0b1..SOPT1 USBSSTB can be written. 11445 */ 11446 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) 11447 /*! @} */ 11448 11449 /*! @name SOPT2 - System Options Register 2 */ 11450 /*! @{ */ 11451 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) 11452 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) 11453 /*! RTCCLKOUTSEL - RTC Clock Out Select 11454 * 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. 11455 * 0b1..OSCERCLK clock is output on the RTC_CLKOUT pin. 11456 */ 11457 #define SIM_SOPT2_RTCCLKOUTSEL(x) \ 11458 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) 11459 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) 11460 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) 11461 /*! CLKOUTSEL - CLKOUT select 11462 * 0b000..Reserved 11463 * 0b001..Reserved 11464 * 0b010..Bus clock 11465 * 0b011..LPO clock (1 kHz) 11466 * 0b100..LIRC_CLK 11467 * 0b101..Reserved 11468 * 0b110..OSCERCLK 11469 * 0b111..IRC48M clock (IRC48M clock can be output to PAD only when chip VDD is 2.7-3.6 V) 11470 */ 11471 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) 11472 #define SIM_SOPT2_USBSRC_MASK (0x40000U) 11473 #define SIM_SOPT2_USBSRC_SHIFT (18U) 11474 /*! USBSRC - USB clock source select 11475 * 0b0..External bypass clock (USB_CLKIN). 11476 * 0b1..IRC48M clock 11477 */ 11478 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) 11479 #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U) 11480 #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U) 11481 /*! FLEXIOSRC - FlexIO Module Clock Source Select 11482 * 0b00..Clock disabled 11483 * 0b01..IRC48M clock 11484 * 0b10..OSCERCLK clock 11485 * 0b11..MCGIRCLK clock 11486 */ 11487 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK) 11488 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) 11489 #define SIM_SOPT2_TPMSRC_SHIFT (24U) 11490 /*! TPMSRC - TPM Clock Source Select 11491 * 0b00..Clock disabled 11492 * 0b01..IRC48M clock 11493 * 0b10..OSCERCLK clock 11494 * 0b11..MCGIRCLK clock 11495 */ 11496 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) 11497 #define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U) 11498 #define SIM_SOPT2_LPUART0SRC_SHIFT (26U) 11499 /*! LPUART0SRC - LPUART0 Clock Source Select 11500 * 0b00..Clock disabled 11501 * 0b01..IRC48M clock 11502 * 0b10..OSCERCLK clock 11503 * 0b11..MCGIRCLK clock 11504 */ 11505 #define SIM_SOPT2_LPUART0SRC(x) \ 11506 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK) 11507 #define SIM_SOPT2_LPUART1SRC_MASK (0x30000000U) 11508 #define SIM_SOPT2_LPUART1SRC_SHIFT (28U) 11509 /*! LPUART1SRC - LPUART1 Clock Source Select 11510 * 0b00..Clock disabled 11511 * 0b01..IRC48M clock 11512 * 0b10..OSCERCLK clock 11513 * 0b11..MCGIRCLK clock 11514 */ 11515 #define SIM_SOPT2_LPUART1SRC(x) \ 11516 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK) 11517 /*! @} */ 11518 11519 /*! @name SOPT4 - System Options Register 4 */ 11520 /*! @{ */ 11521 #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U) 11522 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) 11523 /*! TPM1CH0SRC - TPM1 channel 0 input capture source select 11524 * 0b00..TPM1_CH0 signal 11525 * 0b01..CMP0 output 11526 * 0b10..Reserved 11527 * 0b11..USB start of frame pulse 11528 */ 11529 #define SIM_SOPT4_TPM1CH0SRC(x) \ 11530 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) 11531 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) 11532 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) 11533 /*! TPM2CH0SRC - TPM2 Channel 0 Input Capture Source Select 11534 * 0b0..TPM2_CH0 signal 11535 * 0b1..CMP0 output 11536 */ 11537 #define SIM_SOPT4_TPM2CH0SRC(x) \ 11538 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) 11539 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) 11540 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) 11541 /*! TPM0CLKSEL - TPM0 External Clock Pin Select 11542 * 0b0..TPM0 external clock driven by TPM_CLKIN0 pin. 11543 * 0b1..TPM0 external clock driven by TPM_CLKIN1 pin. 11544 */ 11545 #define SIM_SOPT4_TPM0CLKSEL(x) \ 11546 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) 11547 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) 11548 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) 11549 /*! TPM1CLKSEL - TPM1 External Clock Pin Select 11550 * 0b0..TPM1 external clock driven by TPM_CLKIN0 pin. 11551 * 0b1..TPM1 external clock driven by TPM_CLKIN1 pin. 11552 */ 11553 #define SIM_SOPT4_TPM1CLKSEL(x) \ 11554 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) 11555 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) 11556 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) 11557 /*! TPM2CLKSEL - TPM2 External Clock Pin Select 11558 * 0b0..TPM2 external clock driven by TPM_CLKIN0 pin. 11559 * 0b1..TPM2 external clock driven by TPM_CLKIN1 pin. 11560 */ 11561 #define SIM_SOPT4_TPM2CLKSEL(x) \ 11562 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) 11563 /*! @} */ 11564 11565 /*! @name SOPT5 - System Options Register 5 */ 11566 /*! @{ */ 11567 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U) 11568 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U) 11569 /*! LPUART0TXSRC - LPUART0 Transmit Data Source Select 11570 * 0b00..LPUART0_TX pin 11571 * 0b01..LPUART0_TX pin modulated with TPM1 channel 0 output 11572 * 0b10..LPUART0_TX pin modulated with TPM2 channel 0 output 11573 * 0b11..Reserved 11574 */ 11575 #define SIM_SOPT5_LPUART0TXSRC(x) \ 11576 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) 11577 #define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U) 11578 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U) 11579 /*! LPUART0RXSRC - LPUART0 Receive Data Source Select 11580 * 0b0..LPUART_RX pin 11581 * 0b1..CMP0 output 11582 */ 11583 #define SIM_SOPT5_LPUART0RXSRC(x) \ 11584 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) 11585 #define SIM_SOPT5_LPUART1TXSRC_MASK (0x30U) 11586 #define SIM_SOPT5_LPUART1TXSRC_SHIFT (4U) 11587 /*! LPUART1TXSRC - LPUART1 Transmit Data Source Select 11588 * 0b00..LPUART1_TX pin 11589 * 0b01..LPUART1_TX pin modulated with TPM1 channel 0 output 11590 * 0b10..LPUART1_TX pin modulated with TPM2 channel 0 output 11591 * 0b11..Reserved 11592 */ 11593 #define SIM_SOPT5_LPUART1TXSRC(x) \ 11594 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK) 11595 #define SIM_SOPT5_LPUART1RXSRC_MASK (0x40U) 11596 #define SIM_SOPT5_LPUART1RXSRC_SHIFT (6U) 11597 /*! LPUART1RXSRC - LPUART1 Receive Data Source Select 11598 * 0b0..LPUART1_RX pin 11599 * 0b1..CMP0 output 11600 */ 11601 #define SIM_SOPT5_LPUART1RXSRC(x) \ 11602 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK) 11603 #define SIM_SOPT5_LPUART0ODE_MASK (0x10000U) 11604 #define SIM_SOPT5_LPUART0ODE_SHIFT (16U) 11605 /*! LPUART0ODE - LPUART0 Open Drain Enable 11606 * 0b0..Open drain is disabled on LPUART0. 11607 * 0b1..Open drain is enabled on LPUART0. 11608 */ 11609 #define SIM_SOPT5_LPUART0ODE(x) \ 11610 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK) 11611 #define SIM_SOPT5_LPUART1ODE_MASK (0x20000U) 11612 #define SIM_SOPT5_LPUART1ODE_SHIFT (17U) 11613 /*! LPUART1ODE - LPUART1 Open Drain Enable 11614 * 0b0..Open drain is disabled on LPUART1. 11615 * 0b1..Open drain is enabled on LPUART1 11616 */ 11617 #define SIM_SOPT5_LPUART1ODE(x) \ 11618 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK) 11619 #define SIM_SOPT5_UART2ODE_MASK (0x40000U) 11620 #define SIM_SOPT5_UART2ODE_SHIFT (18U) 11621 /*! UART2ODE - UART2 Open Drain Enable 11622 * 0b0..Open drain is disabled on UART2 11623 * 0b1..Open drain is enabled on UART2 11624 */ 11625 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK) 11626 /*! @} */ 11627 11628 /*! @name SOPT7 - System Options Register 7 */ 11629 /*! @{ */ 11630 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) 11631 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) 11632 /*! ADC0TRGSEL - ADC0 Trigger Select 11633 * 0b0000..External trigger pin input (EXTRG_IN) 11634 * 0b0001..CMP0 output 11635 * 0b0010..Reserved 11636 * 0b0011..Reserved 11637 * 0b0100..PIT trigger 0 11638 * 0b0101..PIT trigger 1 11639 * 0b0110..Reserved 11640 * 0b0111..Reserved 11641 * 0b1000..TPM0 overflow 11642 * 0b1001..TPM1 overflow 11643 * 0b1010..TPM2 overflow 11644 * 0b1011..Reserved 11645 * 0b1100..RTC alarm 11646 * 0b1101..RTC seconds 11647 * 0b1110..LPTMR0 trigger 11648 * 0b1111..Reserved 11649 */ 11650 #define SIM_SOPT7_ADC0TRGSEL(x) \ 11651 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) 11652 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) 11653 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) 11654 /*! ADC0PRETRGSEL - ADC0 Pretrigger Select 11655 * 0b0..Pre-trigger ADHWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion 11656 * and store the result in ADC0_RA register. 11657 * 0b1..Pre-trigger ADHWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion 11658 * and store the result in ADC0_RB register. 11659 */ 11660 #define SIM_SOPT7_ADC0PRETRGSEL(x) \ 11661 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) 11662 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) 11663 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) 11664 /*! ADC0ALTTRGEN - ADC0 Alternate Trigger Enable 11665 * 0b0..ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a 11666 * pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and 11667 * store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will 11668 * be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in 11669 * ADCx_RB Register. 11670 * 0b1..ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select 11671 * the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result 11672 * regsiter to store the ADC conversion. 11673 */ 11674 #define SIM_SOPT7_ADC0ALTTRGEN(x) \ 11675 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) 11676 /*! @} */ 11677 11678 /*! @name SDID - System Device Identification Register */ 11679 /*! @{ */ 11680 #define SIM_SDID_PINID_MASK (0xFU) 11681 #define SIM_SDID_PINID_SHIFT (0U) 11682 /*! PINID - Pincount Identification 11683 * 0b0010..32-pin 11684 * 0b0100..48-pin 11685 * 0b0101..64-pin 11686 * 0b1011..Custom pinout (WLCSP) 11687 */ 11688 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 11689 #define SIM_SDID_REVID_MASK (0xF000U) 11690 #define SIM_SDID_REVID_SHIFT (12U) 11691 /*! REVID - Device Revision Number 11692 */ 11693 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 11694 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U) 11695 #define SIM_SDID_SRAMSIZE_SHIFT (16U) 11696 /*! SRAMSIZE - System SRAM Size 11697 * 0b0101..16 KB 11698 * 0b0110..32 KB 11699 */ 11700 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) 11701 #define SIM_SDID_SERIESID_MASK (0xF00000U) 11702 #define SIM_SDID_SERIESID_SHIFT (20U) 11703 /*! SERIESID - Series ID 11704 * 0b0001..K32 L2 family 11705 */ 11706 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) 11707 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 11708 #define SIM_SDID_SUBFAMID_SHIFT (24U) 11709 /*! SUBFAMID - Sub-Family ID 11710 * 0b0000..Dual core 11711 * 0b0001..Single core 11712 */ 11713 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 11714 #define SIM_SDID_FAMID_MASK (0xF0000000U) 11715 #define SIM_SDID_FAMID_SHIFT (28U) 11716 /*! FAMID 11717 * 0b0000..K32L3A 11718 * 0b0100..K32L2B 11719 * 0b0010..K32L2A 11720 */ 11721 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 11722 /*! @} */ 11723 11724 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 11725 /*! @{ */ 11726 #define SIM_SCGC4_I2C0_MASK (0x40U) 11727 #define SIM_SCGC4_I2C0_SHIFT (6U) 11728 /*! I2C0 - I2C0 Clock Gate Control 11729 * 0b0..Clock disabled 11730 * 0b1..Clock enabled 11731 */ 11732 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 11733 #define SIM_SCGC4_I2C1_MASK (0x80U) 11734 #define SIM_SCGC4_I2C1_SHIFT (7U) 11735 /*! I2C1 - I2C1 Clock Gate Control 11736 * 0b0..Clock disabled 11737 * 0b1..Clock enabled 11738 */ 11739 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) 11740 #define SIM_SCGC4_UART2_MASK (0x1000U) 11741 #define SIM_SCGC4_UART2_SHIFT (12U) 11742 /*! UART2 - UART2 Clock Gate Control 11743 * 0b0..Clock disabled 11744 * 0b1..Clock enabled 11745 */ 11746 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) 11747 #define SIM_SCGC4_USBFS_MASK (0x40000U) 11748 #define SIM_SCGC4_USBFS_SHIFT (18U) 11749 /*! USBFS - USB Clock Gate Control 11750 * 0b0..Clock disabled 11751 * 0b1..Clock enabled 11752 */ 11753 #define SIM_SCGC4_USBFS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK) 11754 #define SIM_SCGC4_CMP0_MASK (0x80000U) 11755 #define SIM_SCGC4_CMP0_SHIFT (19U) 11756 /*! CMP0 - Comparator Clock Gate Control 11757 * 0b0..Clock disabled 11758 * 0b1..Clock enabled 11759 */ 11760 #define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK) 11761 #define SIM_SCGC4_VREF_MASK (0x100000U) 11762 #define SIM_SCGC4_VREF_SHIFT (20U) 11763 /*! VREF - VREF Clock Gate Control 11764 * 0b0..Clock disabled 11765 * 0b1..Clock enabled 11766 */ 11767 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) 11768 #define SIM_SCGC4_SPI0_MASK (0x400000U) 11769 #define SIM_SCGC4_SPI0_SHIFT (22U) 11770 /*! SPI0 - SPI0 Clock Gate Control 11771 * 0b0..Clock disabled 11772 * 0b1..Clock enabled 11773 */ 11774 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) 11775 #define SIM_SCGC4_SPI1_MASK (0x800000U) 11776 #define SIM_SCGC4_SPI1_SHIFT (23U) 11777 /*! SPI1 - SPI1 Clock Gate Control 11778 * 0b0..Clock disabled 11779 * 0b1..Clock enabled 11780 */ 11781 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) 11782 /*! @} */ 11783 11784 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 11785 /*! @{ */ 11786 #define SIM_SCGC5_LPTMR_MASK (0x1U) 11787 #define SIM_SCGC5_LPTMR_SHIFT (0U) 11788 /*! LPTMR - Low Power Timer Access Control 11789 * 0b0..Access disabled 11790 * 0b1..Access enabled 11791 */ 11792 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) 11793 #define SIM_SCGC5_PORTA_MASK (0x200U) 11794 #define SIM_SCGC5_PORTA_SHIFT (9U) 11795 /*! PORTA - Port A Clock Gate Control 11796 * 0b0..Clock disabled 11797 * 0b1..Clock enabled 11798 */ 11799 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 11800 #define SIM_SCGC5_PORTB_MASK (0x400U) 11801 #define SIM_SCGC5_PORTB_SHIFT (10U) 11802 /*! PORTB - Port B Clock Gate Control 11803 * 0b0..Clock disabled 11804 * 0b1..Clock enabled 11805 */ 11806 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 11807 #define SIM_SCGC5_PORTC_MASK (0x800U) 11808 #define SIM_SCGC5_PORTC_SHIFT (11U) 11809 /*! PORTC - Port C Clock Gate Control 11810 * 0b0..Clock disabled 11811 * 0b1..Clock enabled 11812 */ 11813 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 11814 #define SIM_SCGC5_PORTD_MASK (0x1000U) 11815 #define SIM_SCGC5_PORTD_SHIFT (12U) 11816 /*! PORTD - Port D Clock Gate Control 11817 * 0b0..Clock disabled 11818 * 0b1..Clock enabled 11819 */ 11820 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 11821 #define SIM_SCGC5_PORTE_MASK (0x2000U) 11822 #define SIM_SCGC5_PORTE_SHIFT (13U) 11823 /*! PORTE - Port E Clock Gate Control 11824 * 0b0..Clock disabled 11825 * 0b1..Clock enabled 11826 */ 11827 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 11828 #define SIM_SCGC5_SLCD_MASK (0x80000U) 11829 #define SIM_SCGC5_SLCD_SHIFT (19U) 11830 /*! SLCD - Segment LCD Clock Gate Control 11831 * 0b0..Clock disabled 11832 * 0b1..Clock enabled 11833 */ 11834 #define SIM_SCGC5_SLCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SLCD_SHIFT)) & SIM_SCGC5_SLCD_MASK) 11835 #define SIM_SCGC5_LPUART0_MASK (0x100000U) 11836 #define SIM_SCGC5_LPUART0_SHIFT (20U) 11837 /*! LPUART0 - LPUART0 Clock Gate Control 11838 * 0b0..Clock disabled 11839 * 0b1..Clock enabled 11840 */ 11841 #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK) 11842 #define SIM_SCGC5_LPUART1_MASK (0x200000U) 11843 #define SIM_SCGC5_LPUART1_SHIFT (21U) 11844 /*! LPUART1 - LPUART1 Clock Gate Control 11845 * 0b0..Clock disabled 11846 * 0b1..Clock enabled 11847 */ 11848 #define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK) 11849 #define SIM_SCGC5_FLEXIO_MASK (0x80000000U) 11850 #define SIM_SCGC5_FLEXIO_SHIFT (31U) 11851 /*! FLEXIO - FlexIO Module 11852 * 0b0..Clock disabled 11853 * 0b1..Clock enabled 11854 */ 11855 #define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK) 11856 /*! @} */ 11857 11858 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 11859 /*! @{ */ 11860 #define SIM_SCGC6_FTF_MASK (0x1U) 11861 #define SIM_SCGC6_FTF_SHIFT (0U) 11862 /*! FTF - Flash Memory Clock Gate Control 11863 * 0b0..Clock disabled 11864 * 0b1..Clock enabled 11865 */ 11866 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) 11867 #define SIM_SCGC6_DMAMUX_MASK (0x2U) 11868 #define SIM_SCGC6_DMAMUX_SHIFT (1U) 11869 /*! DMAMUX - DMA Mux Clock Gate Control 11870 * 0b0..Clock disabled 11871 * 0b1..Clock enabled 11872 */ 11873 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) 11874 #define SIM_SCGC6_PIT_MASK (0x800000U) 11875 #define SIM_SCGC6_PIT_SHIFT (23U) 11876 /*! PIT - PIT Clock Gate Control 11877 * 0b0..Clock disabled 11878 * 0b1..Clock enabled 11879 */ 11880 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) 11881 #define SIM_SCGC6_TPM0_MASK (0x1000000U) 11882 #define SIM_SCGC6_TPM0_SHIFT (24U) 11883 /*! TPM0 - TPM0 Clock Gate Control 11884 * 0b0..Clock disabled 11885 * 0b1..Clock enabled 11886 */ 11887 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) 11888 #define SIM_SCGC6_TPM1_MASK (0x2000000U) 11889 #define SIM_SCGC6_TPM1_SHIFT (25U) 11890 /*! TPM1 - TPM1 Clock Gate Control 11891 * 0b0..Clock disabled 11892 * 0b1..Clock enabled 11893 */ 11894 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) 11895 #define SIM_SCGC6_TPM2_MASK (0x4000000U) 11896 #define SIM_SCGC6_TPM2_SHIFT (26U) 11897 /*! TPM2 - TPM2 Clock Gate Control 11898 * 0b0..Clock disabled 11899 * 0b1..Clock enabled 11900 */ 11901 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) 11902 #define SIM_SCGC6_ADC0_MASK (0x8000000U) 11903 #define SIM_SCGC6_ADC0_SHIFT (27U) 11904 /*! ADC0 - ADC0 Clock Gate Control 11905 * 0b0..Clock disabled 11906 * 0b1..Clock enabled 11907 */ 11908 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) 11909 #define SIM_SCGC6_RTC_MASK (0x20000000U) 11910 #define SIM_SCGC6_RTC_SHIFT (29U) 11911 /*! RTC - RTC Access Control 11912 * 0b0..Access and interrupts disabled 11913 * 0b1..Access and interrupts enabled 11914 */ 11915 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) 11916 #define SIM_SCGC6_DAC0_MASK (0x80000000U) 11917 #define SIM_SCGC6_DAC0_SHIFT (31U) 11918 /*! DAC0 - DAC0 Clock Gate Control 11919 * 0b0..Clock disabled 11920 * 0b1..Clock enabled 11921 */ 11922 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) 11923 /*! @} */ 11924 11925 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 11926 /*! @{ */ 11927 #define SIM_SCGC7_DMA_MASK (0x100U) 11928 #define SIM_SCGC7_DMA_SHIFT (8U) 11929 /*! DMA - DMA Clock Gate Control 11930 * 0b0..Clock disabled 11931 * 0b1..Clock enabled 11932 */ 11933 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 11934 /*! @} */ 11935 11936 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 11937 /*! @{ */ 11938 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) 11939 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) 11940 /*! OUTDIV4 - Clock 4 Output Divider value 11941 * 0b000..Divide-by-1. 11942 * 0b001..Divide-by-2. 11943 * 0b010..Divide-by-3. 11944 * 0b011..Divide-by-4. 11945 * 0b100..Divide-by-5. 11946 * 0b101..Divide-by-6. 11947 * 0b110..Divide-by-7. 11948 * 0b111..Divide-by-8. 11949 */ 11950 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) 11951 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) 11952 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) 11953 /*! OUTDIV1 - Clock 1 Output Divider value 11954 * 0b0000..Divide-by-1. 11955 * 0b0001..Divide-by-2. 11956 * 0b0010..Divide-by-3. 11957 * 0b0011..Divide-by-4. 11958 * 0b0100..Divide-by-5. 11959 * 0b0101..Divide-by-6. 11960 * 0b0110..Divide-by-7. 11961 * 0b0111..Divide-by-8. 11962 * 0b1000..Divide-by-9. 11963 * 0b1001..Divide-by-10. 11964 * 0b1010..Divide-by-11. 11965 * 0b1011..Divide-by-12. 11966 * 0b1100..Divide-by-13. 11967 * 0b1101..Divide-by-14. 11968 * 0b1110..Divide-by-15. 11969 * 0b1111..Divide-by-16. 11970 */ 11971 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) 11972 /*! @} */ 11973 11974 /*! @name FCFG1 - Flash Configuration Register 1 */ 11975 /*! @{ */ 11976 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 11977 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 11978 /*! FLASHDIS - Flash Disable 11979 * 0b0..Flash is enabled. 11980 * 0b1..Flash is disabled. 11981 */ 11982 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 11983 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 11984 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 11985 /*! FLASHDOZE - Flash Doze 11986 * 0b0..Flash remains enabled during Doze mode. 11987 * 0b1..Flash is disabled for the duration of Doze mode. 11988 */ 11989 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 11990 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 11991 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 11992 /*! PFSIZE - Program Flash Size 11993 * 0b0000..8 KB of program flash memory, 1 KB protection region 11994 * 0b0001..16 KB of program flash memory, 1 KB protection region 11995 * 0b0011..32 KB of program flash memory, 1 KB protection region 11996 * 0b0101..64 KB of program flash memory, 2 KB protection region 11997 * 0b0111..128 KB of program flash memory, 4 KB protection region 11998 * 0b1001..256 KB of program flash memory, 8 KB protection region 11999 * 0b1111..256 KB of program flash memory, 8 KB protection region 12000 */ 12001 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 12002 /*! @} */ 12003 12004 /*! @name FCFG2 - Flash Configuration Register 2 */ 12005 /*! @{ */ 12006 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) 12007 #define SIM_FCFG2_MAXADDR1_SHIFT (16U) 12008 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) 12009 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) 12010 #define SIM_FCFG2_MAXADDR0_SHIFT (24U) 12011 /*! MAXADDR0 - Max Address lock 12012 */ 12013 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) 12014 /*! @} */ 12015 12016 /*! @name UIDMH - Unique Identification Register Mid-High */ 12017 /*! @{ */ 12018 #define SIM_UIDMH_UID_MASK (0xFFFFU) 12019 #define SIM_UIDMH_UID_SHIFT (0U) 12020 /*! UID - Unique Identification 12021 */ 12022 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) 12023 /*! @} */ 12024 12025 /*! @name UIDML - Unique Identification Register Mid Low */ 12026 /*! @{ */ 12027 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) 12028 #define SIM_UIDML_UID_SHIFT (0U) 12029 /*! UID - Unique Identification 12030 */ 12031 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) 12032 /*! @} */ 12033 12034 /*! @name UIDL - Unique Identification Register Low */ 12035 /*! @{ */ 12036 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) 12037 #define SIM_UIDL_UID_SHIFT (0U) 12038 /*! UID - Unique Identification 12039 */ 12040 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) 12041 /*! @} */ 12042 12043 /*! @name COPC - COP Control Register */ 12044 /*! @{ */ 12045 #define SIM_COPC_COPW_MASK (0x1U) 12046 #define SIM_COPC_COPW_SHIFT (0U) 12047 /*! COPW - COP Windowed Mode 12048 * 0b0..Normal mode 12049 * 0b1..Windowed mode 12050 */ 12051 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) 12052 #define SIM_COPC_COPCLKS_MASK (0x2U) 12053 #define SIM_COPC_COPCLKS_SHIFT (1U) 12054 /*! COPCLKS - COP Clock Select 12055 * 0b0..COP configured for short timeout 12056 * 0b1..COP configured for long timeout 12057 */ 12058 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) 12059 #define SIM_COPC_COPT_MASK (0xCU) 12060 #define SIM_COPC_COPT_SHIFT (2U) 12061 /*! COPT - COP Watchdog Timeout 12062 * 0b00..COP disabled 12063 * 0b01..COP timeout after 25 cycles for short timeout or 213 cycles for long timeout 12064 * 0b10..COP timeout after 28 cycles for short timeout or 216 cycles for long timeout 12065 * 0b11..COP timeout after 210 cycles for short timeout or 218 cycles for long timeout 12066 */ 12067 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) 12068 #define SIM_COPC_COPSTPEN_MASK (0x10U) 12069 #define SIM_COPC_COPSTPEN_SHIFT (4U) 12070 /*! COPSTPEN - COP Stop Enable 12071 * 0b0..COP is disabled and the counter is reset in Stop modes 12072 * 0b1..COP is enabled in Stop modes 12073 */ 12074 #define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK) 12075 #define SIM_COPC_COPDBGEN_MASK (0x20U) 12076 #define SIM_COPC_COPDBGEN_SHIFT (5U) 12077 /*! COPDBGEN - COP Debug Enable 12078 * 0b0..COP is disabled and the counter is reset in Debug mode 12079 * 0b1..COP is enabled in Debug mode 12080 */ 12081 #define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK) 12082 #define SIM_COPC_COPCLKSEL_MASK (0xC0U) 12083 #define SIM_COPC_COPCLKSEL_SHIFT (6U) 12084 /*! COPCLKSEL - COP Clock Select 12085 * 0b00..LPO clock (1 kHz) 12086 * 0b01..MCGIRCLK 12087 * 0b10..OSCERCLK 12088 * 0b11..Bus clock 12089 */ 12090 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK) 12091 /*! @} */ 12092 12093 /*! @name SRVCOP - Service COP */ 12094 /*! @{ */ 12095 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU) 12096 #define SIM_SRVCOP_SRVCOP_SHIFT (0U) 12097 /*! SRVCOP - Service COP Register 12098 */ 12099 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) 12100 /*! @} */ 12101 12102 /*! 12103 * @} 12104 */ /* end of group SIM_Register_Masks */ 12105 12106 /* SIM - Peripheral instance base addresses */ 12107 /** Peripheral SIM base address */ 12108 #define SIM_BASE (0x40047000u) 12109 /** Peripheral SIM base pointer */ 12110 #define SIM ((SIM_Type *)SIM_BASE) 12111 /** Array initializer of SIM peripheral base addresses */ 12112 #define SIM_BASE_ADDRS \ 12113 { \ 12114 SIM_BASE \ 12115 } 12116 /** Array initializer of SIM peripheral base pointers */ 12117 #define SIM_BASE_PTRS \ 12118 { \ 12119 SIM \ 12120 } 12121 12122 /*! 12123 * @} 12124 */ /* end of group SIM_Peripheral_Access_Layer */ 12125 12126 /* ---------------------------------------------------------------------------- 12127 -- SMC Peripheral Access Layer 12128 ---------------------------------------------------------------------------- */ 12129 12130 /*! 12131 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 12132 * @{ 12133 */ 12134 12135 /** SMC - Register Layout Typedef */ 12136 typedef struct 12137 { 12138 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 12139 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 12140 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 12141 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 12142 } SMC_Type; 12143 12144 /* ---------------------------------------------------------------------------- 12145 -- SMC Register Masks 12146 ---------------------------------------------------------------------------- */ 12147 12148 /*! 12149 * @addtogroup SMC_Register_Masks SMC Register Masks 12150 * @{ 12151 */ 12152 12153 /*! @name PMPROT - Power Mode Protection register */ 12154 /*! @{ */ 12155 #define SMC_PMPROT_AVLLS_MASK (0x2U) 12156 #define SMC_PMPROT_AVLLS_SHIFT (1U) 12157 /*! AVLLS - Allow Very-Low-Leakage Stop Mode 12158 * 0b0..Any VLLSx mode is not allowed 12159 * 0b1..Any VLLSx mode is allowed 12160 */ 12161 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 12162 #define SMC_PMPROT_ALLS_MASK (0x8U) 12163 #define SMC_PMPROT_ALLS_SHIFT (3U) 12164 /*! ALLS - Allow Low-Leakage Stop Mode 12165 * 0b0..LLS is not allowed 12166 * 0b1..LLS is allowed 12167 */ 12168 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) 12169 #define SMC_PMPROT_AVLP_MASK (0x20U) 12170 #define SMC_PMPROT_AVLP_SHIFT (5U) 12171 /*! AVLP - Allow Very-Low-Power Modes 12172 * 0b0..VLPR, VLPW, and VLPS are not allowed. 12173 * 0b1..VLPR, VLPW, and VLPS are allowed. 12174 */ 12175 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 12176 /*! @} */ 12177 12178 /*! @name PMCTRL - Power Mode Control register */ 12179 /*! @{ */ 12180 #define SMC_PMCTRL_STOPM_MASK (0x7U) 12181 #define SMC_PMCTRL_STOPM_SHIFT (0U) 12182 /*! STOPM - Stop Mode Control 12183 * 0b000..Normal Stop (STOP) 12184 * 0b001..Reserved 12185 * 0b010..Very-Low-Power Stop (VLPS) 12186 * 0b011..Low-Leakage Stop (LLS) 12187 * 0b100..Very-Low-Leakage Stop (VLLSx) 12188 * 0b101..Reserved 12189 * 0b110..Reseved 12190 * 0b111..Reserved 12191 */ 12192 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 12193 #define SMC_PMCTRL_STOPA_MASK (0x8U) 12194 #define SMC_PMCTRL_STOPA_SHIFT (3U) 12195 /*! STOPA - Stop Aborted 12196 * 0b0..The previous stop mode entry was successful. 12197 * 0b1..The previous stop mode entry was aborted. 12198 */ 12199 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 12200 #define SMC_PMCTRL_RUNM_MASK (0x60U) 12201 #define SMC_PMCTRL_RUNM_SHIFT (5U) 12202 /*! RUNM - Run Mode Control 12203 * 0b00..Normal Run mode (RUN) 12204 * 0b01..Reserved 12205 * 0b10..Very-Low-Power Run mode (VLPR) 12206 * 0b11..Reserved 12207 */ 12208 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 12209 /*! @} */ 12210 12211 /*! @name STOPCTRL - Stop Control Register */ 12212 /*! @{ */ 12213 #define SMC_STOPCTRL_VLLSM_MASK (0x7U) 12214 #define SMC_STOPCTRL_VLLSM_SHIFT (0U) 12215 /*! VLLSM - VLLS Mode Control 12216 * 0b000..VLLS0 12217 * 0b001..VLLS1 12218 * 0b010..Reserved 12219 * 0b011..VLLS3 12220 * 0b100..Reserved 12221 * 0b101..Reserved 12222 * 0b110..Reserved 12223 * 0b111..Reserved 12224 */ 12225 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) 12226 #define SMC_STOPCTRL_PORPO_MASK (0x20U) 12227 #define SMC_STOPCTRL_PORPO_SHIFT (5U) 12228 /*! PORPO - POR Power Option 12229 * 0b0..POR detect circuit is enabled in VLLS0 12230 * 0b1..POR detect circuit is disabled in VLLS0 12231 */ 12232 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) 12233 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 12234 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 12235 /*! PSTOPO - Partial Stop Option 12236 * 0b00..STOP - Normal Stop mode 12237 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled 12238 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 12239 * 0b11..Reserved 12240 */ 12241 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 12242 /*! @} */ 12243 12244 /*! @name PMSTAT - Power Mode Status register */ 12245 /*! @{ */ 12246 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) 12247 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 12248 /*! PMSTAT - Power Mode Status 12249 */ 12250 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 12251 /*! @} */ 12252 12253 /*! 12254 * @} 12255 */ /* end of group SMC_Register_Masks */ 12256 12257 /* SMC - Peripheral instance base addresses */ 12258 /** Peripheral SMC base address */ 12259 #define SMC_BASE (0x4007E000u) 12260 /** Peripheral SMC base pointer */ 12261 #define SMC ((SMC_Type *)SMC_BASE) 12262 /** Array initializer of SMC peripheral base addresses */ 12263 #define SMC_BASE_ADDRS \ 12264 { \ 12265 SMC_BASE \ 12266 } 12267 /** Array initializer of SMC peripheral base pointers */ 12268 #define SMC_BASE_PTRS \ 12269 { \ 12270 SMC \ 12271 } 12272 12273 /*! 12274 * @} 12275 */ /* end of group SMC_Peripheral_Access_Layer */ 12276 12277 /* ---------------------------------------------------------------------------- 12278 -- SPI Peripheral Access Layer 12279 ---------------------------------------------------------------------------- */ 12280 12281 /*! 12282 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 12283 * @{ 12284 */ 12285 12286 /** SPI - Register Layout Typedef */ 12287 typedef struct 12288 { 12289 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */ 12290 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ 12291 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ 12292 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ 12293 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ 12294 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ 12295 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ 12296 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ 12297 uint8_t RESERVED_0[2]; 12298 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ 12299 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ 12300 } SPI_Type; 12301 12302 /* ---------------------------------------------------------------------------- 12303 -- SPI Register Masks 12304 ---------------------------------------------------------------------------- */ 12305 12306 /*! 12307 * @addtogroup SPI_Register_Masks SPI Register Masks 12308 * @{ 12309 */ 12310 12311 /*! @name S - SPI Status Register */ 12312 /*! @{ */ 12313 #define SPI_S_RFIFOEF_MASK (0x1U) 12314 #define SPI_S_RFIFOEF_SHIFT (0U) 12315 /*! RFIFOEF - SPI read FIFO empty flag 12316 * 0b0..Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the 12317 * read FIFO. 0b1..Read FIFO is empty. 12318 */ 12319 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK) 12320 #define SPI_S_TXFULLF_MASK (0x2U) 12321 #define SPI_S_TXFULLF_SHIFT (1U) 12322 /*! TXFULLF - Transmit FIFO full flag 12323 * 0b0..Transmit FIFO has less than 8 bytes 12324 * 0b1..Transmit FIFO has 8 bytes of data 12325 */ 12326 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK) 12327 #define SPI_S_TNEAREF_MASK (0x4U) 12328 #define SPI_S_TNEAREF_SHIFT (2U) 12329 /*! TNEAREF - Transmit FIFO nearly empty flag 12330 * 0b0..Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 12331 * 1) remaining to transmit 0b1..Transmit FIFO has an amount of data equal to or less than 16 bits (when 12332 * C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit 12333 */ 12334 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK) 12335 #define SPI_S_RNFULLF_MASK (0x8U) 12336 #define SPI_S_RNFULLF_SHIFT (3U) 12337 /*! RNFULLF - Receive FIFO nearly full flag 12338 * 0b0..Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when 12339 * C3[RNFULLF_MARK] is 1) 0b1..Receive FIFO has received data of an amount equal to or greater than 48 bits (when 12340 * C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1) 12341 */ 12342 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK) 12343 #define SPI_S_MODF_MASK (0x10U) 12344 #define SPI_S_MODF_SHIFT (4U) 12345 /*! MODF - Master Mode Fault Flag 12346 * 0b0..No mode fault error 12347 * 0b1..Mode fault error detected 12348 */ 12349 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 12350 #define SPI_S_SPTEF_MASK (0x20U) 12351 #define SPI_S_SPTEF_SHIFT (5U) 12352 /*! SPTEF - SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI 12353 * transmit FIFO empty flag (when FIFO is supported and enabled) 12354 * 0b0..SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) 12355 * 0b1..SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) 12356 */ 12357 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 12358 #define SPI_S_SPMF_MASK (0x40U) 12359 #define SPI_S_SPMF_SHIFT (6U) 12360 /*! SPMF - SPI Match Flag 12361 * 0b0..Value in the receive data buffer does not match the value in the MH:ML registers 12362 * 0b1..Value in the receive data buffer matches the value in the MH:ML registers 12363 */ 12364 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 12365 #define SPI_S_SPRF_MASK (0x80U) 12366 #define SPI_S_SPRF_SHIFT (7U) 12367 /*! SPRF - SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO 12368 * FULL flag (when FIFO is supported and enabled) 12369 * 0b0..No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full 12370 * (when FIFOMODE is 1) 0b1..Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read 12371 * FIFO is full (when FIFOMODE is 1) 12372 */ 12373 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 12374 /*! @} */ 12375 12376 /*! @name BR - SPI Baud Rate Register */ 12377 /*! @{ */ 12378 #define SPI_BR_SPR_MASK (0xFU) 12379 #define SPI_BR_SPR_SHIFT (0U) 12380 /*! SPR - SPI Baud Rate Divisor 12381 * 0b0000..Baud rate divisor is 2. 12382 * 0b0001..Baud rate divisor is 4. 12383 * 0b0010..Baud rate divisor is 8. 12384 * 0b0011..Baud rate divisor is 16. 12385 * 0b0100..Baud rate divisor is 32. 12386 * 0b0101..Baud rate divisor is 64. 12387 * 0b0110..Baud rate divisor is 128. 12388 * 0b0111..Baud rate divisor is 256. 12389 * 0b1000..Baud rate divisor is 512. 12390 */ 12391 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 12392 #define SPI_BR_SPPR_MASK (0x70U) 12393 #define SPI_BR_SPPR_SHIFT (4U) 12394 /*! SPPR - SPI Baud Rate Prescale Divisor 12395 * 0b000..Baud rate prescaler divisor is 1. 12396 * 0b001..Baud rate prescaler divisor is 2. 12397 * 0b010..Baud rate prescaler divisor is 3. 12398 * 0b011..Baud rate prescaler divisor is 4. 12399 * 0b100..Baud rate prescaler divisor is 5. 12400 * 0b101..Baud rate prescaler divisor is 6. 12401 * 0b110..Baud rate prescaler divisor is 7. 12402 * 0b111..Baud rate prescaler divisor is 8. 12403 */ 12404 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 12405 /*! @} */ 12406 12407 /*! @name C2 - SPI Control Register 2 */ 12408 /*! @{ */ 12409 #define SPI_C2_SPC0_MASK (0x1U) 12410 #define SPI_C2_SPC0_SHIFT (0U) 12411 /*! SPC0 - SPI Pin Control 0 12412 * 0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: 12413 * MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave 12414 * in. 12415 * 0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of 12416 * operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In 12417 * slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not 12418 * used by SPI. 12419 */ 12420 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 12421 #define SPI_C2_SPISWAI_MASK (0x2U) 12422 #define SPI_C2_SPISWAI_SHIFT (1U) 12423 /*! SPISWAI - SPI Stop in Wait Mode 12424 * 0b0..SPI clocks continue to operate in Wait mode. 12425 * 0b1..SPI clocks stop when the MCU enters Wait mode. 12426 */ 12427 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 12428 #define SPI_C2_RXDMAE_MASK (0x4U) 12429 #define SPI_C2_RXDMAE_SHIFT (2U) 12430 /*! RXDMAE - Receive DMA enable 12431 * 0b0..DMA request for receive is disabled and interrupt from SPRF is allowed 12432 * 0b1..DMA request for receive is enabled and interrupt from SPRF is disabled 12433 */ 12434 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) 12435 #define SPI_C2_BIDIROE_MASK (0x8U) 12436 #define SPI_C2_BIDIROE_SHIFT (3U) 12437 /*! BIDIROE - Bidirectional Mode Output Enable 12438 * 0b0..Output driver disabled so SPI data I/O pin acts as an input 12439 * 0b1..SPI I/O pin enabled as an output 12440 */ 12441 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 12442 #define SPI_C2_MODFEN_MASK (0x10U) 12443 #define SPI_C2_MODFEN_SHIFT (4U) 12444 /*! MODFEN - Master Mode-Fault Function Enable 12445 * 0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 12446 * 0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 12447 */ 12448 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 12449 #define SPI_C2_TXDMAE_MASK (0x20U) 12450 #define SPI_C2_TXDMAE_SHIFT (5U) 12451 /*! TXDMAE - Transmit DMA enable 12452 * 0b0..DMA request for transmit is disabled and interrupt from SPTEF is allowed 12453 * 0b1..DMA request for transmit is enabled and interrupt from SPTEF is disabled 12454 */ 12455 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) 12456 #define SPI_C2_SPIMODE_MASK (0x40U) 12457 #define SPI_C2_SPIMODE_SHIFT (6U) 12458 /*! SPIMODE - SPI 8-bit or 16-bit mode 12459 * 0b0..8-bit SPI shift register, match register, and buffers 12460 * 0b1..16-bit SPI shift register, match register, and buffers 12461 */ 12462 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK) 12463 #define SPI_C2_SPMIE_MASK (0x80U) 12464 #define SPI_C2_SPMIE_SHIFT (7U) 12465 /*! SPMIE - SPI Match Interrupt Enable 12466 * 0b0..Interrupts from SPMF inhibited (use polling) 12467 * 0b1..When SPMF is 1, requests a hardware interrupt 12468 */ 12469 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 12470 /*! @} */ 12471 12472 /*! @name C1 - SPI Control Register 1 */ 12473 /*! @{ */ 12474 #define SPI_C1_LSBFE_MASK (0x1U) 12475 #define SPI_C1_LSBFE_SHIFT (0U) 12476 /*! LSBFE - LSB First (shifter direction) 12477 * 0b0..SPI serial data transfers start with the most significant bit. 12478 * 0b1..SPI serial data transfers start with the least significant bit. 12479 */ 12480 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 12481 #define SPI_C1_SSOE_MASK (0x2U) 12482 #define SPI_C1_SSOE_SHIFT (1U) 12483 /*! SSOE - Slave Select Output Enable 12484 * 0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS 12485 * pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for 12486 * mode fault. In slave mode, SS pin function is slave select input. 12487 * 0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS 12488 * pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS 12489 * output. In slave mode: SS pin function is slave select input. 12490 */ 12491 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 12492 #define SPI_C1_CPHA_MASK (0x4U) 12493 #define SPI_C1_CPHA_SHIFT (2U) 12494 /*! CPHA - Clock Phase 12495 * 0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 12496 * 0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer. 12497 */ 12498 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 12499 #define SPI_C1_CPOL_MASK (0x8U) 12500 #define SPI_C1_CPOL_SHIFT (3U) 12501 /*! CPOL - Clock Polarity 12502 * 0b0..Active-high SPI clock (idles low) 12503 * 0b1..Active-low SPI clock (idles high) 12504 */ 12505 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 12506 #define SPI_C1_MSTR_MASK (0x10U) 12507 #define SPI_C1_MSTR_SHIFT (4U) 12508 /*! MSTR - Master/Slave Mode Select 12509 * 0b0..SPI module configured as a slave SPI device 12510 * 0b1..SPI module configured as a master SPI device 12511 */ 12512 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 12513 #define SPI_C1_SPTIE_MASK (0x20U) 12514 #define SPI_C1_SPTIE_SHIFT (5U) 12515 /*! SPTIE - SPI Transmit Interrupt Enable 12516 * 0b0..Interrupts from SPTEF inhibited (use polling) 12517 * 0b1..When SPTEF is 1, hardware interrupt requested 12518 */ 12519 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 12520 #define SPI_C1_SPE_MASK (0x40U) 12521 #define SPI_C1_SPE_SHIFT (6U) 12522 /*! SPE - SPI System Enable 12523 * 0b0..SPI system inactive 12524 * 0b1..SPI system enabled 12525 */ 12526 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 12527 #define SPI_C1_SPIE_MASK (0x80U) 12528 #define SPI_C1_SPIE_SHIFT (7U) 12529 /*! SPIE - SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or 12530 * for read FIFO (when FIFO is supported and enabled) 12531 * 0b0..Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read 12532 * FIFO Full Interrupts are disabled (when FIFOMODE is 1) 12533 * 0b1..Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO 12534 * Full Interrupts are enabled (when FIFOMODE is 1) 12535 */ 12536 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 12537 /*! @} */ 12538 12539 /*! @name ML - SPI Match Register low */ 12540 /*! @{ */ 12541 #define SPI_ML_Bits_MASK (0xFFU) 12542 #define SPI_ML_Bits_SHIFT (0U) 12543 /*! Bits - Hardware compare value (low byte) 12544 */ 12545 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK) 12546 /*! @} */ 12547 12548 /*! @name MH - SPI match register high */ 12549 /*! @{ */ 12550 #define SPI_MH_Bits_MASK (0xFFU) 12551 #define SPI_MH_Bits_SHIFT (0U) 12552 /*! Bits - Hardware compare value (high byte) 12553 */ 12554 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK) 12555 /*! @} */ 12556 12557 /*! @name DL - SPI Data Register low */ 12558 /*! @{ */ 12559 #define SPI_DL_Bits_MASK (0xFFU) 12560 #define SPI_DL_Bits_SHIFT (0U) 12561 /*! Bits - Data (low byte) 12562 */ 12563 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK) 12564 /*! @} */ 12565 12566 /*! @name DH - SPI data register high */ 12567 /*! @{ */ 12568 #define SPI_DH_Bits_MASK (0xFFU) 12569 #define SPI_DH_Bits_SHIFT (0U) 12570 /*! Bits - Data (high byte) 12571 */ 12572 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK) 12573 /*! @} */ 12574 12575 /*! @name CI - SPI clear interrupt register */ 12576 /*! @{ */ 12577 #define SPI_CI_SPRFCI_MASK (0x1U) 12578 #define SPI_CI_SPRFCI_SHIFT (0U) 12579 /*! SPRFCI - Receive FIFO full flag clear interrupt 12580 */ 12581 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK) 12582 #define SPI_CI_SPTEFCI_MASK (0x2U) 12583 #define SPI_CI_SPTEFCI_SHIFT (1U) 12584 /*! SPTEFCI - Transmit FIFO empty flag clear interrupt 12585 */ 12586 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK) 12587 #define SPI_CI_RNFULLFCI_MASK (0x4U) 12588 #define SPI_CI_RNFULLFCI_SHIFT (2U) 12589 /*! RNFULLFCI - Receive FIFO nearly full flag clear interrupt 12590 */ 12591 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK) 12592 #define SPI_CI_TNEAREFCI_MASK (0x8U) 12593 #define SPI_CI_TNEAREFCI_SHIFT (3U) 12594 /*! TNEAREFCI - Transmit FIFO nearly empty flag clear interrupt 12595 */ 12596 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK) 12597 #define SPI_CI_RXFOF_MASK (0x10U) 12598 #define SPI_CI_RXFOF_SHIFT (4U) 12599 /*! RXFOF - Receive FIFO overflow flag 12600 * 0b0..Receive FIFO overflow condition has not occurred 12601 * 0b1..Receive FIFO overflow condition occurred 12602 */ 12603 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK) 12604 #define SPI_CI_TXFOF_MASK (0x20U) 12605 #define SPI_CI_TXFOF_SHIFT (5U) 12606 /*! TXFOF - Transmit FIFO overflow flag 12607 * 0b0..Transmit FIFO overflow condition has not occurred 12608 * 0b1..Transmit FIFO overflow condition occurred 12609 */ 12610 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK) 12611 #define SPI_CI_RXFERR_MASK (0x40U) 12612 #define SPI_CI_RXFERR_SHIFT (6U) 12613 /*! RXFERR - Receive FIFO error flag 12614 * 0b0..No receive FIFO error occurred 12615 * 0b1..A receive FIFO error occurred 12616 */ 12617 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK) 12618 #define SPI_CI_TXFERR_MASK (0x80U) 12619 #define SPI_CI_TXFERR_SHIFT (7U) 12620 /*! TXFERR - Transmit FIFO error flag 12621 * 0b0..No transmit FIFO error occurred 12622 * 0b1..A transmit FIFO error occurred 12623 */ 12624 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK) 12625 /*! @} */ 12626 12627 /*! @name C3 - SPI control register 3 */ 12628 /*! @{ */ 12629 #define SPI_C3_FIFOMODE_MASK (0x1U) 12630 #define SPI_C3_FIFOMODE_SHIFT (0U) 12631 /*! FIFOMODE - FIFO mode enable 12632 * 0b0..FIFO mode disabled 12633 * 0b1..FIFO mode enabled 12634 */ 12635 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK) 12636 #define SPI_C3_RNFULLIEN_MASK (0x2U) 12637 #define SPI_C3_RNFULLIEN_SHIFT (1U) 12638 /*! RNFULLIEN - Receive FIFO nearly full interrupt enable 12639 * 0b0..No interrupt upon RNFULLF being set 12640 * 0b1..Enable interrupts upon RNFULLF being set 12641 */ 12642 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK) 12643 #define SPI_C3_TNEARIEN_MASK (0x4U) 12644 #define SPI_C3_TNEARIEN_SHIFT (2U) 12645 /*! TNEARIEN - Transmit FIFO nearly empty interrupt enable 12646 * 0b0..No interrupt upon TNEAREF being set 12647 * 0b1..Enable interrupts upon TNEAREF being set 12648 */ 12649 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK) 12650 #define SPI_C3_INTCLR_MASK (0x8U) 12651 #define SPI_C3_INTCLR_SHIFT (3U) 12652 /*! INTCLR - Interrupt clearing mechanism select 12653 * 0b0..These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs 12654 * 0b1..These interrupts are cleared by writing the corresponding bits in the CI register 12655 */ 12656 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK) 12657 #define SPI_C3_RNFULLF_MARK_MASK (0x10U) 12658 #define SPI_C3_RNFULLF_MARK_SHIFT (4U) 12659 /*! RNFULLF_MARK - Receive FIFO nearly full watermark 12660 * 0b0..RNFULLF is set when the receive FIFO has 48 bits or more 12661 * 0b1..RNFULLF is set when the receive FIFO has 32 bits or more 12662 */ 12663 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK) 12664 #define SPI_C3_TNEAREF_MARK_MASK (0x20U) 12665 #define SPI_C3_TNEAREF_MARK_SHIFT (5U) 12666 /*! TNEAREF_MARK - Transmit FIFO nearly empty watermark 12667 * 0b0..TNEAREF is set when the transmit FIFO has 16 bits or less 12668 * 0b1..TNEAREF is set when the transmit FIFO has 32 bits or less 12669 */ 12670 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK) 12671 /*! @} */ 12672 12673 /*! 12674 * @} 12675 */ /* end of group SPI_Register_Masks */ 12676 12677 /* SPI - Peripheral instance base addresses */ 12678 /** Peripheral SPI0 base address */ 12679 #define SPI0_BASE (0x40076000u) 12680 /** Peripheral SPI0 base pointer */ 12681 #define SPI0 ((SPI_Type *)SPI0_BASE) 12682 /** Peripheral SPI1 base address */ 12683 #define SPI1_BASE (0x40077000u) 12684 /** Peripheral SPI1 base pointer */ 12685 #define SPI1 ((SPI_Type *)SPI1_BASE) 12686 /** Array initializer of SPI peripheral base addresses */ 12687 #define SPI_BASE_ADDRS \ 12688 { \ 12689 SPI0_BASE, SPI1_BASE \ 12690 } 12691 /** Array initializer of SPI peripheral base pointers */ 12692 #define SPI_BASE_PTRS \ 12693 { \ 12694 SPI0, SPI1 \ 12695 } 12696 /** Interrupt vectors for the SPI peripheral type */ 12697 #define SPI_IRQS \ 12698 { \ 12699 SPI0_IRQn, SPI1_IRQn \ 12700 } 12701 12702 /*! 12703 * @} 12704 */ /* end of group SPI_Peripheral_Access_Layer */ 12705 12706 /* ---------------------------------------------------------------------------- 12707 -- TPM Peripheral Access Layer 12708 ---------------------------------------------------------------------------- */ 12709 12710 /*! 12711 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer 12712 * @{ 12713 */ 12714 12715 /** TPM - Register Layout Typedef */ 12716 typedef struct 12717 { 12718 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 12719 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 12720 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 12721 struct 12722 { /* offset: 0xC, array step: 0x8 */ 12723 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 12724 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 12725 } CONTROLS[6]; 12726 uint8_t RESERVED_0[20]; 12727 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 12728 uint8_t RESERVED_1[28]; 12729 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ 12730 uint8_t RESERVED_2[16]; 12731 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 12732 } TPM_Type; 12733 12734 /* ---------------------------------------------------------------------------- 12735 -- TPM Register Masks 12736 ---------------------------------------------------------------------------- */ 12737 12738 /*! 12739 * @addtogroup TPM_Register_Masks TPM Register Masks 12740 * @{ 12741 */ 12742 12743 /*! @name SC - Status and Control */ 12744 /*! @{ */ 12745 #define TPM_SC_PS_MASK (0x7U) 12746 #define TPM_SC_PS_SHIFT (0U) 12747 /*! PS - Prescale Factor Selection 12748 * 0b000..Divide by 1 12749 * 0b001..Divide by 2 12750 * 0b010..Divide by 4 12751 * 0b011..Divide by 8 12752 * 0b100..Divide by 16 12753 * 0b101..Divide by 32 12754 * 0b110..Divide by 64 12755 * 0b111..Divide by 128 12756 */ 12757 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) 12758 #define TPM_SC_CMOD_MASK (0x18U) 12759 #define TPM_SC_CMOD_SHIFT (3U) 12760 /*! CMOD - Clock Mode Selection 12761 * 0b00..TPM counter is disabled 12762 * 0b01..TPM counter increments on every TPM counter clock 12763 * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 12764 * 0b11..Reserved. 12765 */ 12766 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) 12767 #define TPM_SC_CPWMS_MASK (0x20U) 12768 #define TPM_SC_CPWMS_SHIFT (5U) 12769 /*! CPWMS - Center-Aligned PWM Select 12770 * 0b0..TPM counter operates in up counting mode. 12771 * 0b1..TPM counter operates in up-down counting mode. 12772 */ 12773 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) 12774 #define TPM_SC_TOIE_MASK (0x40U) 12775 #define TPM_SC_TOIE_SHIFT (6U) 12776 /*! TOIE - Timer Overflow Interrupt Enable 12777 * 0b0..Disable TOF interrupts. Use software polling or DMA request. 12778 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 12779 */ 12780 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) 12781 #define TPM_SC_TOF_MASK (0x80U) 12782 #define TPM_SC_TOF_SHIFT (7U) 12783 /*! TOF - Timer Overflow Flag 12784 * 0b0..TPM counter has not overflowed. 12785 * 0b1..TPM counter has overflowed. 12786 */ 12787 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) 12788 #define TPM_SC_DMA_MASK (0x100U) 12789 #define TPM_SC_DMA_SHIFT (8U) 12790 /*! DMA - DMA Enable 12791 * 0b0..Disables DMA transfers. 12792 * 0b1..Enables DMA transfers. 12793 */ 12794 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) 12795 /*! @} */ 12796 12797 /*! @name CNT - Counter */ 12798 /*! @{ */ 12799 #define TPM_CNT_COUNT_MASK (0xFFFFU) 12800 #define TPM_CNT_COUNT_SHIFT (0U) 12801 /*! COUNT - Counter value 12802 */ 12803 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) 12804 /*! @} */ 12805 12806 /*! @name MOD - Modulo */ 12807 /*! @{ */ 12808 #define TPM_MOD_MOD_MASK (0xFFFFU) 12809 #define TPM_MOD_MOD_SHIFT (0U) 12810 /*! MOD - Modulo value 12811 */ 12812 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) 12813 /*! @} */ 12814 12815 /*! @name CnSC - Channel (n) Status and Control */ 12816 /*! @{ */ 12817 #define TPM_CnSC_DMA_MASK (0x1U) 12818 #define TPM_CnSC_DMA_SHIFT (0U) 12819 /*! DMA - DMA Enable 12820 * 0b0..Disable DMA transfers. 12821 * 0b1..Enable DMA transfers. 12822 */ 12823 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) 12824 #define TPM_CnSC_ELSA_MASK (0x4U) 12825 #define TPM_CnSC_ELSA_SHIFT (2U) 12826 /*! ELSA - Edge or Level Select 12827 */ 12828 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) 12829 #define TPM_CnSC_ELSB_MASK (0x8U) 12830 #define TPM_CnSC_ELSB_SHIFT (3U) 12831 /*! ELSB - Edge or Level Select 12832 */ 12833 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) 12834 #define TPM_CnSC_MSA_MASK (0x10U) 12835 #define TPM_CnSC_MSA_SHIFT (4U) 12836 /*! MSA - Channel Mode Select 12837 */ 12838 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) 12839 #define TPM_CnSC_MSB_MASK (0x20U) 12840 #define TPM_CnSC_MSB_SHIFT (5U) 12841 /*! MSB - Channel Mode Select 12842 */ 12843 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) 12844 #define TPM_CnSC_CHIE_MASK (0x40U) 12845 #define TPM_CnSC_CHIE_SHIFT (6U) 12846 /*! CHIE - Channel Interrupt Enable 12847 * 0b0..Disable channel interrupts. 12848 * 0b1..Enable channel interrupts. 12849 */ 12850 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) 12851 #define TPM_CnSC_CHF_MASK (0x80U) 12852 #define TPM_CnSC_CHF_SHIFT (7U) 12853 /*! CHF - Channel Flag 12854 * 0b0..No channel event has occurred. 12855 * 0b1..A channel event has occurred. 12856 */ 12857 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) 12858 /*! @} */ 12859 12860 /* The count of TPM_CnSC */ 12861 #define TPM_CnSC_COUNT (6U) 12862 12863 /*! @name CnV - Channel (n) Value */ 12864 /*! @{ */ 12865 #define TPM_CnV_VAL_MASK (0xFFFFU) 12866 #define TPM_CnV_VAL_SHIFT (0U) 12867 /*! VAL - Channel Value 12868 */ 12869 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) 12870 /*! @} */ 12871 12872 /* The count of TPM_CnV */ 12873 #define TPM_CnV_COUNT (6U) 12874 12875 /*! @name STATUS - Capture and Compare Status */ 12876 /*! @{ */ 12877 #define TPM_STATUS_CH0F_MASK (0x1U) 12878 #define TPM_STATUS_CH0F_SHIFT (0U) 12879 /*! CH0F - Channel 0 Flag 12880 * 0b0..No channel event has occurred. 12881 * 0b1..A channel event has occurred. 12882 */ 12883 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) 12884 #define TPM_STATUS_CH1F_MASK (0x2U) 12885 #define TPM_STATUS_CH1F_SHIFT (1U) 12886 /*! CH1F - Channel 1 Flag 12887 * 0b0..No channel event has occurred. 12888 * 0b1..A channel event has occurred. 12889 */ 12890 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) 12891 #define TPM_STATUS_CH2F_MASK (0x4U) 12892 #define TPM_STATUS_CH2F_SHIFT (2U) 12893 /*! CH2F - Channel 2 Flag 12894 * 0b0..No channel event has occurred. 12895 * 0b1..A channel event has occurred. 12896 */ 12897 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) 12898 #define TPM_STATUS_CH3F_MASK (0x8U) 12899 #define TPM_STATUS_CH3F_SHIFT (3U) 12900 /*! CH3F - Channel 3 Flag 12901 * 0b0..No channel event has occurred. 12902 * 0b1..A channel event has occurred. 12903 */ 12904 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) 12905 #define TPM_STATUS_CH4F_MASK (0x10U) 12906 #define TPM_STATUS_CH4F_SHIFT (4U) 12907 /*! CH4F - Channel 4 Flag 12908 * 0b0..No channel event has occurred. 12909 * 0b1..A channel event has occurred. 12910 */ 12911 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) 12912 #define TPM_STATUS_CH5F_MASK (0x20U) 12913 #define TPM_STATUS_CH5F_SHIFT (5U) 12914 /*! CH5F - Channel 5 Flag 12915 * 0b0..No channel event has occurred. 12916 * 0b1..A channel event has occurred. 12917 */ 12918 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) 12919 #define TPM_STATUS_TOF_MASK (0x100U) 12920 #define TPM_STATUS_TOF_SHIFT (8U) 12921 /*! TOF - Timer Overflow Flag 12922 * 0b0..TPM counter has not overflowed. 12923 * 0b1..TPM counter has overflowed. 12924 */ 12925 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) 12926 /*! @} */ 12927 12928 /*! @name POL - Channel Polarity */ 12929 /*! @{ */ 12930 #define TPM_POL_POL0_MASK (0x1U) 12931 #define TPM_POL_POL0_SHIFT (0U) 12932 /*! POL0 - Channel 0 Polarity 12933 * 0b0..The channel polarity is active high. 12934 * 0b1..The channel polarity is active low. 12935 */ 12936 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) 12937 #define TPM_POL_POL1_MASK (0x2U) 12938 #define TPM_POL_POL1_SHIFT (1U) 12939 /*! POL1 - Channel 1 Polarity 12940 * 0b0..The channel polarity is active high. 12941 * 0b1..The channel polarity is active low. 12942 */ 12943 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) 12944 #define TPM_POL_POL2_MASK (0x4U) 12945 #define TPM_POL_POL2_SHIFT (2U) 12946 /*! POL2 - Channel 2 Polarity 12947 * 0b0..The channel polarity is active high. 12948 * 0b1..The channel polarity is active low. 12949 */ 12950 #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) 12951 #define TPM_POL_POL3_MASK (0x8U) 12952 #define TPM_POL_POL3_SHIFT (3U) 12953 /*! POL3 - Channel 3 Polarity 12954 * 0b0..The channel polarity is active high. 12955 * 0b1..The channel polarity is active low. 12956 */ 12957 #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) 12958 #define TPM_POL_POL4_MASK (0x10U) 12959 #define TPM_POL_POL4_SHIFT (4U) 12960 /*! POL4 - Channel 4 Polarity 12961 * 0b0..The channel polarity is active high 12962 * 0b1..The channel polarity is active low. 12963 */ 12964 #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) 12965 #define TPM_POL_POL5_MASK (0x20U) 12966 #define TPM_POL_POL5_SHIFT (5U) 12967 /*! POL5 - Channel 5 Polarity 12968 * 0b0..The channel polarity is active high. 12969 * 0b1..The channel polarity is active low. 12970 */ 12971 #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) 12972 /*! @} */ 12973 12974 /*! @name CONF - Configuration */ 12975 /*! @{ */ 12976 #define TPM_CONF_DOZEEN_MASK (0x20U) 12977 #define TPM_CONF_DOZEEN_SHIFT (5U) 12978 /*! DOZEEN - Doze Enable 12979 * 0b0..Internal TPM counter continues in Doze mode. 12980 * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events 12981 * are also ignored. 12982 */ 12983 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) 12984 #define TPM_CONF_DBGMODE_MASK (0xC0U) 12985 #define TPM_CONF_DBGMODE_SHIFT (6U) 12986 /*! DBGMODE - Debug Mode 12987 * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are 12988 * also ignored. 0b11..TPM counter continues in debug mode. 12989 */ 12990 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) 12991 #define TPM_CONF_GTBSYNC_MASK (0x100U) 12992 #define TPM_CONF_GTBSYNC_SHIFT (8U) 12993 /*! GTBSYNC - Global Time Base Synchronization 12994 * 0b0..Global timebase synchronization disabled. 12995 * 0b1..Global timebase synchronization enabled. 12996 */ 12997 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) 12998 #define TPM_CONF_GTBEEN_MASK (0x200U) 12999 #define TPM_CONF_GTBEEN_SHIFT (9U) 13000 /*! GTBEEN - Global time base enable 13001 * 0b0..All channels use the internally generated TPM counter as their timebase 13002 * 0b1..All channels use an externally generated global timebase as their timebase 13003 */ 13004 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) 13005 #define TPM_CONF_CSOT_MASK (0x10000U) 13006 #define TPM_CONF_CSOT_SHIFT (16U) 13007 /*! CSOT - Counter Start on Trigger 13008 * 0b0..TPM counter starts to increment immediately, once it is enabled. 13009 * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, 13010 * after it has been enabled or after it has stopped due to overflow. 13011 */ 13012 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) 13013 #define TPM_CONF_CSOO_MASK (0x20000U) 13014 #define TPM_CONF_CSOO_SHIFT (17U) 13015 /*! CSOO - Counter Stop On Overflow 13016 * 0b0..TPM counter continues incrementing or decrementing after overflow 13017 * 0b1..TPM counter stops incrementing or decrementing after overflow. 13018 */ 13019 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) 13020 #define TPM_CONF_CROT_MASK (0x40000U) 13021 #define TPM_CONF_CROT_SHIFT (18U) 13022 /*! CROT - Counter Reload On Trigger 13023 * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger 13024 * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger 13025 */ 13026 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) 13027 #define TPM_CONF_CPOT_MASK (0x80000U) 13028 #define TPM_CONF_CPOT_SHIFT (19U) 13029 /*! CPOT - Counter Pause On Trigger 13030 */ 13031 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) 13032 #define TPM_CONF_TRGPOL_MASK (0x400000U) 13033 #define TPM_CONF_TRGPOL_SHIFT (22U) 13034 /*! TRGPOL - Trigger Polarity 13035 * 0b0..Trigger is active high. 13036 * 0b1..Trigger is active low. 13037 */ 13038 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) 13039 #define TPM_CONF_TRGSRC_MASK (0x800000U) 13040 #define TPM_CONF_TRGSRC_SHIFT (23U) 13041 /*! TRGSRC - Trigger Source 13042 * 0b0..Trigger source selected by TRGSEL is external. 13043 * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture). 13044 */ 13045 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) 13046 #define TPM_CONF_TRGSEL_MASK (0xF000000U) 13047 #define TPM_CONF_TRGSEL_SHIFT (24U) 13048 /*! TRGSEL - Trigger Select 13049 * 0b0001..Channel 0 pin input capture 13050 * 0b0010..Channel 1 pin input capture 13051 * 0b0011..Channel 0 or Channel 1 pin input capture 13052 * 0b0100..Channel 2 pin input capture 13053 * 0b0101..Channel 0 or Channel 2 pin input capture 13054 * 0b0110..Channel 1 or Channel 2 pin input capture 13055 * 0b0111..Channel 0 or Channel 1 or Channel 2 pin input capture 13056 * 0b1000..Channel 3 pin input capture 13057 * 0b1001..Channel 0 or Channel 3 pin input capture 13058 * 0b1010..Channel 1 or Channel 3 pin input capture 13059 * 0b1011..Channel 0 or Channel 1 or Channel 3 pin input capture 13060 * 0b1100..Channel 2 or Channel 3 pin input capture 13061 * 0b1101..Channel 0 or Channel 2 or Channel 3 pin input capture 13062 * 0b1110..Channel 1 or Channel 2 or Channel 3 pin input capture 13063 * 0b1111..Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture 13064 */ 13065 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) 13066 /*! @} */ 13067 13068 /*! 13069 * @} 13070 */ /* end of group TPM_Register_Masks */ 13071 13072 /* TPM - Peripheral instance base addresses */ 13073 /** Peripheral TPM0 base address */ 13074 #define TPM0_BASE (0x40038000u) 13075 /** Peripheral TPM0 base pointer */ 13076 #define TPM0 ((TPM_Type *)TPM0_BASE) 13077 /** Peripheral TPM1 base address */ 13078 #define TPM1_BASE (0x40039000u) 13079 /** Peripheral TPM1 base pointer */ 13080 #define TPM1 ((TPM_Type *)TPM1_BASE) 13081 /** Peripheral TPM2 base address */ 13082 #define TPM2_BASE (0x4003A000u) 13083 /** Peripheral TPM2 base pointer */ 13084 #define TPM2 ((TPM_Type *)TPM2_BASE) 13085 /** Array initializer of TPM peripheral base addresses */ 13086 #define TPM_BASE_ADDRS \ 13087 { \ 13088 TPM0_BASE, TPM1_BASE, TPM2_BASE \ 13089 } 13090 /** Array initializer of TPM peripheral base pointers */ 13091 #define TPM_BASE_PTRS \ 13092 { \ 13093 TPM0, TPM1, TPM2 \ 13094 } 13095 /** Interrupt vectors for the TPM peripheral type */ 13096 #define TPM_IRQS \ 13097 { \ 13098 TPM0_IRQn, TPM1_IRQn, TPM2_IRQn \ 13099 } 13100 13101 /*! 13102 * @} 13103 */ /* end of group TPM_Peripheral_Access_Layer */ 13104 13105 /* ---------------------------------------------------------------------------- 13106 -- UART Peripheral Access Layer 13107 ---------------------------------------------------------------------------- */ 13108 13109 /*! 13110 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 13111 * @{ 13112 */ 13113 13114 /** UART - Register Layout Typedef */ 13115 typedef struct 13116 { 13117 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ 13118 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ 13119 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 13120 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 13121 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 13122 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 13123 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 13124 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 13125 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 13126 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 13127 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 13128 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 13129 uint8_t RESERVED_0[12]; 13130 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ 13131 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ 13132 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ 13133 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 13134 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ 13135 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ 13136 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ 13137 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ 13138 uint8_t RESERVED_1[26]; 13139 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */ 13140 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */ 13141 union 13142 { /* offset: 0x3C */ 13143 struct 13144 { /* offset: 0x3C */ 13145 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ 13146 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ 13147 } TYPE0; 13148 struct 13149 { /* offset: 0x3C */ 13150 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ 13151 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ 13152 } TYPE1; 13153 }; 13154 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */ 13155 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */ 13156 } UART_Type; 13157 13158 /* ---------------------------------------------------------------------------- 13159 -- UART Register Masks 13160 ---------------------------------------------------------------------------- */ 13161 13162 /*! 13163 * @addtogroup UART_Register_Masks UART Register Masks 13164 * @{ 13165 */ 13166 13167 /*! @name BDH - UART Baud Rate Registers: High */ 13168 /*! @{ */ 13169 #define UART_BDH_SBR_MASK (0x1FU) 13170 #define UART_BDH_SBR_SHIFT (0U) 13171 /*! SBR - UART Baud Rate Bits 13172 */ 13173 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 13174 #define UART_BDH_RXEDGIE_MASK (0x40U) 13175 #define UART_BDH_RXEDGIE_SHIFT (6U) 13176 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable 13177 * 0b0..Hardware interrupts from RXEDGIF disabled using polling. 13178 * 0b1..RXEDGIF interrupt request enabled. 13179 */ 13180 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 13181 /*! @} */ 13182 13183 /*! @name BDL - UART Baud Rate Registers: Low */ 13184 /*! @{ */ 13185 #define UART_BDL_SBR_MASK (0xFFU) 13186 #define UART_BDL_SBR_SHIFT (0U) 13187 /*! SBR - UART Baud Rate Bits 13188 */ 13189 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 13190 /*! @} */ 13191 13192 /*! @name C1 - UART Control Register 1 */ 13193 /*! @{ */ 13194 #define UART_C1_PT_MASK (0x1U) 13195 #define UART_C1_PT_SHIFT (0U) 13196 /*! PT - Parity Type 13197 * 0b0..Even parity. 13198 * 0b1..Odd parity. 13199 */ 13200 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 13201 #define UART_C1_PE_MASK (0x2U) 13202 #define UART_C1_PE_SHIFT (1U) 13203 /*! PE - Parity Enable 13204 * 0b0..Parity function disabled. 13205 * 0b1..Parity function enabled. 13206 */ 13207 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 13208 #define UART_C1_ILT_MASK (0x4U) 13209 #define UART_C1_ILT_SHIFT (2U) 13210 /*! ILT - Idle Line Type Select 13211 * 0b0..Idle character bit count starts after start bit. 13212 * 0b1..Idle character bit count starts after stop bit. 13213 */ 13214 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 13215 #define UART_C1_WAKE_MASK (0x8U) 13216 #define UART_C1_WAKE_SHIFT (3U) 13217 /*! WAKE - Receiver Wakeup Method Select 13218 * 0b0..Idle line wakeup. 13219 * 0b1..Address mark wakeup. 13220 */ 13221 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 13222 #define UART_C1_M_MASK (0x10U) 13223 #define UART_C1_M_SHIFT (4U) 13224 /*! M - 9-bit or 8-bit Mode Select 13225 * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. 13226 * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. 13227 */ 13228 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 13229 #define UART_C1_RSRC_MASK (0x20U) 13230 #define UART_C1_RSRC_SHIFT (5U) 13231 /*! RSRC - Receiver Source Select 13232 * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output. 13233 * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal. 13234 */ 13235 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 13236 #define UART_C1_LOOPS_MASK (0x80U) 13237 #define UART_C1_LOOPS_SHIFT (7U) 13238 /*! LOOPS - Loop Mode Select 13239 * 0b0..Normal operation. 13240 * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined 13241 * by RSRC. 13242 */ 13243 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 13244 /*! @} */ 13245 13246 /*! @name C2 - UART Control Register 2 */ 13247 /*! @{ */ 13248 #define UART_C2_SBK_MASK (0x1U) 13249 #define UART_C2_SBK_SHIFT (0U) 13250 /*! SBK - Send Break 13251 * 0b0..Normal transmitter operation. 13252 * 0b1..Queue break characters to be sent. 13253 */ 13254 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 13255 #define UART_C2_RWU_MASK (0x2U) 13256 #define UART_C2_RWU_SHIFT (1U) 13257 /*! RWU - Receiver Wakeup Control 13258 * 0b0..Normal operation. 13259 * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware 13260 * wakes the receiver by automatically clearing RWU. 13261 */ 13262 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 13263 #define UART_C2_RE_MASK (0x4U) 13264 #define UART_C2_RE_SHIFT (2U) 13265 /*! RE - Receiver Enable 13266 * 0b0..Receiver off. 13267 * 0b1..Receiver on. 13268 */ 13269 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 13270 #define UART_C2_TE_MASK (0x8U) 13271 #define UART_C2_TE_SHIFT (3U) 13272 /*! TE - Transmitter Enable 13273 * 0b0..Transmitter off. 13274 * 0b1..Transmitter on. 13275 */ 13276 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 13277 #define UART_C2_ILIE_MASK (0x10U) 13278 #define UART_C2_ILIE_SHIFT (4U) 13279 /*! ILIE - Idle Line Interrupt Enable 13280 * 0b0..IDLE interrupt requests disabled. 13281 * 0b1..IDLE interrupt requests enabled. 13282 */ 13283 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 13284 #define UART_C2_RIE_MASK (0x20U) 13285 #define UART_C2_RIE_SHIFT (5U) 13286 /*! RIE - Receiver Full Interrupt or DMA Transfer Enable 13287 * 0b0..RDRF interrupt and DMA transfer requests disabled. 13288 * 0b1..RDRF interrupt or DMA transfer requests enabled. 13289 */ 13290 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 13291 #define UART_C2_TCIE_MASK (0x40U) 13292 #define UART_C2_TCIE_SHIFT (6U) 13293 /*! TCIE - Transmission Complete Interrupt Enable 13294 * 0b0..TC interrupt requests disabled. 13295 * 0b1..TC interrupt requests enabled. 13296 */ 13297 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 13298 #define UART_C2_TIE_MASK (0x80U) 13299 #define UART_C2_TIE_SHIFT (7U) 13300 /*! TIE - Transmitter Interrupt or DMA Transfer Enable. 13301 * 0b0..TDRE interrupt and DMA transfer requests disabled. 13302 * 0b1..TDRE interrupt or DMA transfer requests enabled. 13303 */ 13304 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 13305 /*! @} */ 13306 13307 /*! @name S1 - UART Status Register 1 */ 13308 /*! @{ */ 13309 #define UART_S1_PF_MASK (0x1U) 13310 #define UART_S1_PF_SHIFT (0U) 13311 /*! PF - Parity Error Flag 13312 * 0b0..No parity error detected. 13313 * 0b1..Parity error. 13314 */ 13315 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 13316 #define UART_S1_FE_MASK (0x2U) 13317 #define UART_S1_FE_SHIFT (1U) 13318 /*! FE - Framing Error Flag 13319 * 0b0..No framing error detected. 13320 * 0b1..Framing error. 13321 */ 13322 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 13323 #define UART_S1_NF_MASK (0x4U) 13324 #define UART_S1_NF_SHIFT (2U) 13325 /*! NF - Noise Flag 13326 * 0b0..No noise detected. 13327 * 0b1..Noise detected in the received character in D. 13328 */ 13329 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 13330 #define UART_S1_OR_MASK (0x8U) 13331 #define UART_S1_OR_SHIFT (3U) 13332 /*! OR - Receiver Overrun Flag 13333 * 0b0..No overrun has occurred since the last time the flag was cleared. 13334 * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. 13335 */ 13336 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 13337 #define UART_S1_IDLE_MASK (0x10U) 13338 #define UART_S1_IDLE_SHIFT (4U) 13339 /*! IDLE - Idle Line Flag 13340 * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared. 13341 * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted. 13342 */ 13343 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 13344 #define UART_S1_RDRF_MASK (0x20U) 13345 #define UART_S1_RDRF_SHIFT (5U) 13346 /*! RDRF - Receive Data Register Full Flag 13347 * 0b0..Receive data buffer is empty. 13348 * 0b1..Receive data buffer is full. 13349 */ 13350 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 13351 #define UART_S1_TC_MASK (0x40U) 13352 #define UART_S1_TC_SHIFT (6U) 13353 /*! TC - Transmit Complete Flag 13354 * 0b0..Transmitter active (sending data, a preamble, or a break). 13355 * 0b1..Transmitter idle (transmission activity complete). 13356 */ 13357 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 13358 #define UART_S1_TDRE_MASK (0x80U) 13359 #define UART_S1_TDRE_SHIFT (7U) 13360 /*! TDRE - Transmit Data Register Empty Flag 13361 * 0b0..Transmit data buffer is full. 13362 * 0b1..Transmit data buffer is empty. 13363 */ 13364 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 13365 /*! @} */ 13366 13367 /*! @name S2 - UART Status Register 2 */ 13368 /*! @{ */ 13369 #define UART_S2_RAF_MASK (0x1U) 13370 #define UART_S2_RAF_SHIFT (0U) 13371 /*! RAF - Receiver Active Flag 13372 * 0b0..UART receiver idle/inactive waiting for a start bit. 13373 * 0b1..UART receiver active, RxD input not idle. 13374 */ 13375 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 13376 #define UART_S2_BRK13_MASK (0x4U) 13377 #define UART_S2_BRK13_SHIFT (2U) 13378 /*! BRK13 - Break Transmit Character Length 13379 * 0b0..Break character is 10, 11, or 12 bits long. 13380 * 0b1..Break character is 13 or 14 bits long. 13381 */ 13382 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 13383 #define UART_S2_RWUID_MASK (0x8U) 13384 #define UART_S2_RWUID_SHIFT (3U) 13385 /*! RWUID - Receive Wakeup Idle Detect 13386 * 0b0..S1[IDLE] is not set upon detection of an idle character. 13387 * 0b1..S1[IDLE] is set upon detection of an idle character. 13388 */ 13389 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 13390 #define UART_S2_RXINV_MASK (0x10U) 13391 #define UART_S2_RXINV_SHIFT (4U) 13392 /*! RXINV - Receive Data Inversion 13393 * 0b0..Receive data is not inverted. 13394 * 0b1..Receive data is inverted. 13395 */ 13396 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 13397 #define UART_S2_MSBF_MASK (0x20U) 13398 #define UART_S2_MSBF_SHIFT (5U) 13399 /*! MSBF - Most Significant Bit First 13400 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received 13401 * after the start bit is identified as bit0. 13402 * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the 13403 * setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, 13404 * bit7, or bit6, depending on the setting of C1[M] and C1[PE]. 13405 */ 13406 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) 13407 #define UART_S2_RXEDGIF_MASK (0x40U) 13408 #define UART_S2_RXEDGIF_SHIFT (6U) 13409 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 13410 * 0b0..No active edge on the receive pin has occurred. 13411 * 0b1..An active edge on the receive pin has occurred. 13412 */ 13413 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 13414 /*! @} */ 13415 13416 /*! @name C3 - UART Control Register 3 */ 13417 /*! @{ */ 13418 #define UART_C3_PEIE_MASK (0x1U) 13419 #define UART_C3_PEIE_SHIFT (0U) 13420 /*! PEIE - Parity Error Interrupt Enable 13421 * 0b0..PF interrupt requests are disabled. 13422 * 0b1..PF interrupt requests are enabled. 13423 */ 13424 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 13425 #define UART_C3_FEIE_MASK (0x2U) 13426 #define UART_C3_FEIE_SHIFT (1U) 13427 /*! FEIE - Framing Error Interrupt Enable 13428 * 0b0..FE interrupt requests are disabled. 13429 * 0b1..FE interrupt requests are enabled. 13430 */ 13431 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 13432 #define UART_C3_NEIE_MASK (0x4U) 13433 #define UART_C3_NEIE_SHIFT (2U) 13434 /*! NEIE - Noise Error Interrupt Enable 13435 * 0b0..NF interrupt requests are disabled. 13436 * 0b1..NF interrupt requests are enabled. 13437 */ 13438 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 13439 #define UART_C3_ORIE_MASK (0x8U) 13440 #define UART_C3_ORIE_SHIFT (3U) 13441 /*! ORIE - Overrun Error Interrupt Enable 13442 * 0b0..OR interrupts are disabled. 13443 * 0b1..OR interrupt requests are enabled. 13444 */ 13445 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 13446 #define UART_C3_TXINV_MASK (0x10U) 13447 #define UART_C3_TXINV_SHIFT (4U) 13448 /*! TXINV - Transmit Data Inversion. 13449 * 0b0..Transmit data is not inverted. 13450 * 0b1..Transmit data is inverted. 13451 */ 13452 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 13453 #define UART_C3_TXDIR_MASK (0x20U) 13454 #define UART_C3_TXDIR_SHIFT (5U) 13455 /*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode 13456 * 0b0..TXD pin is an input in single wire mode. 13457 * 0b1..TXD pin is an output in single wire mode. 13458 */ 13459 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 13460 #define UART_C3_T8_MASK (0x40U) 13461 #define UART_C3_T8_SHIFT (6U) 13462 /*! T8 - Transmit Bit 8 13463 */ 13464 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 13465 #define UART_C3_R8_MASK (0x80U) 13466 #define UART_C3_R8_SHIFT (7U) 13467 /*! R8 - Received Bit 8 13468 */ 13469 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 13470 /*! @} */ 13471 13472 /*! @name D - UART Data Register */ 13473 /*! @{ */ 13474 #define UART_D_RT_MASK (0xFFU) 13475 #define UART_D_RT_SHIFT (0U) 13476 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) 13477 /*! @} */ 13478 13479 /*! @name MA1 - UART Match Address Registers 1 */ 13480 /*! @{ */ 13481 #define UART_MA1_MA_MASK (0xFFU) 13482 #define UART_MA1_MA_SHIFT (0U) 13483 /*! MA - Match Address 13484 */ 13485 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) 13486 /*! @} */ 13487 13488 /*! @name MA2 - UART Match Address Registers 2 */ 13489 /*! @{ */ 13490 #define UART_MA2_MA_MASK (0xFFU) 13491 #define UART_MA2_MA_SHIFT (0U) 13492 /*! MA - Match Address 13493 */ 13494 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) 13495 /*! @} */ 13496 13497 /*! @name C4 - UART Control Register 4 */ 13498 /*! @{ */ 13499 #define UART_C4_BRFA_MASK (0x1FU) 13500 #define UART_C4_BRFA_SHIFT (0U) 13501 /*! BRFA - Baud Rate Fine Adjust 13502 */ 13503 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) 13504 #define UART_C4_M10_MASK (0x20U) 13505 #define UART_C4_M10_SHIFT (5U) 13506 /*! M10 - 10-bit Mode select 13507 * 0b0..The parity bit is the ninth bit in the serial transmission. 13508 * 0b1..The parity bit is the tenth bit in the serial transmission. 13509 */ 13510 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) 13511 #define UART_C4_MAEN2_MASK (0x40U) 13512 #define UART_C4_MAEN2_SHIFT (6U) 13513 /*! MAEN2 - Match Address Mode Enable 2 13514 * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared. 13515 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most 13516 * significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. 13517 * If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] 13518 * is set/enabled. 13519 */ 13520 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) 13521 #define UART_C4_MAEN1_MASK (0x80U) 13522 #define UART_C4_MAEN1_SHIFT (7U) 13523 /*! MAEN1 - Match Address Mode Enable 1 13524 * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared. 13525 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most 13526 * significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. 13527 * If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is 13528 * set/enabled. 13529 */ 13530 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) 13531 /*! @} */ 13532 13533 /*! @name C5 - UART Control Register 5 */ 13534 /*! @{ */ 13535 #define UART_C5_RDMAS_MASK (0x20U) 13536 #define UART_C5_RDMAS_SHIFT (5U) 13537 /*! RDMAS - Receiver Full DMA Select 13538 * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. 13539 * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. 13540 */ 13541 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) 13542 #define UART_C5_TDMAS_MASK (0x80U) 13543 #define UART_C5_TDMAS_SHIFT (7U) 13544 /*! TDMAS - Transmitter DMA Select 13545 * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request 13546 * interrupt service. 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to 13547 * request a DMA transfer. 13548 */ 13549 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) 13550 /*! @} */ 13551 13552 /*! @name C7816 - UART 7816 Control Register */ 13553 /*! @{ */ 13554 #define UART_C7816_ISO_7816E_MASK (0x1U) 13555 #define UART_C7816_ISO_7816E_SHIFT (0U) 13556 /*! ISO_7816E - ISO-7816 Functionality Enabled 13557 * 0b0..ISO-7816 functionality is turned off/not enabled. 13558 * 0b1..ISO-7816 functionality is turned on/enabled. 13559 */ 13560 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) 13561 #define UART_C7816_TTYPE_MASK (0x2U) 13562 #define UART_C7816_TTYPE_SHIFT (1U) 13563 /*! TTYPE - Transfer Type 13564 * 0b0..T = 0 per the ISO-7816 specification. 13565 * 0b1..T = 1 per the ISO-7816 specification. 13566 */ 13567 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) 13568 #define UART_C7816_INIT_MASK (0x4U) 13569 #define UART_C7816_INIT_SHIFT (2U) 13570 /*! INIT - Detect Initial Character 13571 * 0b0..Normal operating mode. Receiver does not seek to identify initial character. 13572 * 0b1..Receiver searches for initial character. 13573 */ 13574 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) 13575 #define UART_C7816_ANACK_MASK (0x8U) 13576 #define UART_C7816_ANACK_SHIFT (3U) 13577 /*! ANACK - Generate NACK on Error 13578 * 0b0..No NACK is automatically generated. 13579 * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. 13580 */ 13581 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) 13582 #define UART_C7816_ONACK_MASK (0x10U) 13583 #define UART_C7816_ONACK_SHIFT (4U) 13584 /*! ONACK - Generate NACK on Overflow 13585 * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event. 13586 * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character. 13587 */ 13588 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) 13589 /*! @} */ 13590 13591 /*! @name IE7816 - UART 7816 Interrupt Enable Register */ 13592 /*! @{ */ 13593 #define UART_IE7816_RXTE_MASK (0x1U) 13594 #define UART_IE7816_RXTE_SHIFT (0U) 13595 /*! RXTE - Receive Threshold Exceeded Interrupt Enable 13596 * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt. 13597 * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt. 13598 */ 13599 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) 13600 #define UART_IE7816_TXTE_MASK (0x2U) 13601 #define UART_IE7816_TXTE_SHIFT (1U) 13602 /*! TXTE - Transmit Threshold Exceeded Interrupt Enable 13603 * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt. 13604 * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt. 13605 */ 13606 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) 13607 #define UART_IE7816_GTVE_MASK (0x4U) 13608 #define UART_IE7816_GTVE_SHIFT (2U) 13609 /*! GTVE - Guard Timer Violated Interrupt Enable 13610 * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt. 13611 * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt. 13612 */ 13613 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) 13614 #define UART_IE7816_ADTE_MASK (0x8U) 13615 #define UART_IE7816_ADTE_SHIFT (3U) 13616 /*! ADTE - ATR Duration Timer Interrupt Enable 13617 * 0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt. 13618 * 0b1..The assertion of IS7816[ADT] results in the generation of an interrupt. 13619 */ 13620 #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK) 13621 #define UART_IE7816_INITDE_MASK (0x10U) 13622 #define UART_IE7816_INITDE_SHIFT (4U) 13623 /*! INITDE - Initial Character Detected Interrupt Enable 13624 * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt. 13625 * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt. 13626 */ 13627 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) 13628 #define UART_IE7816_BWTE_MASK (0x20U) 13629 #define UART_IE7816_BWTE_SHIFT (5U) 13630 /*! BWTE - Block Wait Timer Interrupt Enable 13631 * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt. 13632 * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt. 13633 */ 13634 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) 13635 #define UART_IE7816_CWTE_MASK (0x40U) 13636 #define UART_IE7816_CWTE_SHIFT (6U) 13637 /*! CWTE - Character Wait Timer Interrupt Enable 13638 * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt. 13639 * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt. 13640 */ 13641 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) 13642 #define UART_IE7816_WTE_MASK (0x80U) 13643 #define UART_IE7816_WTE_SHIFT (7U) 13644 /*! WTE - Wait Timer Interrupt Enable 13645 * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt. 13646 * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt. 13647 */ 13648 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) 13649 /*! @} */ 13650 13651 /*! @name IS7816 - UART 7816 Interrupt Status Register */ 13652 /*! @{ */ 13653 #define UART_IS7816_RXT_MASK (0x1U) 13654 #define UART_IS7816_RXT_SHIFT (0U) 13655 /*! RXT - Receive Threshold Exceeded Interrupt 13656 * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than 13657 * or equal to the value in ET7816[RXTHRESHOLD]. 13658 * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the 13659 * value in ET7816[RXTHRESHOLD]. 13660 */ 13661 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) 13662 #define UART_IS7816_TXT_MASK (0x2U) 13663 #define UART_IS7816_TXT_SHIFT (1U) 13664 /*! TXT - Transmit Threshold Exceeded Interrupt 13665 * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. 13666 * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. 13667 */ 13668 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) 13669 #define UART_IS7816_GTV_MASK (0x4U) 13670 #define UART_IS7816_GTV_SHIFT (2U) 13671 /*! GTV - Guard Timer Violated Interrupt 13672 * 0b0..A guard time (GT, CGT, or BGT) has not been violated. 13673 * 0b1..A guard time (GT, CGT, or BGT) has been violated. 13674 */ 13675 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) 13676 #define UART_IS7816_ADT_MASK (0x8U) 13677 #define UART_IS7816_ADT_SHIFT (3U) 13678 /*! ADT - ATR Duration Time Interrupt 13679 * 0b0..ATR Duration time (ADT) has not been violated. 13680 * 0b1..ATR Duration time (ADT) has been violated. 13681 */ 13682 #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK) 13683 #define UART_IS7816_INITD_MASK (0x10U) 13684 #define UART_IS7816_INITD_SHIFT (4U) 13685 /*! INITD - Initial Character Detected Interrupt 13686 * 0b0..A valid initial character has not been received. 13687 * 0b1..A valid initial character has been received. 13688 */ 13689 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) 13690 #define UART_IS7816_BWT_MASK (0x20U) 13691 #define UART_IS7816_BWT_SHIFT (5U) 13692 /*! BWT - Block Wait Timer Interrupt 13693 * 0b0..Block wait time (BWT) has not been violated. 13694 * 0b1..Block wait time (BWT) has been violated. 13695 */ 13696 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) 13697 #define UART_IS7816_CWT_MASK (0x40U) 13698 #define UART_IS7816_CWT_SHIFT (6U) 13699 /*! CWT - Character Wait Timer Interrupt 13700 * 0b0..Character wait time (CWT) has not been violated. 13701 * 0b1..Character wait time (CWT) has been violated. 13702 */ 13703 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) 13704 #define UART_IS7816_WT_MASK (0x80U) 13705 #define UART_IS7816_WT_SHIFT (7U) 13706 /*! WT - Wait Timer Interrupt 13707 * 0b0..Wait time (WT) has not been violated. 13708 * 0b1..Wait time (WT) has been violated. 13709 */ 13710 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) 13711 /*! @} */ 13712 13713 /*! @name WP7816 - UART 7816 Wait Parameter Register */ 13714 /*! @{ */ 13715 #define UART_WP7816_WTX_MASK (0xFFU) 13716 #define UART_WP7816_WTX_SHIFT (0U) 13717 /*! WTX - Wait Time Multiplier (C7816[TTYPE] = 1) 13718 */ 13719 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK) 13720 /*! @} */ 13721 13722 /*! @name WN7816 - UART 7816 Wait N Register */ 13723 /*! @{ */ 13724 #define UART_WN7816_GTN_MASK (0xFFU) 13725 #define UART_WN7816_GTN_SHIFT (0U) 13726 /*! GTN - Guard Band N 13727 */ 13728 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) 13729 /*! @} */ 13730 13731 /*! @name WF7816 - UART 7816 Wait FD Register */ 13732 /*! @{ */ 13733 #define UART_WF7816_GTFD_MASK (0xFFU) 13734 #define UART_WF7816_GTFD_SHIFT (0U) 13735 /*! GTFD - FD Multiplier 13736 */ 13737 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) 13738 /*! @} */ 13739 13740 /*! @name ET7816 - UART 7816 Error Threshold Register */ 13741 /*! @{ */ 13742 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) 13743 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) 13744 /*! RXTHRESHOLD - Receive NACK Threshold 13745 */ 13746 #define UART_ET7816_RXTHRESHOLD(x) \ 13747 (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) 13748 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) 13749 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) 13750 /*! TXTHRESHOLD - Transmit NACK Threshold 13751 * 0b0000..TXT asserts on the first NACK that is received. 13752 * 0b0001..TXT asserts on the second NACK that is received. 13753 */ 13754 #define UART_ET7816_TXTHRESHOLD(x) \ 13755 (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) 13756 /*! @} */ 13757 13758 /*! @name TL7816 - UART 7816 Transmit Length Register */ 13759 /*! @{ */ 13760 #define UART_TL7816_TLEN_MASK (0xFFU) 13761 #define UART_TL7816_TLEN_SHIFT (0U) 13762 /*! TLEN - Transmit Length 13763 */ 13764 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) 13765 /*! @} */ 13766 13767 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */ 13768 /*! @{ */ 13769 #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU) 13770 #define UART_AP7816A_T0_ADTI_H_SHIFT (0U) 13771 /*! ADTI_H - ATR Duration Time Integer High (C7816[TTYPE] = 0) 13772 */ 13773 #define UART_AP7816A_T0_ADTI_H(x) \ 13774 (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK) 13775 /*! @} */ 13776 13777 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */ 13778 /*! @{ */ 13779 #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU) 13780 #define UART_AP7816B_T0_ADTI_L_SHIFT (0U) 13781 /*! ADTI_L - ATR Duration Time Integer Low (C7816[TTYPE] = 0) 13782 */ 13783 #define UART_AP7816B_T0_ADTI_L(x) \ 13784 (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK) 13785 /*! @} */ 13786 13787 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */ 13788 /*! @{ */ 13789 #define UART_WP7816A_T0_WI_H_MASK (0xFFU) 13790 #define UART_WP7816A_T0_WI_H_SHIFT (0U) 13791 /*! WI_H - Wait Time Integer High (C7816[TTYPE] = 0) 13792 */ 13793 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK) 13794 /*! @} */ 13795 13796 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */ 13797 /*! @{ */ 13798 #define UART_WP7816B_T0_WI_L_MASK (0xFFU) 13799 #define UART_WP7816B_T0_WI_L_SHIFT (0U) 13800 /*! WI_L - Wait Time Integer Low (C7816[TTYPE] = 0) 13801 */ 13802 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK) 13803 /*! @} */ 13804 13805 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */ 13806 /*! @{ */ 13807 #define UART_WP7816A_T1_BWI_H_MASK (0xFFU) 13808 #define UART_WP7816A_T1_BWI_H_SHIFT (0U) 13809 /*! BWI_H - Block Wait Time Integer High (C7816[TTYPE] = 1) 13810 */ 13811 #define UART_WP7816A_T1_BWI_H(x) \ 13812 (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK) 13813 /*! @} */ 13814 13815 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */ 13816 /*! @{ */ 13817 #define UART_WP7816B_T1_BWI_L_MASK (0xFFU) 13818 #define UART_WP7816B_T1_BWI_L_SHIFT (0U) 13819 /*! BWI_L - Block Wait Time Integer Low (C7816[TTYPE] = 1) 13820 */ 13821 #define UART_WP7816B_T1_BWI_L(x) \ 13822 (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK) 13823 /*! @} */ 13824 13825 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */ 13826 /*! @{ */ 13827 #define UART_WGP7816_T1_BGI_MASK (0xFU) 13828 #define UART_WGP7816_T1_BGI_SHIFT (0U) 13829 /*! BGI - Block Guard Time Integer (C7816[TTYPE] = 1) 13830 */ 13831 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK) 13832 #define UART_WGP7816_T1_CWI1_MASK (0xF0U) 13833 #define UART_WGP7816_T1_CWI1_SHIFT (4U) 13834 /*! CWI1 - Character Wait Time Integer 1 (C7816[TTYPE] = 1) 13835 */ 13836 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK) 13837 /*! @} */ 13838 13839 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */ 13840 /*! @{ */ 13841 #define UART_WP7816C_T1_CWI2_MASK (0x1FU) 13842 #define UART_WP7816C_T1_CWI2_SHIFT (0U) 13843 /*! CWI2 - Character Wait Time Integer 2 (C7816[TTYPE] = 1) 13844 */ 13845 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK) 13846 /*! @} */ 13847 13848 /*! 13849 * @} 13850 */ /* end of group UART_Register_Masks */ 13851 13852 /* UART - Peripheral instance base addresses */ 13853 /** Peripheral UART2 base address */ 13854 #define UART2_BASE (0x4006C000u) 13855 /** Peripheral UART2 base pointer */ 13856 #define UART2 ((UART_Type *)UART2_BASE) 13857 /** Array initializer of UART peripheral base addresses */ 13858 #define UART_BASE_ADDRS \ 13859 { \ 13860 0u, 0u, UART2_BASE \ 13861 } 13862 /** Array initializer of UART peripheral base pointers */ 13863 #define UART_BASE_PTRS \ 13864 { \ 13865 (UART_Type *)0u, (UART_Type *)0u, UART2 \ 13866 } 13867 /** Interrupt vectors for the UART peripheral type */ 13868 #define UART_RX_TX_IRQS \ 13869 { \ 13870 NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn \ 13871 } 13872 #define UART_ERR_IRQS \ 13873 { \ 13874 NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn \ 13875 } 13876 13877 /*! 13878 * @} 13879 */ /* end of group UART_Peripheral_Access_Layer */ 13880 13881 /* ---------------------------------------------------------------------------- 13882 -- USB Peripheral Access Layer 13883 ---------------------------------------------------------------------------- */ 13884 13885 /*! 13886 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 13887 * @{ 13888 */ 13889 13890 /** USB - Register Layout Typedef */ 13891 typedef struct 13892 { 13893 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 13894 uint8_t RESERVED_0[3]; 13895 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 13896 uint8_t RESERVED_1[3]; 13897 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 13898 uint8_t RESERVED_2[3]; 13899 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 13900 uint8_t RESERVED_3[115]; 13901 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 13902 uint8_t RESERVED_4[3]; 13903 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 13904 uint8_t RESERVED_5[3]; 13905 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 13906 uint8_t RESERVED_6[3]; 13907 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 13908 uint8_t RESERVED_7[3]; 13909 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 13910 uint8_t RESERVED_8[3]; 13911 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 13912 uint8_t RESERVED_9[3]; 13913 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 13914 uint8_t RESERVED_10[3]; 13915 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ 13916 uint8_t RESERVED_11[3]; 13917 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ 13918 uint8_t RESERVED_12[3]; 13919 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ 13920 uint8_t RESERVED_13[11]; 13921 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 13922 uint8_t RESERVED_14[3]; 13923 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 13924 uint8_t RESERVED_15[11]; 13925 struct 13926 { /* offset: 0xC0, array step: 0x4 */ 13927 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 13928 uint8_t RESERVED_0[3]; 13929 } ENDPOINT[16]; 13930 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 13931 uint8_t RESERVED_16[3]; 13932 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 13933 uint8_t RESERVED_17[3]; 13934 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 13935 uint8_t RESERVED_18[3]; 13936 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ 13937 uint8_t RESERVED_19[7]; 13938 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 13939 uint8_t RESERVED_20[43]; 13940 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ 13941 uint8_t RESERVED_21[3]; 13942 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ 13943 uint8_t RESERVED_22[15]; 13944 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ 13945 uint8_t RESERVED_23[7]; 13946 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ 13947 } USB_Type; 13948 13949 /* ---------------------------------------------------------------------------- 13950 -- USB Register Masks 13951 ---------------------------------------------------------------------------- */ 13952 13953 /*! 13954 * @addtogroup USB_Register_Masks USB Register Masks 13955 * @{ 13956 */ 13957 13958 /*! @name PERID - Peripheral ID register */ 13959 /*! @{ */ 13960 #define USB_PERID_ID_MASK (0x3FU) 13961 #define USB_PERID_ID_SHIFT (0U) 13962 /*! ID - Peripheral Identification 13963 */ 13964 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) 13965 /*! @} */ 13966 13967 /*! @name IDCOMP - Peripheral ID Complement register */ 13968 /*! @{ */ 13969 #define USB_IDCOMP_NID_MASK (0x3FU) 13970 #define USB_IDCOMP_NID_SHIFT (0U) 13971 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) 13972 /*! @} */ 13973 13974 /*! @name REV - Peripheral Revision register */ 13975 /*! @{ */ 13976 #define USB_REV_REV_MASK (0xFFU) 13977 #define USB_REV_REV_SHIFT (0U) 13978 /*! REV - Revision 13979 */ 13980 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) 13981 /*! @} */ 13982 13983 /*! @name ADDINFO - Peripheral Additional Info register */ 13984 /*! @{ */ 13985 #define USB_ADDINFO_IEHOST_MASK (0x1U) 13986 #define USB_ADDINFO_IEHOST_SHIFT (0U) 13987 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) 13988 /*! @} */ 13989 13990 /*! @name ISTAT - Interrupt Status register */ 13991 /*! @{ */ 13992 #define USB_ISTAT_USBRST_MASK (0x1U) 13993 #define USB_ISTAT_USBRST_SHIFT (0U) 13994 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) 13995 #define USB_ISTAT_ERROR_MASK (0x2U) 13996 #define USB_ISTAT_ERROR_SHIFT (1U) 13997 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) 13998 #define USB_ISTAT_SOFTOK_MASK (0x4U) 13999 #define USB_ISTAT_SOFTOK_SHIFT (2U) 14000 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) 14001 #define USB_ISTAT_TOKDNE_MASK (0x8U) 14002 #define USB_ISTAT_TOKDNE_SHIFT (3U) 14003 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) 14004 #define USB_ISTAT_SLEEP_MASK (0x10U) 14005 #define USB_ISTAT_SLEEP_SHIFT (4U) 14006 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) 14007 #define USB_ISTAT_RESUME_MASK (0x20U) 14008 #define USB_ISTAT_RESUME_SHIFT (5U) 14009 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) 14010 #define USB_ISTAT_STALL_MASK (0x80U) 14011 #define USB_ISTAT_STALL_SHIFT (7U) 14012 /*! STALL - Stall Interrupt 14013 */ 14014 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) 14015 /*! @} */ 14016 14017 /*! @name INTEN - Interrupt Enable register */ 14018 /*! @{ */ 14019 #define USB_INTEN_USBRSTEN_MASK (0x1U) 14020 #define USB_INTEN_USBRSTEN_SHIFT (0U) 14021 /*! USBRSTEN - USBRST Interrupt Enable 14022 * 0b0..Disables the USBRST interrupt. 14023 * 0b1..Enables the USBRST interrupt. 14024 */ 14025 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) 14026 #define USB_INTEN_ERROREN_MASK (0x2U) 14027 #define USB_INTEN_ERROREN_SHIFT (1U) 14028 /*! ERROREN - ERROR Interrupt Enable 14029 * 0b0..Disables the ERROR interrupt. 14030 * 0b1..Enables the ERROR interrupt. 14031 */ 14032 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) 14033 #define USB_INTEN_SOFTOKEN_MASK (0x4U) 14034 #define USB_INTEN_SOFTOKEN_SHIFT (2U) 14035 /*! SOFTOKEN - SOFTOK Interrupt Enable 14036 * 0b0..Disbles the SOFTOK interrupt. 14037 * 0b1..Enables the SOFTOK interrupt. 14038 */ 14039 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) 14040 #define USB_INTEN_TOKDNEEN_MASK (0x8U) 14041 #define USB_INTEN_TOKDNEEN_SHIFT (3U) 14042 /*! TOKDNEEN - TOKDNE Interrupt Enable 14043 * 0b0..Disables the TOKDNE interrupt. 14044 * 0b1..Enables the TOKDNE interrupt. 14045 */ 14046 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) 14047 #define USB_INTEN_SLEEPEN_MASK (0x10U) 14048 #define USB_INTEN_SLEEPEN_SHIFT (4U) 14049 /*! SLEEPEN - SLEEP Interrupt Enable 14050 * 0b0..Disables the SLEEP interrupt. 14051 * 0b1..Enables the SLEEP interrupt. 14052 */ 14053 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) 14054 #define USB_INTEN_RESUMEEN_MASK (0x20U) 14055 #define USB_INTEN_RESUMEEN_SHIFT (5U) 14056 /*! RESUMEEN - RESUME Interrupt Enable 14057 * 0b0..Disables the RESUME interrupt. 14058 * 0b1..Enables the RESUME interrupt. 14059 */ 14060 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) 14061 #define USB_INTEN_STALLEN_MASK (0x80U) 14062 #define USB_INTEN_STALLEN_SHIFT (7U) 14063 /*! STALLEN - STALL Interrupt Enable 14064 * 0b0..Diasbles the STALL interrupt. 14065 * 0b1..Enables the STALL interrupt. 14066 */ 14067 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) 14068 /*! @} */ 14069 14070 /*! @name ERRSTAT - Error Interrupt Status register */ 14071 /*! @{ */ 14072 #define USB_ERRSTAT_PIDERR_MASK (0x1U) 14073 #define USB_ERRSTAT_PIDERR_SHIFT (0U) 14074 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) 14075 #define USB_ERRSTAT_CRC5_MASK (0x2U) 14076 #define USB_ERRSTAT_CRC5_SHIFT (1U) 14077 #define USB_ERRSTAT_CRC5(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK) 14078 #define USB_ERRSTAT_CRC16_MASK (0x4U) 14079 #define USB_ERRSTAT_CRC16_SHIFT (2U) 14080 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) 14081 #define USB_ERRSTAT_DFN8_MASK (0x8U) 14082 #define USB_ERRSTAT_DFN8_SHIFT (3U) 14083 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) 14084 #define USB_ERRSTAT_BTOERR_MASK (0x10U) 14085 #define USB_ERRSTAT_BTOERR_SHIFT (4U) 14086 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) 14087 #define USB_ERRSTAT_DMAERR_MASK (0x20U) 14088 #define USB_ERRSTAT_DMAERR_SHIFT (5U) 14089 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) 14090 #define USB_ERRSTAT_BTSERR_MASK (0x80U) 14091 #define USB_ERRSTAT_BTSERR_SHIFT (7U) 14092 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) 14093 /*! @} */ 14094 14095 /*! @name ERREN - Error Interrupt Enable register */ 14096 /*! @{ */ 14097 #define USB_ERREN_PIDERREN_MASK (0x1U) 14098 #define USB_ERREN_PIDERREN_SHIFT (0U) 14099 /*! PIDERREN - PIDERR Interrupt Enable 14100 * 0b0..Disables the PIDERR interrupt. 14101 * 0b1..Enters the PIDERR interrupt. 14102 */ 14103 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) 14104 #define USB_ERREN_CRC5EOFEN_MASK (0x2U) 14105 #define USB_ERREN_CRC5EOFEN_SHIFT (1U) 14106 /*! CRC5EOFEN - CRC5/EOF Interrupt Enable 14107 * 0b0..Disables the CRC5/EOF interrupt. 14108 * 0b1..Enables the CRC5/EOF interrupt. 14109 */ 14110 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) 14111 #define USB_ERREN_CRC16EN_MASK (0x4U) 14112 #define USB_ERREN_CRC16EN_SHIFT (2U) 14113 /*! CRC16EN - CRC16 Interrupt Enable 14114 * 0b0..Disables the CRC16 interrupt. 14115 * 0b1..Enables the CRC16 interrupt. 14116 */ 14117 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) 14118 #define USB_ERREN_DFN8EN_MASK (0x8U) 14119 #define USB_ERREN_DFN8EN_SHIFT (3U) 14120 /*! DFN8EN - DFN8 Interrupt Enable 14121 * 0b0..Disables the DFN8 interrupt. 14122 * 0b1..Enables the DFN8 interrupt. 14123 */ 14124 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) 14125 #define USB_ERREN_BTOERREN_MASK (0x10U) 14126 #define USB_ERREN_BTOERREN_SHIFT (4U) 14127 /*! BTOERREN - BTOERR Interrupt Enable 14128 * 0b0..Disables the BTOERR interrupt. 14129 * 0b1..Enables the BTOERR interrupt. 14130 */ 14131 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) 14132 #define USB_ERREN_DMAERREN_MASK (0x20U) 14133 #define USB_ERREN_DMAERREN_SHIFT (5U) 14134 /*! DMAERREN - DMAERR Interrupt Enable 14135 * 0b0..Disables the DMAERR interrupt. 14136 * 0b1..Enables the DMAERR interrupt. 14137 */ 14138 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) 14139 #define USB_ERREN_BTSERREN_MASK (0x80U) 14140 #define USB_ERREN_BTSERREN_SHIFT (7U) 14141 /*! BTSERREN - BTSERR Interrupt Enable 14142 * 0b0..Disables the BTSERR interrupt. 14143 * 0b1..Enables the BTSERR interrupt. 14144 */ 14145 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) 14146 /*! @} */ 14147 14148 /*! @name STAT - Status register */ 14149 /*! @{ */ 14150 #define USB_STAT_ODD_MASK (0x4U) 14151 #define USB_STAT_ODD_SHIFT (2U) 14152 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) 14153 #define USB_STAT_TX_MASK (0x8U) 14154 #define USB_STAT_TX_SHIFT (3U) 14155 /*! TX - Transmit Indicator 14156 * 0b0..The most recent transaction was a receive operation. 14157 * 0b1..The most recent transaction was a transmit operation. 14158 */ 14159 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) 14160 #define USB_STAT_ENDP_MASK (0xF0U) 14161 #define USB_STAT_ENDP_SHIFT (4U) 14162 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) 14163 /*! @} */ 14164 14165 /*! @name CTL - Control register */ 14166 /*! @{ */ 14167 #define USB_CTL_USBENSOFEN_MASK (0x1U) 14168 #define USB_CTL_USBENSOFEN_SHIFT (0U) 14169 /*! USBENSOFEN - USB Enable 14170 * 0b0..Disables the USB Module. 14171 * 0b1..Enables the USB Module. 14172 */ 14173 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) 14174 #define USB_CTL_ODDRST_MASK (0x2U) 14175 #define USB_CTL_ODDRST_SHIFT (1U) 14176 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) 14177 #define USB_CTL_RESUME_MASK (0x4U) 14178 #define USB_CTL_RESUME_SHIFT (2U) 14179 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) 14180 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) 14181 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) 14182 #define USB_CTL_TXSUSPENDTOKENBUSY(x) \ 14183 (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) 14184 #define USB_CTL_SE0_MASK (0x40U) 14185 #define USB_CTL_SE0_SHIFT (6U) 14186 /*! SE0 - Live USB Single Ended Zero signal 14187 */ 14188 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) 14189 #define USB_CTL_JSTATE_MASK (0x80U) 14190 #define USB_CTL_JSTATE_SHIFT (7U) 14191 /*! JSTATE - Live USB differential receiver JSTATE signal 14192 */ 14193 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) 14194 /*! @} */ 14195 14196 /*! @name ADDR - Address register */ 14197 /*! @{ */ 14198 #define USB_ADDR_ADDR_MASK (0x7FU) 14199 #define USB_ADDR_ADDR_SHIFT (0U) 14200 /*! ADDR - USB Address 14201 */ 14202 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) 14203 /*! @} */ 14204 14205 /*! @name BDTPAGE1 - BDT Page register 1 */ 14206 /*! @{ */ 14207 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) 14208 #define USB_BDTPAGE1_BDTBA_SHIFT (1U) 14209 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) 14210 /*! @} */ 14211 14212 /*! @name FRMNUML - Frame Number register Low */ 14213 /*! @{ */ 14214 #define USB_FRMNUML_FRM_MASK (0xFFU) 14215 #define USB_FRMNUML_FRM_SHIFT (0U) 14216 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) 14217 /*! @} */ 14218 14219 /*! @name FRMNUMH - Frame Number register High */ 14220 /*! @{ */ 14221 #define USB_FRMNUMH_FRM_MASK (0x7U) 14222 #define USB_FRMNUMH_FRM_SHIFT (0U) 14223 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) 14224 /*! @} */ 14225 14226 /*! @name BDTPAGE2 - BDT Page Register 2 */ 14227 /*! @{ */ 14228 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) 14229 #define USB_BDTPAGE2_BDTBA_SHIFT (0U) 14230 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) 14231 /*! @} */ 14232 14233 /*! @name BDTPAGE3 - BDT Page Register 3 */ 14234 /*! @{ */ 14235 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) 14236 #define USB_BDTPAGE3_BDTBA_SHIFT (0U) 14237 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) 14238 /*! @} */ 14239 14240 /*! @name ENDPT - Endpoint Control register */ 14241 /*! @{ */ 14242 #define USB_ENDPT_EPHSHK_MASK (0x1U) 14243 #define USB_ENDPT_EPHSHK_SHIFT (0U) 14244 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) 14245 #define USB_ENDPT_EPSTALL_MASK (0x2U) 14246 #define USB_ENDPT_EPSTALL_SHIFT (1U) 14247 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) 14248 #define USB_ENDPT_EPTXEN_MASK (0x4U) 14249 #define USB_ENDPT_EPTXEN_SHIFT (2U) 14250 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) 14251 #define USB_ENDPT_EPRXEN_MASK (0x8U) 14252 #define USB_ENDPT_EPRXEN_SHIFT (3U) 14253 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) 14254 #define USB_ENDPT_EPCTLDIS_MASK (0x10U) 14255 #define USB_ENDPT_EPCTLDIS_SHIFT (4U) 14256 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) 14257 /*! @} */ 14258 14259 /* The count of USB_ENDPT */ 14260 #define USB_ENDPT_COUNT (16U) 14261 14262 /*! @name USBCTRL - USB Control register */ 14263 /*! @{ */ 14264 #define USB_USBCTRL_PDE_MASK (0x40U) 14265 #define USB_USBCTRL_PDE_SHIFT (6U) 14266 /*! PDE 14267 * 0b0..Weak pulldowns are disabled on D+ and D-. 14268 * 0b1..Weak pulldowns are enabled on D+ and D-. 14269 */ 14270 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) 14271 #define USB_USBCTRL_SUSP_MASK (0x80U) 14272 #define USB_USBCTRL_SUSP_SHIFT (7U) 14273 /*! SUSP 14274 * 0b0..USB transceiver is not in suspend state. 14275 * 0b1..USB transceiver is in suspend state. 14276 */ 14277 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) 14278 /*! @} */ 14279 14280 /*! @name OBSERVE - USB OTG Observe register */ 14281 /*! @{ */ 14282 #define USB_OBSERVE_DMPD_MASK (0x10U) 14283 #define USB_OBSERVE_DMPD_SHIFT (4U) 14284 /*! DMPD 14285 * 0b0..D- pulldown disabled. 14286 * 0b1..D- pulldown enabled. 14287 */ 14288 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) 14289 #define USB_OBSERVE_DPPD_MASK (0x40U) 14290 #define USB_OBSERVE_DPPD_SHIFT (6U) 14291 /*! DPPD 14292 * 0b0..D+ pulldown disabled. 14293 * 0b1..D+ pulldown enabled. 14294 */ 14295 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) 14296 #define USB_OBSERVE_DPPU_MASK (0x80U) 14297 #define USB_OBSERVE_DPPU_SHIFT (7U) 14298 /*! DPPU 14299 * 0b0..D+ pullup disabled. 14300 * 0b1..D+ pullup enabled. 14301 */ 14302 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) 14303 /*! @} */ 14304 14305 /*! @name CONTROL - USB OTG Control register */ 14306 /*! @{ */ 14307 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) 14308 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) 14309 /*! DPPULLUPNONOTG 14310 * 0b0..DP Pullup in non-OTG device mode is not enabled. 14311 * 0b1..DP Pullup in non-OTG device mode is enabled. 14312 */ 14313 #define USB_CONTROL_DPPULLUPNONOTG(x) \ 14314 (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) 14315 /*! @} */ 14316 14317 /*! @name USBTRC0 - USB Transceiver Control register 0 */ 14318 /*! @{ */ 14319 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) 14320 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) 14321 /*! USB_RESUME_INT - USB Asynchronous Interrupt 14322 * 0b0..No interrupt was generated. 14323 * 0b1..Interrupt was generated because of the USB asynchronous interrupt. 14324 */ 14325 #define USB_USBTRC0_USB_RESUME_INT(x) \ 14326 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) 14327 #define USB_USBTRC0_SYNC_DET_MASK (0x2U) 14328 #define USB_USBTRC0_SYNC_DET_SHIFT (1U) 14329 /*! SYNC_DET - Synchronous USB Interrupt Detect 14330 * 0b0..Synchronous interrupt has not been detected. 14331 * 0b1..Synchronous interrupt has been detected. 14332 */ 14333 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) 14334 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) 14335 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) 14336 /*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status 14337 */ 14338 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) \ 14339 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) 14340 #define USB_USBTRC0_USBRESMEN_MASK (0x20U) 14341 #define USB_USBTRC0_USBRESMEN_SHIFT (5U) 14342 /*! USBRESMEN - Asynchronous Resume Interrupt Enable 14343 * 0b0..USB asynchronous wakeup from suspend mode disabled. 14344 * 0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the 14345 * synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ 14346 * and D- pins. This interrupt should only be enabled when the Transceiver is suspended. 14347 */ 14348 #define USB_USBTRC0_USBRESMEN(x) \ 14349 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) 14350 #define USB_USBTRC0_USBRESET_MASK (0x80U) 14351 #define USB_USBTRC0_USBRESET_SHIFT (7U) 14352 /*! USBRESET - USB Reset 14353 * 0b0..Normal USB module operation. 14354 * 0b1..Returns the USB module to its reset state. 14355 */ 14356 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) 14357 /*! @} */ 14358 14359 /*! @name USBFRMADJUST - Frame Adjust Register */ 14360 /*! @{ */ 14361 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) 14362 #define USB_USBFRMADJUST_ADJ_SHIFT (0U) 14363 /*! ADJ - Frame Adjustment 14364 */ 14365 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) 14366 /*! @} */ 14367 14368 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ 14369 /*! @{ */ 14370 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) 14371 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) 14372 /*! RESTART_IFRTRIM_EN - Restart from IFR trim value 14373 * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default) 14374 * 0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is 14375 * desasserted 14376 */ 14377 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) \ 14378 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & \ 14379 USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) 14380 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) 14381 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) 14382 /*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable 14383 * 0b0..Always works in tracking phase after the first time rough to track transition (default) 14384 * 0b1..Go back to rough stage whenever bus reset or bus resume occurs 14385 */ 14386 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) \ 14387 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & \ 14388 USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) 14389 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) 14390 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) 14391 /*! CLOCK_RECOVER_EN - Crystal-less USB enable 14392 * 0b0..Disable clock recovery block (default) 14393 * 0b1..Enable clock recovery block 14394 */ 14395 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) \ 14396 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & \ 14397 USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) 14398 /*! @} */ 14399 14400 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ 14401 /*! @{ */ 14402 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) 14403 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) 14404 /*! IRC_EN - IRC48M enable 14405 * 0b0..Disable the IRC48M module (default) 14406 * 0b1..Enable the IRC48M module 14407 */ 14408 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) \ 14409 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) 14410 /*! @} */ 14411 14412 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ 14413 /*! @{ */ 14414 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) 14415 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) 14416 /*! OVF_ERROR_EN 14417 * 0b0..The interrupt will be masked 14418 * 0b1..The interrupt will be enabled (default) 14419 */ 14420 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) \ 14421 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & \ 14422 USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) 14423 /*! @} */ 14424 14425 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ 14426 /*! @{ */ 14427 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) 14428 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) 14429 /*! OVF_ERROR 14430 * 0b0..No interrupt is reported 14431 * 0b1..Unmasked interrupt has been generated 14432 */ 14433 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) \ 14434 (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & \ 14435 USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) 14436 /*! @} */ 14437 14438 /*! 14439 * @} 14440 */ /* end of group USB_Register_Masks */ 14441 14442 /* USB - Peripheral instance base addresses */ 14443 /** Peripheral USB0 base address */ 14444 #define USB0_BASE (0x40072000u) 14445 /** Peripheral USB0 base pointer */ 14446 #define USB0 ((USB_Type *)USB0_BASE) 14447 /** Array initializer of USB peripheral base addresses */ 14448 #define USB_BASE_ADDRS \ 14449 { \ 14450 USB0_BASE \ 14451 } 14452 /** Array initializer of USB peripheral base pointers */ 14453 #define USB_BASE_PTRS \ 14454 { \ 14455 USB0 \ 14456 } 14457 /** Interrupt vectors for the USB peripheral type */ 14458 #define USB_IRQS \ 14459 { \ 14460 USB0_IRQn \ 14461 } 14462 14463 /*! 14464 * @} 14465 */ /* end of group USB_Peripheral_Access_Layer */ 14466 14467 /* ---------------------------------------------------------------------------- 14468 -- VREF Peripheral Access Layer 14469 ---------------------------------------------------------------------------- */ 14470 14471 /*! 14472 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer 14473 * @{ 14474 */ 14475 14476 /** VREF - Register Layout Typedef */ 14477 typedef struct 14478 { 14479 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ 14480 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ 14481 } VREF_Type; 14482 14483 /* ---------------------------------------------------------------------------- 14484 -- VREF Register Masks 14485 ---------------------------------------------------------------------------- */ 14486 14487 /*! 14488 * @addtogroup VREF_Register_Masks VREF Register Masks 14489 * @{ 14490 */ 14491 14492 /*! @name TRM - VREF Trim Register */ 14493 /*! @{ */ 14494 #define VREF_TRM_TRIM_MASK (0x3FU) 14495 #define VREF_TRM_TRIM_SHIFT (0U) 14496 /*! TRIM - Trim bits 14497 * 0b000000..Min 14498 * 0b111111..Max 14499 */ 14500 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) 14501 #define VREF_TRM_CHOPEN_MASK (0x40U) 14502 #define VREF_TRM_CHOPEN_SHIFT (6U) 14503 /*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the 14504 * internal analog offset will be minimized. 14505 * 0b0..Chop oscillator is disabled. 14506 * 0b1..Chop oscillator is enabled. 14507 */ 14508 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) 14509 /*! @} */ 14510 14511 /*! @name SC - VREF Status and Control Register */ 14512 /*! @{ */ 14513 #define VREF_SC_MODE_LV_MASK (0x3U) 14514 #define VREF_SC_MODE_LV_SHIFT (0U) 14515 /*! MODE_LV - Buffer Mode selection 14516 * 0b00..Bandgap on only, for stabilization and startup 14517 * 0b01..High power buffer mode enabled 14518 * 0b10..Low-power buffer mode enabled 14519 * 0b11..Reserved 14520 */ 14521 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) 14522 #define VREF_SC_VREFST_MASK (0x4U) 14523 #define VREF_SC_VREFST_SHIFT (2U) 14524 /*! VREFST - Internal Voltage Reference stable 14525 * 0b0..The module is disabled or not stable. 14526 * 0b1..The module is stable. 14527 */ 14528 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) 14529 #define VREF_SC_ICOMPEN_MASK (0x20U) 14530 #define VREF_SC_ICOMPEN_SHIFT (5U) 14531 /*! ICOMPEN - Second order curvature compensation enable 14532 * 0b0..Disabled 14533 * 0b1..Enabled 14534 */ 14535 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) 14536 #define VREF_SC_REGEN_MASK (0x40U) 14537 #define VREF_SC_REGEN_SHIFT (6U) 14538 /*! REGEN - Regulator enable 14539 * 0b0..Internal 1.75 V regulator is disabled. 14540 * 0b1..Internal 1.75 V regulator is enabled. 14541 */ 14542 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) 14543 #define VREF_SC_VREFEN_MASK (0x80U) 14544 #define VREF_SC_VREFEN_SHIFT (7U) 14545 /*! VREFEN - Internal Voltage Reference enable 14546 * 0b0..The module is disabled. 14547 * 0b1..The module is enabled. 14548 */ 14549 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) 14550 /*! @} */ 14551 14552 /*! 14553 * @} 14554 */ /* end of group VREF_Register_Masks */ 14555 14556 /* VREF - Peripheral instance base addresses */ 14557 /** Peripheral VREF base address */ 14558 #define VREF_BASE (0x40074000u) 14559 /** Peripheral VREF base pointer */ 14560 #define VREF ((VREF_Type *)VREF_BASE) 14561 /** Array initializer of VREF peripheral base addresses */ 14562 #define VREF_BASE_ADDRS \ 14563 { \ 14564 VREF_BASE \ 14565 } 14566 /** Array initializer of VREF peripheral base pointers */ 14567 #define VREF_BASE_PTRS \ 14568 { \ 14569 VREF \ 14570 } 14571 14572 /*! 14573 * @} 14574 */ /* end of group VREF_Peripheral_Access_Layer */ 14575 14576 /* 14577 ** End of section using anonymous unions 14578 */ 14579 14580 #if defined(__ARMCC_VERSION) 14581 #if (__ARMCC_VERSION >= 6010050) 14582 #pragma clang diagnostic pop 14583 #else 14584 #pragma pop 14585 #endif 14586 #elif defined(__CWCC__) 14587 #pragma pop 14588 #elif defined(__GNUC__) 14589 /* leave anonymous unions enabled */ 14590 #elif defined(__IAR_SYSTEMS_ICC__) 14591 #pragma language = default 14592 #else 14593 #error Not supported compiler type 14594 #endif 14595 14596 /*! 14597 * @} 14598 */ /* end of group Peripheral_access_layer */ 14599 14600 /* ---------------------------------------------------------------------------- 14601 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 14602 ---------------------------------------------------------------------------- */ 14603 14604 /*! 14605 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 14606 * @{ 14607 */ 14608 14609 #if defined(__ARMCC_VERSION) 14610 #if (__ARMCC_VERSION >= 6010050) 14611 #pragma clang system_header 14612 #endif 14613 #elif defined(__IAR_SYSTEMS_ICC__) 14614 #pragma system_include 14615 #endif 14616 14617 /** 14618 * @brief Mask and left-shift a bit field value for use in a register bit range. 14619 * @param field Name of the register bit field. 14620 * @param value Value of the bit field. 14621 * @return Masked and shifted value. 14622 */ 14623 #define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK)) 14624 /** 14625 * @brief Mask and right-shift a register value to extract a bit field value. 14626 * @param field Name of the register bit field. 14627 * @param value Value of the register. 14628 * @return Masked and shifted bit field value. 14629 */ 14630 #define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT)) 14631 14632 /*! 14633 * @} 14634 */ /* end of group Bit_Field_Generic_Macros */ 14635 14636 /* ---------------------------------------------------------------------------- 14637 -- SDK Compatibility 14638 ---------------------------------------------------------------------------- */ 14639 14640 /*! 14641 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 14642 * @{ 14643 */ 14644 14645 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK 14646 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT 14647 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK 14648 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT 14649 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK 14650 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT 14651 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK 14652 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT 14653 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK 14654 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT 14655 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK 14656 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT 14657 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK 14658 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT 14659 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK 14660 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT 14661 #define I2C_S1_REG(base) I2C_S_REG(base) 14662 #define I2C0_S1 I2C0_S 14663 #define I2C1_S1 I2C1_S 14664 #define PTA_BASE GPIOA_BASE 14665 #define PTB_BASE GPIOB_BASE 14666 #define PTC_BASE GPIOC_BASE 14667 #define PTD_BASE GPIOD_BASE 14668 #define PTE_BASE GPIOE_BASE 14669 #define PTA GPIOA 14670 #define PTB GPIOB 14671 #define PTC GPIOC 14672 #define PTD GPIOD 14673 #define PTE GPIOE 14674 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn 14675 #define UART0_FLEXIO_IRQHandler UART2_FLEXIO_IRQHandler 14676 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK 14677 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT 14678 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK 14679 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT 14680 #define UART0_BASE UART2_BASE 14681 #define UART0_BDH UART2_BDH 14682 #define UART0_BDL UART2_BDL 14683 #define UART0_C1 UART2_C1 14684 #define UART0_C2 UART2_C2 14685 #define UART0_S1 UART2_S1 14686 #define UART0_S2 UART2_S2 14687 #define UART0_C3 UART2_C3 14688 #define UART0_D UART2_D 14689 #define UART0_MA1 UART2_MA1 14690 #define UART0_MA2 UART2_MA2 14691 #define UART0_C4 UART2_C4 14692 #define UART0_C5 UART2_C5 14693 #define UART0_ED UART2_ED 14694 #define UART0_MODEM UART2_MODEM 14695 #define UART0_IR UART2_IR 14696 #define UART0_PFIFO UART2_PFIFO 14697 #define UART0_CFIFO UART2_CFIFO 14698 #define UART0_SFIFO UART2_SFIFO 14699 #define UART0_TWFIFO UART2_TWFIFO 14700 #define UART0_TCFIFO UART2_TCFIFO 14701 #define UART0_RWFIFO UART2_RWFIFO 14702 #define UART0_RCFIFO UART2_RCFIFO 14703 #define UART0_C7816 UART2_C7816 14704 #define UART0_IE7816 UART2_IE7816 14705 #define UART0_IS7816 UART2_IS7816 14706 #define UART0_WP7816 UART2_WP7816 14707 #define UART0_WN7816 UART2_WN7816 14708 #define UART0_WF7816 UART2_WF7816 14709 #define UART0_ET7816 UART2_ET7816 14710 #define UART0_TL7816 UART2_TL7816 14711 #define UART0_AP7816A_T0 UART2_AP7816A_T0 14712 #define UART0_AP7816B_T0 UART2_AP7816B_T0 14713 #define UART0_WP7816A_T0 UART2_WP7816A_T0 14714 #define UART0_WP7816A_T1 UART2_WP7816A_T1 14715 #define UART0_WP7816B_T0 UART2_WP7816B_T0 14716 #define UART0_WP7816B_T1 UART2_WP7816B_T1 14717 #define UART0_WGP7816_T1 UART2_WGP7816_T1 14718 #define UART0_WP7816C_T1 UART2_WP7816C_T1 14719 #define CTL0 OTGCTL 14720 #define USB0_CTL0 USB0_OTGCTL 14721 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base) 14722 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK 14723 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT 14724 #define CTL1 CTL 14725 #define USB0_CTL1 USB0_CTL 14726 #define USB_CTL1_REG(base) USB_CTL_REG(base) 14727 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK 14728 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT 14729 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK 14730 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT 14731 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK 14732 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 14733 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK 14734 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT 14735 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK 14736 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT 14737 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK 14738 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT 14739 14740 /*! 14741 * @} 14742 */ /* end of group SDK_Compatibility_Symbols */ 14743 14744 #endif /* _K32L2B31A_H_ */ 14745
