1 /*
2 ** ###################################################################
3 **     Processors:          K32L2A31VLH1A
4 **                          K32L2A31VLL1A
5 **
6 **     Compilers:           Freescale C/C++ for Embedded ARM
7 **                          GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    K32L2AxRM, Rev. 1, 12/2019
13 **     Version:             rev. 1.0, 2019-10-30
14 **     Build:               b191218
15 **
16 **     Abstract:
17 **         CMSIS Peripheral Access Layer for K32L2A31A
18 **
19 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
20 **     Copyright 2016-2019 NXP
21 **     All rights reserved.
22 **
23 **     SPDX-License-Identifier: BSD-3-Clause
24 **
25 **     http:                 www.nxp.com
26 **     mail:                 support@nxp.com
27 **
28 **     Revisions:
29 **     - rev. 1.0 (2019-10-30)
30 **         Initial version.
31 **
32 ** ###################################################################
33 */
34 
35 /*!
36  * @file K32L2A31A.h
37  * @version 1.0
38  * @date 2019-10-30
39  * @brief CMSIS Peripheral Access Layer for K32L2A31A
40  *
41  * CMSIS Peripheral Access Layer for K32L2A31A
42  */
43 
44 #ifndef _K32L2A31A_H_
45 #define _K32L2A31A_H_ /**< Symbol preventing repeated inclusion */
46 
47 /** Memory map major version (memory maps with equal major version number are
48  * compatible) */
49 #define MCU_MEM_MAP_VERSION 0x0100U
50 /** Memory map minor version */
51 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
52 
53 /* ----------------------------------------------------------------------------
54    -- Interrupt vector numbers
55    ---------------------------------------------------------------------------- */
56 
57 /*!
58  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59  * @{
60  */
61 
62 /** Interrupt Number Definitions */
63 #define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */
64 
65 typedef enum IRQn
66 {
67     /* Auxiliary constants */
68     NotAvail_IRQn = -128, /**< Not available device specific interrupt */
69 
70     /* Core interrupts */
71     NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72     HardFault_IRQn      = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
73     SVCall_IRQn         = -5,  /**< Cortex-M0 SV Call Interrupt */
74     PendSV_IRQn         = -2,  /**< Cortex-M0 Pend SV Interrupt */
75     SysTick_IRQn        = -1,  /**< Cortex-M0 System Tick Interrupt */
76 
77     /* Device specific interrupts */
78     DMA0_04_IRQn         = 0,  /**< DMA0 channel 0/4 transfer complete */
79     DMA0_15_IRQn         = 1,  /**< DMA0 channel 1/5 transfer complete */
80     DMA0_26_IRQn         = 2,  /**< DMA0 channel 2/6 transfer complete */
81     DMA0_37_IRQn         = 3,  /**< DMA0 channel 3/7 transfer complete */
82     CTI0_DMA0_Error_IRQn = 4,  /**< CTI0 or DMA0 error */
83     FLEXIO0_IRQn         = 5,  /**< FLEXIO0 */
84     TPM0_IRQn            = 6,  /**< TPM0 single interrupt vector for all sources */
85     TPM1_IRQn            = 7,  /**< TPM1 single interrupt vector for all sources */
86     TPM2_IRQn            = 8,  /**< TPM2 single interrupt vector for all sources */
87     LPIT0_IRQn           = 9,  /**< LPIT0 interrupt */
88     LPSPI0_IRQn          = 10, /**< LPSPI0 single interrupt vector for all sources */
89     LPSPI1_IRQn          = 11, /**< LPSPI1 single interrupt vector for all sources */
90     LPUART0_IRQn         = 12, /**< LPUART0 status and error */
91     LPUART1_IRQn         = 13, /**< LPUART1 status and error */
92     LPI2C0_IRQn          = 14, /**< LPI2C0 interrupt */
93     LPI2C1_IRQn          = 15, /**< LPI2C1 interrupt */
94     Reserved32_IRQn      = 16, /**< Reserved interrupt */
95     PORTA_IRQn           = 17, /**< PORTA Pin detect */
96     PORTB_IRQn           = 18, /**< PORTB Pin detect */
97     PORTC_IRQn           = 19, /**< PORTC Pin detect */
98     PORTD_IRQn           = 20, /**< PORTD Pin detect */
99     PORTE_IRQn           = 21, /**< PORTE Pin detect */
100     LLWU_IRQn            = 22, /**< Low leakage wakeup  */
101     Reserved39_IRQn      = 23, /**< Reserved interrupt */
102     USB0_IRQn            = 24, /**< USB0 interrupt */
103     ADC0_IRQn            = 25, /**< ADC0 interrupt */
104     LPTMR0_IRQn          = 26, /**< LPTMR0 interrupt */
105     RTC_Seconds_IRQn     = 27, /**< RTC seconds */
106     INTMUX0_0_IRQn       = 28, /**< INTMUX0 channel 0 interrupt */
107     INTMUX0_1_IRQn       = 29, /**< INTMUX0 channel 1 interrupt */
108     INTMUX0_2_IRQn       = 30, /**< INTMUX0 channel 2 interrupt */
109     INTMUX0_3_IRQn       = 31, /**< INTMUX0 channel 3 interrupt */
110     LPTMR1_IRQn          = 32, /**< LPTMR1 interrupt  (INTMUX source IRQ0) */
111     Reserved49_IRQn      = 33, /**< Reserved interrupt */
112     Reserved50_IRQn      = 34, /**< Reserved interrupt */
113     Reserved51_IRQn      = 35, /**< Reserved interrupt */
114     LPSPI2_IRQn          = 36, /**< LPSPI2 single interrupt vector for all sources (INTMUX source IRQ4) */
115     LPUART2_IRQn         = 37, /**< LPUART2 status and error (INTMUX source IRQ5) */
116     EMVSIM0_IRQn         = 38, /**< EMVSIM0 interrupt (INTMUX source IRQ6) */
117     LPI2C2_IRQn          = 39, /**< LPI2C2 interrupt (INTMUX source IRQ7) */
118     TSI0_IRQn            = 40, /**< TSI0 interrupt (INTMUX source IRQ8) */
119     PMC_IRQn             = 41, /**< PMC interrupt (INTMUX source IRQ9) */
120     FTFA_IRQn            = 42, /**< FTFA interrupt (INTMUX source IRQ10) */
121     SCG_IRQn             = 43, /**< SCG interrupt (INTMUX source IRQ11) */
122     WDOG0_IRQn           = 44, /**< WDOG0 interrupt (INTMUX source IRQ12) */
123     DAC0_IRQn            = 45, /**< DAC0 interrupt (INTMUX source IRQ13) */
124     TRNG_IRQn            = 46, /**< TRNG interrupt (INTMUX source IRQ14) */
125     RCM_IRQn             = 47, /**< RCM interrupt (INTMUX source IRQ15) */
126     CMP0_IRQn            = 48, /**< CMP0 interrupt (INTMUX source IRQ16) */
127     CMP1_IRQn            = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */
128     RTC_IRQn             = 50, /**< RTC Alarm interrupt (INTMUX source IRQ18) */
129     Reserved67_IRQn      = 51, /**< Reserved interrupt */
130     Reserved68_IRQn      = 52, /**< Reserved interrupt */
131     Reserved69_IRQn      = 53, /**< Reserved interrupt */
132     Reserved70_IRQn      = 54, /**< Reserved interrupt */
133     Reserved71_IRQn      = 55, /**< Reserved interrupt */
134     Reserved72_IRQn      = 56, /**< Reserved interrupt */
135     Reserved73_IRQn      = 57, /**< Reserved interrupt */
136     Reserved74_IRQn      = 58, /**< Reserved interrupt */
137     Reserved75_IRQn      = 59, /**< Reserved interrupt */
138     Reserved76_IRQn      = 60, /**< Reserved interrupt */
139     Reserved77_IRQn      = 61, /**< Reserved interrupt */
140     Reserved78_IRQn      = 62, /**< Reserved interrupt */
141     Reserved79_IRQn      = 63  /**< Reserved interrupt */
142 } IRQn_Type;
143 
144 /*!
145  * @}
146  */ /* end of group Interrupt_vector_numbers */
147 
148 /* ----------------------------------------------------------------------------
149    -- Cortex M0 Core Configuration
150    ---------------------------------------------------------------------------- */
151 
152 /*!
153  * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
154  * @{
155  */
156 
157 #define __CM0PLUS_REV 0x0000     /**< Core revision r0p0 */
158 #define __MPU_PRESENT 1          /**< Defines if an MPU is present or not */
159 #define __VTOR_PRESENT 1         /**< Defines if VTOR is present or not */
160 #define __NVIC_PRIO_BITS 2       /**< Number of priority bits implemented in the NVIC */
161 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
162 
163 #include "core_cm0plus.h"     /* Core Peripheral Access Layer */
164 #include "system_K32L2A31A.h" /* Device specific configuration file */
165 
166 /*!
167  * @}
168  */ /* end of group Cortex_Core_Configuration */
169 
170 /* ----------------------------------------------------------------------------
171    -- Mapping Information
172    ---------------------------------------------------------------------------- */
173 
174 /*!
175  * @addtogroup Mapping_Information Mapping Information
176  * @{
177  */
178 
179 /** Mapping Information */
180 /*!
181  * @addtogroup edma_request
182  * @{
183  */
184 
185 /*******************************************************************************
186  * Definitions
187  ******************************************************************************/
188 
189 /*!
190  * @brief Structure for the DMA hardware request
191  *
192  * Defines the structure for the DMA hardware request collections. The user can configure the
193  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
194  * of the hardware request varies according  to the to SoC.
195  */
196 typedef enum _dma_request_source
197 {
198     kDmaRequestMux0Disable         = 0 | 0x100U,  /**< DMAMUX TriggerDisabled */
199     kDmaRequestMux0FlexIO0Channel0 = 1 | 0x100U,  /**< FLEXIO0 Channel 0 */
200     kDmaRequestMux0FlexIO0Channel1 = 2 | 0x100U,  /**< FLEXIO0 Channel 1 */
201     kDmaRequestMux0FlexIO0Channel2 = 3 | 0x100U,  /**< FLEXIO0 Channel 2 */
202     kDmaRequestMux0FlexIO0Channel3 = 4 | 0x100U,  /**< FLEXIO0 Channel 3 */
203     kDmaRequestMux0FlexIO0Channel4 = 5 | 0x100U,  /**< FLEXIO0 Channel 4 */
204     kDmaRequestMux0FlexIO0Channel5 = 6 | 0x100U,  /**< FLEXIO0 Channel 5 */
205     kDmaRequestMux0FlexIO0Channel6 = 7 | 0x100U,  /**< FLEXIO0 Channel 6 */
206     kDmaRequestMux0FlexIO0Channel7 = 8 | 0x100U,  /**< FLEXIO0 Channel 7 */
207     kDmaRequestMux0LPI2C0Rx        = 9 | 0x100U,  /**< LPI2C0 Receive */
208     kDmaRequestMux0LPI2C0Tx        = 10 | 0x100U, /**< LPI2C0 Transmit */
209     kDmaRequestMux0LPI2C1Rx        = 11 | 0x100U, /**< LPI2C1 Receive */
210     kDmaRequestMux0LPI2C1Tx        = 12 | 0x100U, /**< LPI2C1 Transmit */
211     kDmaRequestMux0LPI2C2Rx        = 13 | 0x100U, /**< LPI2C2 Receive */
212     kDmaRequestMux0LPI2C2Tx        = 14 | 0x100U, /**< LPI2C2 Transmit */
213     kDmaRequestMux0LPUART0Rx       = 15 | 0x100U, /**< LPUART0 Receive */
214     kDmaRequestMux0LPUART0Tx       = 16 | 0x100U, /**< LPUART0 Transmit */
215     kDmaRequestMux0LPUART1Rx       = 17 | 0x100U, /**< LPUART1 Receive */
216     kDmaRequestMux0LPUART1Tx       = 18 | 0x100U, /**< LPUART1 Transmit */
217     kDmaRequestMux0LPUART2Rx       = 19 | 0x100U, /**< LPUART2 Receive */
218     kDmaRequestMux0LPUART2Tx       = 20 | 0x100U, /**< LPUART2 Transmit */
219     kDmaRequestMux0LPSPI0Rx        = 21 | 0x100U, /**< LPSPI0 Receive */
220     kDmaRequestMux0LPSPI0Tx        = 22 | 0x100U, /**< LPSPI0 Transmit */
221     kDmaRequestMux0LPSPI1Rx        = 23 | 0x100U, /**< LPSPI1 Receive */
222     kDmaRequestMux0LPSPI1Tx        = 24 | 0x100U, /**< LPSPI1 Transmit */
223     kDmaRequestMux0LPSPI2Rx        = 25 | 0x100U, /**< LPSPI2 Receive */
224     kDmaRequestMux0LPSPI2Tx        = 26 | 0x100U, /**< LPSPI2 Transmit */
225     kDmaRequestMux0TPM0Channel0    = 27 | 0x100U, /**< TPM0 C0V Transmit */
226     kDmaRequestMux0TPM0Channel1    = 28 | 0x100U, /**< TPM0 C1V Transmit */
227     kDmaRequestMux0TPM0Channel2    = 29 | 0x100U, /**< TPM0 C2V Transmit */
228     kDmaRequestMux0TPM0Channel3    = 30 | 0x100U, /**< TPM0 C3V Transmit */
229     kDmaRequestMux0TPM0Channel4    = 31 | 0x100U, /**< TPM0 C4V Transmit */
230     kDmaRequestMux0TPM0Channel5    = 32 | 0x100U, /**< TPM0 C5V Transmit */
231     kDmaRequestMux0Reserved33      = 33 | 0x100U, /**< Reserved33 */
232     kDmaRequestMux0Reserved34      = 34 | 0x100U, /**< Reserved34 */
233     kDmaRequestMux0TPM0Overflow    = 35 | 0x100U, /**< TPM0 */
234     kDmaRequestMux0TPM1Channel0    = 36 | 0x100U, /**< TPM1 C0V Transmit */
235     kDmaRequestMux0TPM1Channel1    = 37 | 0x100U, /**< TPM1 C1V Transmit */
236     kDmaRequestMux0TPM1Overflow    = 38 | 0x100U, /**< TPM1 */
237     kDmaRequestMux0TPM2Channel0    = 39 | 0x100U, /**< TPM2 C0V Transmit */
238     kDmaRequestMux0TPM2Channel1    = 40 | 0x100U, /**< TPM2 C1V Transmit */
239     kDmaRequestMux0TPM2Overflow    = 41 | 0x100U, /**< TPM2 */
240     kDmaRequestMux0Reserved42      = 42 | 0x100U, /**< Reserved42 */
241     kDmaRequestMux0EMVSIM0Rx       = 43 | 0x100U, /**< EMVSIM0 Receive */
242     kDmaRequestMux0EMVSIM0Tx       = 44 | 0x100U, /**< EMVSIM0 Transmit */
243     kDmaRequestMux0Reserved45      = 45 | 0x100U, /**< Reserved45 */
244     kDmaRequestMux0Reserved46      = 46 | 0x100U, /**< Reserved46 */
245     kDmaRequestMux0PortA           = 47 | 0x100U, /**< PTA */
246     kDmaRequestMux0PortB           = 48 | 0x100U, /**< PTB */
247     kDmaRequestMux0PortC           = 49 | 0x100U, /**< PTC */
248     kDmaRequestMux0PortD           = 50 | 0x100U, /**< PTD */
249     kDmaRequestMux0PortE           = 51 | 0x100U, /**< PTE */
250     kDmaRequestMux0ADC0            = 52 | 0x100U, /**< ADC0 */
251     kDmaRequestMux0Reserved53      = 53 | 0x100U, /**< Reserved53 */
252     kDmaRequestMux0DAC0            = 54 | 0x100U, /**< DAC0 */
253     kDmaRequestMux0Reserved55      = 55 | 0x100U, /**< Reserved55 */
254     kDmaRequestMux0CMP0            = 56 | 0x100U, /**< CMP0 */
255     kDmaRequestMux0CMP1            = 57 | 0x100U, /**< CMP1 */
256     kDmaRequestMux0Reserved58      = 58 | 0x100U, /**< Reserved58 */
257     kDmaRequestMux0Reserved59      = 59 | 0x100U, /**< Reserved59 */
258     kDmaRequestMux0TSI0            = 60 | 0x100U, /**< TSI0 */
259     kDmaRequestMux0LPTMR0          = 61 | 0x100U, /**< LPTMR0 */
260     kDmaRequestMux0LPTMR1          = 62 | 0x100U, /**< LPTMR1 */
261     kDmaRequestMux0AlwaysOn63      = 63 | 0x100U, /**< DMAMUX Always Enabled slot */
262 } dma_request_source_t;
263 
264 /* @} */
265 
266 /*!
267  * @addtogroup trgmux_source
268  * @{ */
269 
270 /*******************************************************************************
271  * Definitions
272  *******************************************************************************/
273 
274 /*!
275  * @brief Structure for the TRGMUX source
276  *
277  * Defines the structure for the TRGMUX source collections.
278  */
279 typedef enum _trgmux_source
280 {
281     kTRGMUX_SourceDisabled          = 0U,  /**< Trigger function is disabled */
282     kTRGMUX_SourcePortPin           = 1U,  /**< Port pin trigger intput is selected */
283     kTRGMUX_SourceFlexIOTimer0      = 2U,  /**< FlexIO Timer 0 input is selected */
284     kTRGMUX_SourceFlexIOTimer1      = 3U,  /**< FlexIO Timer 1 input is selected */
285     kTRGMUX_SourceFlexIOTimer2      = 4U,  /**< FlexIO Timer 2 input is selected */
286     kTRGMUX_SourceFlexIOTimer3      = 5U,  /**< FlexIO Timer 3 input is selected */
287     kTRGMUX_SourceFlexIOTimer4      = 6U,  /**< FlexIO Timer 4 input is selected */
288     kTRGMUX_SourceFlexIOTimer5      = 7U,  /**< FlexIO Timer 5 input is selected */
289     kTRGMUX_SourceFlexIOTimer6      = 8U,  /**< FlexIO Timer 6 input is selected */
290     kTRGMUX_SourceFlexIOTimer7      = 9U,  /**< FlexIO Timer 7 input is selected */
291     kTRGMUX_SourceTpm0Overflow      = 10U, /**< TPM0 Overflow is selected */
292     kTRGMUX_SourceTpm0Ch0           = 11U, /**< TPM0 Channel 0 is selected */
293     kTRGMUX_SourceTpm0Ch1           = 12U, /**< TPM0 Channel 1 is selected */
294     kTRGMUX_SourceTpm1Overflow      = 13U, /**< TPM1 Overflow is selected */
295     kTRGMUX_SourceTpm1Ch0           = 14U, /**< TPM1 Channel 0 is selected */
296     kTRGMUX_SourceTpm1Ch1           = 15U, /**< TPM1 Channel 1 is selected */
297     kTRGMUX_SourceLpit1Ch0          = 16U, /**< LPIT1 Channel 0 is selected */
298     kTRGMUX_SourceLpit1Ch1          = 17U, /**< LPIT1 Channel 1 is selected */
299     kTRGMUX_SourceLpit1Ch2          = 18U, /**< LPIT1 Channel 2 is selected */
300     kTRGMUX_SourceLpit1Ch3          = 19U, /**< LPIT1 Channel 3 is selected */
301     kTRGMUX_SourceLpuart0RxData     = 20U, /**< LPUART0 RX Data is selected */
302     kTRGMUX_SourceLpuart0TxData     = 21U, /**< LPUART0 TX Data is selected */
303     kTRGMUX_SourceLpuart0RxIdle     = 22U, /**< LPUART0 RX Idle is selected */
304     kTRGMUX_SourceLpuart1RxData     = 23U, /**< LPUART1 RX Data is selected */
305     kTRGMUX_SourceLpuart1TxData     = 24U, /**< LPUART1 TX Data is selected */
306     kTRGMUX_SourceLpuart1RxIdle     = 25U, /**< LPUART1 RX Idle is selected */
307     kTRGMUX_SourceLpi2c0MasterStop  = 26U, /**< LPI2C0 Master STOP is selected */
308     kTRGMUX_SourceLpi2c0SlaveStop   = 27U, /**< LPI2C0 Slave STOP is selected */
309     kTRGMUX_SourceLpi2c1MasterStop  = 28U, /**< LPI2C1 Master STOP is selected */
310     kTRGMUX_SourceLpi2c1SlaveStop   = 29U, /**< LPI2C1 Slave STOP is selected */
311     kTRGMUX_SourceLpspi0Frame       = 30U, /**< LPSPI0 Frame is selected */
312     kTRGMUX_SourceLpspi0RxData      = 31U, /**< LPSPI0 RX Data is selected */
313     kTRGMUX_SourceLpspi1Frame       = 32U, /**< LPSPI1 Frame is selected */
314     kTRGMUX_SourceLpspi1RxData      = 33U, /**< LPSPI1 RX Data is selected */
315     kTRGMUX_SourceRtcSecCount       = 34U, /**< RTC Seconds Counter is selected */
316     kTRGMUX_SourceRtcAlarm          = 35U, /**< RTC Alarm is selected */
317     kTRGMUX_SourceLptmr0Trg         = 36U, /**< LPTMR0 Trigger is selected */
318     kTRGMUX_SourceLptmr1Trg         = 37U, /**< LPTMR1 Trigger is selected */
319     kTRGMUX_SourceCmp0Output        = 38U, /**< CMP0 Output is selected */
320     kTRGMUX_SourceCmp1Output        = 39U, /**< CMP1 Output is selected */
321     kTRGMUX_SourceAdc0ConvAComplete = 40U, /**< ADC0 Conversion A Complete is selected */
322     kTRGMUX_SourceAdc0ConvBComplete = 41U, /**< ADC0 Conversion B Complete is selected */
323     kTRGMUX_SourcePortAPinTrg       = 42U, /**< Port A Pin Trigger is selected */
324     kTRGMUX_SourcePortBPinTrg       = 43U, /**< Port B Pin Trigger is selected */
325     kTRGMUX_SourcePortCPinTrg       = 44U, /**< Port C Pin Trigger is selected */
326     kTRGMUX_SourcePortDPinTrg       = 45U, /**< Port D Pin Trigger is selected */
327     kTRGMUX_SourcePortEPinTrg       = 46U, /**< Port E Pin Trigger is selected */
328     kTRGMUX_SourceTpm2Overflow      = 47U, /**< TPM2 Overflow is selected */
329     kTRGMUX_SourceTpm2Ch0           = 48U, /**< TPM2 Channel 0 is selected */
330     kTRGMUX_SourceTpm2Ch1           = 49U, /**< TPM2 Channel 1 is selected */
331     kTRGMUX_SourceLpit0Ch0          = 50U, /**< LPIT0 Channel 0 is selected */
332     kTRGMUX_SourceLpit0Ch1          = 51U, /**< LPIT0 Channel 1 is selected */
333     kTRGMUX_SourceLpit0Ch2          = 52U, /**< LPIT0 Channel 2 is selected */
334     kTRGMUX_SourceLpit0Ch3          = 53U, /**< LPIT0 Channel 3 is selected */
335     kTRGMUX_SourceUsbSof            = 54U, /**< USB Start-of-Frame is selected */
336     kTRGMUX_SourceLpuart2RxData     = 55U, /**< LPUART2 RX Data is selected */
337     kTRGMUX_SourceLpuart2TxData     = 56U, /**< LPUART2 TX Data is selected */
338     kTRGMUX_SourceLpuart2RxIdle     = 57U, /**< LPUART2 RX Idle is selected */
339     kTRGMUX_SourceLpi2c2MasterStop  = 58U, /**< LPI2C2 Master STOP is selected */
340     kTRGMUX_SourceLpi2c2SlaveStop   = 59U, /**< LPI2C2 Slave STOP is selected */
341     kTRGMUX_SourceLpspi2Frame       = 60U, /**< LPSPI2 Frame is selected */
342     kTRGMUX_SourceLpspi2RxData      = 61U, /**< LPSPI2 RX Data is selected */
343     kTRGMUX_SourceI2c0TxFrameSync   = 62U, /**< I2C0 TX Frame Sync is selected */
344     kTRGMUX_SourceI2c0RxFrameSync   = 63U, /**< I2C0 RX Frame Sync is selected */
345 } trgmux_source_t;
346 
347 /*!
348  * @brief Structure for the TRGMUX device
349  *
350  * Defines the structure for the TRGMUX device collections.
351  */
352 typedef enum _trgmux_device
353 {
354     kTRGMUX_Trgmux0Dmamux0 = 0U,  /**< DMAMUX0 device trigger input */
355     kTRGMUX_Trgmux0Lpit0   = 1U,  /**< LPIT0 device trigger input */
356     kTRGMUX_Trgmux0Tpm2    = 2U,  /**< TPM2 device trigger input */
357     kTRGMUX_Trgmux1Tpm0    = 2U,  /**< TPM0 device trigger input */
358     kTRGMUX_Trgmux0Adc0    = 4U,  /**< ADC0 device trigger input */
359     kTRGMUX_Trgmux1Flexio  = 4U,  /**< FLEXIO device trigger input */
360     kTRGMUX_Trgmux0Lpuart2 = 5U,  /**< LPUART2 device trigger input */
361     kTRGMUX_Trgmux1Lpuart0 = 5U,  /**< LPUART0 device trigger input */
362     kTRGMUX_Trgmux0Lpi2c2  = 7U,  /**< LPI2C2 device trigger input */
363     kTRGMUX_Trgmux1Lpi2c0  = 7U,  /**< LPI2C0 device trigger input */
364     kTRGMUX_Trgmux0Lpspi2  = 9U,  /**< LPSPI2 device trigger input */
365     kTRGMUX_Trgmux1Lpspi0  = 9U,  /**< LPSPI0 device trigger input */
366     kTRGMUX_Trgmux0Cmp0    = 11U, /**< CMP0 device trigger input */
367     kTRGMUX_Trgmux0Cmp1    = 12U, /**< CMP1 device trigger input */
368     kTRGMUX_Trgmux0Dac0    = 13U, /**< DAC0 device trigger input */
369     kTRGMUX_Trgmux1Tpm1    = 3U,  /**< TPM1 device trigger input */
370     kTRGMUX_Trgmux1Lpuart1 = 6U,  /**< LPUART1 device trigger input */
371     kTRGMUX_Trgmux1Lpi2c1  = 8U,  /**< LPI2C1 device trigger input */
372     kTRGMUX_Trgmux1Lpspi1  = 10U, /**< LPSPI1 device trigger input */
373 } trgmux_device_t;
374 
375 /* @} */
376 
377 /*!
378  * @}
379  */ /* end of group Mapping_Information */
380 
381 /* ----------------------------------------------------------------------------
382    -- Device Peripheral Access Layer
383    ---------------------------------------------------------------------------- */
384 
385 /*!
386  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
387  * @{
388  */
389 
390 /*
391 ** Start of section using anonymous unions
392 */
393 
394 #if defined(__ARMCC_VERSION)
395 #if (__ARMCC_VERSION >= 6010050)
396 #pragma clang diagnostic push
397 #else
398 #pragma push
399 #pragma anon_unions
400 #endif
401 #elif defined(__CWCC__)
402 #pragma push
403 #pragma cpp_extensions on
404 #elif defined(__GNUC__)
405 /* anonymous unions are enabled by default */
406 #elif defined(__IAR_SYSTEMS_ICC__)
407 #pragma language = extended
408 #else
409 #error Not supported compiler type
410 #endif
411 
412 /* ----------------------------------------------------------------------------
413    -- ADC Peripheral Access Layer
414    ---------------------------------------------------------------------------- */
415 
416 /*!
417  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
418  * @{
419  */
420 
421 /** ADC - Register Layout Typedef */
422 typedef struct
423 {
424     __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
425     __IO uint32_t CFG1;   /**< ADC Configuration Register 1, offset: 0x8 */
426     __IO uint32_t CFG2;   /**< ADC Configuration Register 2, offset: 0xC */
427     __I uint32_t R[2];    /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
428     __IO uint32_t CV1;    /**< Compare Value Registers, offset: 0x18 */
429     __IO uint32_t CV2;    /**< Compare Value Registers, offset: 0x1C */
430     __IO uint32_t SC2;    /**< Status and Control Register 2, offset: 0x20 */
431     __IO uint32_t SC3;    /**< Status and Control Register 3, offset: 0x24 */
432     __IO uint32_t OFS;    /**< ADC Offset Correction Register, offset: 0x28 */
433     __IO uint32_t PG;     /**< ADC Plus-Side Gain Register, offset: 0x2C */
434     __IO uint32_t MG;     /**< ADC Minus-Side Gain Register, offset: 0x30 */
435     __IO uint32_t CLPD;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
436     __IO uint32_t CLPS;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
437     __IO uint32_t CLP4;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
438     __IO uint32_t CLP3;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
439     __IO uint32_t CLP2;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
440     __IO uint32_t CLP1;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
441     __IO uint32_t CLP0;   /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
442     uint8_t RESERVED_0[4];
443     __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
444     __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
445     __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
446     __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
447     __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
448     __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
449     __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
450 } ADC_Type;
451 
452 /* ----------------------------------------------------------------------------
453    -- ADC Register Masks
454    ---------------------------------------------------------------------------- */
455 
456 /*!
457  * @addtogroup ADC_Register_Masks ADC Register Masks
458  * @{
459  */
460 
461 /*! @name SC1 - ADC Status and Control Registers 1 */
462 /*! @{ */
463 #define ADC_SC1_ADCH_MASK (0x1FU)
464 #define ADC_SC1_ADCH_SHIFT (0U)
465 /*! ADCH - Input channel select
466  *  0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
467  *  0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
468  *  0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
469  *  0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
470  *  0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
471  *  0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
472  *  0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
473  *  0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
474  *  0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
475  *  0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
476  *  0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
477  *  0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
478  *  0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
479  *  0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
480  *  0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
481  *  0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
482  *  0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
483  *  0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
484  *  0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
485  *  0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
486  *  0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
487  *  0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
488  *  0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
489  *  0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
490  *  0b11000..Reserved.
491  *  0b11001..Reserved.
492  *  0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is
493  * selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap
494  * (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when
495  * DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
496  *  0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is
497  * determined by SC2[REFSEL]. 0b11111..Module is disabled.
498  */
499 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
500 #define ADC_SC1_DIFF_MASK (0x20U)
501 #define ADC_SC1_DIFF_SHIFT (5U)
502 /*! DIFF - Differential Mode Enable
503  *  0b0..Single-ended conversions and input channels are selected.
504  *  0b1..Differential conversions and input channels are selected.
505  */
506 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
507 #define ADC_SC1_AIEN_MASK (0x40U)
508 #define ADC_SC1_AIEN_SHIFT (6U)
509 /*! AIEN - Interrupt Enable
510  *  0b0..Conversion complete interrupt is disabled.
511  *  0b1..Conversion complete interrupt is enabled.
512  */
513 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
514 #define ADC_SC1_COCO_MASK (0x80U)
515 #define ADC_SC1_COCO_SHIFT (7U)
516 /*! COCO - Conversion Complete Flag
517  *  0b0..Conversion is not completed.
518  *  0b1..Conversion is completed.
519  */
520 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
521 /*! @} */
522 
523 /* The count of ADC_SC1 */
524 #define ADC_SC1_COUNT (2U)
525 
526 /*! @name CFG1 - ADC Configuration Register 1 */
527 /*! @{ */
528 #define ADC_CFG1_ADICLK_MASK (0x3U)
529 #define ADC_CFG1_ADICLK_SHIFT (0U)
530 /*! ADICLK - Input Clock Select
531  *  0b00..Bus clock
532  *  0b01..Bus clock divided by 2(BUSCLK/2)
533  *  0b10..Alternate clock (ALTCLK)
534  *  0b11..Asynchronous clock (ADACK)
535  */
536 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
537 #define ADC_CFG1_MODE_MASK (0xCU)
538 #define ADC_CFG1_MODE_SHIFT (2U)
539 /*! MODE - Conversion mode selection
540  *  0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's
541  * complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit
542  * conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
543  * differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..;
544  * when DIFF=1, it is differential 16-bit conversion with 2's complement output
545  */
546 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
547 #define ADC_CFG1_ADLSMP_MASK (0x10U)
548 #define ADC_CFG1_ADLSMP_SHIFT (4U)
549 /*! ADLSMP - Sample Time Configuration
550  *  0b0..Short sample time.
551  *  0b1..Long sample time.
552  */
553 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
554 #define ADC_CFG1_ADIV_MASK (0x60U)
555 #define ADC_CFG1_ADIV_SHIFT (5U)
556 /*! ADIV - Clock Divide Select
557  *  0b00..The divide ratio is 1 and the clock rate is input clock.
558  *  0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
559  *  0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
560  *  0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
561  */
562 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
563 #define ADC_CFG1_ADLPC_MASK (0x80U)
564 #define ADC_CFG1_ADLPC_SHIFT (7U)
565 /*! ADLPC - Low-Power Configuration
566  *  0b0..Normal power configuration.
567  *  0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
568  */
569 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
570 /*! @} */
571 
572 /*! @name CFG2 - ADC Configuration Register 2 */
573 /*! @{ */
574 #define ADC_CFG2_ADLSTS_MASK (0x3U)
575 #define ADC_CFG2_ADLSTS_SHIFT (0U)
576 /*! ADLSTS - Long Sample Time Select
577  *  0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
578  *  0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
579  *  0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
580  *  0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
581  */
582 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
583 #define ADC_CFG2_ADHSC_MASK (0x4U)
584 #define ADC_CFG2_ADHSC_SHIFT (2U)
585 /*! ADHSC - High-Speed Configuration
586  *  0b0..Normal conversion sequence selected.
587  *  0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
588  */
589 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
590 #define ADC_CFG2_ADACKEN_MASK (0x8U)
591 #define ADC_CFG2_ADACKEN_SHIFT (3U)
592 /*! ADACKEN - Asynchronous Clock Output Enable
593  *  0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion
594  * is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
595  */
596 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
597 #define ADC_CFG2_MUXSEL_MASK (0x10U)
598 #define ADC_CFG2_MUXSEL_SHIFT (4U)
599 /*! MUXSEL - ADC Mux Select
600  *  0b0..ADxxa channels are selected.
601  *  0b1..ADxxb channels are selected.
602  */
603 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
604 /*! @} */
605 
606 /*! @name R - ADC Data Result Register */
607 /*! @{ */
608 #define ADC_R_D_MASK (0xFFFFU)
609 #define ADC_R_D_SHIFT (0U)
610 /*! D - Data result
611  */
612 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
613 /*! @} */
614 
615 /* The count of ADC_R */
616 #define ADC_R_COUNT (2U)
617 
618 /*! @name CV1 - Compare Value Registers */
619 /*! @{ */
620 #define ADC_CV1_CV_MASK (0xFFFFU)
621 #define ADC_CV1_CV_SHIFT (0U)
622 /*! CV - Compare Value.
623  */
624 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
625 /*! @} */
626 
627 /*! @name CV2 - Compare Value Registers */
628 /*! @{ */
629 #define ADC_CV2_CV_MASK (0xFFFFU)
630 #define ADC_CV2_CV_SHIFT (0U)
631 /*! CV - Compare Value.
632  */
633 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
634 /*! @} */
635 
636 /*! @name SC2 - Status and Control Register 2 */
637 /*! @{ */
638 #define ADC_SC2_REFSEL_MASK (0x3U)
639 #define ADC_SC2_REFSEL_SHIFT (0U)
640 /*! REFSEL - Voltage Reference Selection
641  *  0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
642  *  0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or
643  *        internal sources depending on the MCU configuration. See the chip configuration information for details
644  *        specific to this MCU
645  *  0b10..Reserved
646  *  0b11..Reserved
647  */
648 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
649 #define ADC_SC2_DMAEN_MASK (0x4U)
650 #define ADC_SC2_DMAEN_SHIFT (2U)
651 /*! DMAEN - DMA Enable
652  *  0b0..DMA is disabled.
653  *  0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any
654  *       of the SC1n[COCO] flags is asserted.
655  */
656 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
657 #define ADC_SC2_ACREN_MASK (0x8U)
658 #define ADC_SC2_ACREN_SHIFT (3U)
659 /*! ACREN - Compare Function Range Enable
660  *  0b0..Range function disabled. Only CV1 is compared.
661  *  0b1..Range function enabled. Both CV1 and CV2 are compared.
662  */
663 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
664 #define ADC_SC2_ACFGT_MASK (0x10U)
665 #define ADC_SC2_ACFGT_SHIFT (4U)
666 /*! ACFGT - Compare Function Greater Than Enable
667  *  0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality
668  *       based on the values placed in CV1 and CV2.
669  *  0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the
670  * values placed in CV1 and CV2.
671  */
672 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
673 #define ADC_SC2_ACFE_MASK (0x20U)
674 #define ADC_SC2_ACFE_SHIFT (5U)
675 /*! ACFE - Compare Function Enable
676  *  0b0..Compare function disabled.
677  *  0b1..Compare function enabled.
678  */
679 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
680 #define ADC_SC2_ADTRG_MASK (0x40U)
681 #define ADC_SC2_ADTRG_SHIFT (6U)
682 /*! ADTRG - Conversion Trigger Select
683  *  0b0..Software trigger selected.
684  *  0b1..Hardware trigger selected.
685  */
686 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
687 #define ADC_SC2_ADACT_MASK (0x80U)
688 #define ADC_SC2_ADACT_SHIFT (7U)
689 /*! ADACT - Conversion Active
690  *  0b0..Conversion not in progress.
691  *  0b1..Conversion in progress.
692  */
693 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
694 /*! @} */
695 
696 /*! @name SC3 - Status and Control Register 3 */
697 /*! @{ */
698 #define ADC_SC3_AVGS_MASK (0x3U)
699 #define ADC_SC3_AVGS_SHIFT (0U)
700 /*! AVGS - Hardware Average Select
701  *  0b00..4 samples averaged.
702  *  0b01..8 samples averaged.
703  *  0b10..16 samples averaged.
704  *  0b11..32 samples averaged.
705  */
706 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
707 #define ADC_SC3_AVGE_MASK (0x4U)
708 #define ADC_SC3_AVGE_SHIFT (2U)
709 /*! AVGE - Hardware Average Enable
710  *  0b0..Hardware average function disabled.
711  *  0b1..Hardware average function enabled.
712  */
713 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
714 #define ADC_SC3_ADCO_MASK (0x8U)
715 #define ADC_SC3_ADCO_SHIFT (3U)
716 /*! ADCO - Continuous Conversion Enable
717  *  0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after
718  * initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is
719  * enabled, that is, AVGE=1, after initiating a conversion.
720  */
721 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
722 #define ADC_SC3_CALF_MASK (0x40U)
723 #define ADC_SC3_CALF_SHIFT (6U)
724 /*! CALF - Calibration Failed Flag
725  *  0b0..Calibration completed normally.
726  *  0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
727  */
728 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
729 #define ADC_SC3_CAL_MASK (0x80U)
730 #define ADC_SC3_CAL_SHIFT (7U)
731 /*! CAL - Calibration
732  */
733 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
734 /*! @} */
735 
736 /*! @name OFS - ADC Offset Correction Register */
737 /*! @{ */
738 #define ADC_OFS_OFS_MASK (0xFFFFU)
739 #define ADC_OFS_OFS_SHIFT (0U)
740 /*! OFS - Offset Error Correction Value
741  */
742 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
743 /*! @} */
744 
745 /*! @name PG - ADC Plus-Side Gain Register */
746 /*! @{ */
747 #define ADC_PG_PG_MASK (0xFFFFU)
748 #define ADC_PG_PG_SHIFT (0U)
749 /*! PG - Plus-Side Gain
750  */
751 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
752 /*! @} */
753 
754 /*! @name MG - ADC Minus-Side Gain Register */
755 /*! @{ */
756 #define ADC_MG_MG_MASK (0xFFFFU)
757 #define ADC_MG_MG_SHIFT (0U)
758 /*! MG - Minus-Side Gain
759  */
760 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
761 /*! @} */
762 
763 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
764 /*! @{ */
765 #define ADC_CLPD_CLPD_MASK (0x3FU)
766 #define ADC_CLPD_CLPD_SHIFT (0U)
767 /*! CLPD - Calibration Value
768  */
769 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
770 /*! @} */
771 
772 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
773 /*! @{ */
774 #define ADC_CLPS_CLPS_MASK (0x3FU)
775 #define ADC_CLPS_CLPS_SHIFT (0U)
776 /*! CLPS - Calibration Value
777  */
778 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
779 /*! @} */
780 
781 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
782 /*! @{ */
783 #define ADC_CLP4_CLP4_MASK (0x3FFU)
784 #define ADC_CLP4_CLP4_SHIFT (0U)
785 /*! CLP4 - Calibration Value
786  */
787 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
788 /*! @} */
789 
790 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
791 /*! @{ */
792 #define ADC_CLP3_CLP3_MASK (0x1FFU)
793 #define ADC_CLP3_CLP3_SHIFT (0U)
794 /*! CLP3 - Calibration Value
795  */
796 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
797 /*! @} */
798 
799 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
800 /*! @{ */
801 #define ADC_CLP2_CLP2_MASK (0xFFU)
802 #define ADC_CLP2_CLP2_SHIFT (0U)
803 /*! CLP2 - Calibration Value
804  */
805 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
806 /*! @} */
807 
808 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
809 /*! @{ */
810 #define ADC_CLP1_CLP1_MASK (0x7FU)
811 #define ADC_CLP1_CLP1_SHIFT (0U)
812 /*! CLP1 - Calibration Value
813  */
814 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
815 /*! @} */
816 
817 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
818 /*! @{ */
819 #define ADC_CLP0_CLP0_MASK (0x3FU)
820 #define ADC_CLP0_CLP0_SHIFT (0U)
821 /*! CLP0 - Calibration Value
822  */
823 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
824 /*! @} */
825 
826 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
827 /*! @{ */
828 #define ADC_CLMD_CLMD_MASK (0x3FU)
829 #define ADC_CLMD_CLMD_SHIFT (0U)
830 /*! CLMD - Calibration Value
831  */
832 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
833 /*! @} */
834 
835 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
836 /*! @{ */
837 #define ADC_CLMS_CLMS_MASK (0x3FU)
838 #define ADC_CLMS_CLMS_SHIFT (0U)
839 /*! CLMS - Calibration Value
840  */
841 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
842 /*! @} */
843 
844 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
845 /*! @{ */
846 #define ADC_CLM4_CLM4_MASK (0x3FFU)
847 #define ADC_CLM4_CLM4_SHIFT (0U)
848 /*! CLM4 - Calibration Value
849  */
850 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
851 /*! @} */
852 
853 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
854 /*! @{ */
855 #define ADC_CLM3_CLM3_MASK (0x1FFU)
856 #define ADC_CLM3_CLM3_SHIFT (0U)
857 /*! CLM3 - Calibration Value
858  */
859 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
860 /*! @} */
861 
862 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
863 /*! @{ */
864 #define ADC_CLM2_CLM2_MASK (0xFFU)
865 #define ADC_CLM2_CLM2_SHIFT (0U)
866 /*! CLM2 - Calibration Value
867  */
868 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
869 /*! @} */
870 
871 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
872 /*! @{ */
873 #define ADC_CLM1_CLM1_MASK (0x7FU)
874 #define ADC_CLM1_CLM1_SHIFT (0U)
875 /*! CLM1 - Calibration Value
876  */
877 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
878 /*! @} */
879 
880 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
881 /*! @{ */
882 #define ADC_CLM0_CLM0_MASK (0x3FU)
883 #define ADC_CLM0_CLM0_SHIFT (0U)
884 /*! CLM0 - Calibration Value
885  */
886 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
887 /*! @} */
888 
889 /*!
890  * @}
891  */ /* end of group ADC_Register_Masks */
892 
893 /* ADC - Peripheral instance base addresses */
894 /** Peripheral ADC0 base address */
895 #define ADC0_BASE (0x40066000u)
896 /** Peripheral ADC0 base pointer */
897 #define ADC0 ((ADC_Type *)ADC0_BASE)
898 /** Array initializer of ADC peripheral base addresses */
899 #define ADC_BASE_ADDRS \
900     {                  \
901         ADC0_BASE      \
902     }
903 /** Array initializer of ADC peripheral base pointers */
904 #define ADC_BASE_PTRS \
905     {                 \
906         ADC0          \
907     }
908 /** Interrupt vectors for the ADC peripheral type */
909 #define ADC_IRQS  \
910     {             \
911         ADC0_IRQn \
912     }
913 
914 /*!
915  * @}
916  */ /* end of group ADC_Peripheral_Access_Layer */
917 
918 /* ----------------------------------------------------------------------------
919    -- CAU Peripheral Access Layer
920    ---------------------------------------------------------------------------- */
921 
922 /*!
923  * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
924  * @{
925  */
926 
927 /** CAU - Register Layout Typedef */
928 typedef struct
929 {
930     __O uint32_t
931         DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
932     uint8_t RESERVED_0[2048];
933     __O uint32_t LDR_CASR;  /**< Status register - Load Register command, offset: 0x840 */
934     __O uint32_t LDR_CAA;   /**< Accumulator register - Load Register command, offset: 0x844 */
935     __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load
936                                Register command, array offset: 0x848, array step: 0x4 */
937     uint8_t RESERVED_1[20];
938     __I uint32_t STR_CASR;  /**< Status register - Store Register command, offset: 0x880 */
939     __I uint32_t STR_CAA;   /**< Accumulator register - Store Register command, offset: 0x884 */
940     __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store
941                                Register command, array offset: 0x888, array step: 0x4 */
942     uint8_t RESERVED_2[20];
943     __O uint32_t ADR_CASR;  /**< Status register - Add Register command, offset: 0x8C0 */
944     __O uint32_t ADR_CAA;   /**< Accumulator register - Add to register command, offset: 0x8C4 */
945     __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add
946                                to register command, array offset: 0x8C8, array step: 0x4 */
947     uint8_t RESERVED_3[20];
948     __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
949     __O uint32_t RADR_CAA;  /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
950     __O uint32_t
951         RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 -
952                        Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
953     uint8_t RESERVED_4[84];
954     __O uint32_t XOR_CASR;  /**< Status register - Exclusive Or command, offset: 0x980 */
955     __O uint32_t XOR_CAA;   /**< Accumulator register - Exclusive Or command, offset: 0x984 */
956     __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 -
957                                Exclusive Or command, array offset: 0x988, array step: 0x4 */
958     uint8_t RESERVED_5[20];
959     __O uint32_t ROTL_CASR;  /**< Status register - Rotate Left command, offset: 0x9C0 */
960     __O uint32_t ROTL_CAA;   /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
961     __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate
962                                 Left command, array offset: 0x9C8, array step: 0x4 */
963     uint8_t RESERVED_6[276];
964     __O uint32_t AESC_CASR;  /**< Status register - AES Column Operation command, offset: 0xB00 */
965     __O uint32_t AESC_CAA;   /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
966     __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8
967                                 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
968     uint8_t RESERVED_7[20];
969     __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
970     __O uint32_t AESIC_CAA;  /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
971     __O uint32_t
972         AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8
973                         - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
974 } CAU_Type;
975 
976 /* ----------------------------------------------------------------------------
977    -- CAU Register Masks
978    ---------------------------------------------------------------------------- */
979 
980 /*!
981  * @addtogroup CAU_Register_Masks CAU Register Masks
982  * @{
983  */
984 
985 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
986 /*! @{ */
987 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
988 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
989 /*! CAU_DIRECT0 - Direct register 0
990  */
991 #define CAU_DIRECT_CAU_DIRECT0(x) \
992     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
993 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
994 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
995 /*! CAU_DIRECT1 - Direct register 1
996  */
997 #define CAU_DIRECT_CAU_DIRECT1(x) \
998     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
999 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
1000 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
1001 /*! CAU_DIRECT2 - Direct register 2
1002  */
1003 #define CAU_DIRECT_CAU_DIRECT2(x) \
1004     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
1005 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
1006 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
1007 /*! CAU_DIRECT3 - Direct register 3
1008  */
1009 #define CAU_DIRECT_CAU_DIRECT3(x) \
1010     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
1011 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
1012 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
1013 /*! CAU_DIRECT4 - Direct register 4
1014  */
1015 #define CAU_DIRECT_CAU_DIRECT4(x) \
1016     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
1017 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
1018 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
1019 /*! CAU_DIRECT5 - Direct register 5
1020  */
1021 #define CAU_DIRECT_CAU_DIRECT5(x) \
1022     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
1023 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
1024 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
1025 /*! CAU_DIRECT6 - Direct register 6
1026  */
1027 #define CAU_DIRECT_CAU_DIRECT6(x) \
1028     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
1029 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
1030 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
1031 /*! CAU_DIRECT7 - Direct register 7
1032  */
1033 #define CAU_DIRECT_CAU_DIRECT7(x) \
1034     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
1035 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
1036 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
1037 /*! CAU_DIRECT8 - Direct register 8
1038  */
1039 #define CAU_DIRECT_CAU_DIRECT8(x) \
1040     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
1041 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
1042 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
1043 /*! CAU_DIRECT9 - Direct register 9
1044  */
1045 #define CAU_DIRECT_CAU_DIRECT9(x) \
1046     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
1047 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
1048 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
1049 /*! CAU_DIRECT10 - Direct register 10
1050  */
1051 #define CAU_DIRECT_CAU_DIRECT10(x) \
1052     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
1053 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
1054 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
1055 /*! CAU_DIRECT11 - Direct register 11
1056  */
1057 #define CAU_DIRECT_CAU_DIRECT11(x) \
1058     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
1059 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
1060 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
1061 /*! CAU_DIRECT12 - Direct register 12
1062  */
1063 #define CAU_DIRECT_CAU_DIRECT12(x) \
1064     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
1065 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
1066 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
1067 /*! CAU_DIRECT13 - Direct register 13
1068  */
1069 #define CAU_DIRECT_CAU_DIRECT13(x) \
1070     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
1071 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
1072 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
1073 /*! CAU_DIRECT14 - Direct register 14
1074  */
1075 #define CAU_DIRECT_CAU_DIRECT14(x) \
1076     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
1077 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
1078 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
1079 /*! CAU_DIRECT15 - Direct register 15
1080  */
1081 #define CAU_DIRECT_CAU_DIRECT15(x) \
1082     (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
1083 /*! @} */
1084 
1085 /* The count of CAU_DIRECT */
1086 #define CAU_DIRECT_COUNT (16U)
1087 
1088 /*! @name LDR_CASR - Status register - Load Register command */
1089 /*! @{ */
1090 #define CAU_LDR_CASR_IC_MASK (0x1U)
1091 #define CAU_LDR_CASR_IC_SHIFT (0U)
1092 /*! IC
1093  *  0b0..No illegal commands issued
1094  *  0b1..Illegal command issued
1095  */
1096 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
1097 #define CAU_LDR_CASR_DPE_MASK (0x2U)
1098 #define CAU_LDR_CASR_DPE_SHIFT (1U)
1099 /*! DPE
1100  *  0b0..No error detected
1101  *  0b1..DES key parity error detected
1102  */
1103 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
1104 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
1105 #define CAU_LDR_CASR_VER_SHIFT (28U)
1106 /*! VER - CAU version
1107  *  0b0001..Initial CAU version
1108  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1109  */
1110 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
1111 /*! @} */
1112 
1113 /*! @name LDR_CAA - Accumulator register - Load Register command */
1114 /*! @{ */
1115 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
1116 #define CAU_LDR_CAA_ACC_SHIFT (0U)
1117 /*! ACC - ACC
1118  */
1119 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
1120 /*! @} */
1121 
1122 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register
1123  * command */
1124 /*! @{ */
1125 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
1126 #define CAU_LDR_CA_CA0_SHIFT (0U)
1127 /*! CA0 - CA0
1128  */
1129 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
1130 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
1131 #define CAU_LDR_CA_CA1_SHIFT (0U)
1132 /*! CA1 - CA1
1133  */
1134 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
1135 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
1136 #define CAU_LDR_CA_CA2_SHIFT (0U)
1137 /*! CA2 - CA2
1138  */
1139 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
1140 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
1141 #define CAU_LDR_CA_CA3_SHIFT (0U)
1142 /*! CA3 - CA3
1143  */
1144 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
1145 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
1146 #define CAU_LDR_CA_CA4_SHIFT (0U)
1147 /*! CA4 - CA4
1148  */
1149 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
1150 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
1151 #define CAU_LDR_CA_CA5_SHIFT (0U)
1152 /*! CA5 - CA5
1153  */
1154 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
1155 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
1156 #define CAU_LDR_CA_CA6_SHIFT (0U)
1157 /*! CA6 - CA6
1158  */
1159 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
1160 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
1161 #define CAU_LDR_CA_CA7_SHIFT (0U)
1162 /*! CA7 - CA7
1163  */
1164 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
1165 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
1166 #define CAU_LDR_CA_CA8_SHIFT (0U)
1167 /*! CA8 - CA8
1168  */
1169 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
1170 /*! @} */
1171 
1172 /* The count of CAU_LDR_CA */
1173 #define CAU_LDR_CA_COUNT (9U)
1174 
1175 /*! @name STR_CASR - Status register - Store Register command */
1176 /*! @{ */
1177 #define CAU_STR_CASR_IC_MASK (0x1U)
1178 #define CAU_STR_CASR_IC_SHIFT (0U)
1179 /*! IC
1180  *  0b0..No illegal commands issued
1181  *  0b1..Illegal command issued
1182  */
1183 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
1184 #define CAU_STR_CASR_DPE_MASK (0x2U)
1185 #define CAU_STR_CASR_DPE_SHIFT (1U)
1186 /*! DPE
1187  *  0b0..No error detected
1188  *  0b1..DES key parity error detected
1189  */
1190 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
1191 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
1192 #define CAU_STR_CASR_VER_SHIFT (28U)
1193 /*! VER - CAU version
1194  *  0b0001..Initial CAU version
1195  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1196  */
1197 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
1198 /*! @} */
1199 
1200 /*! @name STR_CAA - Accumulator register - Store Register command */
1201 /*! @{ */
1202 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
1203 #define CAU_STR_CAA_ACC_SHIFT (0U)
1204 /*! ACC - ACC
1205  */
1206 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
1207 /*! @} */
1208 
1209 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register
1210  * command */
1211 /*! @{ */
1212 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
1213 #define CAU_STR_CA_CA0_SHIFT (0U)
1214 /*! CA0 - CA0
1215  */
1216 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
1217 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
1218 #define CAU_STR_CA_CA1_SHIFT (0U)
1219 /*! CA1 - CA1
1220  */
1221 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
1222 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
1223 #define CAU_STR_CA_CA2_SHIFT (0U)
1224 /*! CA2 - CA2
1225  */
1226 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
1227 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
1228 #define CAU_STR_CA_CA3_SHIFT (0U)
1229 /*! CA3 - CA3
1230  */
1231 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
1232 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
1233 #define CAU_STR_CA_CA4_SHIFT (0U)
1234 /*! CA4 - CA4
1235  */
1236 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
1237 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
1238 #define CAU_STR_CA_CA5_SHIFT (0U)
1239 /*! CA5 - CA5
1240  */
1241 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
1242 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
1243 #define CAU_STR_CA_CA6_SHIFT (0U)
1244 /*! CA6 - CA6
1245  */
1246 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
1247 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
1248 #define CAU_STR_CA_CA7_SHIFT (0U)
1249 /*! CA7 - CA7
1250  */
1251 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
1252 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
1253 #define CAU_STR_CA_CA8_SHIFT (0U)
1254 /*! CA8 - CA8
1255  */
1256 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
1257 /*! @} */
1258 
1259 /* The count of CAU_STR_CA */
1260 #define CAU_STR_CA_COUNT (9U)
1261 
1262 /*! @name ADR_CASR - Status register - Add Register command */
1263 /*! @{ */
1264 #define CAU_ADR_CASR_IC_MASK (0x1U)
1265 #define CAU_ADR_CASR_IC_SHIFT (0U)
1266 /*! IC
1267  *  0b0..No illegal commands issued
1268  *  0b1..Illegal command issued
1269  */
1270 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
1271 #define CAU_ADR_CASR_DPE_MASK (0x2U)
1272 #define CAU_ADR_CASR_DPE_SHIFT (1U)
1273 /*! DPE
1274  *  0b0..No error detected
1275  *  0b1..DES key parity error detected
1276  */
1277 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
1278 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
1279 #define CAU_ADR_CASR_VER_SHIFT (28U)
1280 /*! VER - CAU version
1281  *  0b0001..Initial CAU version
1282  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1283  */
1284 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
1285 /*! @} */
1286 
1287 /*! @name ADR_CAA - Accumulator register - Add to register command */
1288 /*! @{ */
1289 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
1290 #define CAU_ADR_CAA_ACC_SHIFT (0U)
1291 /*! ACC - ACC
1292  */
1293 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
1294 /*! @} */
1295 
1296 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register
1297  * command */
1298 /*! @{ */
1299 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
1300 #define CAU_ADR_CA_CA0_SHIFT (0U)
1301 /*! CA0 - CA0
1302  */
1303 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
1304 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
1305 #define CAU_ADR_CA_CA1_SHIFT (0U)
1306 /*! CA1 - CA1
1307  */
1308 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
1309 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
1310 #define CAU_ADR_CA_CA2_SHIFT (0U)
1311 /*! CA2 - CA2
1312  */
1313 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
1314 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
1315 #define CAU_ADR_CA_CA3_SHIFT (0U)
1316 /*! CA3 - CA3
1317  */
1318 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
1319 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
1320 #define CAU_ADR_CA_CA4_SHIFT (0U)
1321 /*! CA4 - CA4
1322  */
1323 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
1324 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
1325 #define CAU_ADR_CA_CA5_SHIFT (0U)
1326 /*! CA5 - CA5
1327  */
1328 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
1329 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
1330 #define CAU_ADR_CA_CA6_SHIFT (0U)
1331 /*! CA6 - CA6
1332  */
1333 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
1334 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
1335 #define CAU_ADR_CA_CA7_SHIFT (0U)
1336 /*! CA7 - CA7
1337  */
1338 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
1339 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
1340 #define CAU_ADR_CA_CA8_SHIFT (0U)
1341 /*! CA8 - CA8
1342  */
1343 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
1344 /*! @} */
1345 
1346 /* The count of CAU_ADR_CA */
1347 #define CAU_ADR_CA_COUNT (9U)
1348 
1349 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
1350 /*! @{ */
1351 #define CAU_RADR_CASR_IC_MASK (0x1U)
1352 #define CAU_RADR_CASR_IC_SHIFT (0U)
1353 /*! IC
1354  *  0b0..No illegal commands issued
1355  *  0b1..Illegal command issued
1356  */
1357 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
1358 #define CAU_RADR_CASR_DPE_MASK (0x2U)
1359 #define CAU_RADR_CASR_DPE_SHIFT (1U)
1360 /*! DPE
1361  *  0b0..No error detected
1362  *  0b1..DES key parity error detected
1363  */
1364 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
1365 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
1366 #define CAU_RADR_CASR_VER_SHIFT (28U)
1367 /*! VER - CAU version
1368  *  0b0001..Initial CAU version
1369  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1370  */
1371 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
1372 /*! @} */
1373 
1374 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
1375 /*! @{ */
1376 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
1377 #define CAU_RADR_CAA_ACC_SHIFT (0U)
1378 /*! ACC - ACC
1379  */
1380 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
1381 /*! @} */
1382 
1383 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 -
1384  * Reverse and Add to Register command */
1385 /*! @{ */
1386 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
1387 #define CAU_RADR_CA_CA0_SHIFT (0U)
1388 /*! CA0 - CA0
1389  */
1390 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
1391 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
1392 #define CAU_RADR_CA_CA1_SHIFT (0U)
1393 /*! CA1 - CA1
1394  */
1395 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
1396 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
1397 #define CAU_RADR_CA_CA2_SHIFT (0U)
1398 /*! CA2 - CA2
1399  */
1400 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
1401 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
1402 #define CAU_RADR_CA_CA3_SHIFT (0U)
1403 /*! CA3 - CA3
1404  */
1405 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
1406 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
1407 #define CAU_RADR_CA_CA4_SHIFT (0U)
1408 /*! CA4 - CA4
1409  */
1410 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
1411 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
1412 #define CAU_RADR_CA_CA5_SHIFT (0U)
1413 /*! CA5 - CA5
1414  */
1415 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
1416 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
1417 #define CAU_RADR_CA_CA6_SHIFT (0U)
1418 /*! CA6 - CA6
1419  */
1420 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
1421 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
1422 #define CAU_RADR_CA_CA7_SHIFT (0U)
1423 /*! CA7 - CA7
1424  */
1425 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
1426 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
1427 #define CAU_RADR_CA_CA8_SHIFT (0U)
1428 /*! CA8 - CA8
1429  */
1430 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
1431 /*! @} */
1432 
1433 /* The count of CAU_RADR_CA */
1434 #define CAU_RADR_CA_COUNT (9U)
1435 
1436 /*! @name XOR_CASR - Status register - Exclusive Or command */
1437 /*! @{ */
1438 #define CAU_XOR_CASR_IC_MASK (0x1U)
1439 #define CAU_XOR_CASR_IC_SHIFT (0U)
1440 /*! IC
1441  *  0b0..No illegal commands issued
1442  *  0b1..Illegal command issued
1443  */
1444 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
1445 #define CAU_XOR_CASR_DPE_MASK (0x2U)
1446 #define CAU_XOR_CASR_DPE_SHIFT (1U)
1447 /*! DPE
1448  *  0b0..No error detected
1449  *  0b1..DES key parity error detected
1450  */
1451 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
1452 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
1453 #define CAU_XOR_CASR_VER_SHIFT (28U)
1454 /*! VER - CAU version
1455  *  0b0001..Initial CAU version
1456  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1457  */
1458 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
1459 /*! @} */
1460 
1461 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
1462 /*! @{ */
1463 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
1464 #define CAU_XOR_CAA_ACC_SHIFT (0U)
1465 /*! ACC - ACC
1466  */
1467 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
1468 /*! @} */
1469 
1470 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command
1471  */
1472 /*! @{ */
1473 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
1474 #define CAU_XOR_CA_CA0_SHIFT (0U)
1475 /*! CA0 - CA0
1476  */
1477 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
1478 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
1479 #define CAU_XOR_CA_CA1_SHIFT (0U)
1480 /*! CA1 - CA1
1481  */
1482 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
1483 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
1484 #define CAU_XOR_CA_CA2_SHIFT (0U)
1485 /*! CA2 - CA2
1486  */
1487 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
1488 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
1489 #define CAU_XOR_CA_CA3_SHIFT (0U)
1490 /*! CA3 - CA3
1491  */
1492 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
1493 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
1494 #define CAU_XOR_CA_CA4_SHIFT (0U)
1495 /*! CA4 - CA4
1496  */
1497 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
1498 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
1499 #define CAU_XOR_CA_CA5_SHIFT (0U)
1500 /*! CA5 - CA5
1501  */
1502 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
1503 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
1504 #define CAU_XOR_CA_CA6_SHIFT (0U)
1505 /*! CA6 - CA6
1506  */
1507 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
1508 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
1509 #define CAU_XOR_CA_CA7_SHIFT (0U)
1510 /*! CA7 - CA7
1511  */
1512 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
1513 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
1514 #define CAU_XOR_CA_CA8_SHIFT (0U)
1515 /*! CA8 - CA8
1516  */
1517 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
1518 /*! @} */
1519 
1520 /* The count of CAU_XOR_CA */
1521 #define CAU_XOR_CA_COUNT (9U)
1522 
1523 /*! @name ROTL_CASR - Status register - Rotate Left command */
1524 /*! @{ */
1525 #define CAU_ROTL_CASR_IC_MASK (0x1U)
1526 #define CAU_ROTL_CASR_IC_SHIFT (0U)
1527 /*! IC
1528  *  0b0..No illegal commands issued
1529  *  0b1..Illegal command issued
1530  */
1531 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
1532 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
1533 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
1534 /*! DPE
1535  *  0b0..No error detected
1536  *  0b1..DES key parity error detected
1537  */
1538 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
1539 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
1540 #define CAU_ROTL_CASR_VER_SHIFT (28U)
1541 /*! VER - CAU version
1542  *  0b0001..Initial CAU version
1543  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1544  */
1545 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
1546 /*! @} */
1547 
1548 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
1549 /*! @{ */
1550 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
1551 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
1552 /*! ACC - ACC
1553  */
1554 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
1555 /*! @} */
1556 
1557 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command
1558  */
1559 /*! @{ */
1560 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
1561 #define CAU_ROTL_CA_CA0_SHIFT (0U)
1562 /*! CA0 - CA0
1563  */
1564 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
1565 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
1566 #define CAU_ROTL_CA_CA1_SHIFT (0U)
1567 /*! CA1 - CA1
1568  */
1569 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
1570 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
1571 #define CAU_ROTL_CA_CA2_SHIFT (0U)
1572 /*! CA2 - CA2
1573  */
1574 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
1575 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
1576 #define CAU_ROTL_CA_CA3_SHIFT (0U)
1577 /*! CA3 - CA3
1578  */
1579 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
1580 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
1581 #define CAU_ROTL_CA_CA4_SHIFT (0U)
1582 /*! CA4 - CA4
1583  */
1584 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
1585 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
1586 #define CAU_ROTL_CA_CA5_SHIFT (0U)
1587 /*! CA5 - CA5
1588  */
1589 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
1590 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
1591 #define CAU_ROTL_CA_CA6_SHIFT (0U)
1592 /*! CA6 - CA6
1593  */
1594 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
1595 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
1596 #define CAU_ROTL_CA_CA7_SHIFT (0U)
1597 /*! CA7 - CA7
1598  */
1599 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
1600 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
1601 #define CAU_ROTL_CA_CA8_SHIFT (0U)
1602 /*! CA8 - CA8
1603  */
1604 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
1605 /*! @} */
1606 
1607 /* The count of CAU_ROTL_CA */
1608 #define CAU_ROTL_CA_COUNT (9U)
1609 
1610 /*! @name AESC_CASR - Status register - AES Column Operation command */
1611 /*! @{ */
1612 #define CAU_AESC_CASR_IC_MASK (0x1U)
1613 #define CAU_AESC_CASR_IC_SHIFT (0U)
1614 /*! IC
1615  *  0b0..No illegal commands issued
1616  *  0b1..Illegal command issued
1617  */
1618 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
1619 #define CAU_AESC_CASR_DPE_MASK (0x2U)
1620 #define CAU_AESC_CASR_DPE_SHIFT (1U)
1621 /*! DPE
1622  *  0b0..No error detected
1623  *  0b1..DES key parity error detected
1624  */
1625 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
1626 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
1627 #define CAU_AESC_CASR_VER_SHIFT (28U)
1628 /*! VER - CAU version
1629  *  0b0001..Initial CAU version
1630  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1631  */
1632 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
1633 /*! @} */
1634 
1635 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
1636 /*! @{ */
1637 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
1638 #define CAU_AESC_CAA_ACC_SHIFT (0U)
1639 /*! ACC - ACC
1640  */
1641 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
1642 /*! @} */
1643 
1644 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column
1645  * Operation command */
1646 /*! @{ */
1647 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
1648 #define CAU_AESC_CA_CA0_SHIFT (0U)
1649 /*! CA0 - CA0
1650  */
1651 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
1652 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
1653 #define CAU_AESC_CA_CA1_SHIFT (0U)
1654 /*! CA1 - CA1
1655  */
1656 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
1657 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
1658 #define CAU_AESC_CA_CA2_SHIFT (0U)
1659 /*! CA2 - CA2
1660  */
1661 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
1662 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
1663 #define CAU_AESC_CA_CA3_SHIFT (0U)
1664 /*! CA3 - CA3
1665  */
1666 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
1667 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
1668 #define CAU_AESC_CA_CA4_SHIFT (0U)
1669 /*! CA4 - CA4
1670  */
1671 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
1672 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
1673 #define CAU_AESC_CA_CA5_SHIFT (0U)
1674 /*! CA5 - CA5
1675  */
1676 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
1677 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
1678 #define CAU_AESC_CA_CA6_SHIFT (0U)
1679 /*! CA6 - CA6
1680  */
1681 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
1682 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
1683 #define CAU_AESC_CA_CA7_SHIFT (0U)
1684 /*! CA7 - CA7
1685  */
1686 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
1687 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
1688 #define CAU_AESC_CA_CA8_SHIFT (0U)
1689 /*! CA8 - CA8
1690  */
1691 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
1692 /*! @} */
1693 
1694 /* The count of CAU_AESC_CA */
1695 #define CAU_AESC_CA_COUNT (9U)
1696 
1697 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
1698 /*! @{ */
1699 #define CAU_AESIC_CASR_IC_MASK (0x1U)
1700 #define CAU_AESIC_CASR_IC_SHIFT (0U)
1701 /*! IC
1702  *  0b0..No illegal commands issued
1703  *  0b1..Illegal command issued
1704  */
1705 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
1706 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
1707 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
1708 /*! DPE
1709  *  0b0..No error detected
1710  *  0b1..DES key parity error detected
1711  */
1712 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
1713 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
1714 #define CAU_AESIC_CASR_VER_SHIFT (28U)
1715 /*! VER - CAU version
1716  *  0b0001..Initial CAU version
1717  *  0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1718  */
1719 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
1720 /*! @} */
1721 
1722 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
1723 /*! @{ */
1724 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
1725 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
1726 /*! ACC - ACC
1727  */
1728 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
1729 /*! @} */
1730 
1731 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES
1732  * Inverse Column Operation command */
1733 /*! @{ */
1734 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
1735 #define CAU_AESIC_CA_CA0_SHIFT (0U)
1736 /*! CA0 - CA0
1737  */
1738 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
1739 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
1740 #define CAU_AESIC_CA_CA1_SHIFT (0U)
1741 /*! CA1 - CA1
1742  */
1743 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
1744 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
1745 #define CAU_AESIC_CA_CA2_SHIFT (0U)
1746 /*! CA2 - CA2
1747  */
1748 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
1749 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
1750 #define CAU_AESIC_CA_CA3_SHIFT (0U)
1751 /*! CA3 - CA3
1752  */
1753 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
1754 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
1755 #define CAU_AESIC_CA_CA4_SHIFT (0U)
1756 /*! CA4 - CA4
1757  */
1758 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
1759 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
1760 #define CAU_AESIC_CA_CA5_SHIFT (0U)
1761 /*! CA5 - CA5
1762  */
1763 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
1764 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
1765 #define CAU_AESIC_CA_CA6_SHIFT (0U)
1766 /*! CA6 - CA6
1767  */
1768 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
1769 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
1770 #define CAU_AESIC_CA_CA7_SHIFT (0U)
1771 /*! CA7 - CA7
1772  */
1773 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
1774 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
1775 #define CAU_AESIC_CA_CA8_SHIFT (0U)
1776 /*! CA8 - CA8
1777  */
1778 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
1779 /*! @} */
1780 
1781 /* The count of CAU_AESIC_CA */
1782 #define CAU_AESIC_CA_COUNT (9U)
1783 
1784 /*!
1785  * @}
1786  */ /* end of group CAU_Register_Masks */
1787 
1788 /* CAU - Peripheral instance base addresses */
1789 /** Peripheral CAU0 base address */
1790 #define CAU0_BASE (0xF0005000u)
1791 /** Peripheral CAU0 base pointer */
1792 #define CAU0 ((CAU_Type *)CAU0_BASE)
1793 /** Array initializer of CAU peripheral base addresses */
1794 #define CAU_BASE_ADDRS \
1795     {                  \
1796         CAU0_BASE      \
1797     }
1798 /** Array initializer of CAU peripheral base pointers */
1799 #define CAU_BASE_PTRS \
1800     {                 \
1801         CAU0          \
1802     }
1803 
1804 /*!
1805  * @}
1806  */ /* end of group CAU_Peripheral_Access_Layer */
1807 
1808 /* ----------------------------------------------------------------------------
1809    -- CMP Peripheral Access Layer
1810    ---------------------------------------------------------------------------- */
1811 
1812 /*!
1813  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1814  * @{
1815  */
1816 
1817 /** CMP - Register Layout Typedef */
1818 typedef struct
1819 {
1820     __IO uint8_t CR0;   /**< CMP Control Register 0, offset: 0x0 */
1821     __IO uint8_t CR1;   /**< CMP Control Register 1, offset: 0x1 */
1822     __IO uint8_t FPR;   /**< CMP Filter Period Register, offset: 0x2 */
1823     __IO uint8_t SCR;   /**< CMP Status and Control Register, offset: 0x3 */
1824     __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
1825     __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
1826 } CMP_Type;
1827 
1828 /* ----------------------------------------------------------------------------
1829    -- CMP Register Masks
1830    ---------------------------------------------------------------------------- */
1831 
1832 /*!
1833  * @addtogroup CMP_Register_Masks CMP Register Masks
1834  * @{
1835  */
1836 
1837 /*! @name CR0 - CMP Control Register 0 */
1838 /*! @{ */
1839 #define CMP_CR0_HYSTCTR_MASK (0x3U)
1840 #define CMP_CR0_HYSTCTR_SHIFT (0U)
1841 /*! HYSTCTR - Comparator hard block hysteresis control
1842  *  0b00..Level 0
1843  *  0b01..Level 1
1844  *  0b10..Level 2
1845  *  0b11..Level 3
1846  */
1847 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
1848 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
1849 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
1850 /*! FILTER_CNT - Filter Sample Count
1851  *  0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If
1852  * SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive
1853  * samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5
1854  * consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.
1855  */
1856 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
1857 /*! @} */
1858 
1859 /*! @name CR1 - CMP Control Register 1 */
1860 /*! @{ */
1861 #define CMP_CR1_EN_MASK (0x1U)
1862 #define CMP_CR1_EN_SHIFT (0U)
1863 /*! EN - Comparator Module Enable
1864  *  0b0..Analog Comparator is disabled.
1865  *  0b1..Analog Comparator is enabled.
1866  */
1867 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
1868 #define CMP_CR1_OPE_MASK (0x2U)
1869 #define CMP_CR1_OPE_SHIFT (1U)
1870 /*! OPE - Comparator Output Pin Enable
1871  *  0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has
1872  * no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on
1873  * the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has
1874  * no effect.
1875  */
1876 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
1877 #define CMP_CR1_COS_MASK (0x4U)
1878 #define CMP_CR1_COS_SHIFT (2U)
1879 /*! COS - Comparator Output Select
1880  *  0b0..Set the filtered comparator output (CMPO) to equal COUT.
1881  *  0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
1882  */
1883 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
1884 #define CMP_CR1_INV_MASK (0x8U)
1885 #define CMP_CR1_INV_SHIFT (3U)
1886 /*! INV - Comparator INVERT
1887  *  0b0..Does not invert the comparator output.
1888  *  0b1..Inverts the comparator output.
1889  */
1890 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
1891 #define CMP_CR1_PMODE_MASK (0x10U)
1892 #define CMP_CR1_PMODE_SHIFT (4U)
1893 /*! PMODE - Power Mode Select
1894  *  0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower
1895  * current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation
1896  * delay and higher current consumption.
1897  */
1898 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
1899 #define CMP_CR1_TRIGM_MASK (0x20U)
1900 #define CMP_CR1_TRIGM_SHIFT (5U)
1901 /*! TRIGM - Trigger Mode Enable
1902  *  0b0..Trigger mode is disabled.
1903  *  0b1..Trigger mode is enabled.
1904  */
1905 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
1906 #define CMP_CR1_WE_MASK (0x40U)
1907 #define CMP_CR1_WE_SHIFT (6U)
1908 /*! WE - Windowing Enable
1909  *  0b0..Windowing mode is not selected.
1910  *  0b1..Windowing mode is selected.
1911  */
1912 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
1913 #define CMP_CR1_SE_MASK (0x80U)
1914 #define CMP_CR1_SE_SHIFT (7U)
1915 /*! SE - Sample Enable
1916  *  0b0..Sampling mode is not selected.
1917  *  0b1..Sampling mode is selected.
1918  */
1919 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
1920 /*! @} */
1921 
1922 /*! @name FPR - CMP Filter Period Register */
1923 /*! @{ */
1924 #define CMP_FPR_FILT_PER_MASK (0xFFU)
1925 #define CMP_FPR_FILT_PER_SHIFT (0U)
1926 /*! FILT_PER - Filter Sample Period
1927  */
1928 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
1929 /*! @} */
1930 
1931 /*! @name SCR - CMP Status and Control Register */
1932 /*! @{ */
1933 #define CMP_SCR_COUT_MASK (0x1U)
1934 #define CMP_SCR_COUT_SHIFT (0U)
1935 /*! COUT - Analog Comparator Output
1936  */
1937 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
1938 #define CMP_SCR_CFF_MASK (0x2U)
1939 #define CMP_SCR_CFF_SHIFT (1U)
1940 /*! CFF - Analog Comparator Flag Falling
1941  *  0b0..Falling-edge on COUT has not been detected.
1942  *  0b1..Falling-edge on COUT has occurred.
1943  */
1944 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
1945 #define CMP_SCR_CFR_MASK (0x4U)
1946 #define CMP_SCR_CFR_SHIFT (2U)
1947 /*! CFR - Analog Comparator Flag Rising
1948  *  0b0..Rising-edge on COUT has not been detected.
1949  *  0b1..Rising-edge on COUT has occurred.
1950  */
1951 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
1952 #define CMP_SCR_IEF_MASK (0x8U)
1953 #define CMP_SCR_IEF_SHIFT (3U)
1954 /*! IEF - Comparator Interrupt Enable Falling
1955  *  0b0..Interrupt is disabled.
1956  *  0b1..Interrupt is enabled.
1957  */
1958 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
1959 #define CMP_SCR_IER_MASK (0x10U)
1960 #define CMP_SCR_IER_SHIFT (4U)
1961 /*! IER - Comparator Interrupt Enable Rising
1962  *  0b0..Interrupt is disabled.
1963  *  0b1..Interrupt is enabled.
1964  */
1965 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
1966 #define CMP_SCR_DMAEN_MASK (0x40U)
1967 #define CMP_SCR_DMAEN_SHIFT (6U)
1968 /*! DMAEN - DMA Enable Control
1969  *  0b0..DMA is disabled.
1970  *  0b1..DMA is enabled.
1971  */
1972 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
1973 /*! @} */
1974 
1975 /*! @name DACCR - DAC Control Register */
1976 /*! @{ */
1977 #define CMP_DACCR_VOSEL_MASK (0x3FU)
1978 #define CMP_DACCR_VOSEL_SHIFT (0U)
1979 /*! VOSEL - DAC Output Voltage Select
1980  */
1981 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1982 #define CMP_DACCR_VRSEL_MASK (0x40U)
1983 #define CMP_DACCR_VRSEL_SHIFT (6U)
1984 /*! VRSEL - Supply Voltage Reference Source Select
1985  *  0b0..Vin1 is selected as resistor ladder network supply reference.
1986  *  0b1..Vin2 is selected as resistor ladder network supply reference.
1987  */
1988 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
1989 #define CMP_DACCR_DACEN_MASK (0x80U)
1990 #define CMP_DACCR_DACEN_SHIFT (7U)
1991 /*! DACEN - DAC Enable
1992  *  0b0..DAC is disabled.
1993  *  0b1..DAC is enabled.
1994  */
1995 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1996 /*! @} */
1997 
1998 /*! @name MUXCR - MUX Control Register */
1999 /*! @{ */
2000 #define CMP_MUXCR_MSEL_MASK (0x7U)
2001 #define CMP_MUXCR_MSEL_SHIFT (0U)
2002 /*! MSEL - Minus Input Mux Control
2003  *  0b000..IN0
2004  *  0b001..IN1
2005  *  0b010..IN2
2006  *  0b011..IN3
2007  *  0b100..IN4
2008  *  0b101..IN5
2009  *  0b110..IN6
2010  *  0b111..IN7
2011  */
2012 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
2013 #define CMP_MUXCR_PSEL_MASK (0x38U)
2014 #define CMP_MUXCR_PSEL_SHIFT (3U)
2015 /*! PSEL - Plus Input Mux Control
2016  *  0b000..IN0
2017  *  0b001..IN1
2018  *  0b010..IN2
2019  *  0b011..IN3
2020  *  0b100..IN4
2021  *  0b101..IN5
2022  *  0b110..IN6
2023  *  0b111..IN7
2024  */
2025 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
2026 #define CMP_MUXCR_PSTM_MASK (0x80U)
2027 #define CMP_MUXCR_PSTM_SHIFT (7U)
2028 /*! PSTM - Pass Through Mode Enable
2029  *  0b0..Pass Through Mode is disabled.
2030  *  0b1..Pass Through Mode is enabled.
2031  */
2032 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
2033 /*! @} */
2034 
2035 /*!
2036  * @}
2037  */ /* end of group CMP_Register_Masks */
2038 
2039 /* CMP - Peripheral instance base addresses */
2040 /** Peripheral CMP0 base address */
2041 #define CMP0_BASE (0x4006E000u)
2042 /** Peripheral CMP0 base pointer */
2043 #define CMP0 ((CMP_Type *)CMP0_BASE)
2044 /** Peripheral CMP1 base address */
2045 #define CMP1_BASE (0x400EF000u)
2046 /** Peripheral CMP1 base pointer */
2047 #define CMP1 ((CMP_Type *)CMP1_BASE)
2048 /** Array initializer of CMP peripheral base addresses */
2049 #define CMP_BASE_ADDRS       \
2050     {                        \
2051         CMP0_BASE, CMP1_BASE \
2052     }
2053 /** Array initializer of CMP peripheral base pointers */
2054 #define CMP_BASE_PTRS \
2055     {                 \
2056         CMP0, CMP1    \
2057     }
2058 /** Interrupt vectors for the CMP peripheral type */
2059 #define CMP_IRQS             \
2060     {                        \
2061         CMP0_IRQn, CMP1_IRQn \
2062     }
2063 
2064 /*!
2065  * @}
2066  */ /* end of group CMP_Peripheral_Access_Layer */
2067 
2068 /* ----------------------------------------------------------------------------
2069    -- CRC Peripheral Access Layer
2070    ---------------------------------------------------------------------------- */
2071 
2072 /*!
2073  * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2074  * @{
2075  */
2076 
2077 /** CRC - Register Layout Typedef */
2078 typedef struct
2079 {
2080     union
2081     { /* offset: 0x0 */
2082         struct
2083         {                        /* offset: 0x0 */
2084             __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
2085             __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
2086             __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
2087             __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
2088         } ACCESS8BIT;
2089         struct
2090         {                        /* offset: 0x0 */
2091             __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
2092             __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
2093         } ACCESS16BIT;
2094         __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
2095     };
2096     union
2097     { /* offset: 0x4 */
2098         struct
2099         {                         /* offset: 0x4 */
2100             __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
2101             __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
2102             __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
2103             __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
2104         } GPOLY_ACCESS8BIT;
2105         struct
2106         {                         /* offset: 0x4 */
2107             __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
2108             __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
2109         } GPOLY_ACCESS16BIT;
2110         __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
2111     };
2112     union
2113     { /* offset: 0x8 */
2114         struct
2115         { /* offset: 0x8 */
2116             uint8_t RESERVED_0[3];
2117             __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
2118         } CTRL_ACCESS8BIT;
2119         __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
2120     };
2121 } CRC_Type;
2122 
2123 /* ----------------------------------------------------------------------------
2124    -- CRC Register Masks
2125    ---------------------------------------------------------------------------- */
2126 
2127 /*!
2128  * @addtogroup CRC_Register_Masks CRC Register Masks
2129  * @{
2130  */
2131 
2132 /*! @name DATALL - CRC_DATALL register. */
2133 /*! @{ */
2134 #define CRC_DATALL_DATALL_MASK (0xFFU)
2135 #define CRC_DATALL_DATALL_SHIFT (0U)
2136 /*! DATALL - CRCLL stores the first 8 bits of the 32 bit DATA
2137  */
2138 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
2139 /*! @} */
2140 
2141 /*! @name DATALU - CRC_DATALU register. */
2142 /*! @{ */
2143 #define CRC_DATALU_DATALU_MASK (0xFFU)
2144 #define CRC_DATALU_DATALU_SHIFT (0U)
2145 /*! DATALU - DATALL stores the second 8 bits of the 32 bit CRC
2146  */
2147 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
2148 /*! @} */
2149 
2150 /*! @name DATAHL - CRC_DATAHL register. */
2151 /*! @{ */
2152 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
2153 #define CRC_DATAHL_DATAHL_SHIFT (0U)
2154 /*! DATAHL - DATAHL stores the third 8 bits of the 32 bit CRC
2155  */
2156 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
2157 /*! @} */
2158 
2159 /*! @name DATAHU - CRC_DATAHU register. */
2160 /*! @{ */
2161 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
2162 #define CRC_DATAHU_DATAHU_SHIFT (0U)
2163 /*! DATAHU - DATAHU stores the fourth 8 bits of the 32 bit CRC
2164  */
2165 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
2166 /*! @} */
2167 
2168 /*! @name DATAL - CRC_DATAL register. */
2169 /*! @{ */
2170 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
2171 #define CRC_DATAL_DATAL_SHIFT (0U)
2172 /*! DATAL - DATAL stores the lower 16 bits of the 16/32 bit CRC
2173  */
2174 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
2175 /*! @} */
2176 
2177 /*! @name DATAH - CRC_DATAH register. */
2178 /*! @{ */
2179 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
2180 #define CRC_DATAH_DATAH_SHIFT (0U)
2181 /*! DATAH - DATAH stores the high 16 bits of the 16/32 bit CRC
2182  */
2183 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
2184 /*! @} */
2185 
2186 /*! @name DATA - CRC Data register */
2187 /*! @{ */
2188 #define CRC_DATA_LL_MASK (0xFFU)
2189 #define CRC_DATA_LL_SHIFT (0U)
2190 /*! LL - CRC Low Lower Byte
2191  */
2192 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
2193 #define CRC_DATA_LU_MASK (0xFF00U)
2194 #define CRC_DATA_LU_SHIFT (8U)
2195 /*! LU - CRC Low Upper Byte
2196  */
2197 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
2198 #define CRC_DATA_HL_MASK (0xFF0000U)
2199 #define CRC_DATA_HL_SHIFT (16U)
2200 /*! HL - CRC High Lower Byte
2201  */
2202 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
2203 #define CRC_DATA_HU_MASK (0xFF000000U)
2204 #define CRC_DATA_HU_SHIFT (24U)
2205 /*! HU - CRC High Upper Byte
2206  */
2207 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
2208 /*! @} */
2209 
2210 /*! @name GPOLYLL - CRC_GPOLYLL register. */
2211 /*! @{ */
2212 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
2213 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
2214 /*! GPOLYLL - POLYLL stores the first 8 bits of the 32 bit CRC
2215  */
2216 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
2217 /*! @} */
2218 
2219 /*! @name GPOLYLU - CRC_GPOLYLU register. */
2220 /*! @{ */
2221 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
2222 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
2223 /*! GPOLYLU - POLYLL stores the second 8 bits of the 32 bit CRC
2224  */
2225 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
2226 /*! @} */
2227 
2228 /*! @name GPOLYHL - CRC_GPOLYHL register. */
2229 /*! @{ */
2230 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
2231 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
2232 /*! GPOLYHL - POLYHL stores the third 8 bits of the 32 bit CRC
2233  */
2234 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
2235 /*! @} */
2236 
2237 /*! @name GPOLYHU - CRC_GPOLYHU register. */
2238 /*! @{ */
2239 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
2240 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
2241 /*! GPOLYHU - POLYHU stores the fourth 8 bits of the 32 bit CRC
2242  */
2243 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
2244 /*! @} */
2245 
2246 /*! @name GPOLYL - CRC_GPOLYL register. */
2247 /*! @{ */
2248 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
2249 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
2250 /*! GPOLYL - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
2251  */
2252 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
2253 /*! @} */
2254 
2255 /*! @name GPOLYH - CRC_GPOLYH register. */
2256 /*! @{ */
2257 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
2258 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
2259 /*! GPOLYH - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
2260  */
2261 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
2262 /*! @} */
2263 
2264 /*! @name GPOLY - CRC Polynomial register */
2265 /*! @{ */
2266 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
2267 #define CRC_GPOLY_LOW_SHIFT (0U)
2268 /*! LOW - Low Polynominal Half-word
2269  */
2270 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
2271 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
2272 #define CRC_GPOLY_HIGH_SHIFT (16U)
2273 /*! HIGH - High Polynominal Half-word
2274  */
2275 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
2276 /*! @} */
2277 
2278 /*! @name CTRLHU - CRC_CTRLHU register. */
2279 /*! @{ */
2280 #define CRC_CTRLHU_TCRC_MASK (0x1U)
2281 #define CRC_CTRLHU_TCRC_SHIFT (0U)
2282 /*! TCRC
2283  *  0b0..16-bit CRC protocol.
2284  *  0b1..32-bit CRC protocol.
2285  */
2286 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
2287 #define CRC_CTRLHU_WAS_MASK (0x2U)
2288 #define CRC_CTRLHU_WAS_SHIFT (1U)
2289 /*! WAS
2290  *  0b0..Writes to CRC data register are data values.
2291  *  0b1..Writes to CRC data reguster are seed values.
2292  */
2293 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
2294 #define CRC_CTRLHU_FXOR_MASK (0x4U)
2295 #define CRC_CTRLHU_FXOR_SHIFT (2U)
2296 /*! FXOR
2297  *  0b0..No XOR on reading.
2298  *  0b1..Invert or complement the read value of CRC data register.
2299  */
2300 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
2301 #define CRC_CTRLHU_TOTR_MASK (0x30U)
2302 #define CRC_CTRLHU_TOTR_SHIFT (4U)
2303 /*! TOTR
2304  *  0b00..No Transposition.
2305  *  0b01..Bits in bytes are transposed, bytes are not transposed.
2306  *  0b10..Both bits in bytes and bytes are transposed.
2307  *  0b11..Only bytes are transposed; no bits in a byte are transposed.
2308  */
2309 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
2310 #define CRC_CTRLHU_TOT_MASK (0xC0U)
2311 #define CRC_CTRLHU_TOT_SHIFT (6U)
2312 /*! TOT
2313  *  0b00..No Transposition.
2314  *  0b01..Bits in bytes are transposed, bytes are not transposed.
2315  *  0b10..Both bits in bytes and bytes are transposed.
2316  *  0b11..Only bytes are transposed; no bits in a byte are transposed.
2317  */
2318 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
2319 /*! @} */
2320 
2321 /*! @name CTRL - CRC Control register */
2322 /*! @{ */
2323 #define CRC_CTRL_TCRC_MASK (0x1000000U)
2324 #define CRC_CTRL_TCRC_SHIFT (24U)
2325 /*! TCRC
2326  *  0b0..16-bit CRC protocol.
2327  *  0b1..32-bit CRC protocol.
2328  */
2329 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
2330 #define CRC_CTRL_WAS_MASK (0x2000000U)
2331 #define CRC_CTRL_WAS_SHIFT (25U)
2332 /*! WAS - Write CRC Data Register As Seed
2333  *  0b0..Writes to the CRC data register are data values.
2334  *  0b1..Writes to the CRC data register are seed values.
2335  */
2336 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
2337 #define CRC_CTRL_FXOR_MASK (0x4000000U)
2338 #define CRC_CTRL_FXOR_SHIFT (26U)
2339 /*! FXOR - Complement Read Of CRC Data Register
2340  *  0b0..No XOR on reading.
2341  *  0b1..Invert or complement the read value of the CRC Data register.
2342  */
2343 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
2344 #define CRC_CTRL_TOTR_MASK (0x30000000U)
2345 #define CRC_CTRL_TOTR_SHIFT (28U)
2346 /*! TOTR - Type Of Transpose For Read
2347  *  0b00..No transposition.
2348  *  0b01..Bits in bytes are transposed; bytes are not transposed.
2349  *  0b10..Both bits in bytes and bytes are transposed.
2350  *  0b11..Only bytes are transposed; no bits in a byte are transposed.
2351  */
2352 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
2353 #define CRC_CTRL_TOT_MASK (0xC0000000U)
2354 #define CRC_CTRL_TOT_SHIFT (30U)
2355 /*! TOT - Type Of Transpose For Writes
2356  *  0b00..No transposition.
2357  *  0b01..Bits in bytes are transposed; bytes are not transposed.
2358  *  0b10..Both bits in bytes and bytes are transposed.
2359  *  0b11..Only bytes are transposed; no bits in a byte are transposed.
2360  */
2361 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
2362 /*! @} */
2363 
2364 /*!
2365  * @}
2366  */ /* end of group CRC_Register_Masks */
2367 
2368 /* CRC - Peripheral instance base addresses */
2369 /** Peripheral CRC base address */
2370 #define CRC_BASE (0x40078000u)
2371 /** Peripheral CRC base pointer */
2372 #define CRC0 ((CRC_Type *)CRC_BASE)
2373 /** Array initializer of CRC peripheral base addresses */
2374 #define CRC_BASE_ADDRS \
2375     {                  \
2376         CRC_BASE       \
2377     }
2378 /** Array initializer of CRC peripheral base pointers */
2379 #define CRC_BASE_PTRS \
2380     {                 \
2381         CRC0          \
2382     }
2383 
2384 /*!
2385  * @}
2386  */ /* end of group CRC_Peripheral_Access_Layer */
2387 
2388 /* ----------------------------------------------------------------------------
2389    -- DAC Peripheral Access Layer
2390    ---------------------------------------------------------------------------- */
2391 
2392 /*!
2393  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2394  * @{
2395  */
2396 
2397 /** DAC - Register Layout Typedef */
2398 typedef struct
2399 {
2400     struct
2401     {                      /* offset: 0x0, array step: 0x2 */
2402         __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
2403         __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
2404     } DAT[16];
2405     __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
2406     __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
2407     __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
2408     __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
2409 } DAC_Type;
2410 
2411 /* ----------------------------------------------------------------------------
2412    -- DAC Register Masks
2413    ---------------------------------------------------------------------------- */
2414 
2415 /*!
2416  * @addtogroup DAC_Register_Masks DAC Register Masks
2417  * @{
2418  */
2419 
2420 /*! @name DATL - DAC Data Low Register */
2421 /*! @{ */
2422 #define DAC_DATL_DATA0_MASK (0xFFU)
2423 #define DAC_DATL_DATA0_SHIFT (0U)
2424 /*! DATA0 - DATA0
2425  */
2426 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
2427 /*! @} */
2428 
2429 /* The count of DAC_DATL */
2430 #define DAC_DATL_COUNT (16U)
2431 
2432 /*! @name DATH - DAC Data High Register */
2433 /*! @{ */
2434 #define DAC_DATH_DATA1_MASK (0xFU)
2435 #define DAC_DATH_DATA1_SHIFT (0U)
2436 /*! DATA1 - DATA1
2437  */
2438 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
2439 /*! @} */
2440 
2441 /* The count of DAC_DATH */
2442 #define DAC_DATH_COUNT (16U)
2443 
2444 /*! @name SR - DAC Status Register */
2445 /*! @{ */
2446 #define DAC_SR_DACBFRPBF_MASK (0x1U)
2447 #define DAC_SR_DACBFRPBF_SHIFT (0U)
2448 /*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
2449  *  0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
2450  *  0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
2451  */
2452 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
2453 #define DAC_SR_DACBFRPTF_MASK (0x2U)
2454 #define DAC_SR_DACBFRPTF_SHIFT (1U)
2455 /*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
2456  *  0b0..The DAC buffer read pointer is not zero.
2457  *  0b1..The DAC buffer read pointer is zero.
2458  */
2459 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
2460 #define DAC_SR_DACBFWMF_MASK (0x4U)
2461 #define DAC_SR_DACBFWMF_SHIFT (2U)
2462 /*! DACBFWMF - DAC Buffer Watermark Flag
2463  *  0b0..The DAC buffer read pointer has not reached the watermark level.
2464  *  0b1..The DAC buffer read pointer has reached the watermark level.
2465  */
2466 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
2467 /*! @} */
2468 
2469 /*! @name C0 - DAC Control Register */
2470 /*! @{ */
2471 #define DAC_C0_DACBBIEN_MASK (0x1U)
2472 #define DAC_C0_DACBBIEN_SHIFT (0U)
2473 /*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
2474  *  0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
2475  *  0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
2476  */
2477 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
2478 #define DAC_C0_DACBTIEN_MASK (0x2U)
2479 #define DAC_C0_DACBTIEN_SHIFT (1U)
2480 /*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
2481  *  0b0..The DAC buffer read pointer top flag interrupt is disabled.
2482  *  0b1..The DAC buffer read pointer top flag interrupt is enabled.
2483  */
2484 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
2485 #define DAC_C0_DACBWIEN_MASK (0x4U)
2486 #define DAC_C0_DACBWIEN_SHIFT (2U)
2487 /*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
2488  *  0b0..The DAC buffer watermark interrupt is disabled.
2489  *  0b1..The DAC buffer watermark interrupt is enabled.
2490  */
2491 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
2492 #define DAC_C0_LPEN_MASK (0x8U)
2493 #define DAC_C0_LPEN_SHIFT (3U)
2494 /*! LPEN - DAC Low Power Control
2495  *  0b0..High-Power mode
2496  *  0b1..Low-Power mode
2497  */
2498 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
2499 #define DAC_C0_DACSWTRG_MASK (0x10U)
2500 #define DAC_C0_DACSWTRG_SHIFT (4U)
2501 /*! DACSWTRG - DAC Software Trigger
2502  *  0b0..The DAC soft trigger is not valid.
2503  *  0b1..The DAC soft trigger is valid.
2504  */
2505 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
2506 #define DAC_C0_DACTRGSEL_MASK (0x20U)
2507 #define DAC_C0_DACTRGSEL_SHIFT (5U)
2508 /*! DACTRGSEL - DAC Trigger Select
2509  *  0b0..The DAC hardware trigger is selected.
2510  *  0b1..The DAC software trigger is selected.
2511  */
2512 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
2513 #define DAC_C0_DACRFS_MASK (0x40U)
2514 #define DAC_C0_DACRFS_SHIFT (6U)
2515 /*! DACRFS - DAC Reference Select
2516  *  0b0..The DAC selects DACREF_1 as the reference voltage.
2517  *  0b1..The DAC selects DACREF_2 as the reference voltage.
2518  */
2519 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
2520 #define DAC_C0_DACEN_MASK (0x80U)
2521 #define DAC_C0_DACEN_SHIFT (7U)
2522 /*! DACEN - DAC Enable
2523  *  0b0..The DAC system is disabled.
2524  *  0b1..The DAC system is enabled.
2525  */
2526 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
2527 /*! @} */
2528 
2529 /*! @name C1 - DAC Control Register 1 */
2530 /*! @{ */
2531 #define DAC_C1_DACBFEN_MASK (0x1U)
2532 #define DAC_C1_DACBFEN_SHIFT (0U)
2533 /*! DACBFEN - DAC Buffer Enable
2534  *  0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
2535  *  0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means
2536  *       converted data can be from any word of the buffer.
2537  */
2538 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
2539 #define DAC_C1_DACBFMD_MASK (0x6U)
2540 #define DAC_C1_DACBFMD_SHIFT (1U)
2541 /*! DACBFMD - DAC Buffer Work Mode Select
2542  *  0b00..Normal mode
2543  *  0b01..Swing mode
2544  *  0b10..One-Time Scan mode
2545  *  0b11..Reserved
2546  */
2547 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
2548 #define DAC_C1_DACBFWM_MASK (0x18U)
2549 #define DAC_C1_DACBFWM_SHIFT (3U)
2550 /*! DACBFWM - DAC Buffer Watermark Select
2551  *  0b00..1 word
2552  *  0b01..2 words
2553  *  0b10..3 words
2554  *  0b11..4 words
2555  */
2556 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
2557 #define DAC_C1_DMAEN_MASK (0x80U)
2558 #define DAC_C1_DMAEN_SHIFT (7U)
2559 /*! DMAEN - DMA Enable Select
2560  *  0b0..DMA is disabled.
2561  *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
2562  *       interrupts will not be presented on this module at the same time.
2563  */
2564 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
2565 /*! @} */
2566 
2567 /*! @name C2 - DAC Control Register 2 */
2568 /*! @{ */
2569 #define DAC_C2_DACBFUP_MASK (0xFU)
2570 #define DAC_C2_DACBFUP_SHIFT (0U)
2571 /*! DACBFUP - DAC Buffer Upper Limit
2572  */
2573 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
2574 #define DAC_C2_DACBFRP_MASK (0xF0U)
2575 #define DAC_C2_DACBFRP_SHIFT (4U)
2576 /*! DACBFRP - DAC Buffer Read Pointer
2577  */
2578 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
2579 /*! @} */
2580 
2581 /*!
2582  * @}
2583  */ /* end of group DAC_Register_Masks */
2584 
2585 /* DAC - Peripheral instance base addresses */
2586 /** Peripheral DAC0 base address */
2587 #define DAC0_BASE (0x4006A000u)
2588 /** Peripheral DAC0 base pointer */
2589 #define DAC0 ((DAC_Type *)DAC0_BASE)
2590 /** Array initializer of DAC peripheral base addresses */
2591 #define DAC_BASE_ADDRS \
2592     {                  \
2593         DAC0_BASE      \
2594     }
2595 /** Array initializer of DAC peripheral base pointers */
2596 #define DAC_BASE_PTRS \
2597     {                 \
2598         DAC0          \
2599     }
2600 /** Interrupt vectors for the DAC peripheral type */
2601 #define DAC_IRQS  \
2602     {             \
2603         DAC0_IRQn \
2604     }
2605 
2606 /*!
2607  * @}
2608  */ /* end of group DAC_Peripheral_Access_Layer */
2609 
2610 /* ----------------------------------------------------------------------------
2611    -- DMA Peripheral Access Layer
2612    ---------------------------------------------------------------------------- */
2613 
2614 /*!
2615  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2616  * @{
2617  */
2618 
2619 /** DMA - Register Layout Typedef */
2620 typedef struct
2621 {
2622     __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2623     __I uint32_t ES;  /**< Error Status Register, offset: 0x4 */
2624     uint8_t RESERVED_0[4];
2625     __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2626     uint8_t RESERVED_1[4];
2627     __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2628     __O uint8_t CEEI;  /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2629     __O uint8_t SEEI;  /**< Set Enable Error Interrupt Register, offset: 0x19 */
2630     __O uint8_t CERQ;  /**< Clear Enable Request Register, offset: 0x1A */
2631     __O uint8_t SERQ;  /**< Set Enable Request Register, offset: 0x1B */
2632     __O uint8_t CDNE;  /**< Clear DONE Status Bit Register, offset: 0x1C */
2633     __O uint8_t SSRT;  /**< Set START Bit Register, offset: 0x1D */
2634     __O uint8_t CERR;  /**< Clear Error Register, offset: 0x1E */
2635     __O uint8_t CINT;  /**< Clear Interrupt Request Register, offset: 0x1F */
2636     uint8_t RESERVED_2[4];
2637     __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2638     uint8_t RESERVED_3[4];
2639     __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2640     uint8_t RESERVED_4[4];
2641     __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2642     uint8_t RESERVED_5[12];
2643     __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
2644     uint8_t RESERVED_6[184];
2645     __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
2646     __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
2647     __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
2648     __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
2649     __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
2650     __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
2651     __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
2652     __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
2653     uint8_t RESERVED_7[3832];
2654     struct
2655     {                        /* offset: 0x1000, array step: 0x20 */
2656         __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2657         __IO uint16_t SOFF;  /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2658         __IO uint16_t ATTR;  /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2659         union
2660         {                                 /* offset: 0x1008, array step: 0x20 */
2661             __IO uint32_t NBYTES_MLNO;    /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008,
2662                                              array step: 0x20 */
2663             __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset
2664                                              Disabled), array offset: 0x1008, array step: 0x20 */
2665             __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled),
2666                                               array offset: 0x1008, array step: 0x20 */
2667         };
2668         __IO int32_t SLAST;  /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2669         __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2670         __IO uint16_t DOFF;  /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2671         union
2672         {                                 /* offset: 0x1016, array step: 0x20 */
2673             __IO uint16_t CITER_ELINKNO;  /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled),
2674                                              array offset: 0x1016, array step: 0x20 */
2675             __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled),
2676                                              array offset: 0x1016, array step: 0x20 */
2677         };
2678         __IO int32_t DLAST_SGA;  /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset:
2679                                     0x1018, array step: 0x20 */
2680         __IO uint16_t CSR;       /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2681         union
2682         {                                 /* offset: 0x101E, array step: 0x20 */
2683             __IO uint16_t BITER_ELINKNO;  /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
2684                                              Disabled), array offset: 0x101E, array step: 0x20 */
2685             __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
2686                                              Enabled), array offset: 0x101E, array step: 0x20 */
2687         };
2688     } TCD[8];
2689 } DMA_Type;
2690 
2691 /* ----------------------------------------------------------------------------
2692    -- DMA Register Masks
2693    ---------------------------------------------------------------------------- */
2694 
2695 /*!
2696  * @addtogroup DMA_Register_Masks DMA Register Masks
2697  * @{
2698  */
2699 
2700 /*! @name CR - Control Register */
2701 /*! @{ */
2702 #define DMA_CR_EDBG_MASK (0x2U)
2703 #define DMA_CR_EDBG_SHIFT (1U)
2704 /*! EDBG - Enable Debug
2705  *  0b0..When in debug mode, the DMA continues to operate.
2706  *  0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
2707  *       complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
2708  */
2709 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
2710 #define DMA_CR_ERCA_MASK (0x4U)
2711 #define DMA_CR_ERCA_SHIFT (2U)
2712 /*! ERCA - Enable Round Robin Channel Arbitration
2713  *  0b0..Fixed priority arbitration is used for channel selection .
2714  *  0b1..Round robin arbitration is used for channel selection .
2715  */
2716 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
2717 #define DMA_CR_HOE_MASK (0x10U)
2718 #define DMA_CR_HOE_SHIFT (4U)
2719 /*! HOE - Halt On Error
2720  *  0b0..Normal operation
2721  *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is
2722  * cleared.
2723  */
2724 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
2725 #define DMA_CR_HALT_MASK (0x20U)
2726 #define DMA_CR_HALT_SHIFT (5U)
2727 /*! HALT - Halt DMA Operations
2728  *  0b0..Normal operation
2729  *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when
2730  * this bit is cleared.
2731  */
2732 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
2733 #define DMA_CR_CLM_MASK (0x40U)
2734 #define DMA_CR_CLM_SHIFT (6U)
2735 /*! CLM - Continuous Link Mode
2736  *  0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
2737  *  0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
2738  *       again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
2739  *       link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
2740  *       next minor loop.
2741  */
2742 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
2743 #define DMA_CR_EMLM_MASK (0x80U)
2744 #define DMA_CR_EMLM_SHIFT (7U)
2745 /*! EMLM - Enable Minor Loop Mapping
2746  *  0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
2747  *  0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
2748  *       field. The individual enable fields allow the minor loop offset to be applied to the source address, the
2749  *       destination address, or both. The NBYTES field is reduced when either offset is enabled.
2750  */
2751 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
2752 #define DMA_CR_ECX_MASK (0x10000U)
2753 #define DMA_CR_ECX_SHIFT (16U)
2754 /*! ECX - Error Cancel Transfer
2755  *  0b0..Normal operation
2756  *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
2757  *       force the minor loop to finish. The cancel takes effect after the last write of the current read/write
2758  *       sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
2759  *       treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
2760  *       optional error interrupt.
2761  */
2762 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
2763 #define DMA_CR_CX_MASK (0x20000U)
2764 #define DMA_CR_CX_SHIFT (17U)
2765 /*! CX - Cancel Transfer
2766  *  0b0..Normal operation
2767  *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
2768  *       cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
2769  *       the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
2770  */
2771 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
2772 #define DMA_CR_ACTIVE_MASK (0x80000000U)
2773 #define DMA_CR_ACTIVE_SHIFT (31U)
2774 /*! ACTIVE - DMA Active Status
2775  *  0b0..eDMA is idle.
2776  *  0b1..eDMA is executing a channel.
2777  */
2778 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
2779 /*! @} */
2780 
2781 /*! @name ES - Error Status Register */
2782 /*! @{ */
2783 #define DMA_ES_DBE_MASK (0x1U)
2784 #define DMA_ES_DBE_SHIFT (0U)
2785 /*! DBE - Destination Bus Error
2786  *  0b0..No destination bus error
2787  *  0b1..The last recorded error was a bus error on a destination write
2788  */
2789 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
2790 #define DMA_ES_SBE_MASK (0x2U)
2791 #define DMA_ES_SBE_SHIFT (1U)
2792 /*! SBE - Source Bus Error
2793  *  0b0..No source bus error
2794  *  0b1..The last recorded error was a bus error on a source read
2795  */
2796 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
2797 #define DMA_ES_SGE_MASK (0x4U)
2798 #define DMA_ES_SGE_SHIFT (2U)
2799 /*! SGE - Scatter/Gather Configuration Error
2800  *  0b0..No scatter/gather configuration error
2801  *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
2802  *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
2803  *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
2804  */
2805 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
2806 #define DMA_ES_NCE_MASK (0x8U)
2807 #define DMA_ES_NCE_SHIFT (3U)
2808 /*! NCE - NBYTES/CITER Configuration Error
2809  *  0b0..No NBYTES/CITER configuration error
2810  *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
2811  *       TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
2812  *       or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
2813  */
2814 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
2815 #define DMA_ES_DOE_MASK (0x10U)
2816 #define DMA_ES_DOE_SHIFT (4U)
2817 /*! DOE - Destination Offset Error
2818  *  0b0..No destination offset configuration error
2819  *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent
2820  * with TCDn_ATTR[DSIZE].
2821  */
2822 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
2823 #define DMA_ES_DAE_MASK (0x20U)
2824 #define DMA_ES_DAE_SHIFT (5U)
2825 /*! DAE - Destination Address Error
2826  *  0b0..No destination address configuration error
2827  *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent
2828  * with TCDn_ATTR[DSIZE].
2829  */
2830 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
2831 #define DMA_ES_SOE_MASK (0x40U)
2832 #define DMA_ES_SOE_SHIFT (6U)
2833 /*! SOE - Source Offset Error
2834  *  0b0..No source offset configuration error
2835  *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent
2836  * with TCDn_ATTR[SSIZE].
2837  */
2838 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
2839 #define DMA_ES_SAE_MASK (0x80U)
2840 #define DMA_ES_SAE_SHIFT (7U)
2841 /*! SAE - Source Address Error
2842  *  0b0..No source address configuration error.
2843  *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent
2844  * with TCDn_ATTR[SSIZE].
2845  */
2846 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
2847 #define DMA_ES_ERRCHN_MASK (0x700U)
2848 #define DMA_ES_ERRCHN_SHIFT (8U)
2849 /*! ERRCHN - Error Channel Number or Canceled Channel Number
2850  */
2851 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
2852 #define DMA_ES_CPE_MASK (0x4000U)
2853 #define DMA_ES_CPE_SHIFT (14U)
2854 /*! CPE - Channel Priority Error
2855  *  0b0..No channel priority error
2856  *  0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not
2857  * unique.
2858  */
2859 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
2860 #define DMA_ES_ECX_MASK (0x10000U)
2861 #define DMA_ES_ECX_SHIFT (16U)
2862 /*! ECX - Transfer Canceled
2863  *  0b0..No canceled transfers
2864  *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
2865  */
2866 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
2867 #define DMA_ES_VLD_MASK (0x80000000U)
2868 #define DMA_ES_VLD_SHIFT (31U)
2869 /*! VLD
2870  *  0b0..No ERR bits are set.
2871  *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
2872  */
2873 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
2874 /*! @} */
2875 
2876 /*! @name ERQ - Enable Request Register */
2877 /*! @{ */
2878 #define DMA_ERQ_ERQ0_MASK (0x1U)
2879 #define DMA_ERQ_ERQ0_SHIFT (0U)
2880 /*! ERQ0 - Enable DMA Request 0
2881  *  0b0..The DMA request signal for the corresponding channel is disabled
2882  *  0b1..The DMA request signal for the corresponding channel is enabled
2883  */
2884 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
2885 #define DMA_ERQ_ERQ1_MASK (0x2U)
2886 #define DMA_ERQ_ERQ1_SHIFT (1U)
2887 /*! ERQ1 - Enable DMA Request 1
2888  *  0b0..The DMA request signal for the corresponding channel is disabled
2889  *  0b1..The DMA request signal for the corresponding channel is enabled
2890  */
2891 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
2892 #define DMA_ERQ_ERQ2_MASK (0x4U)
2893 #define DMA_ERQ_ERQ2_SHIFT (2U)
2894 /*! ERQ2 - Enable DMA Request 2
2895  *  0b0..The DMA request signal for the corresponding channel is disabled
2896  *  0b1..The DMA request signal for the corresponding channel is enabled
2897  */
2898 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
2899 #define DMA_ERQ_ERQ3_MASK (0x8U)
2900 #define DMA_ERQ_ERQ3_SHIFT (3U)
2901 /*! ERQ3 - Enable DMA Request 3
2902  *  0b0..The DMA request signal for the corresponding channel is disabled
2903  *  0b1..The DMA request signal for the corresponding channel is enabled
2904  */
2905 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
2906 #define DMA_ERQ_ERQ4_MASK (0x10U)
2907 #define DMA_ERQ_ERQ4_SHIFT (4U)
2908 /*! ERQ4 - Enable DMA Request 4
2909  *  0b0..The DMA request signal for the corresponding channel is disabled
2910  *  0b1..The DMA request signal for the corresponding channel is enabled
2911  */
2912 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
2913 #define DMA_ERQ_ERQ5_MASK (0x20U)
2914 #define DMA_ERQ_ERQ5_SHIFT (5U)
2915 /*! ERQ5 - Enable DMA Request 5
2916  *  0b0..The DMA request signal for the corresponding channel is disabled
2917  *  0b1..The DMA request signal for the corresponding channel is enabled
2918  */
2919 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
2920 #define DMA_ERQ_ERQ6_MASK (0x40U)
2921 #define DMA_ERQ_ERQ6_SHIFT (6U)
2922 /*! ERQ6 - Enable DMA Request 6
2923  *  0b0..The DMA request signal for the corresponding channel is disabled
2924  *  0b1..The DMA request signal for the corresponding channel is enabled
2925  */
2926 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
2927 #define DMA_ERQ_ERQ7_MASK (0x80U)
2928 #define DMA_ERQ_ERQ7_SHIFT (7U)
2929 /*! ERQ7 - Enable DMA Request 7
2930  *  0b0..The DMA request signal for the corresponding channel is disabled
2931  *  0b1..The DMA request signal for the corresponding channel is enabled
2932  */
2933 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
2934 /*! @} */
2935 
2936 /*! @name EEI - Enable Error Interrupt Register */
2937 /*! @{ */
2938 #define DMA_EEI_EEI0_MASK (0x1U)
2939 #define DMA_EEI_EEI0_SHIFT (0U)
2940 /*! EEI0 - Enable Error Interrupt 0
2941  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2942  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2943  */
2944 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
2945 #define DMA_EEI_EEI1_MASK (0x2U)
2946 #define DMA_EEI_EEI1_SHIFT (1U)
2947 /*! EEI1 - Enable Error Interrupt 1
2948  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2949  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2950  */
2951 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
2952 #define DMA_EEI_EEI2_MASK (0x4U)
2953 #define DMA_EEI_EEI2_SHIFT (2U)
2954 /*! EEI2 - Enable Error Interrupt 2
2955  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2956  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2957  */
2958 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
2959 #define DMA_EEI_EEI3_MASK (0x8U)
2960 #define DMA_EEI_EEI3_SHIFT (3U)
2961 /*! EEI3 - Enable Error Interrupt 3
2962  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2963  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2964  */
2965 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
2966 #define DMA_EEI_EEI4_MASK (0x10U)
2967 #define DMA_EEI_EEI4_SHIFT (4U)
2968 /*! EEI4 - Enable Error Interrupt 4
2969  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2970  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2971  */
2972 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
2973 #define DMA_EEI_EEI5_MASK (0x20U)
2974 #define DMA_EEI_EEI5_SHIFT (5U)
2975 /*! EEI5 - Enable Error Interrupt 5
2976  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2977  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2978  */
2979 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
2980 #define DMA_EEI_EEI6_MASK (0x40U)
2981 #define DMA_EEI_EEI6_SHIFT (6U)
2982 /*! EEI6 - Enable Error Interrupt 6
2983  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2984  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2985  */
2986 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
2987 #define DMA_EEI_EEI7_MASK (0x80U)
2988 #define DMA_EEI_EEI7_SHIFT (7U)
2989 /*! EEI7 - Enable Error Interrupt 7
2990  *  0b0..The error signal for corresponding channel does not generate an error interrupt
2991  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2992  */
2993 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
2994 /*! @} */
2995 
2996 /*! @name CEEI - Clear Enable Error Interrupt Register */
2997 /*! @{ */
2998 #define DMA_CEEI_CEEI_MASK (0x7U)
2999 #define DMA_CEEI_CEEI_SHIFT (0U)
3000 /*! CEEI - Clear Enable Error Interrupt
3001  */
3002 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
3003 #define DMA_CEEI_CAEE_MASK (0x40U)
3004 #define DMA_CEEI_CAEE_SHIFT (6U)
3005 /*! CAEE - Clear All Enable Error Interrupts
3006  *  0b0..Clear only the EEI bit specified in the CEEI field
3007  *  0b1..Clear all bits in EEI
3008  */
3009 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
3010 #define DMA_CEEI_NOP_MASK (0x80U)
3011 #define DMA_CEEI_NOP_SHIFT (7U)
3012 /*! NOP - No Op enable
3013  *  0b0..Normal operation
3014  *  0b1..No operation, ignore the other bits in this register
3015  */
3016 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
3017 /*! @} */
3018 
3019 /*! @name SEEI - Set Enable Error Interrupt Register */
3020 /*! @{ */
3021 #define DMA_SEEI_SEEI_MASK (0x7U)
3022 #define DMA_SEEI_SEEI_SHIFT (0U)
3023 /*! SEEI - Set Enable Error Interrupt
3024  */
3025 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
3026 #define DMA_SEEI_SAEE_MASK (0x40U)
3027 #define DMA_SEEI_SAEE_SHIFT (6U)
3028 /*! SAEE - Sets All Enable Error Interrupts
3029  *  0b0..Set only the EEI bit specified in the SEEI field.
3030  *  0b1..Sets all bits in EEI
3031  */
3032 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
3033 #define DMA_SEEI_NOP_MASK (0x80U)
3034 #define DMA_SEEI_NOP_SHIFT (7U)
3035 /*! NOP - No Op enable
3036  *  0b0..Normal operation
3037  *  0b1..No operation, ignore the other bits in this register
3038  */
3039 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
3040 /*! @} */
3041 
3042 /*! @name CERQ - Clear Enable Request Register */
3043 /*! @{ */
3044 #define DMA_CERQ_CERQ_MASK (0x7U)
3045 #define DMA_CERQ_CERQ_SHIFT (0U)
3046 /*! CERQ - Clear Enable Request
3047  */
3048 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
3049 #define DMA_CERQ_CAER_MASK (0x40U)
3050 #define DMA_CERQ_CAER_SHIFT (6U)
3051 /*! CAER - Clear All Enable Requests
3052  *  0b0..Clear only the ERQ bit specified in the CERQ field
3053  *  0b1..Clear all bits in ERQ
3054  */
3055 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
3056 #define DMA_CERQ_NOP_MASK (0x80U)
3057 #define DMA_CERQ_NOP_SHIFT (7U)
3058 /*! NOP - No Op enable
3059  *  0b0..Normal operation
3060  *  0b1..No operation, ignore the other bits in this register
3061  */
3062 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
3063 /*! @} */
3064 
3065 /*! @name SERQ - Set Enable Request Register */
3066 /*! @{ */
3067 #define DMA_SERQ_SERQ_MASK (0x7U)
3068 #define DMA_SERQ_SERQ_SHIFT (0U)
3069 /*! SERQ - Set Enable Request
3070  */
3071 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
3072 #define DMA_SERQ_SAER_MASK (0x40U)
3073 #define DMA_SERQ_SAER_SHIFT (6U)
3074 /*! SAER - Set All Enable Requests
3075  *  0b0..Set only the ERQ bit specified in the SERQ field
3076  *  0b1..Set all bits in ERQ
3077  */
3078 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
3079 #define DMA_SERQ_NOP_MASK (0x80U)
3080 #define DMA_SERQ_NOP_SHIFT (7U)
3081 /*! NOP - No Op enable
3082  *  0b0..Normal operation
3083  *  0b1..No operation, ignore the other bits in this register
3084  */
3085 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
3086 /*! @} */
3087 
3088 /*! @name CDNE - Clear DONE Status Bit Register */
3089 /*! @{ */
3090 #define DMA_CDNE_CDNE_MASK (0x7U)
3091 #define DMA_CDNE_CDNE_SHIFT (0U)
3092 /*! CDNE - Clear DONE Bit
3093  */
3094 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
3095 #define DMA_CDNE_CADN_MASK (0x40U)
3096 #define DMA_CDNE_CADN_SHIFT (6U)
3097 /*! CADN - Clears All DONE Bits
3098  *  0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
3099  *  0b1..Clears all bits in TCDn_CSR[DONE]
3100  */
3101 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
3102 #define DMA_CDNE_NOP_MASK (0x80U)
3103 #define DMA_CDNE_NOP_SHIFT (7U)
3104 /*! NOP - No Op enable
3105  *  0b0..Normal operation
3106  *  0b1..No operation, ignore the other bits in this register
3107  */
3108 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
3109 /*! @} */
3110 
3111 /*! @name SSRT - Set START Bit Register */
3112 /*! @{ */
3113 #define DMA_SSRT_SSRT_MASK (0x7U)
3114 #define DMA_SSRT_SSRT_SHIFT (0U)
3115 /*! SSRT - Set START Bit
3116  */
3117 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
3118 #define DMA_SSRT_SAST_MASK (0x40U)
3119 #define DMA_SSRT_SAST_SHIFT (6U)
3120 /*! SAST - Set All START Bits (activates all channels)
3121  *  0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
3122  *  0b1..Set all bits in TCDn_CSR[START]
3123  */
3124 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
3125 #define DMA_SSRT_NOP_MASK (0x80U)
3126 #define DMA_SSRT_NOP_SHIFT (7U)
3127 /*! NOP - No Op enable
3128  *  0b0..Normal operation
3129  *  0b1..No operation, ignore the other bits in this register
3130  */
3131 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
3132 /*! @} */
3133 
3134 /*! @name CERR - Clear Error Register */
3135 /*! @{ */
3136 #define DMA_CERR_CERR_MASK (0x7U)
3137 #define DMA_CERR_CERR_SHIFT (0U)
3138 /*! CERR - Clear Error Indicator
3139  */
3140 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
3141 #define DMA_CERR_CAEI_MASK (0x40U)
3142 #define DMA_CERR_CAEI_SHIFT (6U)
3143 /*! CAEI - Clear All Error Indicators
3144  *  0b0..Clear only the ERR bit specified in the CERR field
3145  *  0b1..Clear all bits in ERR
3146  */
3147 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
3148 #define DMA_CERR_NOP_MASK (0x80U)
3149 #define DMA_CERR_NOP_SHIFT (7U)
3150 /*! NOP - No Op enable
3151  *  0b0..Normal operation
3152  *  0b1..No operation, ignore the other bits in this register
3153  */
3154 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
3155 /*! @} */
3156 
3157 /*! @name CINT - Clear Interrupt Request Register */
3158 /*! @{ */
3159 #define DMA_CINT_CINT_MASK (0x7U)
3160 #define DMA_CINT_CINT_SHIFT (0U)
3161 /*! CINT - Clear Interrupt Request
3162  */
3163 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
3164 #define DMA_CINT_CAIR_MASK (0x40U)
3165 #define DMA_CINT_CAIR_SHIFT (6U)
3166 /*! CAIR - Clear All Interrupt Requests
3167  *  0b0..Clear only the INT bit specified in the CINT field
3168  *  0b1..Clear all bits in INT
3169  */
3170 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
3171 #define DMA_CINT_NOP_MASK (0x80U)
3172 #define DMA_CINT_NOP_SHIFT (7U)
3173 /*! NOP - No Op enable
3174  *  0b0..Normal operation
3175  *  0b1..No operation, ignore the other bits in this register
3176  */
3177 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
3178 /*! @} */
3179 
3180 /*! @name INT - Interrupt Request Register */
3181 /*! @{ */
3182 #define DMA_INT_INT0_MASK (0x1U)
3183 #define DMA_INT_INT0_SHIFT (0U)
3184 /*! INT0 - Interrupt Request 0
3185  *  0b0..The interrupt request for corresponding channel is cleared
3186  *  0b1..The interrupt request for corresponding channel is active
3187  */
3188 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
3189 #define DMA_INT_INT1_MASK (0x2U)
3190 #define DMA_INT_INT1_SHIFT (1U)
3191 /*! INT1 - Interrupt Request 1
3192  *  0b0..The interrupt request for corresponding channel is cleared
3193  *  0b1..The interrupt request for corresponding channel is active
3194  */
3195 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
3196 #define DMA_INT_INT2_MASK (0x4U)
3197 #define DMA_INT_INT2_SHIFT (2U)
3198 /*! INT2 - Interrupt Request 2
3199  *  0b0..The interrupt request for corresponding channel is cleared
3200  *  0b1..The interrupt request for corresponding channel is active
3201  */
3202 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
3203 #define DMA_INT_INT3_MASK (0x8U)
3204 #define DMA_INT_INT3_SHIFT (3U)
3205 /*! INT3 - Interrupt Request 3
3206  *  0b0..The interrupt request for corresponding channel is cleared
3207  *  0b1..The interrupt request for corresponding channel is active
3208  */
3209 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
3210 #define DMA_INT_INT4_MASK (0x10U)
3211 #define DMA_INT_INT4_SHIFT (4U)
3212 /*! INT4 - Interrupt Request 4
3213  *  0b0..The interrupt request for corresponding channel is cleared
3214  *  0b1..The interrupt request for corresponding channel is active
3215  */
3216 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
3217 #define DMA_INT_INT5_MASK (0x20U)
3218 #define DMA_INT_INT5_SHIFT (5U)
3219 /*! INT5 - Interrupt Request 5
3220  *  0b0..The interrupt request for corresponding channel is cleared
3221  *  0b1..The interrupt request for corresponding channel is active
3222  */
3223 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
3224 #define DMA_INT_INT6_MASK (0x40U)
3225 #define DMA_INT_INT6_SHIFT (6U)
3226 /*! INT6 - Interrupt Request 6
3227  *  0b0..The interrupt request for corresponding channel is cleared
3228  *  0b1..The interrupt request for corresponding channel is active
3229  */
3230 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
3231 #define DMA_INT_INT7_MASK (0x80U)
3232 #define DMA_INT_INT7_SHIFT (7U)
3233 /*! INT7 - Interrupt Request 7
3234  *  0b0..The interrupt request for corresponding channel is cleared
3235  *  0b1..The interrupt request for corresponding channel is active
3236  */
3237 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
3238 /*! @} */
3239 
3240 /*! @name ERR - Error Register */
3241 /*! @{ */
3242 #define DMA_ERR_ERR0_MASK (0x1U)
3243 #define DMA_ERR_ERR0_SHIFT (0U)
3244 /*! ERR0 - Error In Channel 0
3245  *  0b0..An error in this channel has not occurred
3246  *  0b1..An error in this channel has occurred
3247  */
3248 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
3249 #define DMA_ERR_ERR1_MASK (0x2U)
3250 #define DMA_ERR_ERR1_SHIFT (1U)
3251 /*! ERR1 - Error In Channel 1
3252  *  0b0..An error in this channel has not occurred
3253  *  0b1..An error in this channel has occurred
3254  */
3255 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
3256 #define DMA_ERR_ERR2_MASK (0x4U)
3257 #define DMA_ERR_ERR2_SHIFT (2U)
3258 /*! ERR2 - Error In Channel 2
3259  *  0b0..An error in this channel has not occurred
3260  *  0b1..An error in this channel has occurred
3261  */
3262 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
3263 #define DMA_ERR_ERR3_MASK (0x8U)
3264 #define DMA_ERR_ERR3_SHIFT (3U)
3265 /*! ERR3 - Error In Channel 3
3266  *  0b0..An error in this channel has not occurred
3267  *  0b1..An error in this channel has occurred
3268  */
3269 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
3270 #define DMA_ERR_ERR4_MASK (0x10U)
3271 #define DMA_ERR_ERR4_SHIFT (4U)
3272 /*! ERR4 - Error In Channel 4
3273  *  0b0..An error in this channel has not occurred
3274  *  0b1..An error in this channel has occurred
3275  */
3276 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
3277 #define DMA_ERR_ERR5_MASK (0x20U)
3278 #define DMA_ERR_ERR5_SHIFT (5U)
3279 /*! ERR5 - Error In Channel 5
3280  *  0b0..An error in this channel has not occurred
3281  *  0b1..An error in this channel has occurred
3282  */
3283 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
3284 #define DMA_ERR_ERR6_MASK (0x40U)
3285 #define DMA_ERR_ERR6_SHIFT (6U)
3286 /*! ERR6 - Error In Channel 6
3287  *  0b0..An error in this channel has not occurred
3288  *  0b1..An error in this channel has occurred
3289  */
3290 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
3291 #define DMA_ERR_ERR7_MASK (0x80U)
3292 #define DMA_ERR_ERR7_SHIFT (7U)
3293 /*! ERR7 - Error In Channel 7
3294  *  0b0..An error in this channel has not occurred
3295  *  0b1..An error in this channel has occurred
3296  */
3297 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
3298 /*! @} */
3299 
3300 /*! @name HRS - Hardware Request Status Register */
3301 /*! @{ */
3302 #define DMA_HRS_HRS0_MASK (0x1U)
3303 #define DMA_HRS_HRS0_SHIFT (0U)
3304 /*! HRS0 - Hardware Request Status Channel 0
3305  *  0b0..A hardware service request for channel 0 is not present
3306  *  0b1..A hardware service request for channel 0 is present
3307  */
3308 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
3309 #define DMA_HRS_HRS1_MASK (0x2U)
3310 #define DMA_HRS_HRS1_SHIFT (1U)
3311 /*! HRS1 - Hardware Request Status Channel 1
3312  *  0b0..A hardware service request for channel 1 is not present
3313  *  0b1..A hardware service request for channel 1 is present
3314  */
3315 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
3316 #define DMA_HRS_HRS2_MASK (0x4U)
3317 #define DMA_HRS_HRS2_SHIFT (2U)
3318 /*! HRS2 - Hardware Request Status Channel 2
3319  *  0b0..A hardware service request for channel 2 is not present
3320  *  0b1..A hardware service request for channel 2 is present
3321  */
3322 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
3323 #define DMA_HRS_HRS3_MASK (0x8U)
3324 #define DMA_HRS_HRS3_SHIFT (3U)
3325 /*! HRS3 - Hardware Request Status Channel 3
3326  *  0b0..A hardware service request for channel 3 is not present
3327  *  0b1..A hardware service request for channel 3 is present
3328  */
3329 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
3330 #define DMA_HRS_HRS4_MASK (0x10U)
3331 #define DMA_HRS_HRS4_SHIFT (4U)
3332 /*! HRS4 - Hardware Request Status Channel 4
3333  *  0b0..A hardware service request for channel 4 is not present
3334  *  0b1..A hardware service request for channel 4 is present
3335  */
3336 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
3337 #define DMA_HRS_HRS5_MASK (0x20U)
3338 #define DMA_HRS_HRS5_SHIFT (5U)
3339 /*! HRS5 - Hardware Request Status Channel 5
3340  *  0b0..A hardware service request for channel 5 is not present
3341  *  0b1..A hardware service request for channel 5 is present
3342  */
3343 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
3344 #define DMA_HRS_HRS6_MASK (0x40U)
3345 #define DMA_HRS_HRS6_SHIFT (6U)
3346 /*! HRS6 - Hardware Request Status Channel 6
3347  *  0b0..A hardware service request for channel 6 is not present
3348  *  0b1..A hardware service request for channel 6 is present
3349  */
3350 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
3351 #define DMA_HRS_HRS7_MASK (0x80U)
3352 #define DMA_HRS_HRS7_SHIFT (7U)
3353 /*! HRS7 - Hardware Request Status Channel 7
3354  *  0b0..A hardware service request for channel 7 is not present
3355  *  0b1..A hardware service request for channel 7 is present
3356  */
3357 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
3358 /*! @} */
3359 
3360 /*! @name EARS - Enable Asynchronous Request in Stop Register */
3361 /*! @{ */
3362 #define DMA_EARS_EDREQ_0_MASK (0x1U)
3363 #define DMA_EARS_EDREQ_0_SHIFT (0U)
3364 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
3365  *  0b0..Disable asynchronous DMA request for channel 0.
3366  *  0b1..Enable asynchronous DMA request for channel 0.
3367  */
3368 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
3369 #define DMA_EARS_EDREQ_1_MASK (0x2U)
3370 #define DMA_EARS_EDREQ_1_SHIFT (1U)
3371 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
3372  *  0b0..Disable asynchronous DMA request for channel 1
3373  *  0b1..Enable asynchronous DMA request for channel 1.
3374  */
3375 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
3376 #define DMA_EARS_EDREQ_2_MASK (0x4U)
3377 #define DMA_EARS_EDREQ_2_SHIFT (2U)
3378 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
3379  *  0b0..Disable asynchronous DMA request for channel 2.
3380  *  0b1..Enable asynchronous DMA request for channel 2.
3381  */
3382 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
3383 #define DMA_EARS_EDREQ_3_MASK (0x8U)
3384 #define DMA_EARS_EDREQ_3_SHIFT (3U)
3385 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
3386  *  0b0..Disable asynchronous DMA request for channel 3.
3387  *  0b1..Enable asynchronous DMA request for channel 3.
3388  */
3389 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
3390 #define DMA_EARS_EDREQ_4_MASK (0x10U)
3391 #define DMA_EARS_EDREQ_4_SHIFT (4U)
3392 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
3393  *  0b0..Disable asynchronous DMA request for channel 4.
3394  *  0b1..Enable asynchronous DMA request for channel 4.
3395  */
3396 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
3397 #define DMA_EARS_EDREQ_5_MASK (0x20U)
3398 #define DMA_EARS_EDREQ_5_SHIFT (5U)
3399 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
3400  *  0b0..Disable asynchronous DMA request for channel 5.
3401  *  0b1..Enable asynchronous DMA request for channel 5.
3402  */
3403 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
3404 #define DMA_EARS_EDREQ_6_MASK (0x40U)
3405 #define DMA_EARS_EDREQ_6_SHIFT (6U)
3406 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
3407  *  0b0..Disable asynchronous DMA request for channel 6.
3408  *  0b1..Enable asynchronous DMA request for channel 6.
3409  */
3410 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
3411 #define DMA_EARS_EDREQ_7_MASK (0x80U)
3412 #define DMA_EARS_EDREQ_7_SHIFT (7U)
3413 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
3414  *  0b0..Disable asynchronous DMA request for channel 7.
3415  *  0b1..Enable asynchronous DMA request for channel 7.
3416  */
3417 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
3418 /*! @} */
3419 
3420 /*! @name DCHPRI3 - Channel n Priority Register */
3421 /*! @{ */
3422 #define DMA_DCHPRI3_CHPRI_MASK (0x7U)
3423 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
3424 /*! CHPRI - Channel n Arbitration Priority
3425  */
3426 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
3427 #define DMA_DCHPRI3_DPA_MASK (0x40U)
3428 #define DMA_DCHPRI3_DPA_SHIFT (6U)
3429 /*! DPA - Disable Preempt Ability.
3430  *  0b0..Channel n can suspend a lower priority channel.
3431  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3432  */
3433 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
3434 #define DMA_DCHPRI3_ECP_MASK (0x80U)
3435 #define DMA_DCHPRI3_ECP_SHIFT (7U)
3436 /*! ECP - Enable Channel Preemption.
3437  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3438  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3439  */
3440 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
3441 /*! @} */
3442 
3443 /*! @name DCHPRI2 - Channel n Priority Register */
3444 /*! @{ */
3445 #define DMA_DCHPRI2_CHPRI_MASK (0x7U)
3446 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
3447 /*! CHPRI - Channel n Arbitration Priority
3448  */
3449 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
3450 #define DMA_DCHPRI2_DPA_MASK (0x40U)
3451 #define DMA_DCHPRI2_DPA_SHIFT (6U)
3452 /*! DPA - Disable Preempt Ability.
3453  *  0b0..Channel n can suspend a lower priority channel.
3454  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3455  */
3456 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
3457 #define DMA_DCHPRI2_ECP_MASK (0x80U)
3458 #define DMA_DCHPRI2_ECP_SHIFT (7U)
3459 /*! ECP - Enable Channel Preemption.
3460  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3461  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3462  */
3463 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
3464 /*! @} */
3465 
3466 /*! @name DCHPRI1 - Channel n Priority Register */
3467 /*! @{ */
3468 #define DMA_DCHPRI1_CHPRI_MASK (0x7U)
3469 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
3470 /*! CHPRI - Channel n Arbitration Priority
3471  */
3472 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
3473 #define DMA_DCHPRI1_DPA_MASK (0x40U)
3474 #define DMA_DCHPRI1_DPA_SHIFT (6U)
3475 /*! DPA - Disable Preempt Ability.
3476  *  0b0..Channel n can suspend a lower priority channel.
3477  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3478  */
3479 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
3480 #define DMA_DCHPRI1_ECP_MASK (0x80U)
3481 #define DMA_DCHPRI1_ECP_SHIFT (7U)
3482 /*! ECP - Enable Channel Preemption.
3483  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3484  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3485  */
3486 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
3487 /*! @} */
3488 
3489 /*! @name DCHPRI0 - Channel n Priority Register */
3490 /*! @{ */
3491 #define DMA_DCHPRI0_CHPRI_MASK (0x7U)
3492 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
3493 /*! CHPRI - Channel n Arbitration Priority
3494  */
3495 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
3496 #define DMA_DCHPRI0_DPA_MASK (0x40U)
3497 #define DMA_DCHPRI0_DPA_SHIFT (6U)
3498 /*! DPA - Disable Preempt Ability.
3499  *  0b0..Channel n can suspend a lower priority channel.
3500  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3501  */
3502 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
3503 #define DMA_DCHPRI0_ECP_MASK (0x80U)
3504 #define DMA_DCHPRI0_ECP_SHIFT (7U)
3505 /*! ECP - Enable Channel Preemption.
3506  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3507  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3508  */
3509 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
3510 /*! @} */
3511 
3512 /*! @name DCHPRI7 - Channel n Priority Register */
3513 /*! @{ */
3514 #define DMA_DCHPRI7_CHPRI_MASK (0x7U)
3515 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
3516 /*! CHPRI - Channel n Arbitration Priority
3517  */
3518 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
3519 #define DMA_DCHPRI7_DPA_MASK (0x40U)
3520 #define DMA_DCHPRI7_DPA_SHIFT (6U)
3521 /*! DPA - Disable Preempt Ability.
3522  *  0b0..Channel n can suspend a lower priority channel.
3523  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3524  */
3525 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
3526 #define DMA_DCHPRI7_ECP_MASK (0x80U)
3527 #define DMA_DCHPRI7_ECP_SHIFT (7U)
3528 /*! ECP - Enable Channel Preemption.
3529  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3530  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3531  */
3532 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
3533 /*! @} */
3534 
3535 /*! @name DCHPRI6 - Channel n Priority Register */
3536 /*! @{ */
3537 #define DMA_DCHPRI6_CHPRI_MASK (0x7U)
3538 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
3539 /*! CHPRI - Channel n Arbitration Priority
3540  */
3541 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
3542 #define DMA_DCHPRI6_DPA_MASK (0x40U)
3543 #define DMA_DCHPRI6_DPA_SHIFT (6U)
3544 /*! DPA - Disable Preempt Ability.
3545  *  0b0..Channel n can suspend a lower priority channel.
3546  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3547  */
3548 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
3549 #define DMA_DCHPRI6_ECP_MASK (0x80U)
3550 #define DMA_DCHPRI6_ECP_SHIFT (7U)
3551 /*! ECP - Enable Channel Preemption.
3552  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3553  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3554  */
3555 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
3556 /*! @} */
3557 
3558 /*! @name DCHPRI5 - Channel n Priority Register */
3559 /*! @{ */
3560 #define DMA_DCHPRI5_CHPRI_MASK (0x7U)
3561 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
3562 /*! CHPRI - Channel n Arbitration Priority
3563  */
3564 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
3565 #define DMA_DCHPRI5_DPA_MASK (0x40U)
3566 #define DMA_DCHPRI5_DPA_SHIFT (6U)
3567 /*! DPA - Disable Preempt Ability.
3568  *  0b0..Channel n can suspend a lower priority channel.
3569  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3570  */
3571 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
3572 #define DMA_DCHPRI5_ECP_MASK (0x80U)
3573 #define DMA_DCHPRI5_ECP_SHIFT (7U)
3574 /*! ECP - Enable Channel Preemption.
3575  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3576  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3577  */
3578 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
3579 /*! @} */
3580 
3581 /*! @name DCHPRI4 - Channel n Priority Register */
3582 /*! @{ */
3583 #define DMA_DCHPRI4_CHPRI_MASK (0x7U)
3584 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
3585 /*! CHPRI - Channel n Arbitration Priority
3586  */
3587 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
3588 #define DMA_DCHPRI4_DPA_MASK (0x40U)
3589 #define DMA_DCHPRI4_DPA_SHIFT (6U)
3590 /*! DPA - Disable Preempt Ability.
3591  *  0b0..Channel n can suspend a lower priority channel.
3592  *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
3593  */
3594 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
3595 #define DMA_DCHPRI4_ECP_MASK (0x80U)
3596 #define DMA_DCHPRI4_ECP_SHIFT (7U)
3597 /*! ECP - Enable Channel Preemption.
3598  *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
3599  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3600  */
3601 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
3602 /*! @} */
3603 
3604 /*! @name SADDR - TCD Source Address */
3605 /*! @{ */
3606 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
3607 #define DMA_SADDR_SADDR_SHIFT (0U)
3608 /*! SADDR - Source Address
3609  */
3610 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
3611 /*! @} */
3612 
3613 /* The count of DMA_SADDR */
3614 #define DMA_SADDR_COUNT (8U)
3615 
3616 /*! @name SOFF - TCD Signed Source Address Offset */
3617 /*! @{ */
3618 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
3619 #define DMA_SOFF_SOFF_SHIFT (0U)
3620 /*! SOFF - Source address signed offset
3621  */
3622 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
3623 /*! @} */
3624 
3625 /* The count of DMA_SOFF */
3626 #define DMA_SOFF_COUNT (8U)
3627 
3628 /*! @name ATTR - TCD Transfer Attributes */
3629 /*! @{ */
3630 #define DMA_ATTR_DSIZE_MASK (0x7U)
3631 #define DMA_ATTR_DSIZE_SHIFT (0U)
3632 /*! DSIZE - Destination data transfer size
3633  */
3634 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
3635 #define DMA_ATTR_DMOD_MASK (0xF8U)
3636 #define DMA_ATTR_DMOD_SHIFT (3U)
3637 /*! DMOD - Destination Address Modulo
3638  */
3639 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
3640 #define DMA_ATTR_SSIZE_MASK (0x700U)
3641 #define DMA_ATTR_SSIZE_SHIFT (8U)
3642 /*! SSIZE - Source data transfer size
3643  *  0b000..8-bit
3644  *  0b001..16-bit
3645  *  0b010..32-bit
3646  *  0b011..Reserved
3647  *  0b100..16-byte
3648  *  0b101..32-byte
3649  *  0b110..Reserved
3650  *  0b111..Reserved
3651  */
3652 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
3653 #define DMA_ATTR_SMOD_MASK (0xF800U)
3654 #define DMA_ATTR_SMOD_SHIFT (11U)
3655 /*! SMOD - Source Address Modulo
3656  *  0b00000..Source address modulo feature is disabled
3657  */
3658 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
3659 /*! @} */
3660 
3661 /* The count of DMA_ATTR */
3662 #define DMA_ATTR_COUNT (8U)
3663 
3664 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
3665 /*! @{ */
3666 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
3667 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
3668 /*! NBYTES - Minor Byte Transfer Count
3669  */
3670 #define DMA_NBYTES_MLNO_NBYTES(x) \
3671     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
3672 /*! @} */
3673 
3674 /* The count of DMA_NBYTES_MLNO */
3675 #define DMA_NBYTES_MLNO_COUNT (8U)
3676 
3677 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
3678 /*! @{ */
3679 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
3680 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
3681 /*! NBYTES - Minor Byte Transfer Count
3682  */
3683 #define DMA_NBYTES_MLOFFNO_NBYTES(x) \
3684     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
3685 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
3686 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
3687 /*! DMLOE - Destination Minor Loop Offset enable
3688  *  0b0..The minor loop offset is not applied to the DADDR
3689  *  0b1..The minor loop offset is applied to the DADDR
3690  */
3691 #define DMA_NBYTES_MLOFFNO_DMLOE(x) \
3692     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
3693 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
3694 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
3695 /*! SMLOE - Source Minor Loop Offset Enable
3696  *  0b0..The minor loop offset is not applied to the SADDR
3697  *  0b1..The minor loop offset is applied to the SADDR
3698  */
3699 #define DMA_NBYTES_MLOFFNO_SMLOE(x) \
3700     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
3701 /*! @} */
3702 
3703 /* The count of DMA_NBYTES_MLOFFNO */
3704 #define DMA_NBYTES_MLOFFNO_COUNT (8U)
3705 
3706 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
3707 /*! @{ */
3708 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
3709 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
3710 /*! NBYTES - Minor Byte Transfer Count
3711  */
3712 #define DMA_NBYTES_MLOFFYES_NBYTES(x) \
3713     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
3714 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
3715 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
3716 /*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the
3717  *    source or destination address to form the next-state value after the minor loop completes.
3718  */
3719 #define DMA_NBYTES_MLOFFYES_MLOFF(x) \
3720     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
3721 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
3722 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
3723 /*! DMLOE - Destination Minor Loop Offset enable
3724  *  0b0..The minor loop offset is not applied to the DADDR
3725  *  0b1..The minor loop offset is applied to the DADDR
3726  */
3727 #define DMA_NBYTES_MLOFFYES_DMLOE(x) \
3728     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
3729 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
3730 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
3731 /*! SMLOE - Source Minor Loop Offset Enable
3732  *  0b0..The minor loop offset is not applied to the SADDR
3733  *  0b1..The minor loop offset is applied to the SADDR
3734  */
3735 #define DMA_NBYTES_MLOFFYES_SMLOE(x) \
3736     (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
3737 /*! @} */
3738 
3739 /* The count of DMA_NBYTES_MLOFFYES */
3740 #define DMA_NBYTES_MLOFFYES_COUNT (8U)
3741 
3742 /*! @name SLAST - TCD Last Source Address Adjustment */
3743 /*! @{ */
3744 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
3745 #define DMA_SLAST_SLAST_SHIFT (0U)
3746 /*! SLAST - Last Source Address Adjustment
3747  */
3748 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
3749 /*! @} */
3750 
3751 /* The count of DMA_SLAST */
3752 #define DMA_SLAST_COUNT (8U)
3753 
3754 /*! @name DADDR - TCD Destination Address */
3755 /*! @{ */
3756 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
3757 #define DMA_DADDR_DADDR_SHIFT (0U)
3758 /*! DADDR - Destination Address
3759  */
3760 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
3761 /*! @} */
3762 
3763 /* The count of DMA_DADDR */
3764 #define DMA_DADDR_COUNT (8U)
3765 
3766 /*! @name DOFF - TCD Signed Destination Address Offset */
3767 /*! @{ */
3768 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
3769 #define DMA_DOFF_DOFF_SHIFT (0U)
3770 /*! DOFF - Destination Address Signed Offset
3771  */
3772 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
3773 /*! @} */
3774 
3775 /* The count of DMA_DOFF */
3776 #define DMA_DOFF_COUNT (8U)
3777 
3778 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3779 /*! @{ */
3780 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
3781 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
3782 /*! CITER - Current Major Iteration Count
3783  */
3784 #define DMA_CITER_ELINKNO_CITER(x) \
3785     (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
3786 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
3787 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
3788 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
3789  *  0b0..The channel-to-channel linking is disabled
3790  *  0b1..The channel-to-channel linking is enabled
3791  */
3792 #define DMA_CITER_ELINKNO_ELINK(x) \
3793     (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
3794 /*! @} */
3795 
3796 /* The count of DMA_CITER_ELINKNO */
3797 #define DMA_CITER_ELINKNO_COUNT (8U)
3798 
3799 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3800 /*! @{ */
3801 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
3802 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
3803 /*! CITER - Current Major Iteration Count
3804  */
3805 #define DMA_CITER_ELINKYES_CITER(x) \
3806     (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
3807 #define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U)
3808 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
3809 /*! LINKCH - Minor Loop Link Channel Number
3810  */
3811 #define DMA_CITER_ELINKYES_LINKCH(x) \
3812     (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
3813 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
3814 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
3815 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
3816  *  0b0..The channel-to-channel linking is disabled
3817  *  0b1..The channel-to-channel linking is enabled
3818  */
3819 #define DMA_CITER_ELINKYES_ELINK(x) \
3820     (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
3821 /*! @} */
3822 
3823 /* The count of DMA_CITER_ELINKYES */
3824 #define DMA_CITER_ELINKYES_COUNT (8U)
3825 
3826 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
3827 /*! @{ */
3828 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
3829 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
3830 #define DMA_DLAST_SGA_DLASTSGA(x) \
3831     (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
3832 /*! @} */
3833 
3834 /* The count of DMA_DLAST_SGA */
3835 #define DMA_DLAST_SGA_COUNT (8U)
3836 
3837 /*! @name CSR - TCD Control and Status */
3838 /*! @{ */
3839 #define DMA_CSR_START_MASK (0x1U)
3840 #define DMA_CSR_START_SHIFT (0U)
3841 /*! START - Channel Start
3842  *  0b0..The channel is not explicitly started.
3843  *  0b1..The channel is explicitly started via a software initiated service request.
3844  */
3845 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
3846 #define DMA_CSR_INTMAJOR_MASK (0x2U)
3847 #define DMA_CSR_INTMAJOR_SHIFT (1U)
3848 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
3849  *  0b0..The end-of-major loop interrupt is disabled.
3850  *  0b1..The end-of-major loop interrupt is enabled.
3851  */
3852 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
3853 #define DMA_CSR_INTHALF_MASK (0x4U)
3854 #define DMA_CSR_INTHALF_SHIFT (2U)
3855 /*! INTHALF - Enable an interrupt when major counter is half complete.
3856  *  0b0..The half-point interrupt is disabled.
3857  *  0b1..The half-point interrupt is enabled.
3858  */
3859 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
3860 #define DMA_CSR_DREQ_MASK (0x8U)
3861 #define DMA_CSR_DREQ_SHIFT (3U)
3862 /*! DREQ - Disable Request
3863  *  0b0..The channel's ERQ bit is not affected.
3864  *  0b1..The channel's ERQ bit is cleared when the major loop is complete.
3865  */
3866 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
3867 #define DMA_CSR_ESG_MASK (0x10U)
3868 #define DMA_CSR_ESG_SHIFT (4U)
3869 /*! ESG - Enable Scatter/Gather Processing
3870  *  0b0..The current channel's TCD is normal format.
3871  *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
3872  *       to the next TCD to be loaded into this channel after the major loop completes its execution.
3873  */
3874 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
3875 #define DMA_CSR_MAJORELINK_MASK (0x20U)
3876 #define DMA_CSR_MAJORELINK_SHIFT (5U)
3877 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
3878  *  0b0..The channel-to-channel linking is disabled.
3879  *  0b1..The channel-to-channel linking is enabled.
3880  */
3881 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
3882 #define DMA_CSR_ACTIVE_MASK (0x40U)
3883 #define DMA_CSR_ACTIVE_SHIFT (6U)
3884 /*! ACTIVE - Channel Active
3885  */
3886 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
3887 #define DMA_CSR_DONE_MASK (0x80U)
3888 #define DMA_CSR_DONE_SHIFT (7U)
3889 /*! DONE - Channel Done
3890  */
3891 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
3892 #define DMA_CSR_MAJORLINKCH_MASK (0x700U)
3893 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
3894 /*! MAJORLINKCH - Major Loop Link Channel Number
3895  */
3896 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
3897 #define DMA_CSR_BWC_MASK (0xC000U)
3898 #define DMA_CSR_BWC_SHIFT (14U)
3899 /*! BWC - Bandwidth Control
3900  *  0b00..No eDMA engine stalls.
3901  *  0b01..Reserved
3902  *  0b10..eDMA engine stalls for 4 cycles after each R/W.
3903  *  0b11..eDMA engine stalls for 8 cycles after each R/W.
3904  */
3905 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
3906 /*! @} */
3907 
3908 /* The count of DMA_CSR */
3909 #define DMA_CSR_COUNT (8U)
3910 
3911 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3912 /*! @{ */
3913 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
3914 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
3915 /*! BITER - Starting Major Iteration Count
3916  */
3917 #define DMA_BITER_ELINKNO_BITER(x) \
3918     (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
3919 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
3920 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
3921 /*! ELINK - Enables channel-to-channel linking on minor loop complete
3922  *  0b0..The channel-to-channel linking is disabled
3923  *  0b1..The channel-to-channel linking is enabled
3924  */
3925 #define DMA_BITER_ELINKNO_ELINK(x) \
3926     (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
3927 /*! @} */
3928 
3929 /* The count of DMA_BITER_ELINKNO */
3930 #define DMA_BITER_ELINKNO_COUNT (8U)
3931 
3932 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3933 /*! @{ */
3934 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
3935 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
3936 /*! BITER - Starting major iteration count
3937  */
3938 #define DMA_BITER_ELINKYES_BITER(x) \
3939     (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
3940 #define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U)
3941 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
3942 /*! LINKCH - Link Channel Number
3943  */
3944 #define DMA_BITER_ELINKYES_LINKCH(x) \
3945     (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
3946 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
3947 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
3948 /*! ELINK - Enables channel-to-channel linking on minor loop complete
3949  *  0b0..The channel-to-channel linking is disabled
3950  *  0b1..The channel-to-channel linking is enabled
3951  */
3952 #define DMA_BITER_ELINKYES_ELINK(x) \
3953     (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
3954 /*! @} */
3955 
3956 /* The count of DMA_BITER_ELINKYES */
3957 #define DMA_BITER_ELINKYES_COUNT (8U)
3958 
3959 /*!
3960  * @}
3961  */ /* end of group DMA_Register_Masks */
3962 
3963 /* DMA - Peripheral instance base addresses */
3964 /** Peripheral DMA0 base address */
3965 #define DMA0_BASE (0x40008000u)
3966 /** Peripheral DMA0 base pointer */
3967 #define DMA0 ((DMA_Type *)DMA0_BASE)
3968 /** Array initializer of DMA peripheral base addresses */
3969 #define DMA_BASE_ADDRS \
3970     {                  \
3971         DMA0_BASE      \
3972     }
3973 /** Array initializer of DMA peripheral base pointers */
3974 #define DMA_BASE_PTRS \
3975     {                 \
3976         DMA0          \
3977     }
3978 /** Interrupt vectors for the DMA peripheral type */
3979 #define DMA_CHN_IRQS                                                                                          \
3980     {                                                                                                         \
3981         {                                                                                                     \
3982             DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn, DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, \
3983                 DMA0_37_IRQn                                                                                  \
3984         }                                                                                                     \
3985     }
3986 #define DMA_ERROR_IRQS       \
3987     {                        \
3988         CTI0_DMA0_Error_IRQn \
3989     }
3990 
3991 /*!
3992  * @}
3993  */ /* end of group DMA_Peripheral_Access_Layer */
3994 
3995 /* ----------------------------------------------------------------------------
3996    -- DMAMUX Peripheral Access Layer
3997    ---------------------------------------------------------------------------- */
3998 
3999 /*!
4000  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
4001  * @{
4002  */
4003 
4004 /** DMAMUX - Register Layout Typedef */
4005 typedef struct
4006 {
4007     __IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
4008 } DMAMUX_Type;
4009 
4010 /* ----------------------------------------------------------------------------
4011    -- DMAMUX Register Masks
4012    ---------------------------------------------------------------------------- */
4013 
4014 /*!
4015  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
4016  * @{
4017  */
4018 
4019 /*! @name CHCFG - Channel Configuration register */
4020 /*! @{ */
4021 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
4022 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
4023 /*! SOURCE - DMA Channel Source (Slot)
4024  */
4025 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
4026 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
4027 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
4028 /*! TRIG - DMA Channel Trigger Enable
4029  *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
4030  *       specified source to the DMA channel. (Normal mode)
4031  *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
4032  */
4033 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
4034 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
4035 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
4036 /*! ENBL - DMA Channel Enable
4037  *  0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has
4038  *       separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
4039  *  0b1..DMA channel is enabled
4040  */
4041 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
4042 /*! @} */
4043 
4044 /* The count of DMAMUX_CHCFG */
4045 #define DMAMUX_CHCFG_COUNT (8U)
4046 
4047 /*!
4048  * @}
4049  */ /* end of group DMAMUX_Register_Masks */
4050 
4051 /* DMAMUX - Peripheral instance base addresses */
4052 /** Peripheral DMAMUX0 base address */
4053 #define DMAMUX0_BASE (0x40021000u)
4054 /** Peripheral DMAMUX0 base pointer */
4055 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
4056 /** Array initializer of DMAMUX peripheral base addresses */
4057 #define DMAMUX_BASE_ADDRS \
4058     {                     \
4059         DMAMUX0_BASE      \
4060     }
4061 /** Array initializer of DMAMUX peripheral base pointers */
4062 #define DMAMUX_BASE_PTRS \
4063     {                    \
4064         DMAMUX0          \
4065     }
4066 
4067 /*!
4068  * @}
4069  */ /* end of group DMAMUX_Peripheral_Access_Layer */
4070 
4071 /* ----------------------------------------------------------------------------
4072    -- EMVSIM Peripheral Access Layer
4073    ---------------------------------------------------------------------------- */
4074 
4075 /*!
4076  * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
4077  * @{
4078  */
4079 
4080 /** EMVSIM - Register Layout Typedef */
4081 typedef struct
4082 {
4083     __I uint32_t VER_ID;      /**< Version ID Register, offset: 0x0 */
4084     __I uint32_t PARAM;       /**< Parameter Register, offset: 0x4 */
4085     __IO uint32_t CLKCFG;     /**< Clock Configuration Register, offset: 0x8 */
4086     __IO uint32_t DIVISOR;    /**< Baud Rate Divisor Register, offset: 0xC */
4087     __IO uint32_t CTRL;       /**< Control Register, offset: 0x10 */
4088     __IO uint32_t INT_MASK;   /**< Interrupt Mask Register, offset: 0x14 */
4089     __IO uint32_t RX_THD;     /**< Receiver Threshold Register, offset: 0x18 */
4090     __IO uint32_t TX_THD;     /**< Transmitter Threshold Register, offset: 0x1C */
4091     __IO uint32_t RX_STATUS;  /**< Receive Status Register, offset: 0x20 */
4092     __IO uint32_t TX_STATUS;  /**< Transmitter Status Register, offset: 0x24 */
4093     __IO uint32_t PCSR;       /**< Port Control and Status Register, offset: 0x28 */
4094     __I uint32_t RX_BUF;      /**< Receive Data Read Buffer, offset: 0x2C */
4095     __O uint32_t TX_BUF;      /**< Transmit Data Buffer, offset: 0x30 */
4096     __IO uint32_t TX_GETU;    /**< Transmitter Guard ETU Value Register, offset: 0x34 */
4097     __IO uint32_t CWT_VAL;    /**< Character Wait Time Value Register, offset: 0x38 */
4098     __IO uint32_t BWT_VAL;    /**< Block Wait Time Value Register, offset: 0x3C */
4099     __IO uint32_t BGT_VAL;    /**< Block Guard Time Value Register, offset: 0x40 */
4100     __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
4101     __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
4102 } EMVSIM_Type;
4103 
4104 /* ----------------------------------------------------------------------------
4105    -- EMVSIM Register Masks
4106    ---------------------------------------------------------------------------- */
4107 
4108 /*!
4109  * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
4110  * @{
4111  */
4112 
4113 /*! @name VER_ID - Version ID Register */
4114 /*! @{ */
4115 #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
4116 #define EMVSIM_VER_ID_VER_SHIFT (0U)
4117 /*! VER - Version ID of the module
4118  */
4119 #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
4120 /*! @} */
4121 
4122 /*! @name PARAM - Parameter Register */
4123 /*! @{ */
4124 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
4125 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
4126 /*! RX_FIFO_DEPTH - Receive FIFO Depth
4127  */
4128 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) \
4129     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
4130 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
4131 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
4132 /*! TX_FIFO_DEPTH - Transmit FIFO Depth
4133  */
4134 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) \
4135     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
4136 /*! @} */
4137 
4138 /*! @name CLKCFG - Clock Configuration Register */
4139 /*! @{ */
4140 #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
4141 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
4142 /*! CLK_PRSC - Clock Prescaler Value
4143  *  0b00000010..Divide by 2
4144  */
4145 #define EMVSIM_CLKCFG_CLK_PRSC(x) \
4146     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
4147 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
4148 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
4149 /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
4150  *  0b00..Disabled / Reset (default)
4151  *  0b01..Card Clock
4152  *  0b10..Receive Clock
4153  *  0b11..ETU Clock (transmit clock)
4154  */
4155 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) \
4156     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
4157 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
4158 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
4159 /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
4160  *  0b00..Disabled / Reset (default)
4161  *  0b01..Card Clock
4162  *  0b10..Receive Clock
4163  *  0b11..ETU Clock (transmit clock)
4164  */
4165 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) \
4166     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
4167 /*! @} */
4168 
4169 /*! @name DIVISOR - Baud Rate Divisor Register */
4170 /*! @{ */
4171 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
4172 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
4173 /*! DIVISOR_VALUE - Divisor (F/D) Value
4174  *  0b101110100..Divisor value for F = 372 and D = 1 (default)
4175  */
4176 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) \
4177     (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
4178 /*! @} */
4179 
4180 /*! @name CTRL - Control Register */
4181 /*! @{ */
4182 #define EMVSIM_CTRL_IC_MASK (0x1U)
4183 #define EMVSIM_CTRL_IC_SHIFT (0U)
4184 /*! IC - Inverse Convention
4185  *  0b0..Direction convention transfers enabled (default)
4186  *  0b1..Inverse convention transfers enabled
4187  */
4188 #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
4189 #define EMVSIM_CTRL_ICM_MASK (0x2U)
4190 #define EMVSIM_CTRL_ICM_SHIFT (1U)
4191 /*! ICM - Initial Character Mode
4192  *  0b0..Initial Character Mode disabled
4193  *  0b1..Initial Character Mode enabled (default)
4194  */
4195 #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
4196 #define EMVSIM_CTRL_ANACK_MASK (0x4U)
4197 #define EMVSIM_CTRL_ANACK_SHIFT (2U)
4198 /*! ANACK - Auto NACK Enable
4199  *  0b0..NACK generation on errors disabled
4200  *  0b1..NACK generation on errors enabled (default)
4201  */
4202 #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
4203 #define EMVSIM_CTRL_ONACK_MASK (0x8U)
4204 #define EMVSIM_CTRL_ONACK_SHIFT (3U)
4205 /*! ONACK - Overrun NACK Enable
4206  *  0b0..NACK generation on overrun is disabled (default)
4207  *  0b1..NACK generation on overrun is enabled
4208  */
4209 #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
4210 #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
4211 #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
4212 /*! FLSH_RX - Flush Receiver Bit
4213  *  0b0..EMV SIM Receiver normal operation (default)
4214  *  0b1..EMV SIM Receiver held in Reset
4215  */
4216 #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
4217 #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
4218 #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
4219 /*! FLSH_TX - Flush Transmitter Bit
4220  *  0b0..EMV SIM Transmitter normal operation (default)
4221  *  0b1..EMV SIM Transmitter held in Reset
4222  */
4223 #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
4224 #define EMVSIM_CTRL_SW_RST_MASK (0x400U)
4225 #define EMVSIM_CTRL_SW_RST_SHIFT (10U)
4226 /*! SW_RST - Software Reset Bit
4227  *  0b0..EMV SIM Normal operation (default)
4228  *  0b1..EMV SIM held in Reset
4229  */
4230 #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
4231 #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
4232 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
4233 /*! KILL_CLOCKS - Kill all internal clocks
4234  *  0b0..EMV SIM input clock enabled (default)
4235  *  0b1..EMV SIM input clock is disabled
4236  */
4237 #define EMVSIM_CTRL_KILL_CLOCKS(x) \
4238     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
4239 #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
4240 #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
4241 /*! DOZE_EN - Doze Enable
4242  *  0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO
4243  * is empty (default) 0b1..DOZE instruction has no effect on EMV SIM module
4244  */
4245 #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
4246 #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
4247 #define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
4248 /*! STOP_EN - STOP Enable
4249  *  0b0..STOP instruction shuts down all EMV SIM clocks (default)
4250  *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
4251  */
4252 #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
4253 #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
4254 #define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
4255 /*! RCV_EN - Receiver Enable
4256  *  0b0..EMV SIM Receiver disabled (default)
4257  *  0b1..EMV SIM Receiver enabled
4258  */
4259 #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
4260 #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
4261 #define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
4262 /*! XMT_EN - Transmitter Enable
4263  *  0b0..EMV SIM Transmitter disabled (default)
4264  *  0b1..EMV SIM Transmitter enabled
4265  */
4266 #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
4267 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
4268 #define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
4269 /*! RCVR_11 - Receiver 11 ETU Mode Enable
4270  *  0b0..Receiver configured for 12 ETU operation mode (default)
4271  *  0b1..Receiver configured for 11 ETU operation mode
4272  */
4273 #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
4274 #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
4275 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
4276 /*! RX_DMA_EN - Receive DMA Enable
4277  *  0b0..No DMA Read Request asserted for Receiver (default)
4278  *  0b1..DMA Read Request asserted for Receiver
4279  */
4280 #define EMVSIM_CTRL_RX_DMA_EN(x) \
4281     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
4282 #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
4283 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
4284 /*! TX_DMA_EN - Transmit DMA Enable
4285  *  0b0..No DMA Write Request asserted for Transmitter (default)
4286  *  0b1..DMA Write Request asserted for Transmitter
4287  */
4288 #define EMVSIM_CTRL_TX_DMA_EN(x) \
4289     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
4290 #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
4291 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
4292 /*! INV_CRC_VAL - Invert bits in the CRC Output Value
4293  *  0b0..Bits in CRC Output value will not be inverted.
4294  *  0b1..Bits in CRC Output value will be inverted. (default)
4295  */
4296 #define EMVSIM_CTRL_INV_CRC_VAL(x) \
4297     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
4298 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
4299 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
4300 /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
4301  *  0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
4302  *  0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
4303  */
4304 #define EMVSIM_CTRL_CRC_OUT_FLIP(x) \
4305     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
4306 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
4307 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
4308 /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
4309  *  0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
4310  *  0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
4311  */
4312 #define EMVSIM_CTRL_CRC_IN_FLIP(x) \
4313     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
4314 #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
4315 #define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
4316 /*! CWT_EN - Character Wait Time Counter Enable
4317  *  0b0..Character Wait time Counter is disabled (default)
4318  *  0b1..Character Wait time counter is enabled
4319  */
4320 #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
4321 #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
4322 #define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
4323 /*! LRC_EN - LRC Enable
4324  *  0b0..8-bit Linear Redundancy Checking disabled (default)
4325  *  0b1..8-bit Linear Redundancy Checking enabled
4326  */
4327 #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
4328 #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
4329 #define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
4330 /*! CRC_EN - CRC Enable
4331  *  0b0..16-bit Cyclic Redundancy Checking disabled (default)
4332  *  0b1..16-bit Cyclic Redundancy Checking enabled
4333  */
4334 #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
4335 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
4336 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
4337 /*! XMT_CRC_LRC - Transmit CRC or LRC Enable
4338  *  0b0..No CRC or LRC value is transmitted (default)
4339  *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
4340  */
4341 #define EMVSIM_CTRL_XMT_CRC_LRC(x) \
4342     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
4343 #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
4344 #define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
4345 /*! BWT_EN - Block Wait Time Counter Enable
4346  *  0b0..Disable BWT, BGT Counters (default)
4347  *  0b1..Enable BWT, BGT Counters
4348  */
4349 #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
4350 /*! @} */
4351 
4352 /*! @name INT_MASK - Interrupt Mask Register */
4353 /*! @{ */
4354 #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
4355 #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
4356 /*! RDT_IM - Receive Data Threshold Interrupt Mask
4357  *  0b0..RDTF interrupt enabled
4358  *  0b1..RDTF interrupt masked (default)
4359  */
4360 #define EMVSIM_INT_MASK_RDT_IM(x) \
4361     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
4362 #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
4363 #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
4364 /*! TC_IM - Transmit Complete Interrupt Mask
4365  *  0b0..TCF interrupt enabled
4366  *  0b1..TCF interrupt masked (default)
4367  */
4368 #define EMVSIM_INT_MASK_TC_IM(x) \
4369     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
4370 #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
4371 #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
4372 /*! RFO_IM - Receive FIFO Overflow Interrupt Mask
4373  *  0b0..RFO interrupt enabled
4374  *  0b1..RFO interrupt masked (default)
4375  */
4376 #define EMVSIM_INT_MASK_RFO_IM(x) \
4377     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
4378 #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
4379 #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
4380 /*! ETC_IM - Early Transmit Complete Interrupt Mask
4381  *  0b0..ETC interrupt enabled
4382  *  0b1..ETC interrupt masked (default)
4383  */
4384 #define EMVSIM_INT_MASK_ETC_IM(x) \
4385     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
4386 #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
4387 #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
4388 /*! TFE_IM - Transmit FIFO Empty Interrupt Mask
4389  *  0b0..TFE interrupt enabled
4390  *  0b1..TFE interrupt masked (default)
4391  */
4392 #define EMVSIM_INT_MASK_TFE_IM(x) \
4393     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
4394 #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
4395 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
4396 /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
4397  *  0b0..TNTE interrupt enabled
4398  *  0b1..TNTE interrupt masked (default)
4399  */
4400 #define EMVSIM_INT_MASK_TNACK_IM(x) \
4401     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
4402 #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
4403 #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
4404 /*! TFF_IM - Transmit FIFO Full Interrupt Mask
4405  *  0b0..TFF interrupt enabled
4406  *  0b1..TFF interrupt masked (default)
4407  */
4408 #define EMVSIM_INT_MASK_TFF_IM(x) \
4409     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
4410 #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
4411 #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
4412 /*! TDT_IM - Transmit Data Threshold Interrupt Mask
4413  *  0b0..TDTF interrupt enabled
4414  *  0b1..TDTF interrupt masked (default)
4415  */
4416 #define EMVSIM_INT_MASK_TDT_IM(x) \
4417     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
4418 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
4419 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
4420 /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
4421  *  0b0..GPCNT0_TO interrupt enabled
4422  *  0b1..GPCNT0_TO interrupt masked (default)
4423  */
4424 #define EMVSIM_INT_MASK_GPCNT0_IM(x) \
4425     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
4426 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
4427 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
4428 /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
4429  *  0b0..CWT_ERR interrupt enabled
4430  *  0b1..CWT_ERR interrupt masked (default)
4431  */
4432 #define EMVSIM_INT_MASK_CWT_ERR_IM(x) \
4433     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
4434 #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
4435 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
4436 /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
4437  *  0b0..RTE interrupt enabled
4438  *  0b1..RTE interrupt masked (default)
4439  */
4440 #define EMVSIM_INT_MASK_RNACK_IM(x) \
4441     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
4442 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
4443 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
4444 /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
4445  *  0b0..BWT_ERR interrupt enabled
4446  *  0b1..BWT_ERR interrupt masked (default)
4447  */
4448 #define EMVSIM_INT_MASK_BWT_ERR_IM(x) \
4449     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
4450 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
4451 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
4452 /*! BGT_ERR_IM - Block Guard Time Error Interrupt
4453  *  0b0..BGT_ERR interrupt enabled
4454  *  0b1..BGT_ERR interrupt masked (default)
4455  */
4456 #define EMVSIM_INT_MASK_BGT_ERR_IM(x) \
4457     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
4458 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
4459 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
4460 /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
4461  *  0b0..GPCNT1_TO interrupt enabled
4462  *  0b1..GPCNT1_TO interrupt masked (default)
4463  */
4464 #define EMVSIM_INT_MASK_GPCNT1_IM(x) \
4465     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
4466 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
4467 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
4468 /*! RX_DATA_IM - Receive Data Interrupt Mask
4469  *  0b0..RX_DATA interrupt enabled
4470  *  0b1..RX_DATA interrupt masked (default)
4471  */
4472 #define EMVSIM_INT_MASK_RX_DATA_IM(x) \
4473     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
4474 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
4475 #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
4476 /*! PEF_IM - Parity Error Interrupt Mask
4477  *  0b0..PEF interrupt enabled
4478  *  0b1..PEF interrupt masked (default)
4479  */
4480 #define EMVSIM_INT_MASK_PEF_IM(x) \
4481     (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
4482 /*! @} */
4483 
4484 /*! @name RX_THD - Receiver Threshold Register */
4485 /*! @{ */
4486 #define EMVSIM_RX_THD_RDT_MASK (0xFU)
4487 #define EMVSIM_RX_THD_RDT_SHIFT (0U)
4488 /*! RDT - Receiver Data Threshold Value
4489  */
4490 #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
4491 #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
4492 #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
4493 /*! RNCK_THD - Receiver NACK Threshold Value
4494  *  0b0000..Zero Threshold. RTE will not be set
4495  */
4496 #define EMVSIM_RX_THD_RNCK_THD(x) \
4497     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
4498 /*! @} */
4499 
4500 /*! @name TX_THD - Transmitter Threshold Register */
4501 /*! @{ */
4502 #define EMVSIM_TX_THD_TDT_MASK (0xFU)
4503 #define EMVSIM_TX_THD_TDT_SHIFT (0U)
4504 /*! TDT - Transmitter Data Threshold Value
4505  */
4506 #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
4507 #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
4508 #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
4509 /*! TNCK_THD - Transmitter NACK Threshold Value
4510  *  0b0000..TNTE will never be set; retransmission after NACK reception is disabled.
4511  *  0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs.
4512  *  0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
4513  *  0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
4514  *  0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
4515  */
4516 #define EMVSIM_TX_THD_TNCK_THD(x) \
4517     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
4518 /*! @} */
4519 
4520 /*! @name RX_STATUS - Receive Status Register */
4521 /*! @{ */
4522 #define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
4523 #define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
4524 /*! RFO - Receive FIFO Overflow Flag
4525  *  0b0..No overrun error has occurred (default)
4526  *  0b1..A byte was received when the received FIFO was already full
4527  */
4528 #define EMVSIM_RX_STATUS_RFO(x) \
4529     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
4530 #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
4531 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
4532 /*! RX_DATA - Receive Data Interrupt Flag
4533  *  0b0..No new byte is received
4534  *  0b1..New byte is received ans stored in Receive FIFO
4535  */
4536 #define EMVSIM_RX_STATUS_RX_DATA(x) \
4537     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
4538 #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
4539 #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
4540 /*! RDTF - Receive Data Threshold Interrupt Flag
4541  *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
4542  *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
4543  */
4544 #define EMVSIM_RX_STATUS_RDTF(x) \
4545     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
4546 #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
4547 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
4548 /*! LRC_OK - LRC Check OK Flag
4549  *  0b0..Current LRC value does not match remainder.
4550  *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
4551  */
4552 #define EMVSIM_RX_STATUS_LRC_OK(x) \
4553     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
4554 #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
4555 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
4556 /*! CRC_OK - CRC Check OK Flag
4557  *  0b0..Current CRC value does not match remainder.
4558  *  0b1..Current calculated CRC value matches the expected result.
4559  */
4560 #define EMVSIM_RX_STATUS_CRC_OK(x) \
4561     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
4562 #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
4563 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
4564 /*! CWT_ERR - Character Wait Time Error Flag
4565  *  0b0..No CWT violation has occurred (default).
4566  *  0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT.
4567  */
4568 #define EMVSIM_RX_STATUS_CWT_ERR(x) \
4569     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
4570 #define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
4571 #define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
4572 /*! RTE - Received NACK Threshold Error Flag
4573  *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
4574  *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
4575  */
4576 #define EMVSIM_RX_STATUS_RTE(x) \
4577     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
4578 #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
4579 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
4580 /*! BWT_ERR - Block Wait Time Error Flag
4581  *  0b0..Block wait time not exceeded
4582  *  0b1..Block wait time was exceeded
4583  */
4584 #define EMVSIM_RX_STATUS_BWT_ERR(x) \
4585     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
4586 #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
4587 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
4588 /*! BGT_ERR - Block Guard Time Error Flag
4589  *  0b0..Block guard time was sufficient
4590  *  0b1..Block guard time was too small
4591  */
4592 #define EMVSIM_RX_STATUS_BGT_ERR(x) \
4593     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
4594 #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
4595 #define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
4596 /*! PEF - Parity Error Flag
4597  *  0b0..No parity error detected
4598  *  0b1..Parity error detected
4599  */
4600 #define EMVSIM_RX_STATUS_PEF(x) \
4601     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
4602 #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
4603 #define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
4604 /*! FEF - Frame Error Flag
4605  *  0b0..No frame error detected
4606  *  0b1..Frame error detected
4607  */
4608 #define EMVSIM_RX_STATUS_FEF(x) \
4609     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
4610 #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0x30000U)
4611 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
4612 /*! RX_WPTR - Receive FIFO Write Pointer Value
4613  */
4614 #define EMVSIM_RX_STATUS_RX_WPTR(x) \
4615     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
4616 #define EMVSIM_RX_STATUS_RX_CNT_MASK (0x1C00000U)
4617 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (22U)
4618 /*! RX_CNT - Receive FIFO Byte Count
4619  *  0b000..FIFO is emtpy
4620  */
4621 #define EMVSIM_RX_STATUS_RX_CNT(x) \
4622     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
4623 /*! @} */
4624 
4625 /*! @name TX_STATUS - Transmitter Status Register */
4626 /*! @{ */
4627 #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
4628 #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
4629 /*! TNTE - Transmit NACK Threshold Error Flag
4630  *  0b0..Transmit NACK threshold has not been reached (default)
4631  *  0b1..Transmit NACK threshold reached; transmitter frozen
4632  */
4633 #define EMVSIM_TX_STATUS_TNTE(x) \
4634     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
4635 #define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
4636 #define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
4637 /*! TFE - Transmit FIFO Empty Flag
4638  *  0b0..Transmit FIFO is not empty
4639  *  0b1..Transmit FIFO is empty (default)
4640  */
4641 #define EMVSIM_TX_STATUS_TFE(x) \
4642     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
4643 #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
4644 #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
4645 /*! ETCF - Early Transmit Complete Flag
4646  *  0b0..Transmit pending or in progress
4647  *  0b1..Transmit complete (default)
4648  */
4649 #define EMVSIM_TX_STATUS_ETCF(x) \
4650     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
4651 #define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
4652 #define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
4653 /*! TCF - Transmit Complete Flag
4654  *  0b0..Transmit pending or in progress
4655  *  0b1..Transmit complete (default)
4656  */
4657 #define EMVSIM_TX_STATUS_TCF(x) \
4658     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
4659 #define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
4660 #define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
4661 /*! TFF - Transmit FIFO Full Flag
4662  *  0b0..Transmit FIFO Full condition has not occurred (default)
4663  *  0b1..A Transmit FIFO Full condition has occurred
4664  */
4665 #define EMVSIM_TX_STATUS_TFF(x) \
4666     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
4667 #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
4668 #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
4669 /*! TDTF - Transmit Data Threshold Flag
4670  *  0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
4671  *  0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
4672  */
4673 #define EMVSIM_TX_STATUS_TDTF(x) \
4674     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
4675 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
4676 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
4677 /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
4678  *  0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default)
4679  *  0b1..General Purpose counter has reached the GPCNT0_VAL value
4680  */
4681 #define EMVSIM_TX_STATUS_GPCNT0_TO(x) \
4682     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
4683 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
4684 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
4685 /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
4686  *  0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default)
4687  *  0b1..General Purpose counter has reached the GPCNT1_VAL value
4688  */
4689 #define EMVSIM_TX_STATUS_GPCNT1_TO(x) \
4690     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
4691 #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0x30000U)
4692 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
4693 /*! TX_RPTR - Transmit FIFO Read Pointer
4694  */
4695 #define EMVSIM_TX_STATUS_TX_RPTR(x) \
4696     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
4697 #define EMVSIM_TX_STATUS_TX_CNT_MASK (0x1C00000U)
4698 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (22U)
4699 /*! TX_CNT - Transmit FIFO Byte Count
4700  *  0b000..FIFO is emtpy
4701  */
4702 #define EMVSIM_TX_STATUS_TX_CNT(x) \
4703     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
4704 /*! @} */
4705 
4706 /*! @name PCSR - Port Control and Status Register */
4707 /*! @{ */
4708 #define EMVSIM_PCSR_SAPD_MASK (0x1U)
4709 #define EMVSIM_PCSR_SAPD_SHIFT (0U)
4710 /*! SAPD - Auto Power Down Enable
4711  *  0b0..Auto power down disabled (default)
4712  *  0b1..Auto power down enabled
4713  */
4714 #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
4715 #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
4716 #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
4717 /*! SVCC_EN - Vcc Enable for Smart Card
4718  *  0b0..Smart Card Voltage disabled (default)
4719  *  0b1..Smart Card Voltage enabled
4720  */
4721 #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
4722 #define EMVSIM_PCSR_VCCENP_MASK (0x4U)
4723 #define EMVSIM_PCSR_VCCENP_SHIFT (2U)
4724 /*! VCCENP - VCC Enable Polarity Control
4725  *  0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged.
4726  *  0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted.
4727  */
4728 #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
4729 #define EMVSIM_PCSR_SRST_MASK (0x8U)
4730 #define EMVSIM_PCSR_SRST_SHIFT (3U)
4731 /*! SRST - Reset to Smart Card
4732  *  0b0..Smart Card Reset is asserted (default)
4733  *  0b1..Smart Card Reset is de-asserted
4734  */
4735 #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
4736 #define EMVSIM_PCSR_SCEN_MASK (0x10U)
4737 #define EMVSIM_PCSR_SCEN_SHIFT (4U)
4738 /*! SCEN - Clock Enable for Smart Card
4739  *  0b0..Smart Card Clock Disabled
4740  *  0b1..Smart Card Clock Enabled
4741  */
4742 #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
4743 #define EMVSIM_PCSR_SCSP_MASK (0x20U)
4744 #define EMVSIM_PCSR_SCSP_SHIFT (5U)
4745 /*! SCSP - Smart Card Clock Stop Polarity
4746  *  0b0..Clock is logic 0 when stopped by SCEN
4747  *  0b1..Clock is logic 1 when stopped by SCEN
4748  */
4749 #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
4750 #define EMVSIM_PCSR_SPD_MASK (0x80U)
4751 #define EMVSIM_PCSR_SPD_SHIFT (7U)
4752 /*! SPD - Auto Power Down Control
4753  *  0b0..No effect (default)
4754  *  0b1..Start Auto Powerdown or Power Down is in progress
4755  */
4756 #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
4757 #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
4758 #define EMVSIM_PCSR_SPDIM_SHIFT (24U)
4759 /*! SPDIM - Smart Card Presence Detect Interrupt Mask
4760  *  0b0..SIM presence detect interrupt is enabled
4761  *  0b1..SIM presence detect interrupt is masked (default)
4762  */
4763 #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
4764 #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
4765 #define EMVSIM_PCSR_SPDIF_SHIFT (25U)
4766 /*! SPDIF - Smart Card Presence Detect Interrupt Flag
4767  *  0b0..No insertion or removal of Smart Card detected on Port (default)
4768  *  0b1..Insertion or removal of Smart Card detected on Port
4769  */
4770 #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
4771 #define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
4772 #define EMVSIM_PCSR_SPDP_SHIFT (26U)
4773 /*! SPDP - Smart Card Presence Detect Pin Status
4774  *  0b0..SIM Presence Detect pin is logic low
4775  *  0b1..SIM Presence Detectpin is logic high
4776  */
4777 #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
4778 #define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
4779 #define EMVSIM_PCSR_SPDES_SHIFT (27U)
4780 /*! SPDES - SIM Presence Detect Edge Select
4781  *  0b0..Falling edge on the pin (default)
4782  *  0b1..Rising edge on the pin
4783  */
4784 #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
4785 /*! @} */
4786 
4787 /*! @name RX_BUF - Receive Data Read Buffer */
4788 /*! @{ */
4789 #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
4790 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
4791 /*! RX_BYTE - Receive Data Byte Read
4792  */
4793 #define EMVSIM_RX_BUF_RX_BYTE(x) \
4794     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
4795 /*! @} */
4796 
4797 /*! @name TX_BUF - Transmit Data Buffer */
4798 /*! @{ */
4799 #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
4800 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
4801 /*! TX_BYTE - Transmit Data Byte
4802  */
4803 #define EMVSIM_TX_BUF_TX_BYTE(x) \
4804     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
4805 /*! @} */
4806 
4807 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
4808 /*! @{ */
4809 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
4810 #define EMVSIM_TX_GETU_GETU_SHIFT (0U)
4811 /*! GETU - Transmitter Guard Time Value in ETU
4812  *  0b00000000..no additional ETUs inserted (default)
4813  *  0b00000001..1 additional ETU inserted
4814  *  0b11111110..254 additional ETUs inserted
4815  *  0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one
4816  */
4817 #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
4818 /*! @} */
4819 
4820 /*! @name CWT_VAL - Character Wait Time Value Register */
4821 /*! @{ */
4822 #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
4823 #define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
4824 /*! CWT - Character Wait Time Value
4825  */
4826 #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
4827 /*! @} */
4828 
4829 /*! @name BWT_VAL - Block Wait Time Value Register */
4830 /*! @{ */
4831 #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
4832 #define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
4833 /*! BWT - Block Wait Time Value
4834  */
4835 #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
4836 /*! @} */
4837 
4838 /*! @name BGT_VAL - Block Guard Time Value Register */
4839 /*! @{ */
4840 #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
4841 #define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
4842 /*! BGT - Block Guard Time Value
4843  */
4844 #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
4845 /*! @} */
4846 
4847 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
4848 /*! @{ */
4849 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
4850 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
4851 /*! GPCNT0 - General Purpose Counter 0 Timeout Value
4852  */
4853 #define EMVSIM_GPCNT0_VAL_GPCNT0(x) \
4854     (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
4855 /*! @} */
4856 
4857 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
4858 /*! @{ */
4859 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
4860 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
4861 /*! GPCNT1 - General Purpose Counter 1 Timeout Value
4862  */
4863 #define EMVSIM_GPCNT1_VAL_GPCNT1(x) \
4864     (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
4865 /*! @} */
4866 
4867 /*!
4868  * @}
4869  */ /* end of group EMVSIM_Register_Masks */
4870 
4871 /* EMVSIM - Peripheral instance base addresses */
4872 /** Peripheral EMVSIM0 base address */
4873 #define EMVSIM0_BASE (0x4004E000u)
4874 /** Peripheral EMVSIM0 base pointer */
4875 #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
4876 /** Array initializer of EMVSIM peripheral base addresses */
4877 #define EMVSIM_BASE_ADDRS \
4878     {                     \
4879         EMVSIM0_BASE      \
4880     }
4881 /** Array initializer of EMVSIM peripheral base pointers */
4882 #define EMVSIM_BASE_PTRS \
4883     {                    \
4884         EMVSIM0          \
4885     }
4886 /** Interrupt vectors for the EMVSIM peripheral type */
4887 #define EMVSIM_IRQS  \
4888     {                \
4889         EMVSIM0_IRQn \
4890     }
4891 
4892 /*!
4893  * @}
4894  */ /* end of group EMVSIM_Peripheral_Access_Layer */
4895 
4896 /* ----------------------------------------------------------------------------
4897    -- FGPIO Peripheral Access Layer
4898    ---------------------------------------------------------------------------- */
4899 
4900 /*!
4901  * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
4902  * @{
4903  */
4904 
4905 /** FGPIO - Register Layout Typedef */
4906 typedef struct
4907 {
4908     __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
4909     __O uint32_t PSOR;  /**< Port Set Output Register, offset: 0x4 */
4910     __O uint32_t PCOR;  /**< Port Clear Output Register, offset: 0x8 */
4911     __O uint32_t PTOR;  /**< Port Toggle Output Register, offset: 0xC */
4912     __I uint32_t PDIR;  /**< Port Data Input Register, offset: 0x10 */
4913     __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
4914 } FGPIO_Type;
4915 
4916 /* ----------------------------------------------------------------------------
4917    -- FGPIO Register Masks
4918    ---------------------------------------------------------------------------- */
4919 
4920 /*!
4921  * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
4922  * @{
4923  */
4924 
4925 /*! @name PDOR - Port Data Output Register */
4926 /*! @{ */
4927 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
4928 #define FGPIO_PDOR_PDO_SHIFT (0U)
4929 /*! PDO - Port Data Output
4930  *  0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose
4931  * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for
4932  * general-purpose output.
4933  */
4934 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
4935 /*! @} */
4936 
4937 /*! @name PSOR - Port Set Output Register */
4938 /*! @{ */
4939 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
4940 #define FGPIO_PSOR_PTSO_SHIFT (0U)
4941 /*! PTSO - Port Set Output
4942  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
4943  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
4944  */
4945 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
4946 /*! @} */
4947 
4948 /*! @name PCOR - Port Clear Output Register */
4949 /*! @{ */
4950 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
4951 #define FGPIO_PCOR_PTCO_SHIFT (0U)
4952 /*! PTCO - Port Clear Output
4953  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
4954  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
4955  */
4956 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
4957 /*! @} */
4958 
4959 /*! @name PTOR - Port Toggle Output Register */
4960 /*! @{ */
4961 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
4962 #define FGPIO_PTOR_PTTO_SHIFT (0U)
4963 /*! PTTO - Port Toggle Output
4964  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
4965  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
4966  */
4967 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
4968 /*! @} */
4969 
4970 /*! @name PDIR - Port Data Input Register */
4971 /*! @{ */
4972 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
4973 #define FGPIO_PDIR_PDI_SHIFT (0U)
4974 /*! PDI - Port Data Input
4975  *  0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
4976  *  0b00000000000000000000000000000001..Pin logic level is logic 1.
4977  */
4978 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
4979 /*! @} */
4980 
4981 /*! @name PDDR - Port Data Direction Register */
4982 /*! @{ */
4983 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
4984 #define FGPIO_PDDR_PDD_SHIFT (0U)
4985 /*! PDD - Port Data Direction
4986  *  0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
4987  *  0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
4988  */
4989 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
4990 /*! @} */
4991 
4992 /*!
4993  * @}
4994  */ /* end of group FGPIO_Register_Masks */
4995 
4996 /* FGPIO - Peripheral instance base addresses */
4997 /** Peripheral FGPIOA base address */
4998 #define FGPIOA_BASE (0xF8000000u)
4999 /** Peripheral FGPIOA base pointer */
5000 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
5001 /** Array initializer of FGPIO peripheral base addresses */
5002 #define FGPIO_BASE_ADDRS \
5003     {                    \
5004         FGPIOA_BASE      \
5005     }
5006 /** Array initializer of FGPIO peripheral base pointers */
5007 #define FGPIO_BASE_PTRS \
5008     {                   \
5009         FGPIOA          \
5010     }
5011 
5012 /*!
5013  * @}
5014  */ /* end of group FGPIO_Peripheral_Access_Layer */
5015 
5016 /* ----------------------------------------------------------------------------
5017    -- FLEXIO Peripheral Access Layer
5018    ---------------------------------------------------------------------------- */
5019 
5020 /*!
5021  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
5022  * @{
5023  */
5024 
5025 /** FLEXIO - Register Layout Typedef */
5026 typedef struct
5027 {
5028     __I uint32_t VERID;      /**< Version ID Register, offset: 0x0 */
5029     __I uint32_t PARAM;      /**< Parameter Register, offset: 0x4 */
5030     __IO uint32_t CTRL;      /**< FlexIO Control Register, offset: 0x8 */
5031     __I uint32_t PIN;        /**< Pin State Register, offset: 0xC */
5032     __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
5033     __IO uint32_t SHIFTERR;  /**< Shifter Error Register, offset: 0x14 */
5034     __IO uint32_t TIMSTAT;   /**< Timer Status Register, offset: 0x18 */
5035     uint8_t RESERVED_0[4];
5036     __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
5037     __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
5038     __IO uint32_t TIMIEN;    /**< Timer Interrupt Enable Register, offset: 0x28 */
5039     uint8_t RESERVED_1[4];
5040     __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
5041     uint8_t RESERVED_2[12];
5042     __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
5043     uint8_t RESERVED_3[60];
5044     __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
5045     uint8_t RESERVED_4[96];
5046     __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
5047     uint8_t RESERVED_5[224];
5048     __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
5049     uint8_t RESERVED_6[96];
5050     __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
5051     uint8_t RESERVED_7[96];
5052     __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
5053     uint8_t RESERVED_8[96];
5054     __IO uint32_t
5055         SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
5056     uint8_t RESERVED_9[96];
5057     __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
5058     uint8_t RESERVED_10[96];
5059     __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
5060     uint8_t RESERVED_11[96];
5061     __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
5062     uint8_t RESERVED_12[352];
5063     __IO uint32_t
5064         SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
5065     uint8_t RESERVED_13[96];
5066     __IO uint32_t
5067         SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
5068     uint8_t RESERVED_14[96];
5069     __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
5070 } FLEXIO_Type;
5071 
5072 /* ----------------------------------------------------------------------------
5073    -- FLEXIO Register Masks
5074    ---------------------------------------------------------------------------- */
5075 
5076 /*!
5077  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
5078  * @{
5079  */
5080 
5081 /*! @name VERID - Version ID Register */
5082 /*! @{ */
5083 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
5084 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
5085 /*! FEATURE - Feature Specification Number
5086  *  0b0000000000000000..Standard features implemented.
5087  *  0b0000000000000001..Supports state, logic and parallel modes.
5088  */
5089 #define FLEXIO_VERID_FEATURE(x) \
5090     (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
5091 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
5092 #define FLEXIO_VERID_MINOR_SHIFT (16U)
5093 /*! MINOR - Minor Version Number
5094  */
5095 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
5096 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
5097 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
5098 /*! MAJOR - Major Version Number
5099  */
5100 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
5101 /*! @} */
5102 
5103 /*! @name PARAM - Parameter Register */
5104 /*! @{ */
5105 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
5106 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
5107 /*! SHIFTER - Shifter Number
5108  */
5109 #define FLEXIO_PARAM_SHIFTER(x) \
5110     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
5111 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
5112 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
5113 /*! TIMER - Timer Number
5114  */
5115 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
5116 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
5117 #define FLEXIO_PARAM_PIN_SHIFT (16U)
5118 /*! PIN - Pin Number
5119  */
5120 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
5121 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
5122 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
5123 /*! TRIGGER - Trigger Number
5124  */
5125 #define FLEXIO_PARAM_TRIGGER(x) \
5126     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
5127 /*! @} */
5128 
5129 /*! @name CTRL - FlexIO Control Register */
5130 /*! @{ */
5131 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
5132 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
5133 /*! FLEXEN - FlexIO Enable
5134  *  0b0..FlexIO module is disabled.
5135  *  0b1..FlexIO module is enabled.
5136  */
5137 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
5138 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
5139 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
5140 /*! SWRST - Software Reset
5141  *  0b0..Software reset is disabled
5142  *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
5143  */
5144 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
5145 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
5146 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
5147 /*! FASTACC - Fast Access
5148  *  0b0..Configures for normal register accesses to FlexIO
5149  *  0b1..Configures for fast register accesses to FlexIO
5150  */
5151 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
5152 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
5153 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
5154 /*! DBGE - Debug Enable
5155  *  0b0..FlexIO is disabled in debug modes.
5156  *  0b1..FlexIO is enabled in debug modes
5157  */
5158 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
5159 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
5160 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
5161 /*! DOZEN - Doze Enable
5162  *  0b0..FlexIO enabled in Doze modes.
5163  *  0b1..FlexIO disabled in Doze modes.
5164  */
5165 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
5166 /*! @} */
5167 
5168 /*! @name PIN - Pin State Register */
5169 /*! @{ */
5170 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
5171 #define FLEXIO_PIN_PDI_SHIFT (0U)
5172 /*! PDI - Pin Data Input
5173  */
5174 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
5175 /*! @} */
5176 
5177 /*! @name SHIFTSTAT - Shifter Status Register */
5178 /*! @{ */
5179 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
5180 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
5181 /*! SSF - Shifter Status Flag
5182  *  0b00000000..Status flag is clear
5183  *  0b00000001..Status flag is set
5184  */
5185 #define FLEXIO_SHIFTSTAT_SSF(x) \
5186     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
5187 /*! @} */
5188 
5189 /*! @name SHIFTERR - Shifter Error Register */
5190 /*! @{ */
5191 #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
5192 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
5193 /*! SEF - Shifter Error Flags
5194  *  0b00000000..Shifter Error Flag is clear
5195  *  0b00000001..Shifter Error Flag is set
5196  */
5197 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
5198 /*! @} */
5199 
5200 /*! @name TIMSTAT - Timer Status Register */
5201 /*! @{ */
5202 #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
5203 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
5204 /*! TSF - Timer Status Flags
5205  *  0b00000000..Timer Status Flag is clear
5206  *  0b00000001..Timer Status Flag is set
5207  */
5208 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
5209 /*! @} */
5210 
5211 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
5212 /*! @{ */
5213 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
5214 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
5215 /*! SSIE - Shifter Status Interrupt Enable
5216  *  0b00000000..Shifter Status Flag interrupt disabled
5217  *  0b00000001..Shifter Status Flag interrupt enabled
5218  */
5219 #define FLEXIO_SHIFTSIEN_SSIE(x) \
5220     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
5221 /*! @} */
5222 
5223 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
5224 /*! @{ */
5225 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
5226 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
5227 /*! SEIE - Shifter Error Interrupt Enable
5228  *  0b00000000..Shifter Error Flag interrupt disabled
5229  *  0b00000001..Shifter Error Flag interrupt enabled
5230  */
5231 #define FLEXIO_SHIFTEIEN_SEIE(x) \
5232     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
5233 /*! @} */
5234 
5235 /*! @name TIMIEN - Timer Interrupt Enable Register */
5236 /*! @{ */
5237 #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
5238 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
5239 /*! TEIE - Timer Status Interrupt Enable
5240  *  0b00000000..Timer Status Flag interrupt is disabled
5241  *  0b00000001..Timer Status Flag interrupt is enabled
5242  */
5243 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
5244 /*! @} */
5245 
5246 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
5247 /*! @{ */
5248 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
5249 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
5250 /*! SSDE - Shifter Status DMA Enable
5251  *  0b00000000..Shifter Status Flag DMA request is disabled
5252  *  0b00000001..Shifter Status Flag DMA request is enabled
5253  */
5254 #define FLEXIO_SHIFTSDEN_SSDE(x) \
5255     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
5256 /*! @} */
5257 
5258 /*! @name SHIFTSTATE - Shifter State Register */
5259 /*! @{ */
5260 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
5261 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
5262 /*! STATE - Current State Pointer
5263  */
5264 #define FLEXIO_SHIFTSTATE_STATE(x) \
5265     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
5266 /*! @} */
5267 
5268 /*! @name SHIFTCTL - Shifter Control N Register */
5269 /*! @{ */
5270 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
5271 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
5272 /*! SMOD - Shifter Mode
5273  *  0b000..Disabled.
5274  *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
5275  *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
5276  *  0b011..Reserved.
5277  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
5278  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
5279  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
5280  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
5281  */
5282 #define FLEXIO_SHIFTCTL_SMOD(x) \
5283     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
5284 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
5285 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
5286 /*! PINPOL - Shifter Pin Polarity
5287  *  0b0..Pin is active high
5288  *  0b1..Pin is active low
5289  */
5290 #define FLEXIO_SHIFTCTL_PINPOL(x) \
5291     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
5292 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
5293 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
5294 /*! PINSEL - Shifter Pin Select
5295  */
5296 #define FLEXIO_SHIFTCTL_PINSEL(x) \
5297     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
5298 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
5299 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
5300 /*! PINCFG - Shifter Pin Configuration
5301  *  0b00..Shifter pin output disabled
5302  *  0b01..Shifter pin open drain or bidirectional output enable
5303  *  0b10..Shifter pin bidirectional output data
5304  *  0b11..Shifter pin output
5305  */
5306 #define FLEXIO_SHIFTCTL_PINCFG(x) \
5307     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
5308 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
5309 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
5310 /*! TIMPOL - Timer Polarity
5311  *  0b0..Shift on posedge of Shift clock
5312  *  0b1..Shift on negedge of Shift clock
5313  */
5314 #define FLEXIO_SHIFTCTL_TIMPOL(x) \
5315     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
5316 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
5317 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
5318 /*! TIMSEL - Timer Select
5319  */
5320 #define FLEXIO_SHIFTCTL_TIMSEL(x) \
5321     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
5322 /*! @} */
5323 
5324 /* The count of FLEXIO_SHIFTCTL */
5325 #define FLEXIO_SHIFTCTL_COUNT (8U)
5326 
5327 /*! @name SHIFTCFG - Shifter Configuration N Register */
5328 /*! @{ */
5329 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
5330 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
5331 /*! SSTART - Shifter Start bit
5332  *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
5333  *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
5334  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag
5335  * if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match
5336  * store sets error flag if start bit is not 1
5337  */
5338 #define FLEXIO_SHIFTCFG_SSTART(x) \
5339     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
5340 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
5341 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
5342 /*! SSTOP - Shifter Stop bit
5343  *  0b00..Stop bit disabled for transmitter/receiver/match store
5344  *  0b01..Reserved for transmitter/receiver/match store
5345  *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
5346  *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
5347  */
5348 #define FLEXIO_SHIFTCFG_SSTOP(x) \
5349     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
5350 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
5351 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
5352 /*! INSRC - Input Source
5353  *  0b0..Pin
5354  *  0b1..Shifter N+1 Output
5355  */
5356 #define FLEXIO_SHIFTCFG_INSRC(x) \
5357     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
5358 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
5359 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
5360 /*! PWIDTH - Parallel Width
5361  */
5362 #define FLEXIO_SHIFTCFG_PWIDTH(x) \
5363     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
5364 /*! @} */
5365 
5366 /* The count of FLEXIO_SHIFTCFG */
5367 #define FLEXIO_SHIFTCFG_COUNT (8U)
5368 
5369 /*! @name SHIFTBUF - Shifter Buffer N Register */
5370 /*! @{ */
5371 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
5372 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
5373 /*! SHIFTBUF - Shift Buffer
5374  */
5375 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) \
5376     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
5377 /*! @} */
5378 
5379 /* The count of FLEXIO_SHIFTBUF */
5380 #define FLEXIO_SHIFTBUF_COUNT (8U)
5381 
5382 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
5383 /*! @{ */
5384 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
5385 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
5386 /*! SHIFTBUFBIS - Shift Buffer
5387  */
5388 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) \
5389     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
5390 /*! @} */
5391 
5392 /* The count of FLEXIO_SHIFTBUFBIS */
5393 #define FLEXIO_SHIFTBUFBIS_COUNT (8U)
5394 
5395 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
5396 /*! @{ */
5397 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
5398 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
5399 /*! SHIFTBUFBYS - Shift Buffer
5400  */
5401 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) \
5402     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
5403 /*! @} */
5404 
5405 /* The count of FLEXIO_SHIFTBUFBYS */
5406 #define FLEXIO_SHIFTBUFBYS_COUNT (8U)
5407 
5408 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
5409 /*! @{ */
5410 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
5411 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
5412 /*! SHIFTBUFBBS - Shift Buffer
5413  */
5414 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) \
5415     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
5416 /*! @} */
5417 
5418 /* The count of FLEXIO_SHIFTBUFBBS */
5419 #define FLEXIO_SHIFTBUFBBS_COUNT (8U)
5420 
5421 /*! @name TIMCTL - Timer Control N Register */
5422 /*! @{ */
5423 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
5424 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
5425 /*! TIMOD - Timer Mode
5426  *  0b00..Timer Disabled.
5427  *  0b01..Dual 8-bit counters baud/bit mode.
5428  *  0b10..Dual 8-bit counters PWM mode.
5429  *  0b11..Single 16-bit counter mode.
5430  */
5431 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
5432 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
5433 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
5434 /*! PINPOL - Timer Pin Polarity
5435  *  0b0..Pin is active high
5436  *  0b1..Pin is active low
5437  */
5438 #define FLEXIO_TIMCTL_PINPOL(x) \
5439     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
5440 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
5441 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
5442 /*! PINSEL - Timer Pin Select
5443  */
5444 #define FLEXIO_TIMCTL_PINSEL(x) \
5445     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
5446 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
5447 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
5448 /*! PINCFG - Timer Pin Configuration
5449  *  0b00..Timer pin output disabled
5450  *  0b01..Timer pin open drain or bidirectional output enable
5451  *  0b10..Timer pin bidirectional output data
5452  *  0b11..Timer pin output
5453  */
5454 #define FLEXIO_TIMCTL_PINCFG(x) \
5455     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
5456 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
5457 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
5458 /*! TRGSRC - Trigger Source
5459  *  0b0..External trigger selected
5460  *  0b1..Internal trigger selected
5461  */
5462 #define FLEXIO_TIMCTL_TRGSRC(x) \
5463     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
5464 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
5465 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
5466 /*! TRGPOL - Trigger Polarity
5467  *  0b0..Trigger active high
5468  *  0b1..Trigger active low
5469  */
5470 #define FLEXIO_TIMCTL_TRGPOL(x) \
5471     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
5472 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
5473 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
5474 /*! TRGSEL - Trigger Select
5475  */
5476 #define FLEXIO_TIMCTL_TRGSEL(x) \
5477     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
5478 /*! @} */
5479 
5480 /* The count of FLEXIO_TIMCTL */
5481 #define FLEXIO_TIMCTL_COUNT (8U)
5482 
5483 /*! @name TIMCFG - Timer Configuration N Register */
5484 /*! @{ */
5485 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
5486 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
5487 /*! TSTART - Timer Start Bit
5488  *  0b0..Start bit disabled
5489  *  0b1..Start bit enabled
5490  */
5491 #define FLEXIO_TIMCFG_TSTART(x) \
5492     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
5493 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
5494 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
5495 /*! TSTOP - Timer Stop Bit
5496  *  0b00..Stop bit disabled
5497  *  0b01..Stop bit is enabled on timer compare
5498  *  0b10..Stop bit is enabled on timer disable
5499  *  0b11..Stop bit is enabled on timer compare and timer disable
5500  */
5501 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
5502 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
5503 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
5504 /*! TIMENA - Timer Enable
5505  *  0b000..Timer always enabled
5506  *  0b001..Timer enabled on Timer N-1 enable
5507  *  0b010..Timer enabled on Trigger high
5508  *  0b011..Timer enabled on Trigger high and Pin high
5509  *  0b100..Timer enabled on Pin rising edge
5510  *  0b101..Timer enabled on Pin rising edge and Trigger high
5511  *  0b110..Timer enabled on Trigger rising edge
5512  *  0b111..Timer enabled on Trigger rising or falling edge
5513  */
5514 #define FLEXIO_TIMCFG_TIMENA(x) \
5515     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
5516 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
5517 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
5518 /*! TIMDIS - Timer Disable
5519  *  0b000..Timer never disabled
5520  *  0b001..Timer disabled on Timer N-1 disable
5521  *  0b010..Timer disabled on Timer compare
5522  *  0b011..Timer disabled on Timer compare and Trigger Low
5523  *  0b100..Timer disabled on Pin rising or falling edge
5524  *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
5525  *  0b110..Timer disabled on Trigger falling edge
5526  *  0b111..Reserved
5527  */
5528 #define FLEXIO_TIMCFG_TIMDIS(x) \
5529     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
5530 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
5531 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
5532 /*! TIMRST - Timer Reset
5533  *  0b000..Timer never reset
5534  *  0b001..Reserved
5535  *  0b010..Timer reset on Timer Pin equal to Timer Output
5536  *  0b011..Timer reset on Timer Trigger equal to Timer Output
5537  *  0b100..Timer reset on Timer Pin rising edge
5538  *  0b101..Reserved
5539  *  0b110..Timer reset on Trigger rising edge
5540  *  0b111..Timer reset on Trigger rising or falling edge
5541  */
5542 #define FLEXIO_TIMCFG_TIMRST(x) \
5543     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
5544 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
5545 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
5546 /*! TIMDEC - Timer Decrement
5547  *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
5548  *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
5549  *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
5550  *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
5551  */
5552 #define FLEXIO_TIMCFG_TIMDEC(x) \
5553     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
5554 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
5555 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
5556 /*! TIMOUT - Timer Output
5557  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
5558  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
5559  *  0b10..Timer output is logic one when enabled and on timer reset
5560  *  0b11..Timer output is logic zero when enabled and on timer reset
5561  */
5562 #define FLEXIO_TIMCFG_TIMOUT(x) \
5563     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
5564 /*! @} */
5565 
5566 /* The count of FLEXIO_TIMCFG */
5567 #define FLEXIO_TIMCFG_COUNT (8U)
5568 
5569 /*! @name TIMCMP - Timer Compare N Register */
5570 /*! @{ */
5571 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
5572 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
5573 /*! CMP - Timer Compare Value
5574  */
5575 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
5576 /*! @} */
5577 
5578 /* The count of FLEXIO_TIMCMP */
5579 #define FLEXIO_TIMCMP_COUNT (8U)
5580 
5581 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
5582 /*! @{ */
5583 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
5584 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
5585 /*! SHIFTBUFNBS - Shift Buffer
5586  */
5587 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) \
5588     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
5589 /*! @} */
5590 
5591 /* The count of FLEXIO_SHIFTBUFNBS */
5592 #define FLEXIO_SHIFTBUFNBS_COUNT (8U)
5593 
5594 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
5595 /*! @{ */
5596 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
5597 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
5598 /*! SHIFTBUFHWS - Shift Buffer
5599  */
5600 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) \
5601     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
5602 /*! @} */
5603 
5604 /* The count of FLEXIO_SHIFTBUFHWS */
5605 #define FLEXIO_SHIFTBUFHWS_COUNT (8U)
5606 
5607 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
5608 /*! @{ */
5609 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
5610 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
5611 /*! SHIFTBUFNIS - Shift Buffer
5612  */
5613 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) \
5614     (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
5615 /*! @} */
5616 
5617 /* The count of FLEXIO_SHIFTBUFNIS */
5618 #define FLEXIO_SHIFTBUFNIS_COUNT (8U)
5619 
5620 /*!
5621  * @}
5622  */ /* end of group FLEXIO_Register_Masks */
5623 
5624 /* FLEXIO - Peripheral instance base addresses */
5625 /** Peripheral FLEXIO0 base address */
5626 #define FLEXIO0_BASE (0x400CA000u)
5627 /** Peripheral FLEXIO0 base pointer */
5628 #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
5629 /** Array initializer of FLEXIO peripheral base addresses */
5630 #define FLEXIO_BASE_ADDRS \
5631     {                     \
5632         FLEXIO0_BASE      \
5633     }
5634 /** Array initializer of FLEXIO peripheral base pointers */
5635 #define FLEXIO_BASE_PTRS \
5636     {                    \
5637         FLEXIO0          \
5638     }
5639 /** Interrupt vectors for the FLEXIO peripheral type */
5640 #define FLEXIO_IRQS  \
5641     {                \
5642         FLEXIO0_IRQn \
5643     }
5644 
5645 /*!
5646  * @}
5647  */ /* end of group FLEXIO_Peripheral_Access_Layer */
5648 
5649 /* ----------------------------------------------------------------------------
5650    -- FTFA Peripheral Access Layer
5651    ---------------------------------------------------------------------------- */
5652 
5653 /*!
5654  * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
5655  * @{
5656  */
5657 
5658 /** FTFA - Register Layout Typedef */
5659 typedef struct
5660 {
5661     __IO uint8_t FSTAT;  /**< Flash Status Register, offset: 0x0 */
5662     __IO uint8_t FCNFG;  /**< Flash Configuration Register, offset: 0x1 */
5663     __I uint8_t FSEC;    /**< Flash Security Register, offset: 0x2 */
5664     __I uint8_t FOPT;    /**< Flash Option Register, offset: 0x3 */
5665     __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
5666     __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
5667     __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
5668     __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
5669     __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
5670     __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
5671     __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
5672     __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
5673     __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
5674     __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
5675     __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
5676     __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
5677     __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
5678     __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
5679     __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
5680     __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
5681     uint8_t RESERVED_0[4];
5682     __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
5683     __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
5684     __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
5685     __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
5686     __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
5687     __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
5688     __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
5689     __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
5690     __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
5691     __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
5692     __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
5693     __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
5694     __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
5695     __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
5696     __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
5697     __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
5698     __I uint8_t FACSS;  /**< Flash Access Segment Size Register, offset: 0x28 */
5699     uint8_t RESERVED_1[2];
5700     __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
5701 } FTFA_Type;
5702 
5703 /* ----------------------------------------------------------------------------
5704    -- FTFA Register Masks
5705    ---------------------------------------------------------------------------- */
5706 
5707 /*!
5708  * @addtogroup FTFA_Register_Masks FTFA Register Masks
5709  * @{
5710  */
5711 
5712 /*! @name FSTAT - Flash Status Register */
5713 /*! @{ */
5714 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
5715 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
5716 /*! MGSTAT0 - Memory Controller Command Completion Status Flag
5717  */
5718 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
5719 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
5720 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
5721 /*! FPVIOL - Flash Protection Violation Flag
5722  *  0b0..No protection violation detected
5723  *  0b1..Protection violation detected
5724  */
5725 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
5726 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
5727 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
5728 /*! ACCERR - Flash Access Error Flag
5729  *  0b0..No access error detected
5730  *  0b1..Access error detected
5731  */
5732 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
5733 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
5734 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
5735 /*! RDCOLERR - Flash Read Collision Error Flag
5736  *  0b0..No collision error detected
5737  *  0b1..Collision error detected
5738  */
5739 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
5740 #define FTFA_FSTAT_CCIF_MASK (0x80U)
5741 #define FTFA_FSTAT_CCIF_SHIFT (7U)
5742 /*! CCIF - Command Complete Interrupt Flag
5743  *  0b0..Flash command in progress
5744  *  0b1..Flash command has completed
5745  */
5746 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
5747 /*! @} */
5748 
5749 /*! @name FCNFG - Flash Configuration Register */
5750 /*! @{ */
5751 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
5752 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
5753 /*! ERSSUSP - Erase Suspend
5754  *  0b0..No suspend requested
5755  *  0b1..Suspend the current Erase Flash Sector command execution.
5756  */
5757 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
5758 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
5759 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
5760 /*! ERSAREQ - Erase All Request
5761  *  0b0..No request or request complete
5762  *  0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the
5763  *       Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to
5764  *       the unsecure state.
5765  */
5766 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
5767 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
5768 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
5769 /*! RDCOLLIE - Read Collision Error Interrupt Enable
5770  *  0b0..Read collision error interrupt disabled
5771  *  0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read
5772  *       collision error is detected (see the description of FSTAT[RDCOLERR]).
5773  */
5774 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
5775 #define FTFA_FCNFG_CCIE_MASK (0x80U)
5776 #define FTFA_FCNFG_CCIE_SHIFT (7U)
5777 /*! CCIE - Command Complete Interrupt Enable
5778  *  0b0..Command complete interrupt disabled
5779  *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
5780  */
5781 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
5782 /*! @} */
5783 
5784 /*! @name FSEC - Flash Security Register */
5785 /*! @{ */
5786 #define FTFA_FSEC_SEC_MASK (0x3U)
5787 #define FTFA_FSEC_SEC_SHIFT (0U)
5788 /*! SEC - Flash Security
5789  *  0b00..MCU security status is secure.
5790  *  0b01..MCU security status is secure.
5791  *  0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
5792  *  0b11..MCU security status is secure.
5793  */
5794 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
5795 #define FTFA_FSEC_FSLACC_MASK (0xCU)
5796 #define FTFA_FSEC_FSLACC_SHIFT (2U)
5797 /*! FSLACC - Factory Security Level Access Code
5798  *  0b00..NXP factory access granted
5799  *  0b01..NXP factory access denied
5800  *  0b10..NXP factory access denied
5801  *  0b11..NXP factory access granted
5802  */
5803 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
5804 #define FTFA_FSEC_MEEN_MASK (0x30U)
5805 #define FTFA_FSEC_MEEN_SHIFT (4U)
5806 /*! MEEN - Mass Erase Enable
5807  *  0b00..Mass erase is enabled
5808  *  0b01..Mass erase is enabled
5809  *  0b10..Mass erase is disabled
5810  *  0b11..Mass erase is enabled
5811  */
5812 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
5813 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
5814 #define FTFA_FSEC_KEYEN_SHIFT (6U)
5815 /*! KEYEN - Backdoor Key Security Enable
5816  *  0b00..Backdoor key access disabled
5817  *  0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
5818  *  0b10..Backdoor key access enabled
5819  *  0b11..Backdoor key access disabled
5820  */
5821 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
5822 /*! @} */
5823 
5824 /*! @name FOPT - Flash Option Register */
5825 /*! @{ */
5826 #define FTFA_FOPT_OPT_MASK (0xFFU)
5827 #define FTFA_FOPT_OPT_SHIFT (0U)
5828 /*! OPT - Nonvolatile Option
5829  */
5830 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
5831 /*! @} */
5832 
5833 /*! @name FCCOB3 - Flash Common Command Object Registers */
5834 /*! @{ */
5835 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
5836 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
5837 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
5838 /*! @} */
5839 
5840 /*! @name FCCOB2 - Flash Common Command Object Registers */
5841 /*! @{ */
5842 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
5843 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
5844 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
5845 /*! @} */
5846 
5847 /*! @name FCCOB1 - Flash Common Command Object Registers */
5848 /*! @{ */
5849 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
5850 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
5851 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
5852 /*! @} */
5853 
5854 /*! @name FCCOB0 - Flash Common Command Object Registers */
5855 /*! @{ */
5856 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
5857 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
5858 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
5859 /*! @} */
5860 
5861 /*! @name FCCOB7 - Flash Common Command Object Registers */
5862 /*! @{ */
5863 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
5864 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
5865 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
5866 /*! @} */
5867 
5868 /*! @name FCCOB6 - Flash Common Command Object Registers */
5869 /*! @{ */
5870 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
5871 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
5872 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
5873 /*! @} */
5874 
5875 /*! @name FCCOB5 - Flash Common Command Object Registers */
5876 /*! @{ */
5877 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
5878 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
5879 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
5880 /*! @} */
5881 
5882 /*! @name FCCOB4 - Flash Common Command Object Registers */
5883 /*! @{ */
5884 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
5885 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
5886 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
5887 /*! @} */
5888 
5889 /*! @name FCCOBB - Flash Common Command Object Registers */
5890 /*! @{ */
5891 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
5892 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
5893 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
5894 /*! @} */
5895 
5896 /*! @name FCCOBA - Flash Common Command Object Registers */
5897 /*! @{ */
5898 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
5899 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
5900 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
5901 /*! @} */
5902 
5903 /*! @name FCCOB9 - Flash Common Command Object Registers */
5904 /*! @{ */
5905 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
5906 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
5907 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
5908 /*! @} */
5909 
5910 /*! @name FCCOB8 - Flash Common Command Object Registers */
5911 /*! @{ */
5912 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
5913 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
5914 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
5915 /*! @} */
5916 
5917 /*! @name FPROT3 - Program Flash Protection Registers */
5918 /*! @{ */
5919 #define FTFA_FPROT3_PROT_MASK (0xFFU)
5920 #define FTFA_FPROT3_PROT_SHIFT (0U)
5921 /*! PROT - Program Flash Region Protect
5922  *  0b00000000..Program flash region is protected.
5923  *  0b00000001..Program flash region is not protected
5924  */
5925 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
5926 /*! @} */
5927 
5928 /*! @name FPROT2 - Program Flash Protection Registers */
5929 /*! @{ */
5930 #define FTFA_FPROT2_PROT_MASK (0xFFU)
5931 #define FTFA_FPROT2_PROT_SHIFT (0U)
5932 /*! PROT - Program Flash Region Protect
5933  *  0b00000000..Program flash region is protected.
5934  *  0b00000001..Program flash region is not protected
5935  */
5936 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
5937 /*! @} */
5938 
5939 /*! @name FPROT1 - Program Flash Protection Registers */
5940 /*! @{ */
5941 #define FTFA_FPROT1_PROT_MASK (0xFFU)
5942 #define FTFA_FPROT1_PROT_SHIFT (0U)
5943 /*! PROT - Program Flash Region Protect
5944  *  0b00000000..Program flash region is protected.
5945  *  0b00000001..Program flash region is not protected
5946  */
5947 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
5948 /*! @} */
5949 
5950 /*! @name FPROT0 - Program Flash Protection Registers */
5951 /*! @{ */
5952 #define FTFA_FPROT0_PROT_MASK (0xFFU)
5953 #define FTFA_FPROT0_PROT_SHIFT (0U)
5954 /*! PROT - Program Flash Region Protect
5955  *  0b00000000..Program flash region is protected.
5956  *  0b00000001..Program flash region is not protected
5957  */
5958 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
5959 /*! @} */
5960 
5961 /*! @name XACCH3 - Execute-only Access Registers */
5962 /*! @{ */
5963 #define FTFA_XACCH3_XA_MASK (0xFFU)
5964 #define FTFA_XACCH3_XA_SHIFT (0U)
5965 /*! XA - Execute-only access control
5966  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
5967  *  0b00000001..Associated segment is accessible as data or in execute mode
5968  */
5969 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
5970 /*! @} */
5971 
5972 /*! @name XACCH2 - Execute-only Access Registers */
5973 /*! @{ */
5974 #define FTFA_XACCH2_XA_MASK (0xFFU)
5975 #define FTFA_XACCH2_XA_SHIFT (0U)
5976 /*! XA - Execute-only access control
5977  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
5978  *  0b00000001..Associated segment is accessible as data or in execute mode
5979  */
5980 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
5981 /*! @} */
5982 
5983 /*! @name XACCH1 - Execute-only Access Registers */
5984 /*! @{ */
5985 #define FTFA_XACCH1_XA_MASK (0xFFU)
5986 #define FTFA_XACCH1_XA_SHIFT (0U)
5987 /*! XA - Execute-only access control
5988  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
5989  *  0b00000001..Associated segment is accessible as data or in execute mode
5990  */
5991 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
5992 /*! @} */
5993 
5994 /*! @name XACCH0 - Execute-only Access Registers */
5995 /*! @{ */
5996 #define FTFA_XACCH0_XA_MASK (0xFFU)
5997 #define FTFA_XACCH0_XA_SHIFT (0U)
5998 /*! XA - Execute-only access control
5999  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
6000  *  0b00000001..Associated segment is accessible as data or in execute mode
6001  */
6002 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
6003 /*! @} */
6004 
6005 /*! @name XACCL3 - Execute-only Access Registers */
6006 /*! @{ */
6007 #define FTFA_XACCL3_XA_MASK (0xFFU)
6008 #define FTFA_XACCL3_XA_SHIFT (0U)
6009 /*! XA - Execute-only access control
6010  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
6011  *  0b00000001..Associated segment is accessible as data or in execute mode
6012  */
6013 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
6014 /*! @} */
6015 
6016 /*! @name XACCL2 - Execute-only Access Registers */
6017 /*! @{ */
6018 #define FTFA_XACCL2_XA_MASK (0xFFU)
6019 #define FTFA_XACCL2_XA_SHIFT (0U)
6020 /*! XA - Execute-only access control
6021  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
6022  *  0b00000001..Associated segment is accessible as data or in execute mode
6023  */
6024 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
6025 /*! @} */
6026 
6027 /*! @name XACCL1 - Execute-only Access Registers */
6028 /*! @{ */
6029 #define FTFA_XACCL1_XA_MASK (0xFFU)
6030 #define FTFA_XACCL1_XA_SHIFT (0U)
6031 /*! XA - Execute-only access control
6032  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
6033  *  0b00000001..Associated segment is accessible as data or in execute mode
6034  */
6035 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
6036 /*! @} */
6037 
6038 /*! @name XACCL0 - Execute-only Access Registers */
6039 /*! @{ */
6040 #define FTFA_XACCL0_XA_MASK (0xFFU)
6041 #define FTFA_XACCL0_XA_SHIFT (0U)
6042 /*! XA - Execute-only access control
6043  *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
6044  *  0b00000001..Associated segment is accessible as data or in execute mode
6045  */
6046 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
6047 /*! @} */
6048 
6049 /*! @name SACCH3 - Supervisor-only Access Registers */
6050 /*! @{ */
6051 #define FTFA_SACCH3_SA_MASK (0xFFU)
6052 #define FTFA_SACCH3_SA_SHIFT (0U)
6053 /*! SA - Supervisor-only access control
6054  *  0b00000000..Associated segment is accessible in supervisor mode only
6055  *  0b00000001..Associated segment is accessible in user or supervisor mode
6056  */
6057 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
6058 /*! @} */
6059 
6060 /*! @name SACCH2 - Supervisor-only Access Registers */
6061 /*! @{ */
6062 #define FTFA_SACCH2_SA_MASK (0xFFU)
6063 #define FTFA_SACCH2_SA_SHIFT (0U)
6064 /*! SA - Supervisor-only access control
6065  *  0b00000000..Associated segment is accessible in supervisor mode only
6066  *  0b00000001..Associated segment is accessible in user or supervisor mode
6067  */
6068 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
6069 /*! @} */
6070 
6071 /*! @name SACCH1 - Supervisor-only Access Registers */
6072 /*! @{ */
6073 #define FTFA_SACCH1_SA_MASK (0xFFU)
6074 #define FTFA_SACCH1_SA_SHIFT (0U)
6075 /*! SA - Supervisor-only access control
6076  *  0b00000000..Associated segment is accessible in supervisor mode only
6077  *  0b00000001..Associated segment is accessible in user or supervisor mode
6078  */
6079 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
6080 /*! @} */
6081 
6082 /*! @name SACCH0 - Supervisor-only Access Registers */
6083 /*! @{ */
6084 #define FTFA_SACCH0_SA_MASK (0xFFU)
6085 #define FTFA_SACCH0_SA_SHIFT (0U)
6086 /*! SA - Supervisor-only access control
6087  *  0b00000000..Associated segment is accessible in supervisor mode only
6088  *  0b00000001..Associated segment is accessible in user or supervisor mode
6089  */
6090 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
6091 /*! @} */
6092 
6093 /*! @name SACCL3 - Supervisor-only Access Registers */
6094 /*! @{ */
6095 #define FTFA_SACCL3_SA_MASK (0xFFU)
6096 #define FTFA_SACCL3_SA_SHIFT (0U)
6097 /*! SA - Supervisor-only access control
6098  *  0b00000000..Associated segment is accessible in supervisor mode only
6099  *  0b00000001..Associated segment is accessible in user or supervisor mode
6100  */
6101 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
6102 /*! @} */
6103 
6104 /*! @name SACCL2 - Supervisor-only Access Registers */
6105 /*! @{ */
6106 #define FTFA_SACCL2_SA_MASK (0xFFU)
6107 #define FTFA_SACCL2_SA_SHIFT (0U)
6108 /*! SA - Supervisor-only access control
6109  *  0b00000000..Associated segment is accessible in supervisor mode only
6110  *  0b00000001..Associated segment is accessible in user or supervisor mode
6111  */
6112 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
6113 /*! @} */
6114 
6115 /*! @name SACCL1 - Supervisor-only Access Registers */
6116 /*! @{ */
6117 #define FTFA_SACCL1_SA_MASK (0xFFU)
6118 #define FTFA_SACCL1_SA_SHIFT (0U)
6119 /*! SA - Supervisor-only access control
6120  *  0b00000000..Associated segment is accessible in supervisor mode only
6121  *  0b00000001..Associated segment is accessible in user or supervisor mode
6122  */
6123 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
6124 /*! @} */
6125 
6126 /*! @name SACCL0 - Supervisor-only Access Registers */
6127 /*! @{ */
6128 #define FTFA_SACCL0_SA_MASK (0xFFU)
6129 #define FTFA_SACCL0_SA_SHIFT (0U)
6130 /*! SA - Supervisor-only access control
6131  *  0b00000000..Associated segment is accessible in supervisor mode only
6132  *  0b00000001..Associated segment is accessible in user or supervisor mode
6133  */
6134 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
6135 /*! @} */
6136 
6137 /*! @name FACSS - Flash Access Segment Size Register */
6138 /*! @{ */
6139 #define FTFA_FACSS_SGSIZE_MASK (0xFFU)
6140 #define FTFA_FACSS_SGSIZE_SHIFT (0U)
6141 /*! SGSIZE - Segment Size
6142  */
6143 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
6144 /*! @} */
6145 
6146 /*! @name FACSN - Flash Access Segment Number Register */
6147 /*! @{ */
6148 #define FTFA_FACSN_NUMSG_MASK (0xFFU)
6149 #define FTFA_FACSN_NUMSG_SHIFT (0U)
6150 /*! NUMSG - Number of Segments Indicator
6151  */
6152 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
6153 /*! @} */
6154 
6155 /*!
6156  * @}
6157  */ /* end of group FTFA_Register_Masks */
6158 
6159 /* FTFA - Peripheral instance base addresses */
6160 /** Peripheral FTFA base address */
6161 #define FTFA_BASE (0x40020000u)
6162 /** Peripheral FTFA base pointer */
6163 #define FTFA ((FTFA_Type *)FTFA_BASE)
6164 /** Array initializer of FTFA peripheral base addresses */
6165 #define FTFA_BASE_ADDRS \
6166     {                   \
6167         FTFA_BASE       \
6168     }
6169 /** Array initializer of FTFA peripheral base pointers */
6170 #define FTFA_BASE_PTRS \
6171     {                  \
6172         FTFA           \
6173     }
6174 /** Interrupt vectors for the FTFA peripheral type */
6175 #define FTFA_COMMAND_COMPLETE_IRQS \
6176     {                              \
6177         FTFA_IRQn                  \
6178     }
6179 
6180 /*!
6181  * @}
6182  */ /* end of group FTFA_Peripheral_Access_Layer */
6183 
6184 /* ----------------------------------------------------------------------------
6185    -- GPIO Peripheral Access Layer
6186    ---------------------------------------------------------------------------- */
6187 
6188 /*!
6189  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
6190  * @{
6191  */
6192 
6193 /** GPIO - Register Layout Typedef */
6194 typedef struct
6195 {
6196     __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
6197     __O uint32_t PSOR;  /**< Port Set Output Register, offset: 0x4 */
6198     __O uint32_t PCOR;  /**< Port Clear Output Register, offset: 0x8 */
6199     __O uint32_t PTOR;  /**< Port Toggle Output Register, offset: 0xC */
6200     __I uint32_t PDIR;  /**< Port Data Input Register, offset: 0x10 */
6201     __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
6202 } GPIO_Type;
6203 
6204 /* ----------------------------------------------------------------------------
6205    -- GPIO Register Masks
6206    ---------------------------------------------------------------------------- */
6207 
6208 /*!
6209  * @addtogroup GPIO_Register_Masks GPIO Register Masks
6210  * @{
6211  */
6212 
6213 /*! @name PDOR - Port Data Output Register */
6214 /*! @{ */
6215 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
6216 #define GPIO_PDOR_PDO_SHIFT (0U)
6217 /*! PDO - Port Data Output
6218  *  0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose
6219  * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for
6220  * general-purpose output.
6221  */
6222 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
6223 /*! @} */
6224 
6225 /*! @name PSOR - Port Set Output Register */
6226 /*! @{ */
6227 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
6228 #define GPIO_PSOR_PTSO_SHIFT (0U)
6229 /*! PTSO - Port Set Output
6230  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
6231  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
6232  */
6233 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
6234 /*! @} */
6235 
6236 /*! @name PCOR - Port Clear Output Register */
6237 /*! @{ */
6238 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
6239 #define GPIO_PCOR_PTCO_SHIFT (0U)
6240 /*! PTCO - Port Clear Output
6241  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
6242  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
6243  */
6244 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
6245 /*! @} */
6246 
6247 /*! @name PTOR - Port Toggle Output Register */
6248 /*! @{ */
6249 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
6250 #define GPIO_PTOR_PTTO_SHIFT (0U)
6251 /*! PTTO - Port Toggle Output
6252  *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
6253  *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
6254  */
6255 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
6256 /*! @} */
6257 
6258 /*! @name PDIR - Port Data Input Register */
6259 /*! @{ */
6260 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
6261 #define GPIO_PDIR_PDI_SHIFT (0U)
6262 /*! PDI - Port Data Input
6263  *  0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
6264  *  0b00000000000000000000000000000001..Pin logic level is logic 1.
6265  */
6266 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
6267 /*! @} */
6268 
6269 /*! @name PDDR - Port Data Direction Register */
6270 /*! @{ */
6271 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
6272 #define GPIO_PDDR_PDD_SHIFT (0U)
6273 /*! PDD - Port Data Direction
6274  *  0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
6275  *  0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
6276  */
6277 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
6278 /*! @} */
6279 
6280 /*!
6281  * @}
6282  */ /* end of group GPIO_Register_Masks */
6283 
6284 /* GPIO - Peripheral instance base addresses */
6285 /** Peripheral GPIOA base address */
6286 #define GPIOA_BASE (0x4000F000u)
6287 /** Peripheral GPIOA base pointer */
6288 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
6289 /** Peripheral GPIOB base address */
6290 #define GPIOB_BASE (0x4000F040u)
6291 /** Peripheral GPIOB base pointer */
6292 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
6293 /** Peripheral GPIOC base address */
6294 #define GPIOC_BASE (0x4000F080u)
6295 /** Peripheral GPIOC base pointer */
6296 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
6297 /** Peripheral GPIOD base address */
6298 #define GPIOD_BASE (0x4000F0C0u)
6299 /** Peripheral GPIOD base pointer */
6300 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
6301 /** Peripheral GPIOE base address */
6302 #define GPIOE_BASE (0x4000F100u)
6303 /** Peripheral GPIOE base pointer */
6304 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
6305 /** Array initializer of GPIO peripheral base addresses */
6306 #define GPIO_BASE_ADDRS                                            \
6307     {                                                              \
6308         GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE \
6309     }
6310 /** Array initializer of GPIO peripheral base pointers */
6311 #define GPIO_BASE_PTRS                    \
6312     {                                     \
6313         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE \
6314     }
6315 
6316 /*!
6317  * @}
6318  */ /* end of group GPIO_Peripheral_Access_Layer */
6319 
6320 /* ----------------------------------------------------------------------------
6321    -- INTMUX Peripheral Access Layer
6322    ---------------------------------------------------------------------------- */
6323 
6324 /*!
6325  * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
6326  * @{
6327  */
6328 
6329 /** INTMUX - Register Layout Typedef */
6330 typedef struct
6331 {
6332     struct
6333     {                          /* offset: 0x0, array step: 0x40 */
6334         __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
6335         __I uint32_t CHn_VEC;  /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
6336         uint8_t RESERVED_0[8];
6337         __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
6338         uint8_t RESERVED_1[12];
6339         __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
6340         uint8_t RESERVED_2[28];
6341     } CHANNEL[4];
6342 } INTMUX_Type;
6343 
6344 /* ----------------------------------------------------------------------------
6345    -- INTMUX Register Masks
6346    ---------------------------------------------------------------------------- */
6347 
6348 /*!
6349  * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
6350  * @{
6351  */
6352 
6353 /*! @name CHn_CSR - Channel n Control Status Register */
6354 /*! @{ */
6355 #define INTMUX_CHn_CSR_RST_MASK (0x1U)
6356 #define INTMUX_CHn_CSR_RST_SHIFT (0U)
6357 /*! RST - Software Reset
6358  *  0b0..No operation.
6359  *  0b1..Perform a software reset on this channel.
6360  */
6361 #define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
6362 #define INTMUX_CHn_CSR_AND_MASK (0x2U)
6363 #define INTMUX_CHn_CSR_AND_SHIFT (1U)
6364 /*! AND - Logic AND
6365  *  0b0..Logic OR all enabled interrupt inputs.
6366  *  0b1..Logic AND all enabled interrupt inputs.
6367  */
6368 #define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
6369 #define INTMUX_CHn_CSR_IRQN_MASK (0x30U)
6370 #define INTMUX_CHn_CSR_IRQN_SHIFT (4U)
6371 /*! IRQN - Channel Input Number
6372  *  0b00..32 interrupt inputs
6373  *  0b01..Reserved
6374  *  0b10..Reserved
6375  *  0b11..Reserved
6376  */
6377 #define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
6378 #define INTMUX_CHn_CSR_CHIN_MASK (0xF00U)
6379 #define INTMUX_CHn_CSR_CHIN_SHIFT (8U)
6380 /*! CHIN - Channel Instance Number
6381  */
6382 #define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
6383 #define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U)
6384 #define INTMUX_CHn_CSR_IRQP_SHIFT (31U)
6385 /*! IRQP - Channel Interrupt Request Pending
6386  *  0b0..No interrupt is pending.
6387  *  0b1..The interrupt output of this channel is pending.
6388  */
6389 #define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
6390 /*! @} */
6391 
6392 /* The count of INTMUX_CHn_CSR */
6393 #define INTMUX_CHn_CSR_COUNT (4U)
6394 
6395 /*! @name CHn_VEC - Channel n Vector Number Register */
6396 /*! @{ */
6397 #define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU)
6398 #define INTMUX_CHn_VEC_VECN_SHIFT (2U)
6399 /*! VECN - Vector Number
6400  */
6401 #define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
6402 /*! @} */
6403 
6404 /* The count of INTMUX_CHn_VEC */
6405 #define INTMUX_CHn_VEC_COUNT (4U)
6406 
6407 /*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
6408 /*! @{ */
6409 #define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU)
6410 #define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U)
6411 /*! INTE - Interrupt Enable
6412  *  0b00000000000000000000000000000000..Interrupt is disabled.
6413  *  0b00000000000000000000000000000001..Interrupt is enabled.
6414  */
6415 #define INTMUX_CHn_IER_31_0_INTE(x) \
6416     (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
6417 /*! @} */
6418 
6419 /* The count of INTMUX_CHn_IER_31_0 */
6420 #define INTMUX_CHn_IER_31_0_COUNT (4U)
6421 
6422 /*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
6423 /*! @{ */
6424 #define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU)
6425 #define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U)
6426 /*! INTP - Interrupt Pending
6427  *  0b00000000000000000000000000000000..No interrupt.
6428  *  0b00000000000000000000000000000001..Interrupt is pending.
6429  */
6430 #define INTMUX_CHn_IPR_31_0_INTP(x) \
6431     (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
6432 /*! @} */
6433 
6434 /* The count of INTMUX_CHn_IPR_31_0 */
6435 #define INTMUX_CHn_IPR_31_0_COUNT (4U)
6436 
6437 /*!
6438  * @}
6439  */ /* end of group INTMUX_Register_Masks */
6440 
6441 /* INTMUX - Peripheral instance base addresses */
6442 /** Peripheral INTMUX0 base address */
6443 #define INTMUX0_BASE (0x40024000u)
6444 /** Peripheral INTMUX0 base pointer */
6445 #define INTMUX0 ((INTMUX_Type *)INTMUX0_BASE)
6446 /** Array initializer of INTMUX peripheral base addresses */
6447 #define INTMUX_BASE_ADDRS \
6448     {                     \
6449         INTMUX0_BASE      \
6450     }
6451 /** Array initializer of INTMUX peripheral base pointers */
6452 #define INTMUX_BASE_PTRS \
6453     {                    \
6454         INTMUX0          \
6455     }
6456 /** Interrupt vectors for the INTMUX peripheral type */
6457 #define INTMUX_IRQS                                                        \
6458     {                                                                      \
6459         {                                                                  \
6460             INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn \
6461         }                                                                  \
6462     }
6463 
6464 /*!
6465  * @}
6466  */ /* end of group INTMUX_Peripheral_Access_Layer */
6467 
6468 /* ----------------------------------------------------------------------------
6469    -- LLWU Peripheral Access Layer
6470    ---------------------------------------------------------------------------- */
6471 
6472 /*!
6473  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
6474  * @{
6475  */
6476 
6477 /** LLWU - Register Layout Typedef */
6478 typedef struct
6479 {
6480     __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
6481     __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
6482     __IO uint32_t PE1;  /**< LLWU Pin Enable 1 register, offset: 0x8 */
6483     __IO uint32_t PE2;  /**< LLWU Pin Enable 2 register, offset: 0xC */
6484     uint8_t RESERVED_0[8];
6485     __IO uint32_t ME; /**< LLWU Module Interrupt Enable register, offset: 0x18 */
6486     __IO uint32_t DE; /**< LLWU Module DMA Enable register, offset: 0x1C */
6487     __IO uint32_t PF; /**< LLWU Pin Flag register, offset: 0x20 */
6488     uint8_t RESERVED_1[4];
6489     __I uint32_t MF; /**< LLWU Module Interrupt Flag register, offset: 0x28 */
6490     uint8_t RESERVED_2[4];
6491     __IO uint32_t FILT; /**< LLWU Pin Filter register, offset: 0x30 */
6492 } LLWU_Type;
6493 
6494 /* ----------------------------------------------------------------------------
6495    -- LLWU Register Masks
6496    ---------------------------------------------------------------------------- */
6497 
6498 /*!
6499  * @addtogroup LLWU_Register_Masks LLWU Register Masks
6500  * @{
6501  */
6502 
6503 /*! @name VERID - Version ID Register */
6504 /*! @{ */
6505 #define LLWU_VERID_FEATURE_MASK (0xFFFFU)
6506 #define LLWU_VERID_FEATURE_SHIFT (0U)
6507 /*! FEATURE - Feature Specification Number
6508  *  0b0000000000000000..Standard features implemented
6509  */
6510 #define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK)
6511 #define LLWU_VERID_MINOR_MASK (0xFF0000U)
6512 #define LLWU_VERID_MINOR_SHIFT (16U)
6513 /*! MINOR - Minor Version Number
6514  */
6515 #define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK)
6516 #define LLWU_VERID_MAJOR_MASK (0xFF000000U)
6517 #define LLWU_VERID_MAJOR_SHIFT (24U)
6518 /*! MAJOR - Major Version Number
6519  */
6520 #define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK)
6521 /*! @} */
6522 
6523 /*! @name PARAM - Parameter Register */
6524 /*! @{ */
6525 #define LLWU_PARAM_FILTERS_MASK (0xFFU)
6526 #define LLWU_PARAM_FILTERS_SHIFT (0U)
6527 /*! FILTERS - Filter Number
6528  */
6529 #define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK)
6530 #define LLWU_PARAM_DMAS_MASK (0xFF00U)
6531 #define LLWU_PARAM_DMAS_SHIFT (8U)
6532 /*! DMAS - DMA Number
6533  */
6534 #define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK)
6535 #define LLWU_PARAM_MODULES_MASK (0xFF0000U)
6536 #define LLWU_PARAM_MODULES_SHIFT (16U)
6537 /*! MODULES - Module Number
6538  */
6539 #define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK)
6540 #define LLWU_PARAM_PINS_MASK (0xFF000000U)
6541 #define LLWU_PARAM_PINS_SHIFT (24U)
6542 /*! PINS - Pin Number
6543  */
6544 #define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK)
6545 /*! @} */
6546 
6547 /*! @name PE1 - LLWU Pin Enable 1 register */
6548 /*! @{ */
6549 #define LLWU_PE1_WUPE0_MASK (0x3U)
6550 #define LLWU_PE1_WUPE0_SHIFT (0U)
6551 /*! WUPE0 - Wakeup Pin Enable For LLWU_P0
6552  *  0b00..External input pin disabled as wakeup input
6553  *  0b01..External input pin enabled with rising edge detection
6554  *  0b10..External input pin enabled with falling edge detection
6555  *  0b11..External input pin enabled with any change detection
6556  */
6557 #define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
6558 #define LLWU_PE1_WUPE1_MASK (0xCU)
6559 #define LLWU_PE1_WUPE1_SHIFT (2U)
6560 /*! WUPE1 - Wakeup Pin Enable For LLWU_P1
6561  *  0b00..External input pin disabled as wakeup input
6562  *  0b01..External input pin enabled with rising edge detection
6563  *  0b10..External input pin enabled with falling edge detection
6564  *  0b11..External input pin enabled with any change detection
6565  */
6566 #define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
6567 #define LLWU_PE1_WUPE2_MASK (0x30U)
6568 #define LLWU_PE1_WUPE2_SHIFT (4U)
6569 /*! WUPE2 - Wakeup Pin Enable For LLWU_P2
6570  *  0b00..External input pin disabled as wakeup input
6571  *  0b01..External input pin enabled with rising edge detection
6572  *  0b10..External input pin enabled with falling edge detection
6573  *  0b11..External input pin enabled with any change detection
6574  */
6575 #define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
6576 #define LLWU_PE1_WUPE3_MASK (0xC0U)
6577 #define LLWU_PE1_WUPE3_SHIFT (6U)
6578 /*! WUPE3 - Wakeup Pin Enable For LLWU_P3
6579  *  0b00..External input pin disabled as wakeup input
6580  *  0b01..External input pin enabled with rising edge detection
6581  *  0b10..External input pin enabled with falling edge detection
6582  *  0b11..External input pin enabled with any change detection
6583  */
6584 #define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
6585 #define LLWU_PE1_WUPE4_MASK (0x300U)
6586 #define LLWU_PE1_WUPE4_SHIFT (8U)
6587 /*! WUPE4 - Wakeup Pin Enable For LLWU_P4
6588  *  0b00..External input pin disabled as wakeup input
6589  *  0b01..External input pin enabled with rising edge detection
6590  *  0b10..External input pin enabled with falling edge detection
6591  *  0b11..External input pin enabled with any change detection
6592  */
6593 #define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK)
6594 #define LLWU_PE1_WUPE5_MASK (0xC00U)
6595 #define LLWU_PE1_WUPE5_SHIFT (10U)
6596 /*! WUPE5 - Wakeup Pin Enable For LLWU_P5
6597  *  0b00..External input pin disabled as wakeup input
6598  *  0b01..External input pin enabled with rising edge detection
6599  *  0b10..External input pin enabled with falling edge detection
6600  *  0b11..External input pin enabled with any change detection
6601  */
6602 #define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK)
6603 #define LLWU_PE1_WUPE6_MASK (0x3000U)
6604 #define LLWU_PE1_WUPE6_SHIFT (12U)
6605 /*! WUPE6 - Wakeup Pin Enable For LLWU_P6
6606  *  0b00..External input pin disabled as wakeup input
6607  *  0b01..External input pin enabled with rising edge detection
6608  *  0b10..External input pin enabled with falling edge detection
6609  *  0b11..External input pin enabled with any change detection
6610  */
6611 #define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK)
6612 #define LLWU_PE1_WUPE7_MASK (0xC000U)
6613 #define LLWU_PE1_WUPE7_SHIFT (14U)
6614 /*! WUPE7 - Wakeup Pin Enable For LLWU_P7
6615  *  0b00..External input pin disabled as wakeup input
6616  *  0b01..External input pin enabled with rising edge detection
6617  *  0b10..External input pin enabled with falling edge detection
6618  *  0b11..External input pin enabled with any change detection
6619  */
6620 #define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK)
6621 #define LLWU_PE1_WUPE8_MASK (0x30000U)
6622 #define LLWU_PE1_WUPE8_SHIFT (16U)
6623 /*! WUPE8 - Wakeup Pin Enable For LLWU_P8
6624  *  0b00..External input pin disabled as wakeup input
6625  *  0b01..External input pin enabled with rising edge detection
6626  *  0b10..External input pin enabled with falling edge detection
6627  *  0b11..External input pin enabled with any change detection
6628  */
6629 #define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK)
6630 #define LLWU_PE1_WUPE9_MASK (0xC0000U)
6631 #define LLWU_PE1_WUPE9_SHIFT (18U)
6632 /*! WUPE9 - Wakeup Pin Enable For LLWU_P9
6633  *  0b00..External input pin disabled as wakeup input
6634  *  0b01..External input pin enabled with rising edge detection
6635  *  0b10..External input pin enabled with falling edge detection
6636  *  0b11..External input pin enabled with any change detection
6637  */
6638 #define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK)
6639 #define LLWU_PE1_WUPE10_MASK (0x300000U)
6640 #define LLWU_PE1_WUPE10_SHIFT (20U)
6641 /*! WUPE10 - Wakeup Pin Enable For LLWU_P10
6642  *  0b00..External input pin disabled as wakeup input
6643  *  0b01..External input pin enabled with rising edge detection
6644  *  0b10..External input pin enabled with falling edge detection
6645  *  0b11..External input pin enabled with any change detection
6646  */
6647 #define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK)
6648 #define LLWU_PE1_WUPE11_MASK (0xC00000U)
6649 #define LLWU_PE1_WUPE11_SHIFT (22U)
6650 /*! WUPE11 - Wakeup Pin Enable For LLWU_P11
6651  *  0b00..External input pin disabled as wakeup input
6652  *  0b01..External input pin enabled with rising edge detection
6653  *  0b10..External input pin enabled with falling edge detection
6654  *  0b11..External input pin enabled with any change detection
6655  */
6656 #define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK)
6657 #define LLWU_PE1_WUPE12_MASK (0x3000000U)
6658 #define LLWU_PE1_WUPE12_SHIFT (24U)
6659 /*! WUPE12 - Wakeup Pin Enable For LLWU_P12
6660  *  0b00..External input pin disabled as wakeup input
6661  *  0b01..External input pin enabled with rising edge detection
6662  *  0b10..External input pin enabled with falling edge detection
6663  *  0b11..External input pin enabled with any change detection
6664  */
6665 #define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK)
6666 #define LLWU_PE1_WUPE13_MASK (0xC000000U)
6667 #define LLWU_PE1_WUPE13_SHIFT (26U)
6668 /*! WUPE13 - Wakeup Pin Enable For LLWU_P13
6669  *  0b00..External input pin disabled as wakeup input
6670  *  0b01..External input pin enabled with rising edge detection
6671  *  0b10..External input pin enabled with falling edge detection
6672  *  0b11..External input pin enabled with any change detection
6673  */
6674 #define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK)
6675 #define LLWU_PE1_WUPE14_MASK (0x30000000U)
6676 #define LLWU_PE1_WUPE14_SHIFT (28U)
6677 /*! WUPE14 - Wakeup Pin Enable For LLWU_P14
6678  *  0b00..External input pin disabled as wakeup input
6679  *  0b01..External input pin enabled with rising edge detection
6680  *  0b10..External input pin enabled with falling edge detection
6681  *  0b11..External input pin enabled with any change detection
6682  */
6683 #define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK)
6684 #define LLWU_PE1_WUPE15_MASK (0xC0000000U)
6685 #define LLWU_PE1_WUPE15_SHIFT (30U)
6686 /*! WUPE15 - Wakeup Pin Enable For LLWU_P15
6687  *  0b00..External input pin disabled as wakeup input
6688  *  0b01..External input pin enabled with rising edge detection
6689  *  0b10..External input pin enabled with falling edge detection
6690  *  0b11..External input pin enabled with any change detection
6691  */
6692 #define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK)
6693 /*! @} */
6694 
6695 /*! @name PE2 - LLWU Pin Enable 2 register */
6696 /*! @{ */
6697 #define LLWU_PE2_WUPE16_MASK (0x3U)
6698 #define LLWU_PE2_WUPE16_SHIFT (0U)
6699 /*! WUPE16 - Wakeup Pin Enable For LLWU_P16
6700  *  0b00..External input pin disabled as wakeup input
6701  *  0b01..External input pin enabled with rising edge detection
6702  *  0b10..External input pin enabled with falling edge detection
6703  *  0b11..External input pin enabled with any change detection
6704  */
6705 #define LLWU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK)
6706 #define LLWU_PE2_WUPE17_MASK (0xCU)
6707 #define LLWU_PE2_WUPE17_SHIFT (2U)
6708 /*! WUPE17 - Wakeup Pin Enable For LLWU_P17
6709  *  0b00..External input pin disabled as wakeup input
6710  *  0b01..External input pin enabled with rising edge detection
6711  *  0b10..External input pin enabled with falling edge detection
6712  *  0b11..External input pin enabled with any change detection
6713  */
6714 #define LLWU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK)
6715 #define LLWU_PE2_WUPE18_MASK (0x30U)
6716 #define LLWU_PE2_WUPE18_SHIFT (4U)
6717 /*! WUPE18 - Wakeup Pin Enable For LLWU_P18
6718  *  0b00..External input pin disabled as wakeup input
6719  *  0b01..External input pin enabled with rising edge detection
6720  *  0b10..External input pin enabled with falling edge detection
6721  *  0b11..External input pin enabled with any change detection
6722  */
6723 #define LLWU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK)
6724 #define LLWU_PE2_WUPE19_MASK (0xC0U)
6725 #define LLWU_PE2_WUPE19_SHIFT (6U)
6726 /*! WUPE19 - Wakeup Pin Enable For LLWU_P19
6727  *  0b00..External input pin disabled as wakeup input
6728  *  0b01..External input pin enabled with rising edge detection
6729  *  0b10..External input pin enabled with falling edge detection
6730  *  0b11..External input pin enabled with any change detection
6731  */
6732 #define LLWU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK)
6733 #define LLWU_PE2_WUPE20_MASK (0x300U)
6734 #define LLWU_PE2_WUPE20_SHIFT (8U)
6735 /*! WUPE20 - Wakeup Pin Enable For LLWU_P20
6736  *  0b00..External input pin disabled as wakeup input
6737  *  0b01..External input pin enabled with rising edge detection
6738  *  0b10..External input pin enabled with falling edge detection
6739  *  0b11..External input pin enabled with any change detection
6740  */
6741 #define LLWU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK)
6742 #define LLWU_PE2_WUPE21_MASK (0xC00U)
6743 #define LLWU_PE2_WUPE21_SHIFT (10U)
6744 /*! WUPE21 - Wakeup Pin Enable For LLWU_P21
6745  *  0b00..External input pin disabled as wakeup input
6746  *  0b01..External input pin enabled with rising edge detection
6747  *  0b10..External input pin enabled with falling edge detection
6748  *  0b11..External input pin enabled with any change detection
6749  */
6750 #define LLWU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK)
6751 #define LLWU_PE2_WUPE22_MASK (0x3000U)
6752 #define LLWU_PE2_WUPE22_SHIFT (12U)
6753 /*! WUPE22 - Wakeup Pin Enable For LLWU_P22
6754  *  0b00..External input pin disabled as wakeup input
6755  *  0b01..External input pin enabled with rising edge detection
6756  *  0b10..External input pin enabled with falling edge detection
6757  *  0b11..External input pin enabled with any change detection
6758  */
6759 #define LLWU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK)
6760 #define LLWU_PE2_WUPE23_MASK (0xC000U)
6761 #define LLWU_PE2_WUPE23_SHIFT (14U)
6762 /*! WUPE23 - Wakeup Pin Enable For LLWU_P23
6763  *  0b00..External input pin disabled as wakeup input
6764  *  0b01..External input pin enabled with rising edge detection
6765  *  0b10..External input pin enabled with falling edge detection
6766  *  0b11..External input pin enabled with any change detection
6767  */
6768 #define LLWU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK)
6769 #define LLWU_PE2_WUPE24_MASK (0x30000U)
6770 #define LLWU_PE2_WUPE24_SHIFT (16U)
6771 /*! WUPE24 - Wakeup Pin Enable For LLWU_P24
6772  *  0b00..External input pin disabled as wakeup input
6773  *  0b01..External input pin enabled with rising edge detection
6774  *  0b10..External input pin enabled with falling edge detection
6775  *  0b11..External input pin enabled with any change detection
6776  */
6777 #define LLWU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK)
6778 #define LLWU_PE2_WUPE25_MASK (0xC0000U)
6779 #define LLWU_PE2_WUPE25_SHIFT (18U)
6780 /*! WUPE25 - Wakeup Pin Enable For LLWU_P25
6781  *  0b00..External input pin disabled as wakeup input
6782  *  0b01..External input pin enabled with rising edge detection
6783  *  0b10..External input pin enabled with falling edge detection
6784  *  0b11..External input pin enabled with any change detection
6785  */
6786 #define LLWU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK)
6787 #define LLWU_PE2_WUPE26_MASK (0x300000U)
6788 #define LLWU_PE2_WUPE26_SHIFT (20U)
6789 /*! WUPE26 - Wakeup Pin Enable For LLWU_P26
6790  *  0b00..External input pin disabled as wakeup input
6791  *  0b01..External input pin enabled with rising edge detection
6792  *  0b10..External input pin enabled with falling edge detection
6793  *  0b11..External input pin enabled with any change detection
6794  */
6795 #define LLWU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK)
6796 #define LLWU_PE2_WUPE27_MASK (0xC00000U)
6797 #define LLWU_PE2_WUPE27_SHIFT (22U)
6798 /*! WUPE27 - Wakeup Pin Enable For LLWU_P27
6799  *  0b00..External input pin disabled as wakeup input
6800  *  0b01..External input pin enabled with rising edge detection
6801  *  0b10..External input pin enabled with falling edge detection
6802  *  0b11..External input pin enabled with any change detection
6803  */
6804 #define LLWU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE27_SHIFT)) & LLWU_PE2_WUPE27_MASK)
6805 #define LLWU_PE2_WUPE28_MASK (0x3000000U)
6806 #define LLWU_PE2_WUPE28_SHIFT (24U)
6807 /*! WUPE28 - Wakeup Pin Enable For LLWU_P28
6808  *  0b00..External input pin disabled as wakeup input
6809  *  0b01..External input pin enabled with rising edge detection
6810  *  0b10..External input pin enabled with falling edge detection
6811  *  0b11..External input pin enabled with any change detection
6812  */
6813 #define LLWU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE28_SHIFT)) & LLWU_PE2_WUPE28_MASK)
6814 #define LLWU_PE2_WUPE29_MASK (0xC000000U)
6815 #define LLWU_PE2_WUPE29_SHIFT (26U)
6816 /*! WUPE29 - Wakeup Pin Enable For LLWU_P29
6817  *  0b00..External input pin disabled as wakeup input
6818  *  0b01..External input pin enabled with rising edge detection
6819  *  0b10..External input pin enabled with falling edge detection
6820  *  0b11..External input pin enabled with any change detection
6821  */
6822 #define LLWU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK)
6823 #define LLWU_PE2_WUPE30_MASK (0x30000000U)
6824 #define LLWU_PE2_WUPE30_SHIFT (28U)
6825 /*! WUPE30 - Wakeup Pin Enable For LLWU_P30
6826  *  0b00..External input pin disabled as wakeup input
6827  *  0b01..External input pin enabled with rising edge detection
6828  *  0b10..External input pin enabled with falling edge detection
6829  *  0b11..External input pin enabled with any change detection
6830  */
6831 #define LLWU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK)
6832 #define LLWU_PE2_WUPE31_MASK (0xC0000000U)
6833 #define LLWU_PE2_WUPE31_SHIFT (30U)
6834 /*! WUPE31 - Wakeup Pin Enable For LLWU_P31
6835  *  0b00..External input pin disabled as wakeup input
6836  *  0b01..External input pin enabled with rising edge detection
6837  *  0b10..External input pin enabled with falling edge detection
6838  *  0b11..External input pin enabled with any change detection
6839  */
6840 #define LLWU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK)
6841 /*! @} */
6842 
6843 /*! @name ME - LLWU Module Interrupt Enable register */
6844 /*! @{ */
6845 #define LLWU_ME_WUME0_MASK (0x1U)
6846 #define LLWU_ME_WUME0_SHIFT (0U)
6847 /*! WUME0 - Wakeup Module Enable For Module 0
6848  *  0b0..Internal module flag not used as wakeup source
6849  *  0b1..Internal module flag used as wakeup source
6850  */
6851 #define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
6852 #define LLWU_ME_WUME1_MASK (0x2U)
6853 #define LLWU_ME_WUME1_SHIFT (1U)
6854 /*! WUME1 - Wakeup Module Enable for Module 1
6855  *  0b0..Internal module flag not used as wakeup source
6856  *  0b1..Internal module flag used as wakeup source
6857  */
6858 #define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
6859 #define LLWU_ME_WUME2_MASK (0x4U)
6860 #define LLWU_ME_WUME2_SHIFT (2U)
6861 /*! WUME2 - Wakeup Module Enable For Module 2
6862  *  0b0..Internal module flag not used as wakeup source
6863  *  0b1..Internal module flag used as wakeup source
6864  */
6865 #define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
6866 #define LLWU_ME_WUME3_MASK (0x8U)
6867 #define LLWU_ME_WUME3_SHIFT (3U)
6868 /*! WUME3 - Wakeup Module Enable For Module 3
6869  *  0b0..Internal module flag not used as wakeup source
6870  *  0b1..Internal module flag used as wakeup source
6871  */
6872 #define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
6873 #define LLWU_ME_WUME4_MASK (0x10U)
6874 #define LLWU_ME_WUME4_SHIFT (4U)
6875 /*! WUME4 - Wakeup Module Enable For Module 4
6876  *  0b0..Internal module flag not used as wakeup source
6877  *  0b1..Internal module flag used as wakeup source
6878  */
6879 #define LLWU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
6880 #define LLWU_ME_WUME5_MASK (0x20U)
6881 #define LLWU_ME_WUME5_SHIFT (5U)
6882 /*! WUME5 - Wakeup Module Enable For Module 5
6883  *  0b0..Internal module flag not used as wakeup source
6884  *  0b1..Internal module flag used as wakeup source
6885  */
6886 #define LLWU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
6887 #define LLWU_ME_WUME6_MASK (0x40U)
6888 #define LLWU_ME_WUME6_SHIFT (6U)
6889 /*! WUME6 - Wakeup Module Enable For Module 6
6890  *  0b0..Internal module flag not used as wakeup source
6891  *  0b1..Internal module flag used as wakeup source
6892  */
6893 #define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
6894 #define LLWU_ME_WUME7_MASK (0x80U)
6895 #define LLWU_ME_WUME7_SHIFT (7U)
6896 /*! WUME7 - Wakeup Module Enable For Module 7
6897  *  0b0..Internal module flag not used as wakeup source
6898  *  0b1..Internal module flag used as wakeup source
6899  */
6900 #define LLWU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
6901 /*! @} */
6902 
6903 /*! @name DE - LLWU Module DMA Enable register */
6904 /*! @{ */
6905 #define LLWU_DE_WUDE0_MASK (0x1U)
6906 #define LLWU_DE_WUDE0_SHIFT (0U)
6907 /*! WUDE0 - DMA Wakeup Enable For Module 0
6908  *  0b0..Internal module request not used as a DMA wakeup source
6909  *  0b1..Internal module request used as a DMA wakeup source
6910  */
6911 #define LLWU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK)
6912 #define LLWU_DE_WUDE1_MASK (0x2U)
6913 #define LLWU_DE_WUDE1_SHIFT (1U)
6914 /*! WUDE1 - DMA Wakeup Enable for Module 1
6915  *  0b0..Internal module request not used as a DMA wakeup source
6916  *  0b1..Internal module request used as a DMA wakeup source
6917  */
6918 #define LLWU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK)
6919 #define LLWU_DE_WUDE2_MASK (0x4U)
6920 #define LLWU_DE_WUDE2_SHIFT (2U)
6921 /*! WUDE2 - DMA Wakeup Enable For Module 2
6922  *  0b0..Internal module request not used as a DMA wakeup source
6923  *  0b1..Internal module request used as a DMA wakeup source
6924  */
6925 #define LLWU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK)
6926 #define LLWU_DE_WUDE3_MASK (0x8U)
6927 #define LLWU_DE_WUDE3_SHIFT (3U)
6928 /*! WUDE3 - DMA Wakeup Enable For Module 3
6929  *  0b0..Internal module request not used as a DMA wakeup source
6930  *  0b1..Internal module request used as a DMA wakeup source
6931  */
6932 #define LLWU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE3_SHIFT)) & LLWU_DE_WUDE3_MASK)
6933 #define LLWU_DE_WUDE4_MASK (0x10U)
6934 #define LLWU_DE_WUDE4_SHIFT (4U)
6935 /*! WUDE4 - DMA Wakeup Enable For Module 4
6936  *  0b0..Internal module request not used as a DMA wakeup source
6937  *  0b1..Internal module request used as a DMA wakeup source
6938  */
6939 #define LLWU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK)
6940 #define LLWU_DE_WUDE5_MASK (0x20U)
6941 #define LLWU_DE_WUDE5_SHIFT (5U)
6942 /*! WUDE5 - DMA Wakeup Enable For Module 5
6943  *  0b0..Internal module request not used as a DMA wakeup source
6944  *  0b1..Internal module request used as a DMA wakeup source
6945  */
6946 #define LLWU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK)
6947 #define LLWU_DE_WUDE6_MASK (0x40U)
6948 #define LLWU_DE_WUDE6_SHIFT (6U)
6949 /*! WUDE6 - DMA Wakeup Enable For Module 6
6950  *  0b0..Internal module request not used as a DMA wakeup source
6951  *  0b1..Internal module request used as a DMA wakeup source
6952  */
6953 #define LLWU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK)
6954 #define LLWU_DE_WUDE7_MASK (0x80U)
6955 #define LLWU_DE_WUDE7_SHIFT (7U)
6956 /*! WUDE7 - DMA Wakeup Enable For Module 7
6957  *  0b0..Internal module request not used as a DMA wakeup source
6958  *  0b1..Internal module request used as a DMA wakeup source
6959  */
6960 #define LLWU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE7_SHIFT)) & LLWU_DE_WUDE7_MASK)
6961 /*! @} */
6962 
6963 /*! @name PF - LLWU Pin Flag register */
6964 /*! @{ */
6965 #define LLWU_PF_WUF0_MASK (0x1U)
6966 #define LLWU_PF_WUF0_SHIFT (0U)
6967 /*! WUF0 - Wakeup Flag For LLWU_P0
6968  *  0b0..LLWU_P0 input was not a wakeup source
6969  *  0b1..LLWU_P0 input was a wakeup source
6970  */
6971 #define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK)
6972 #define LLWU_PF_WUF1_MASK (0x2U)
6973 #define LLWU_PF_WUF1_SHIFT (1U)
6974 /*! WUF1 - Wakeup Flag For LLWU_P1
6975  *  0b0..LLWU_P1 input was not a wakeup source
6976  *  0b1..LLWU_P1 input was a wakeup source
6977  */
6978 #define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK)
6979 #define LLWU_PF_WUF2_MASK (0x4U)
6980 #define LLWU_PF_WUF2_SHIFT (2U)
6981 /*! WUF2 - Wakeup Flag For LLWU_P2
6982  *  0b0..LLWU_P2 input was not a wakeup source
6983  *  0b1..LLWU_P2 input was a wakeup source
6984  */
6985 #define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK)
6986 #define LLWU_PF_WUF3_MASK (0x8U)
6987 #define LLWU_PF_WUF3_SHIFT (3U)
6988 /*! WUF3 - Wakeup Flag For LLWU_P3
6989  *  0b0..LLWU_P3 input was not a wakeup source
6990  *  0b1..LLWU_P3 input was a wakeup source
6991  */
6992 #define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK)
6993 #define LLWU_PF_WUF4_MASK (0x10U)
6994 #define LLWU_PF_WUF4_SHIFT (4U)
6995 /*! WUF4 - Wakeup Flag For LLWU_P4
6996  *  0b0..LLWU_P4 input was not a wakeup source
6997  *  0b1..LLWU_P4 input was a wakeup source
6998  */
6999 #define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK)
7000 #define LLWU_PF_WUF5_MASK (0x20U)
7001 #define LLWU_PF_WUF5_SHIFT (5U)
7002 /*! WUF5 - Wakeup Flag For LLWU_P5
7003  *  0b0..LLWU_P5 input was not a wakeup source
7004  *  0b1..LLWU_P5 input was a wakeup source
7005  */
7006 #define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK)
7007 #define LLWU_PF_WUF6_MASK (0x40U)
7008 #define LLWU_PF_WUF6_SHIFT (6U)
7009 /*! WUF6 - Wakeup Flag For LLWU_P6
7010  *  0b0..LLWU_P6 input was not a wakeup source
7011  *  0b1..LLWU_P6 input was a wakeup source
7012  */
7013 #define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK)
7014 #define LLWU_PF_WUF7_MASK (0x80U)
7015 #define LLWU_PF_WUF7_SHIFT (7U)
7016 /*! WUF7 - Wakeup Flag For LLWU_P7
7017  *  0b0..LLWU_P7 input was not a wakeup source
7018  *  0b1..LLWU_P7 input was a wakeup source
7019  */
7020 #define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK)
7021 #define LLWU_PF_WUF8_MASK (0x100U)
7022 #define LLWU_PF_WUF8_SHIFT (8U)
7023 /*! WUF8 - Wakeup Flag For LLWU_P8
7024  *  0b0..LLWU_P8 input was not a wakeup source
7025  *  0b1..LLWU_P8 input was a wakeup source
7026  */
7027 #define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK)
7028 #define LLWU_PF_WUF9_MASK (0x200U)
7029 #define LLWU_PF_WUF9_SHIFT (9U)
7030 /*! WUF9 - Wakeup Flag For LLWU_P9
7031  *  0b0..LLWU_P9 input was not a wakeup source
7032  *  0b1..LLWU_P9 input was a wakeup source
7033  */
7034 #define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK)
7035 #define LLWU_PF_WUF10_MASK (0x400U)
7036 #define LLWU_PF_WUF10_SHIFT (10U)
7037 /*! WUF10 - Wakeup Flag For LLWU_P10
7038  *  0b0..LLWU_P10 input was not a wakeup source
7039  *  0b1..LLWU_P10 input was a wakeup source
7040  */
7041 #define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK)
7042 #define LLWU_PF_WUF11_MASK (0x800U)
7043 #define LLWU_PF_WUF11_SHIFT (11U)
7044 /*! WUF11 - Wakeup Flag For LLWU_P11
7045  *  0b0..LLWU_P11 input was not a wakeup source
7046  *  0b1..LLWU_P11 input was a wakeup source
7047  */
7048 #define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK)
7049 #define LLWU_PF_WUF12_MASK (0x1000U)
7050 #define LLWU_PF_WUF12_SHIFT (12U)
7051 /*! WUF12 - Wakeup Flag For LLWU_P12
7052  *  0b0..LLWU_P12 input was not a wakeup source
7053  *  0b1..LLWU_P12 input was a wakeup source
7054  */
7055 #define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK)
7056 #define LLWU_PF_WUF13_MASK (0x2000U)
7057 #define LLWU_PF_WUF13_SHIFT (13U)
7058 /*! WUF13 - Wakeup Flag For LLWU_P13
7059  *  0b0..LLWU_P13 input was not a wakeup source
7060  *  0b1..LLWU_P13 input was a wakeup source
7061  */
7062 #define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK)
7063 #define LLWU_PF_WUF14_MASK (0x4000U)
7064 #define LLWU_PF_WUF14_SHIFT (14U)
7065 /*! WUF14 - Wakeup Flag For LLWU_P14
7066  *  0b0..LLWU_P14 input was not a wakeup source
7067  *  0b1..LLWU_P14 input was a wakeup source
7068  */
7069 #define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK)
7070 #define LLWU_PF_WUF15_MASK (0x8000U)
7071 #define LLWU_PF_WUF15_SHIFT (15U)
7072 /*! WUF15 - Wakeup Flag For LLWU_P15
7073  *  0b0..LLWU_P15 input was not a wakeup source
7074  *  0b1..LLWU_P15 input was a wakeup source
7075  */
7076 #define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK)
7077 #define LLWU_PF_WUF16_MASK (0x10000U)
7078 #define LLWU_PF_WUF16_SHIFT (16U)
7079 /*! WUF16 - Wakeup Flag For LLWU_P16
7080  *  0b0..LLWU_P16 input was not a wakeup source
7081  *  0b1..LLWU_P16 input was a wakeup source
7082  */
7083 #define LLWU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK)
7084 #define LLWU_PF_WUF17_MASK (0x20000U)
7085 #define LLWU_PF_WUF17_SHIFT (17U)
7086 /*! WUF17 - Wakeup Flag For LLWU_P17
7087  *  0b0..LLWU_P17 input was not a wakeup source
7088  *  0b1..LLWU_P17 input was a wakeup source
7089  */
7090 #define LLWU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK)
7091 #define LLWU_PF_WUF18_MASK (0x40000U)
7092 #define LLWU_PF_WUF18_SHIFT (18U)
7093 /*! WUF18 - Wakeup Flag For LLWU_P18
7094  *  0b0..LLWU_P18 input was not a wakeup source
7095  *  0b1..LLWU_P18 input was a wakeup source
7096  */
7097 #define LLWU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK)
7098 #define LLWU_PF_WUF19_MASK (0x80000U)
7099 #define LLWU_PF_WUF19_SHIFT (19U)
7100 /*! WUF19 - Wakeup Flag For LLWU_P19
7101  *  0b0..LLWU_P19 input was not a wakeup source
7102  *  0b1..LLWU_P19 input was a wakeup source
7103  */
7104 #define LLWU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK)
7105 #define LLWU_PF_WUF20_MASK (0x100000U)
7106 #define LLWU_PF_WUF20_SHIFT (20U)
7107 /*! WUF20 - Wakeup Flag For LLWU_P20
7108  *  0b0..LLWU_P20 input was not a wakeup source
7109  *  0b1..LLWU_P20 input was a wakeup source
7110  */
7111 #define LLWU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK)
7112 #define LLWU_PF_WUF21_MASK (0x200000U)
7113 #define LLWU_PF_WUF21_SHIFT (21U)
7114 /*! WUF21 - Wakeup Flag For LLWU_P21
7115  *  0b0..LLWU_P21 input was not a wakeup source
7116  *  0b1..LLWU_P21 input was a wakeup source
7117  */
7118 #define LLWU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK)
7119 #define LLWU_PF_WUF22_MASK (0x400000U)
7120 #define LLWU_PF_WUF22_SHIFT (22U)
7121 /*! WUF22 - Wakeup Flag For LLWU_P22
7122  *  0b0..LLWU_P22 input was not a wakeup source
7123  *  0b1..LLWU_P22 input was a wakeup source
7124  */
7125 #define LLWU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK)
7126 #define LLWU_PF_WUF23_MASK (0x800000U)
7127 #define LLWU_PF_WUF23_SHIFT (23U)
7128 /*! WUF23 - Wakeup Flag For LLWU_P23
7129  *  0b0..LLWU_P23 input was not a wakeup source
7130  *  0b1..LLWU_P23 input was a wakeup source
7131  */
7132 #define LLWU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK)
7133 #define LLWU_PF_WUF24_MASK (0x1000000U)
7134 #define LLWU_PF_WUF24_SHIFT (24U)
7135 /*! WUF24 - Wakeup Flag For LLWU_P24
7136  *  0b0..LLWU_P24 input was not a wakeup source
7137  *  0b1..LLWU_P24 input was a wakeup source
7138  */
7139 #define LLWU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK)
7140 #define LLWU_PF_WUF25_MASK (0x2000000U)
7141 #define LLWU_PF_WUF25_SHIFT (25U)
7142 /*! WUF25 - Wakeup Flag For LLWU_P25
7143  *  0b0..LLWU_P25 input was not a wakeup source
7144  *  0b1..LLWU_P25 input was a wakeup source
7145  */
7146 #define LLWU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK)
7147 #define LLWU_PF_WUF26_MASK (0x4000000U)
7148 #define LLWU_PF_WUF26_SHIFT (26U)
7149 /*! WUF26 - Wakeup Flag For LLWU_P26
7150  *  0b0..LLWU_P26 input was not a wakeup source
7151  *  0b1..LLWU_P26 input was a wakeup source
7152  */
7153 #define LLWU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK)
7154 #define LLWU_PF_WUF27_MASK (0x8000000U)
7155 #define LLWU_PF_WUF27_SHIFT (27U)
7156 /*! WUF27 - Wakeup Flag For LLWU_P27
7157  *  0b0..LLWU_P27 input was not a wakeup source
7158  *  0b1..LLWU_P27 input was a wakeup source
7159  */
7160 #define LLWU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF27_SHIFT)) & LLWU_PF_WUF27_MASK)
7161 #define LLWU_PF_WUF28_MASK (0x10000000U)
7162 #define LLWU_PF_WUF28_SHIFT (28U)
7163 /*! WUF28 - Wakeup Flag For LLWU_P28
7164  *  0b0..LLWU_P28 input was not a wakeup source
7165  *  0b1..LLWU_P28 input was a wakeup source
7166  */
7167 #define LLWU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF28_SHIFT)) & LLWU_PF_WUF28_MASK)
7168 #define LLWU_PF_WUF29_MASK (0x20000000U)
7169 #define LLWU_PF_WUF29_SHIFT (29U)
7170 /*! WUF29 - Wakeup Flag For LLWU_P29
7171  *  0b0..LLWU_P29 input was not a wakeup source
7172  *  0b1..LLWU_P29 input was a wakeup source
7173  */
7174 #define LLWU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK)
7175 #define LLWU_PF_WUF30_MASK (0x40000000U)
7176 #define LLWU_PF_WUF30_SHIFT (30U)
7177 /*! WUF30 - Wakeup Flag For LLWU_P30
7178  *  0b0..LLWU_P30 input was not a wakeup source
7179  *  0b1..LLWU_P30 input was a wakeup source
7180  */
7181 #define LLWU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK)
7182 #define LLWU_PF_WUF31_MASK (0x80000000U)
7183 #define LLWU_PF_WUF31_SHIFT (31U)
7184 /*! WUF31 - Wakeup Flag For LLWU_P31
7185  *  0b0..LLWU_P31 input was not a wakeup source
7186  *  0b1..LLWU_P31 input was a wakeup source
7187  */
7188 #define LLWU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK)
7189 /*! @} */
7190 
7191 /*! @name MF - LLWU Module Interrupt Flag register */
7192 /*! @{ */
7193 #define LLWU_MF_MWUF0_MASK (0x1U)
7194 #define LLWU_MF_MWUF0_SHIFT (0U)
7195 /*! MWUF0 - Wakeup flag For module 0
7196  *  0b0..Module 0 input was not a wakeup source
7197  *  0b1..Module 0 input was a wakeup source
7198  */
7199 #define LLWU_MF_MWUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF0_SHIFT)) & LLWU_MF_MWUF0_MASK)
7200 #define LLWU_MF_MWUF1_MASK (0x2U)
7201 #define LLWU_MF_MWUF1_SHIFT (1U)
7202 /*! MWUF1 - Wakeup flag For module 1
7203  *  0b0..Module 1 input was not a wakeup source
7204  *  0b1..Module 1 input was a wakeup source
7205  */
7206 #define LLWU_MF_MWUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF1_SHIFT)) & LLWU_MF_MWUF1_MASK)
7207 #define LLWU_MF_MWUF2_MASK (0x4U)
7208 #define LLWU_MF_MWUF2_SHIFT (2U)
7209 /*! MWUF2 - Wakeup flag For module 2
7210  *  0b0..Module 2 input was not a wakeup source
7211  *  0b1..Module 2 input was a wakeup source
7212  */
7213 #define LLWU_MF_MWUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF2_SHIFT)) & LLWU_MF_MWUF2_MASK)
7214 #define LLWU_MF_MWUF3_MASK (0x8U)
7215 #define LLWU_MF_MWUF3_SHIFT (3U)
7216 /*! MWUF3 - Wakeup flag For module 3
7217  *  0b0..Module 3 input was not a wakeup source
7218  *  0b1..Module 3 input was a wakeup source
7219  */
7220 #define LLWU_MF_MWUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF3_SHIFT)) & LLWU_MF_MWUF3_MASK)
7221 #define LLWU_MF_MWUF4_MASK (0x10U)
7222 #define LLWU_MF_MWUF4_SHIFT (4U)
7223 /*! MWUF4 - Wakeup flag For module 4
7224  *  0b0..Module 4 input was not a wakeup source
7225  *  0b1..Module 4 input was a wakeup source
7226  */
7227 #define LLWU_MF_MWUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF4_SHIFT)) & LLWU_MF_MWUF4_MASK)
7228 #define LLWU_MF_MWUF5_MASK (0x20U)
7229 #define LLWU_MF_MWUF5_SHIFT (5U)
7230 /*! MWUF5 - Wakeup flag For module 5
7231  *  0b0..Module 5 input was not a wakeup source
7232  *  0b1..Module 5 input was a wakeup source
7233  */
7234 #define LLWU_MF_MWUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF5_SHIFT)) & LLWU_MF_MWUF5_MASK)
7235 #define LLWU_MF_MWUF6_MASK (0x40U)
7236 #define LLWU_MF_MWUF6_SHIFT (6U)
7237 /*! MWUF6 - Wakeup flag For module 6
7238  *  0b0..Module 6 input was not a wakeup source
7239  *  0b1..Module 6 input was a wakeup source
7240  */
7241 #define LLWU_MF_MWUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF6_SHIFT)) & LLWU_MF_MWUF6_MASK)
7242 #define LLWU_MF_MWUF7_MASK (0x80U)
7243 #define LLWU_MF_MWUF7_SHIFT (7U)
7244 /*! MWUF7 - Wakeup flag For module 7
7245  *  0b0..Module 7 input was not a wakeup source
7246  *  0b1..Module 7 input was a wakeup source
7247  */
7248 #define LLWU_MF_MWUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF7_SHIFT)) & LLWU_MF_MWUF7_MASK)
7249 /*! @} */
7250 
7251 /*! @name FILT - LLWU Pin Filter register */
7252 /*! @{ */
7253 #define LLWU_FILT_FILTSEL1_MASK (0x1FU)
7254 #define LLWU_FILT_FILTSEL1_SHIFT (0U)
7255 /*! FILTSEL1 - Filter 1 Pin Select
7256  *  0b00000..Select LLWU_P0 for filter
7257  *  0b11111..Select LLWU_P31 for filter
7258  */
7259 #define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK)
7260 #define LLWU_FILT_FILTE1_MASK (0x60U)
7261 #define LLWU_FILT_FILTE1_SHIFT (5U)
7262 /*! FILTE1 - Filter 1 Enable
7263  *  0b00..Filter disabled
7264  *  0b01..Filter posedge detect enabled
7265  *  0b10..Filter negedge detect enabled
7266  *  0b11..Filter any edge detect enabled
7267  */
7268 #define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK)
7269 #define LLWU_FILT_FILTF1_MASK (0x80U)
7270 #define LLWU_FILT_FILTF1_SHIFT (7U)
7271 /*! FILTF1 - Filter 1 Flag
7272  *  0b0..Pin Filter 1 was not a wakeup source
7273  *  0b1..Pin Filter 1 was a wakeup source
7274  */
7275 #define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK)
7276 #define LLWU_FILT_FILTSEL2_MASK (0x1F00U)
7277 #define LLWU_FILT_FILTSEL2_SHIFT (8U)
7278 /*! FILTSEL2 - Filter 2 Pin Select
7279  *  0b00000..Select LLWU_P0 for filter
7280  *  0b11111..Select LLWU_P31 for filter
7281  */
7282 #define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK)
7283 #define LLWU_FILT_FILTE2_MASK (0x6000U)
7284 #define LLWU_FILT_FILTE2_SHIFT (13U)
7285 /*! FILTE2 - Filter 2 Enable
7286  *  0b00..Filter disabled
7287  *  0b01..Filter posedge detect enabled
7288  *  0b10..Filter negedge detect enabled
7289  *  0b11..Filter any edge detect enabled
7290  */
7291 #define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK)
7292 #define LLWU_FILT_FILTF2_MASK (0x8000U)
7293 #define LLWU_FILT_FILTF2_SHIFT (15U)
7294 /*! FILTF2 - Filter 2 Flag
7295  *  0b0..Pin Filter 1 was not a wakeup source
7296  *  0b1..Pin Filter 1 was a wakeup source
7297  */
7298 #define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK)
7299 #define LLWU_FILT_FILTSEL3_MASK (0x1F0000U)
7300 #define LLWU_FILT_FILTSEL3_SHIFT (16U)
7301 /*! FILTSEL3 - Filter 3 Pin Select
7302  *  0b00000..Select LLWU_P0 for filter
7303  *  0b11111..Select LLWU_P31 for filter
7304  */
7305 #define LLWU_FILT_FILTSEL3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL3_SHIFT)) & LLWU_FILT_FILTSEL3_MASK)
7306 #define LLWU_FILT_FILTE3_MASK (0x600000U)
7307 #define LLWU_FILT_FILTE3_SHIFT (21U)
7308 /*! FILTE3 - Filter 3 Enable
7309  *  0b00..Filter disabled
7310  *  0b01..Filter posedge detect enabled
7311  *  0b10..Filter negedge detect enabled
7312  *  0b11..Filter any edge detect enabled
7313  */
7314 #define LLWU_FILT_FILTE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE3_SHIFT)) & LLWU_FILT_FILTE3_MASK)
7315 #define LLWU_FILT_FILTF3_MASK (0x800000U)
7316 #define LLWU_FILT_FILTF3_SHIFT (23U)
7317 /*! FILTF3 - Filter 3 Flag
7318  *  0b0..Pin Filter 1 was not a wakeup source
7319  *  0b1..Pin Filter 1 was a wakeup source
7320  */
7321 #define LLWU_FILT_FILTF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF3_SHIFT)) & LLWU_FILT_FILTF3_MASK)
7322 #define LLWU_FILT_FILTSEL4_MASK (0x1F000000U)
7323 #define LLWU_FILT_FILTSEL4_SHIFT (24U)
7324 /*! FILTSEL4 - Filter 4 Pin Select
7325  *  0b00000..Select LLWU_P0 for filter
7326  *  0b11111..Select LLWU_P31 for filter
7327  */
7328 #define LLWU_FILT_FILTSEL4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL4_SHIFT)) & LLWU_FILT_FILTSEL4_MASK)
7329 #define LLWU_FILT_FILTE4_MASK (0x60000000U)
7330 #define LLWU_FILT_FILTE4_SHIFT (29U)
7331 /*! FILTE4 - Filter 4 Enable
7332  *  0b00..Filter disabled
7333  *  0b01..Filter posedge detect enabled
7334  *  0b10..Filter negedge detect enabled
7335  *  0b11..Filter any edge detect enabled
7336  */
7337 #define LLWU_FILT_FILTE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE4_SHIFT)) & LLWU_FILT_FILTE4_MASK)
7338 #define LLWU_FILT_FILTF4_MASK (0x80000000U)
7339 #define LLWU_FILT_FILTF4_SHIFT (31U)
7340 /*! FILTF4 - Filter 4 Flag
7341  *  0b0..Pin Filter 1 was not a wakeup source
7342  *  0b1..Pin Filter 1 was a wakeup source
7343  */
7344 #define LLWU_FILT_FILTF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF4_SHIFT)) & LLWU_FILT_FILTF4_MASK)
7345 /*! @} */
7346 
7347 /*!
7348  * @}
7349  */ /* end of group LLWU_Register_Masks */
7350 
7351 /* LLWU - Peripheral instance base addresses */
7352 /** Peripheral LLWU base address */
7353 #define LLWU_BASE (0x40061000u)
7354 /** Peripheral LLWU base pointer */
7355 #define LLWU ((LLWU_Type *)LLWU_BASE)
7356 /** Array initializer of LLWU peripheral base addresses */
7357 #define LLWU_BASE_ADDRS \
7358     {                   \
7359         LLWU_BASE       \
7360     }
7361 /** Array initializer of LLWU peripheral base pointers */
7362 #define LLWU_BASE_PTRS \
7363     {                  \
7364         LLWU           \
7365     }
7366 /** Interrupt vectors for the LLWU peripheral type */
7367 #define LLWU_IRQS \
7368     {             \
7369         LLWU_IRQn \
7370     }
7371 
7372 /*!
7373  * @}
7374  */ /* end of group LLWU_Peripheral_Access_Layer */
7375 
7376 /* ----------------------------------------------------------------------------
7377    -- LPI2C Peripheral Access Layer
7378    ---------------------------------------------------------------------------- */
7379 
7380 /*!
7381  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
7382  * @{
7383  */
7384 
7385 /** LPI2C - Register Layout Typedef */
7386 typedef struct
7387 {
7388     __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
7389     __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
7390     uint8_t RESERVED_0[8];
7391     __IO uint32_t MCR;    /**< Master Control Register, offset: 0x10 */
7392     __IO uint32_t MSR;    /**< Master Status Register, offset: 0x14 */
7393     __IO uint32_t MIER;   /**< Master Interrupt Enable Register, offset: 0x18 */
7394     __IO uint32_t MDER;   /**< Master DMA Enable Register, offset: 0x1C */
7395     __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
7396     __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
7397     __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
7398     __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
7399     uint8_t RESERVED_1[16];
7400     __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
7401     uint8_t RESERVED_2[4];
7402     __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
7403     uint8_t RESERVED_3[4];
7404     __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
7405     uint8_t RESERVED_4[4];
7406     __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
7407     __I uint32_t MFSR;  /**< Master FIFO Status Register, offset: 0x5C */
7408     __O uint32_t MTDR;  /**< Master Transmit Data Register, offset: 0x60 */
7409     uint8_t RESERVED_5[12];
7410     __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
7411     uint8_t RESERVED_6[156];
7412     __IO uint32_t SCR;  /**< Slave Control Register, offset: 0x110 */
7413     __IO uint32_t SSR;  /**< Slave Status Register, offset: 0x114 */
7414     __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
7415     __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
7416     uint8_t RESERVED_7[4];
7417     __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
7418     __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
7419     uint8_t RESERVED_8[20];
7420     __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
7421     uint8_t RESERVED_9[12];
7422     __I uint32_t SASR;  /**< Slave Address Status Register, offset: 0x150 */
7423     __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
7424     uint8_t RESERVED_10[8];
7425     __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
7426     uint8_t RESERVED_11[12];
7427     __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
7428 } LPI2C_Type;
7429 
7430 /* ----------------------------------------------------------------------------
7431    -- LPI2C Register Masks
7432    ---------------------------------------------------------------------------- */
7433 
7434 /*!
7435  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
7436  * @{
7437  */
7438 
7439 /*! @name VERID - Version ID Register */
7440 /*! @{ */
7441 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
7442 #define LPI2C_VERID_FEATURE_SHIFT (0U)
7443 /*! FEATURE - Feature Specification Number
7444  *  0b0000000000000010..Master only with standard feature set.
7445  *  0b0000000000000011..Master and slave with standard feature set.
7446  */
7447 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
7448 #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
7449 #define LPI2C_VERID_MINOR_SHIFT (16U)
7450 /*! MINOR - Minor Version Number
7451  */
7452 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
7453 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
7454 #define LPI2C_VERID_MAJOR_SHIFT (24U)
7455 /*! MAJOR - Major Version Number
7456  */
7457 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
7458 /*! @} */
7459 
7460 /*! @name PARAM - Parameter Register */
7461 /*! @{ */
7462 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
7463 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
7464 /*! MTXFIFO - Master Transmit FIFO Size
7465  */
7466 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
7467 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
7468 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
7469 /*! MRXFIFO - Master Receive FIFO Size
7470  */
7471 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
7472 /*! @} */
7473 
7474 /*! @name MCR - Master Control Register */
7475 /*! @{ */
7476 #define LPI2C_MCR_MEN_MASK (0x1U)
7477 #define LPI2C_MCR_MEN_SHIFT (0U)
7478 /*! MEN - Master Enable
7479  *  0b0..Master logic is disabled.
7480  *  0b1..Master logic is enabled.
7481  */
7482 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
7483 #define LPI2C_MCR_RST_MASK (0x2U)
7484 #define LPI2C_MCR_RST_SHIFT (1U)
7485 /*! RST - Software Reset
7486  *  0b0..Master logic is not reset.
7487  *  0b1..Master logic is reset.
7488  */
7489 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
7490 #define LPI2C_MCR_DOZEN_MASK (0x4U)
7491 #define LPI2C_MCR_DOZEN_SHIFT (2U)
7492 /*! DOZEN - Doze mode enable
7493  *  0b0..Master is enabled in Doze mode.
7494  *  0b1..Master is disabled in Doze mode.
7495  */
7496 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
7497 #define LPI2C_MCR_DBGEN_MASK (0x8U)
7498 #define LPI2C_MCR_DBGEN_SHIFT (3U)
7499 /*! DBGEN - Debug Enable
7500  *  0b0..Master is disabled in debug mode.
7501  *  0b1..Master is enabled in debug mode.
7502  */
7503 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
7504 #define LPI2C_MCR_RTF_MASK (0x100U)
7505 #define LPI2C_MCR_RTF_SHIFT (8U)
7506 /*! RTF - Reset Transmit FIFO
7507  *  0b0..No effect.
7508  *  0b1..Transmit FIFO is reset.
7509  */
7510 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
7511 #define LPI2C_MCR_RRF_MASK (0x200U)
7512 #define LPI2C_MCR_RRF_SHIFT (9U)
7513 /*! RRF - Reset Receive FIFO
7514  *  0b0..No effect.
7515  *  0b1..Receive FIFO is reset.
7516  */
7517 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
7518 /*! @} */
7519 
7520 /*! @name MSR - Master Status Register */
7521 /*! @{ */
7522 #define LPI2C_MSR_TDF_MASK (0x1U)
7523 #define LPI2C_MSR_TDF_SHIFT (0U)
7524 /*! TDF - Transmit Data Flag
7525  *  0b0..Transmit data not requested.
7526  *  0b1..Transmit data is requested.
7527  */
7528 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
7529 #define LPI2C_MSR_RDF_MASK (0x2U)
7530 #define LPI2C_MSR_RDF_SHIFT (1U)
7531 /*! RDF - Receive Data Flag
7532  *  0b0..Receive Data is not ready.
7533  *  0b1..Receive data is ready.
7534  */
7535 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
7536 #define LPI2C_MSR_EPF_MASK (0x100U)
7537 #define LPI2C_MSR_EPF_SHIFT (8U)
7538 /*! EPF - End Packet Flag
7539  *  0b0..Master has not generated a STOP or Repeated START condition.
7540  *  0b1..Master has generated a STOP or Repeated START condition.
7541  */
7542 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
7543 #define LPI2C_MSR_SDF_MASK (0x200U)
7544 #define LPI2C_MSR_SDF_SHIFT (9U)
7545 /*! SDF - STOP Detect Flag
7546  *  0b0..Master has not generated a STOP condition.
7547  *  0b1..Master has generated a STOP condition.
7548  */
7549 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
7550 #define LPI2C_MSR_NDF_MASK (0x400U)
7551 #define LPI2C_MSR_NDF_SHIFT (10U)
7552 /*! NDF - NACK Detect Flag
7553  *  0b0..Unexpected NACK not detected.
7554  *  0b1..Unexpected NACK was detected.
7555  */
7556 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
7557 #define LPI2C_MSR_ALF_MASK (0x800U)
7558 #define LPI2C_MSR_ALF_SHIFT (11U)
7559 /*! ALF - Arbitration Lost Flag
7560  *  0b0..Master has not lost arbitration.
7561  *  0b1..Master has lost arbitration.
7562  */
7563 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
7564 #define LPI2C_MSR_FEF_MASK (0x1000U)
7565 #define LPI2C_MSR_FEF_SHIFT (12U)
7566 /*! FEF - FIFO Error Flag
7567  *  0b0..No error.
7568  *  0b1..Master sending or receiving data without START condition.
7569  */
7570 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
7571 #define LPI2C_MSR_PLTF_MASK (0x2000U)
7572 #define LPI2C_MSR_PLTF_SHIFT (13U)
7573 /*! PLTF - Pin Low Timeout Flag
7574  *  0b0..Pin low timeout has not occurred or is disabled.
7575  *  0b1..Pin low timeout has occurred.
7576  */
7577 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
7578 #define LPI2C_MSR_DMF_MASK (0x4000U)
7579 #define LPI2C_MSR_DMF_SHIFT (14U)
7580 /*! DMF - Data Match Flag
7581  *  0b0..Have not received matching data.
7582  *  0b1..Have received matching data.
7583  */
7584 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
7585 #define LPI2C_MSR_MBF_MASK (0x1000000U)
7586 #define LPI2C_MSR_MBF_SHIFT (24U)
7587 /*! MBF - Master Busy Flag
7588  *  0b0..I2C Master is idle.
7589  *  0b1..I2C Master is busy.
7590  */
7591 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
7592 #define LPI2C_MSR_BBF_MASK (0x2000000U)
7593 #define LPI2C_MSR_BBF_SHIFT (25U)
7594 /*! BBF - Bus Busy Flag
7595  *  0b0..I2C Bus is idle.
7596  *  0b1..I2C Bus is busy.
7597  */
7598 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
7599 /*! @} */
7600 
7601 /*! @name MIER - Master Interrupt Enable Register */
7602 /*! @{ */
7603 #define LPI2C_MIER_TDIE_MASK (0x1U)
7604 #define LPI2C_MIER_TDIE_SHIFT (0U)
7605 /*! TDIE - Transmit Data Interrupt Enable
7606  *  0b0..Interrupt disabled.
7607  *  0b1..Interrupt enabled
7608  */
7609 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
7610 #define LPI2C_MIER_RDIE_MASK (0x2U)
7611 #define LPI2C_MIER_RDIE_SHIFT (1U)
7612 /*! RDIE - Receive Data Interrupt Enable
7613  *  0b0..Interrupt disabled.
7614  *  0b1..Interrupt enabled.
7615  */
7616 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
7617 #define LPI2C_MIER_EPIE_MASK (0x100U)
7618 #define LPI2C_MIER_EPIE_SHIFT (8U)
7619 /*! EPIE - End Packet Interrupt Enable
7620  *  0b0..Interrupt disabled.
7621  *  0b1..Interrupt enabled.
7622  */
7623 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
7624 #define LPI2C_MIER_SDIE_MASK (0x200U)
7625 #define LPI2C_MIER_SDIE_SHIFT (9U)
7626 /*! SDIE - STOP Detect Interrupt Enable
7627  *  0b0..Interrupt disabled.
7628  *  0b1..Interrupt enabled.
7629  */
7630 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
7631 #define LPI2C_MIER_NDIE_MASK (0x400U)
7632 #define LPI2C_MIER_NDIE_SHIFT (10U)
7633 /*! NDIE - NACK Detect Interrupt Enable
7634  *  0b0..Interrupt disabled.
7635  *  0b1..Interrupt enabled.
7636  */
7637 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
7638 #define LPI2C_MIER_ALIE_MASK (0x800U)
7639 #define LPI2C_MIER_ALIE_SHIFT (11U)
7640 /*! ALIE - Arbitration Lost Interrupt Enable
7641  *  0b0..Interrupt disabled.
7642  *  0b1..Interrupt enabled.
7643  */
7644 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
7645 #define LPI2C_MIER_FEIE_MASK (0x1000U)
7646 #define LPI2C_MIER_FEIE_SHIFT (12U)
7647 /*! FEIE - FIFO Error Interrupt Enable
7648  *  0b0..Interrupt disabled.
7649  *  0b1..Interrupt enabled.
7650  */
7651 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
7652 #define LPI2C_MIER_PLTIE_MASK (0x2000U)
7653 #define LPI2C_MIER_PLTIE_SHIFT (13U)
7654 /*! PLTIE - Pin Low Timeout Interrupt Enable
7655  *  0b0..Interrupt disabled.
7656  *  0b1..Interrupt enabled.
7657  */
7658 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
7659 #define LPI2C_MIER_DMIE_MASK (0x4000U)
7660 #define LPI2C_MIER_DMIE_SHIFT (14U)
7661 /*! DMIE - Data Match Interrupt Enable
7662  *  0b0..Interrupt disabled.
7663  *  0b1..Interrupt enabled.
7664  */
7665 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
7666 /*! @} */
7667 
7668 /*! @name MDER - Master DMA Enable Register */
7669 /*! @{ */
7670 #define LPI2C_MDER_TDDE_MASK (0x1U)
7671 #define LPI2C_MDER_TDDE_SHIFT (0U)
7672 /*! TDDE - Transmit Data DMA Enable
7673  *  0b0..DMA request disabled.
7674  *  0b1..DMA request enabled
7675  */
7676 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
7677 #define LPI2C_MDER_RDDE_MASK (0x2U)
7678 #define LPI2C_MDER_RDDE_SHIFT (1U)
7679 /*! RDDE - Receive Data DMA Enable
7680  *  0b0..DMA request disabled.
7681  *  0b1..DMA request enabled.
7682  */
7683 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
7684 /*! @} */
7685 
7686 /*! @name MCFGR0 - Master Configuration Register 0 */
7687 /*! @{ */
7688 #define LPI2C_MCFGR0_HREN_MASK (0x1U)
7689 #define LPI2C_MCFGR0_HREN_SHIFT (0U)
7690 /*! HREN - Host Request Enable
7691  *  0b0..Host request input is disabled.
7692  *  0b1..Host request input is enabled.
7693  */
7694 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
7695 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
7696 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
7697 /*! HRPOL - Host Request Polarity
7698  *  0b0..Active low.
7699  *  0b1..Active high.
7700  */
7701 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
7702 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
7703 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
7704 /*! HRSEL - Host Request Select
7705  *  0b0..Host request input is pin LPI2C_HREQ.
7706  *  0b1..Host request input is input trigger.
7707  */
7708 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
7709 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
7710 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
7711 /*! CIRFIFO - Circular FIFO Enable
7712  *  0b0..Circular FIFO is disabled.
7713  *  0b1..Circular FIFO is enabled.
7714  */
7715 #define LPI2C_MCFGR0_CIRFIFO(x) \
7716     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
7717 #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
7718 #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
7719 /*! RDMO - Receive Data Match Only
7720  *  0b0..Received data is stored in the receive FIFO as normal.
7721  *  0b1..Received data is discarded unless the RMF is set.
7722  */
7723 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
7724 /*! @} */
7725 
7726 /*! @name MCFGR1 - Master Configuration Register 1 */
7727 /*! @{ */
7728 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
7729 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
7730 /*! PRESCALE - Prescaler
7731  *  0b000..Divide by 1.
7732  *  0b001..Divide by 2.
7733  *  0b010..Divide by 4.
7734  *  0b011..Divide by 8.
7735  *  0b100..Divide by 16.
7736  *  0b101..Divide by 32.
7737  *  0b110..Divide by 64.
7738  *  0b111..Divide by 128.
7739  */
7740 #define LPI2C_MCFGR1_PRESCALE(x) \
7741     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
7742 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
7743 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
7744 /*! AUTOSTOP - Automatic STOP Generation
7745  *  0b0..No effect.
7746  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy.
7747  */
7748 #define LPI2C_MCFGR1_AUTOSTOP(x) \
7749     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
7750 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
7751 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
7752 /*! IGNACK
7753  *  0b0..LPI2C Master will receive ACK and NACK normally.
7754  *  0b1..LPI2C Master will treat a received NACK as if it was an ACK.
7755  */
7756 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
7757 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
7758 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
7759 /*! TIMECFG - Timeout Configuration
7760  *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout.
7761  *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout.
7762  */
7763 #define LPI2C_MCFGR1_TIMECFG(x) \
7764     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
7765 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
7766 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
7767 /*! MATCFG - Match Configuration
7768  *  0b000..Match disabled.
7769  *  0b001..Reserved.
7770  *  0b010..Match enabled (1st data word equals MATCH0 OR MATCH1).
7771  *  0b011..Match enabled (any data word equals MATCH0 OR MATCH1).
7772  *  0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).
7773  *  0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1).
7774  *  0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1).
7775  *  0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).
7776  */
7777 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
7778 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
7779 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
7780 /*! PINCFG - Pin Configuration
7781  *  0b000..LPI2C configured for 2-pin open drain mode.
7782  *  0b001..LPI2C configured for 2-pin output only mode (ultra-fast mode).
7783  *  0b010..LPI2C configured for 2-pin push-pull mode.
7784  *  0b011..LPI2C configured for 4-pin push-pull mode.
7785  *  0b100..LPI2C configured for 2-pin open drain mode with separate LPI2C slave.
7786  *  0b101..LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave.
7787  *  0b110..LPI2C configured for 2-pin push-pull mode with separate LPI2C slave.
7788  *  0b111..LPI2C configured for 4-pin push-pull mode (inverted outputs).
7789  */
7790 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
7791 /*! @} */
7792 
7793 /*! @name MCFGR2 - Master Configuration Register 2 */
7794 /*! @{ */
7795 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
7796 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
7797 /*! BUSIDLE - Bus Idle Timeout
7798  */
7799 #define LPI2C_MCFGR2_BUSIDLE(x) \
7800     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
7801 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
7802 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
7803 /*! FILTSCL - Glitch Filter SCL
7804  */
7805 #define LPI2C_MCFGR2_FILTSCL(x) \
7806     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
7807 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
7808 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
7809 /*! FILTSDA - Glitch Filter SDA
7810  */
7811 #define LPI2C_MCFGR2_FILTSDA(x) \
7812     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
7813 /*! @} */
7814 
7815 /*! @name MCFGR3 - Master Configuration Register 3 */
7816 /*! @{ */
7817 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
7818 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
7819 /*! PINLOW - Pin Low Timeout
7820  */
7821 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
7822 /*! @} */
7823 
7824 /*! @name MDMR - Master Data Match Register */
7825 /*! @{ */
7826 #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
7827 #define LPI2C_MDMR_MATCH0_SHIFT (0U)
7828 /*! MATCH0 - Match 0 Value
7829  */
7830 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
7831 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
7832 #define LPI2C_MDMR_MATCH1_SHIFT (16U)
7833 /*! MATCH1 - Match 1 Value
7834  */
7835 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
7836 /*! @} */
7837 
7838 /*! @name MCCR0 - Master Clock Configuration Register 0 */
7839 /*! @{ */
7840 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
7841 #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
7842 /*! CLKLO - Clock Low Period
7843  */
7844 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
7845 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
7846 #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
7847 /*! CLKHI - Clock High Period
7848  */
7849 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
7850 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
7851 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
7852 /*! SETHOLD - Setup Hold Delay
7853  */
7854 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
7855 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
7856 #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
7857 /*! DATAVD - Data Valid Delay
7858  */
7859 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
7860 /*! @} */
7861 
7862 /*! @name MCCR1 - Master Clock Configuration Register 1 */
7863 /*! @{ */
7864 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
7865 #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
7866 /*! CLKLO - Clock Low Period
7867  */
7868 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
7869 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
7870 #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
7871 /*! CLKHI - Clock High Period
7872  */
7873 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
7874 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
7875 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
7876 /*! SETHOLD - Setup Hold Delay
7877  */
7878 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
7879 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
7880 #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
7881 /*! DATAVD - Data Valid Delay
7882  */
7883 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
7884 /*! @} */
7885 
7886 /*! @name MFCR - Master FIFO Control Register */
7887 /*! @{ */
7888 #define LPI2C_MFCR_TXWATER_MASK (0xFFU)
7889 #define LPI2C_MFCR_TXWATER_SHIFT (0U)
7890 /*! TXWATER - Transmit FIFO Watermark
7891  */
7892 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
7893 #define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
7894 #define LPI2C_MFCR_RXWATER_SHIFT (16U)
7895 /*! RXWATER - Receive FIFO Watermark
7896  */
7897 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
7898 /*! @} */
7899 
7900 /*! @name MFSR - Master FIFO Status Register */
7901 /*! @{ */
7902 #define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
7903 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
7904 /*! TXCOUNT - Transmit FIFO Count
7905  */
7906 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
7907 #define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
7908 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
7909 /*! RXCOUNT - Receive FIFO Count
7910  */
7911 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
7912 /*! @} */
7913 
7914 /*! @name MTDR - Master Transmit Data Register */
7915 /*! @{ */
7916 #define LPI2C_MTDR_DATA_MASK (0xFFU)
7917 #define LPI2C_MTDR_DATA_SHIFT (0U)
7918 /*! DATA - Transmit Data
7919  */
7920 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
7921 #define LPI2C_MTDR_CMD_MASK (0x700U)
7922 #define LPI2C_MTDR_CMD_SHIFT (8U)
7923 /*! CMD - Command Data
7924  *  0b000..Transmit DATA[7:0].
7925  *  0b001..Receive (DATA[7:0] + 1) bytes.
7926  *  0b010..Generate STOP condition.
7927  *  0b011..Receive and discard (DATA[7:0] + 1) bytes.
7928  *  0b100..Generate (repeated) START and transmit address in DATA[7:0].
7929  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
7930  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode.
7931  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a
7932  * NACK to be returned.
7933  */
7934 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
7935 /*! @} */
7936 
7937 /*! @name MRDR - Master Receive Data Register */
7938 /*! @{ */
7939 #define LPI2C_MRDR_DATA_MASK (0xFFU)
7940 #define LPI2C_MRDR_DATA_SHIFT (0U)
7941 /*! DATA - Receive Data
7942  */
7943 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
7944 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
7945 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
7946 /*! RXEMPTY - RX Empty
7947  *  0b0..Receive FIFO is not empty.
7948  *  0b1..Receive FIFO is empty.
7949  */
7950 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
7951 /*! @} */
7952 
7953 /*! @name SCR - Slave Control Register */
7954 /*! @{ */
7955 #define LPI2C_SCR_SEN_MASK (0x1U)
7956 #define LPI2C_SCR_SEN_SHIFT (0U)
7957 /*! SEN - Slave Enable
7958  *  0b0..Slave mode is disabled.
7959  *  0b1..Slave mode is enabled.
7960  */
7961 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
7962 #define LPI2C_SCR_RST_MASK (0x2U)
7963 #define LPI2C_SCR_RST_SHIFT (1U)
7964 /*! RST - Software Reset
7965  *  0b0..Slave logic is not reset.
7966  *  0b1..Slave logic is reset.
7967  */
7968 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
7969 #define LPI2C_SCR_FILTEN_MASK (0x10U)
7970 #define LPI2C_SCR_FILTEN_SHIFT (4U)
7971 /*! FILTEN - Filter Enable
7972  *  0b0..Disable digital filter and output delay counter for slave mode.
7973  *  0b1..Enable digital filter and output delay counter for slave mode.
7974  */
7975 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
7976 #define LPI2C_SCR_FILTDZ_MASK (0x20U)
7977 #define LPI2C_SCR_FILTDZ_SHIFT (5U)
7978 /*! FILTDZ - Filter Doze Enable
7979  *  0b0..Filter remains enabled in Doze mode.
7980  *  0b1..Filter is disabled in Doze mode.
7981  */
7982 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
7983 #define LPI2C_SCR_RTF_MASK (0x100U)
7984 #define LPI2C_SCR_RTF_SHIFT (8U)
7985 /*! RTF - Reset Transmit FIFO
7986  *  0b0..No effect.
7987  *  0b1..Transmit Data Register is now empty.
7988  */
7989 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
7990 #define LPI2C_SCR_RRF_MASK (0x200U)
7991 #define LPI2C_SCR_RRF_SHIFT (9U)
7992 /*! RRF - Reset Receive FIFO
7993  *  0b0..No effect.
7994  *  0b1..Receive Data Register is now empty.
7995  */
7996 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
7997 /*! @} */
7998 
7999 /*! @name SSR - Slave Status Register */
8000 /*! @{ */
8001 #define LPI2C_SSR_TDF_MASK (0x1U)
8002 #define LPI2C_SSR_TDF_SHIFT (0U)
8003 /*! TDF - Transmit Data Flag
8004  *  0b0..Transmit data not requested.
8005  *  0b1..Transmit data is requested.
8006  */
8007 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
8008 #define LPI2C_SSR_RDF_MASK (0x2U)
8009 #define LPI2C_SSR_RDF_SHIFT (1U)
8010 /*! RDF - Receive Data Flag
8011  *  0b0..Receive Data is not ready.
8012  *  0b1..Receive data is ready.
8013  */
8014 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
8015 #define LPI2C_SSR_AVF_MASK (0x4U)
8016 #define LPI2C_SSR_AVF_SHIFT (2U)
8017 /*! AVF - Address Valid Flag
8018  *  0b0..Address Status Register is not valid.
8019  *  0b1..Address Status Register is valid.
8020  */
8021 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
8022 #define LPI2C_SSR_TAF_MASK (0x8U)
8023 #define LPI2C_SSR_TAF_SHIFT (3U)
8024 /*! TAF - Transmit ACK Flag
8025  *  0b0..Transmit ACK/NACK is not required.
8026  *  0b1..Transmit ACK/NACK is required.
8027  */
8028 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
8029 #define LPI2C_SSR_RSF_MASK (0x100U)
8030 #define LPI2C_SSR_RSF_SHIFT (8U)
8031 /*! RSF - Repeated Start Flag
8032  *  0b0..Slave has not detected a Repeated START condition.
8033  *  0b1..Slave has detected a Repeated START condition.
8034  */
8035 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
8036 #define LPI2C_SSR_SDF_MASK (0x200U)
8037 #define LPI2C_SSR_SDF_SHIFT (9U)
8038 /*! SDF - STOP Detect Flag
8039  *  0b0..Slave has not detected a STOP condition.
8040  *  0b1..Slave has detected a STOP condition.
8041  */
8042 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
8043 #define LPI2C_SSR_BEF_MASK (0x400U)
8044 #define LPI2C_SSR_BEF_SHIFT (10U)
8045 /*! BEF - Bit Error Flag
8046  *  0b0..Slave has not detected a bit error.
8047  *  0b1..Slave has detected a bit error.
8048  */
8049 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
8050 #define LPI2C_SSR_FEF_MASK (0x800U)
8051 #define LPI2C_SSR_FEF_SHIFT (11U)
8052 /*! FEF - FIFO Error Flag
8053  *  0b0..FIFO underflow or overflow not detected.
8054  *  0b1..FIFO underflow or overflow detected.
8055  */
8056 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
8057 #define LPI2C_SSR_AM0F_MASK (0x1000U)
8058 #define LPI2C_SSR_AM0F_SHIFT (12U)
8059 /*! AM0F - Address Match 0 Flag
8060  *  0b0..Have not received ADDR0 matching address.
8061  *  0b1..Have received ADDR0 matching address.
8062  */
8063 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
8064 #define LPI2C_SSR_AM1F_MASK (0x2000U)
8065 #define LPI2C_SSR_AM1F_SHIFT (13U)
8066 /*! AM1F - Address Match 1 Flag
8067  *  0b0..Have not received ADDR1 or ADDR0/ADDR1 range matching address.
8068  *  0b1..Have received ADDR1 or ADDR0/ADDR1 range matching address.
8069  */
8070 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
8071 #define LPI2C_SSR_GCF_MASK (0x4000U)
8072 #define LPI2C_SSR_GCF_SHIFT (14U)
8073 /*! GCF - General Call Flag
8074  *  0b0..Slave has not detected the General Call Address or General Call Address disabled.
8075  *  0b1..Slave has detected the General Call Address.
8076  */
8077 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
8078 #define LPI2C_SSR_SARF_MASK (0x8000U)
8079 #define LPI2C_SSR_SARF_SHIFT (15U)
8080 /*! SARF - SMBus Alert Response Flag
8081  *  0b0..SMBus Alert Response disabled or not detected.
8082  *  0b1..SMBus Alert Response enabled and detected.
8083  */
8084 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
8085 #define LPI2C_SSR_SBF_MASK (0x1000000U)
8086 #define LPI2C_SSR_SBF_SHIFT (24U)
8087 /*! SBF - Slave Busy Flag
8088  *  0b0..I2C Slave is idle.
8089  *  0b1..I2C Slave is busy.
8090  */
8091 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
8092 #define LPI2C_SSR_BBF_MASK (0x2000000U)
8093 #define LPI2C_SSR_BBF_SHIFT (25U)
8094 /*! BBF - Bus Busy Flag
8095  *  0b0..I2C Bus is idle.
8096  *  0b1..I2C Bus is busy.
8097  */
8098 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
8099 /*! @} */
8100 
8101 /*! @name SIER - Slave Interrupt Enable Register */
8102 /*! @{ */
8103 #define LPI2C_SIER_TDIE_MASK (0x1U)
8104 #define LPI2C_SIER_TDIE_SHIFT (0U)
8105 /*! TDIE - Transmit Data Interrupt Enable
8106  *  0b0..Interrupt disabled.
8107  *  0b1..Interrupt enabled
8108  */
8109 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
8110 #define LPI2C_SIER_RDIE_MASK (0x2U)
8111 #define LPI2C_SIER_RDIE_SHIFT (1U)
8112 /*! RDIE - Receive Data Interrupt Enable
8113  *  0b0..Interrupt disabled.
8114  *  0b1..Interrupt enabled.
8115  */
8116 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
8117 #define LPI2C_SIER_AVIE_MASK (0x4U)
8118 #define LPI2C_SIER_AVIE_SHIFT (2U)
8119 /*! AVIE - Address Valid Interrupt Enable
8120  *  0b0..Interrupt disabled.
8121  *  0b1..Interrupt enabled.
8122  */
8123 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
8124 #define LPI2C_SIER_TAIE_MASK (0x8U)
8125 #define LPI2C_SIER_TAIE_SHIFT (3U)
8126 /*! TAIE - Transmit ACK Interrupt Enable
8127  *  0b0..Interrupt disabled.
8128  *  0b1..Interrupt enabled.
8129  */
8130 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
8131 #define LPI2C_SIER_RSIE_MASK (0x100U)
8132 #define LPI2C_SIER_RSIE_SHIFT (8U)
8133 /*! RSIE - Repeated Start Interrupt Enable
8134  *  0b0..Interrupt disabled.
8135  *  0b1..Interrupt enabled.
8136  */
8137 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
8138 #define LPI2C_SIER_SDIE_MASK (0x200U)
8139 #define LPI2C_SIER_SDIE_SHIFT (9U)
8140 /*! SDIE - STOP Detect Interrupt Enable
8141  *  0b0..Interrupt disabled.
8142  *  0b1..Interrupt enabled.
8143  */
8144 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
8145 #define LPI2C_SIER_BEIE_MASK (0x400U)
8146 #define LPI2C_SIER_BEIE_SHIFT (10U)
8147 /*! BEIE - Bit Error Interrupt Enable
8148  *  0b0..Interrupt disabled.
8149  *  0b1..Interrupt enabled.
8150  */
8151 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
8152 #define LPI2C_SIER_FEIE_MASK (0x800U)
8153 #define LPI2C_SIER_FEIE_SHIFT (11U)
8154 /*! FEIE - FIFO Error Interrupt Enable
8155  *  0b0..Interrupt disabled.
8156  *  0b1..Interrupt enabled.
8157  */
8158 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
8159 #define LPI2C_SIER_AM0IE_MASK (0x1000U)
8160 #define LPI2C_SIER_AM0IE_SHIFT (12U)
8161 /*! AM0IE - Address Match 0 Interrupt Enable
8162  *  0b0..Interrupt enabled.
8163  *  0b1..Interrupt disabled.
8164  */
8165 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
8166 #define LPI2C_SIER_AM1F_MASK (0x2000U)
8167 #define LPI2C_SIER_AM1F_SHIFT (13U)
8168 /*! AM1F - Address Match 1 Interrupt Enable
8169  *  0b0..Interrupt disabled.
8170  *  0b1..Interrupt enabled.
8171  */
8172 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
8173 #define LPI2C_SIER_GCIE_MASK (0x4000U)
8174 #define LPI2C_SIER_GCIE_SHIFT (14U)
8175 /*! GCIE - General Call Interrupt Enable
8176  *  0b0..Interrupt disabled.
8177  *  0b1..Interrupt enabled.
8178  */
8179 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
8180 #define LPI2C_SIER_SARIE_MASK (0x8000U)
8181 #define LPI2C_SIER_SARIE_SHIFT (15U)
8182 /*! SARIE - SMBus Alert Response Interrupt Enable
8183  *  0b0..Interrupt disabled.
8184  *  0b1..Interrupt enabled.
8185  */
8186 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
8187 /*! @} */
8188 
8189 /*! @name SDER - Slave DMA Enable Register */
8190 /*! @{ */
8191 #define LPI2C_SDER_TDDE_MASK (0x1U)
8192 #define LPI2C_SDER_TDDE_SHIFT (0U)
8193 /*! TDDE - Transmit Data DMA Enable
8194  *  0b0..DMA request disabled.
8195  *  0b1..DMA request enabled
8196  */
8197 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
8198 #define LPI2C_SDER_RDDE_MASK (0x2U)
8199 #define LPI2C_SDER_RDDE_SHIFT (1U)
8200 /*! RDDE - Receive Data DMA Enable
8201  *  0b0..DMA request disabled.
8202  *  0b1..DMA request enabled.
8203  */
8204 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
8205 #define LPI2C_SDER_AVDE_MASK (0x4U)
8206 #define LPI2C_SDER_AVDE_SHIFT (2U)
8207 /*! AVDE - Address Valid DMA Enable
8208  *  0b0..DMA request disabled.
8209  *  0b1..DMA request enabled.
8210  */
8211 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
8212 /*! @} */
8213 
8214 /*! @name SCFGR1 - Slave Configuration Register 1 */
8215 /*! @{ */
8216 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
8217 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
8218 /*! ADRSTALL - Address SCL Stall
8219  *  0b0..Clock stretching disabled.
8220  *  0b1..Clock stretching enabled.
8221  */
8222 #define LPI2C_SCFGR1_ADRSTALL(x) \
8223     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
8224 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
8225 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
8226 /*! RXSTALL - RX SCL Stall
8227  *  0b0..Clock stretching disabled.
8228  *  0b1..Clock stretching enabled.
8229  */
8230 #define LPI2C_SCFGR1_RXSTALL(x) \
8231     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
8232 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
8233 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
8234 /*! TXDSTALL - TX Data SCL Stall
8235  *  0b0..Clock stretching disabled.
8236  *  0b1..Clock stretching enabled.
8237  */
8238 #define LPI2C_SCFGR1_TXDSTALL(x) \
8239     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
8240 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
8241 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
8242 /*! ACKSTALL - ACK SCL Stall
8243  *  0b0..Clock stretching disabled.
8244  *  0b1..Clock stretching enabled.
8245  */
8246 #define LPI2C_SCFGR1_ACKSTALL(x) \
8247     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
8248 #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
8249 #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
8250 /*! GCEN - General Call Enable
8251  *  0b0..General Call address is disabled.
8252  *  0b1..General call address is enabled.
8253  */
8254 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
8255 #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
8256 #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
8257 /*! SAEN - SMBus Alert Enable
8258  *  0b0..Disables match on SMBus Alert.
8259  *  0b1..Enables match on SMBus Alert.
8260  */
8261 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
8262 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
8263 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
8264 /*! TXCFG - Transmit Flag Configuration
8265  *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty.
8266  *  0b1..Transmit Data Flag will assert whenever the transmit data register is empty.
8267  */
8268 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
8269 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
8270 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
8271 /*! RXCFG - Receive Data Configuration
8272  *  0b0..Reading the receive data register will return receive data and clear the receive data flag.
8273  *  0b1..Reading the receive data register when the address valid flag is set will return the address status
8274  *       register and clear the address valid flag. Reading the receive data register when the address valid flag is
8275  *       clear will return receive data and clear the receive data flag.
8276  */
8277 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
8278 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
8279 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
8280 /*! IGNACK - Ignore NACK
8281  *  0b0..Slave will end transfer when NACK detected.
8282  *  0b1..Slave will not end transfer when NACK detected.
8283  */
8284 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
8285 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
8286 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
8287 /*! HSMEN - High Speed Mode Enable
8288  *  0b0..Disables detection of Hs-mode master code.
8289  *  0b1..Enables detection of Hs-mode master code.
8290  */
8291 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
8292 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
8293 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
8294 /*! ADDRCFG - Address Configuration
8295  *  0b000..Address match 0 (7-bit).
8296  *  0b001..Address match 0 (10-bit).
8297  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit).
8298  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit).
8299  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit).
8300  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit).
8301  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit).
8302  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit).
8303  */
8304 #define LPI2C_SCFGR1_ADDRCFG(x) \
8305     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
8306 /*! @} */
8307 
8308 /*! @name SCFGR2 - Slave Configuration Register 2 */
8309 /*! @{ */
8310 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
8311 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
8312 /*! CLKHOLD - Clock Hold Time
8313  */
8314 #define LPI2C_SCFGR2_CLKHOLD(x) \
8315     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
8316 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
8317 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
8318 /*! DATAVD - Data Valid Delay
8319  */
8320 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
8321 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
8322 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
8323 /*! FILTSCL - Glitch Filter SCL
8324  */
8325 #define LPI2C_SCFGR2_FILTSCL(x) \
8326     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
8327 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
8328 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
8329 /*! FILTSDA - Glitch Filter SDA
8330  */
8331 #define LPI2C_SCFGR2_FILTSDA(x) \
8332     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
8333 /*! @} */
8334 
8335 /*! @name SAMR - Slave Address Match Register */
8336 /*! @{ */
8337 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
8338 #define LPI2C_SAMR_ADDR0_SHIFT (1U)
8339 /*! ADDR0 - Address 0 Value
8340  */
8341 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
8342 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
8343 #define LPI2C_SAMR_ADDR1_SHIFT (17U)
8344 /*! ADDR1 - Address 1 Value
8345  */
8346 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
8347 /*! @} */
8348 
8349 /*! @name SASR - Slave Address Status Register */
8350 /*! @{ */
8351 #define LPI2C_SASR_RADDR_MASK (0x7FFU)
8352 #define LPI2C_SASR_RADDR_SHIFT (0U)
8353 /*! RADDR - Received Address
8354  */
8355 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
8356 #define LPI2C_SASR_ANV_MASK (0x4000U)
8357 #define LPI2C_SASR_ANV_SHIFT (14U)
8358 /*! ANV - Address Not Valid
8359  *  0b0..RADDR is valid.
8360  *  0b1..RADDR is not valid.
8361  */
8362 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
8363 /*! @} */
8364 
8365 /*! @name STAR - Slave Transmit ACK Register */
8366 /*! @{ */
8367 #define LPI2C_STAR_TXNACK_MASK (0x1U)
8368 #define LPI2C_STAR_TXNACK_SHIFT (0U)
8369 /*! TXNACK - Transmit NACK
8370  *  0b0..Transmit ACK for received word.
8371  *  0b1..Transmit NACK for received word.
8372  */
8373 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
8374 /*! @} */
8375 
8376 /*! @name STDR - Slave Transmit Data Register */
8377 /*! @{ */
8378 #define LPI2C_STDR_DATA_MASK (0xFFU)
8379 #define LPI2C_STDR_DATA_SHIFT (0U)
8380 /*! DATA - Transmit Data
8381  */
8382 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
8383 /*! @} */
8384 
8385 /*! @name SRDR - Slave Receive Data Register */
8386 /*! @{ */
8387 #define LPI2C_SRDR_DATA_MASK (0xFFU)
8388 #define LPI2C_SRDR_DATA_SHIFT (0U)
8389 /*! DATA - Receive Data
8390  */
8391 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
8392 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
8393 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
8394 /*! RXEMPTY - RX Empty
8395  *  0b0..The Receive Data Register is not empty.
8396  *  0b1..The Receive Data Register is empty.
8397  */
8398 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
8399 #define LPI2C_SRDR_SOF_MASK (0x8000U)
8400 #define LPI2C_SRDR_SOF_SHIFT (15U)
8401 /*! SOF - Start Of Frame
8402  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition.
8403  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition.
8404  */
8405 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
8406 /*! @} */
8407 
8408 /*!
8409  * @}
8410  */ /* end of group LPI2C_Register_Masks */
8411 
8412 /* LPI2C - Peripheral instance base addresses */
8413 /** Peripheral LPI2C0 base address */
8414 #define LPI2C0_BASE (0x400C0000u)
8415 /** Peripheral LPI2C0 base pointer */
8416 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
8417 /** Peripheral LPI2C1 base address */
8418 #define LPI2C1_BASE (0x400C1000u)
8419 /** Peripheral LPI2C1 base pointer */
8420 #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
8421 /** Peripheral LPI2C2 base address */
8422 #define LPI2C2_BASE (0x40042000u)
8423 /** Peripheral LPI2C2 base pointer */
8424 #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
8425 /** Array initializer of LPI2C peripheral base addresses */
8426 #define LPI2C_BASE_ADDRS                      \
8427     {                                         \
8428         LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE \
8429     }
8430 /** Array initializer of LPI2C peripheral base pointers */
8431 #define LPI2C_BASE_PTRS        \
8432     {                          \
8433         LPI2C0, LPI2C1, LPI2C2 \
8434     }
8435 /** Interrupt vectors for the LPI2C peripheral type */
8436 #define LPI2C_IRQS                            \
8437     {                                         \
8438         LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn \
8439     }
8440 
8441 /*!
8442  * @}
8443  */ /* end of group LPI2C_Peripheral_Access_Layer */
8444 
8445 /* ----------------------------------------------------------------------------
8446    -- LPIT Peripheral Access Layer
8447    ---------------------------------------------------------------------------- */
8448 
8449 /*!
8450  * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
8451  * @{
8452  */
8453 
8454 /** LPIT - Register Layout Typedef */
8455 typedef struct
8456 {
8457     __I uint32_t VERID;   /**< Version ID Register, offset: 0x0 */
8458     __I uint32_t PARAM;   /**< Parameter Register, offset: 0x4 */
8459     __IO uint32_t MCR;    /**< Module Control Register, offset: 0x8 */
8460     __IO uint32_t MSR;    /**< Module Status Register, offset: 0xC */
8461     __IO uint32_t MIER;   /**< Module Interrupt Enable Register, offset: 0x10 */
8462     __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */
8463     __O uint32_t CLRTEN;  /**< Clear Timer Enable Register, offset: 0x18 */
8464     uint8_t RESERVED_0[4];
8465     struct
8466     {                        /* offset: 0x20, array step: 0x10 */
8467         __IO uint32_t TVAL;  /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
8468         __I uint32_t CVAL;   /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
8469         __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
8470         uint8_t RESERVED_0[4];
8471     } CHANNEL[4];
8472 } LPIT_Type;
8473 
8474 /* ----------------------------------------------------------------------------
8475    -- LPIT Register Masks
8476    ---------------------------------------------------------------------------- */
8477 
8478 /*!
8479  * @addtogroup LPIT_Register_Masks LPIT Register Masks
8480  * @{
8481  */
8482 
8483 /*! @name VERID - Version ID Register */
8484 /*! @{ */
8485 #define LPIT_VERID_FEATURE_MASK (0xFFFFU)
8486 #define LPIT_VERID_FEATURE_SHIFT (0U)
8487 /*! FEATURE - Feature Number
8488  */
8489 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
8490 #define LPIT_VERID_MINOR_MASK (0xFF0000U)
8491 #define LPIT_VERID_MINOR_SHIFT (16U)
8492 /*! MINOR - Minor Version Number
8493  */
8494 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
8495 #define LPIT_VERID_MAJOR_MASK (0xFF000000U)
8496 #define LPIT_VERID_MAJOR_SHIFT (24U)
8497 /*! MAJOR - Major Version Number
8498  */
8499 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
8500 /*! @} */
8501 
8502 /*! @name PARAM - Parameter Register */
8503 /*! @{ */
8504 #define LPIT_PARAM_CHANNEL_MASK (0xFFU)
8505 #define LPIT_PARAM_CHANNEL_SHIFT (0U)
8506 /*! CHANNEL - Number of Timer Channels
8507  */
8508 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
8509 #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U)
8510 #define LPIT_PARAM_EXT_TRIG_SHIFT (8U)
8511 /*! EXT_TRIG - Number of External Trigger Inputs
8512  */
8513 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
8514 /*! @} */
8515 
8516 /*! @name MCR - Module Control Register */
8517 /*! @{ */
8518 #define LPIT_MCR_M_CEN_MASK (0x1U)
8519 #define LPIT_MCR_M_CEN_SHIFT (0U)
8520 /*! M_CEN - Module Clock Enable
8521  *  0b0..Protocol clock to timers is disabled
8522  *  0b1..Protocol clock to timers is enabled
8523  */
8524 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
8525 #define LPIT_MCR_SW_RST_MASK (0x2U)
8526 #define LPIT_MCR_SW_RST_SHIFT (1U)
8527 /*! SW_RST - Software Reset Bit
8528  *  0b0..Timer channels and registers are not reset
8529  *  0b1..Timer channels and registers are reset
8530  */
8531 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
8532 #define LPIT_MCR_DOZE_EN_MASK (0x4U)
8533 #define LPIT_MCR_DOZE_EN_SHIFT (2U)
8534 /*! DOZE_EN - DOZE Mode Enable Bit
8535  *  0b0..Timer channels are stopped in DOZE mode
8536  *  0b1..Timer channels continue to run in DOZE mode
8537  */
8538 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
8539 #define LPIT_MCR_DBG_EN_MASK (0x8U)
8540 #define LPIT_MCR_DBG_EN_SHIFT (3U)
8541 /*! DBG_EN - Debug Enable Bit
8542  *  0b0..Timer channels are stopped in Debug mode
8543  *  0b1..Timer channels continue to run in Debug mode
8544  */
8545 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
8546 /*! @} */
8547 
8548 /*! @name MSR - Module Status Register */
8549 /*! @{ */
8550 #define LPIT_MSR_TIF0_MASK (0x1U)
8551 #define LPIT_MSR_TIF0_SHIFT (0U)
8552 /*! TIF0 - Channel 0 Timer Interrupt Flag
8553  *  0b0..Timer has not timed out
8554  *  0b1..Timeout has occurred
8555  */
8556 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
8557 #define LPIT_MSR_TIF1_MASK (0x2U)
8558 #define LPIT_MSR_TIF1_SHIFT (1U)
8559 /*! TIF1 - Channel 1 Timer Interrupt Flag
8560  *  0b0..Timer has not timed out
8561  *  0b1..Timeout has occurred
8562  */
8563 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
8564 #define LPIT_MSR_TIF2_MASK (0x4U)
8565 #define LPIT_MSR_TIF2_SHIFT (2U)
8566 /*! TIF2 - Channel 2 Timer Interrupt Flag
8567  *  0b0..Timer has not timed out
8568  *  0b1..Timeout has occurred
8569  */
8570 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
8571 #define LPIT_MSR_TIF3_MASK (0x8U)
8572 #define LPIT_MSR_TIF3_SHIFT (3U)
8573 /*! TIF3 - Channel 3 Timer Interrupt Flag
8574  *  0b0..Timer has not timed out
8575  *  0b1..Timeout has occurred
8576  */
8577 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
8578 /*! @} */
8579 
8580 /*! @name MIER - Module Interrupt Enable Register */
8581 /*! @{ */
8582 #define LPIT_MIER_TIE0_MASK (0x1U)
8583 #define LPIT_MIER_TIE0_SHIFT (0U)
8584 /*! TIE0 - Channel 0 Timer Interrupt Enable
8585  *  0b0..Interrupt generation is disabled
8586  *  0b1..Interrupt generation is enabled
8587  */
8588 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
8589 #define LPIT_MIER_TIE1_MASK (0x2U)
8590 #define LPIT_MIER_TIE1_SHIFT (1U)
8591 /*! TIE1 - Channel 1 Timer Interrupt Enable
8592  *  0b0..Interrupt generation is disabled
8593  *  0b1..Interrupt generation is enabled
8594  */
8595 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
8596 #define LPIT_MIER_TIE2_MASK (0x4U)
8597 #define LPIT_MIER_TIE2_SHIFT (2U)
8598 /*! TIE2 - Channel 2 Timer Interrupt Enable
8599  *  0b0..Interrupt generation is disabled
8600  *  0b1..Interrupt generation is enabled
8601  */
8602 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
8603 #define LPIT_MIER_TIE3_MASK (0x8U)
8604 #define LPIT_MIER_TIE3_SHIFT (3U)
8605 /*! TIE3 - Channel 3 Timer Interrupt Enable
8606  *  0b0..Interrupt generation is disabled
8607  *  0b1..Interrupt generation is enabled
8608  */
8609 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
8610 /*! @} */
8611 
8612 /*! @name SETTEN - Set Timer Enable Register */
8613 /*! @{ */
8614 #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U)
8615 #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U)
8616 /*! SET_T_EN_0 - Set Timer 0 Enable
8617  *  0b0..No effect
8618  *  0b1..Enables the Timer Channel 0
8619  */
8620 #define LPIT_SETTEN_SET_T_EN_0(x) \
8621     (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
8622 #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U)
8623 #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U)
8624 /*! SET_T_EN_1 - Set Timer 1 Enable
8625  *  0b0..No Effect
8626  *  0b1..Enables the Timer Channel 1
8627  */
8628 #define LPIT_SETTEN_SET_T_EN_1(x) \
8629     (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
8630 #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U)
8631 #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U)
8632 /*! SET_T_EN_2 - Set Timer 2 Enable
8633  *  0b0..No Effect
8634  *  0b1..Enables the Timer Channel 2
8635  */
8636 #define LPIT_SETTEN_SET_T_EN_2(x) \
8637     (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
8638 #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U)
8639 #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U)
8640 /*! SET_T_EN_3 - Set Timer 3 Enable
8641  *  0b0..No effect
8642  *  0b1..Enables the Timer Channel 3
8643  */
8644 #define LPIT_SETTEN_SET_T_EN_3(x) \
8645     (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
8646 /*! @} */
8647 
8648 /*! @name CLRTEN - Clear Timer Enable Register */
8649 /*! @{ */
8650 #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U)
8651 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U)
8652 /*! CLR_T_EN_0 - Clear Timer 0 Enable
8653  *  0b0..No action
8654  *  0b1..Clear T_EN bit for Timer Channel 0
8655  */
8656 #define LPIT_CLRTEN_CLR_T_EN_0(x) \
8657     (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
8658 #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U)
8659 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U)
8660 /*! CLR_T_EN_1 - Clear Timer 1 Enable
8661  *  0b0..No Action
8662  *  0b1..Clear T_EN bit for Timer Channel 1
8663  */
8664 #define LPIT_CLRTEN_CLR_T_EN_1(x) \
8665     (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
8666 #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U)
8667 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U)
8668 /*! CLR_T_EN_2 - Clear Timer 2 Enable
8669  *  0b0..No Action
8670  *  0b1..Clear T_EN bit for Timer Channel 2
8671  */
8672 #define LPIT_CLRTEN_CLR_T_EN_2(x) \
8673     (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
8674 #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U)
8675 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U)
8676 /*! CLR_T_EN_3 - Clear Timer 3 Enable
8677  *  0b0..No Action
8678  *  0b1..Clear T_EN bit for Timer Channel 3
8679  */
8680 #define LPIT_CLRTEN_CLR_T_EN_3(x) \
8681     (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
8682 /*! @} */
8683 
8684 /*! @name TVAL - Timer Value Register */
8685 /*! @{ */
8686 #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU)
8687 #define LPIT_TVAL_TMR_VAL_SHIFT (0U)
8688 /*! TMR_VAL - Timer Value
8689  *  0b00000000000000000000000000000000..Invalid load value in compare modes
8690  */
8691 #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
8692 /*! @} */
8693 
8694 /* The count of LPIT_TVAL */
8695 #define LPIT_TVAL_COUNT (4U)
8696 
8697 /*! @name CVAL - Current Timer Value */
8698 /*! @{ */
8699 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU)
8700 #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U)
8701 /*! TMR_CUR_VAL - Current Timer Value
8702  */
8703 #define LPIT_CVAL_TMR_CUR_VAL(x) \
8704     (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
8705 /*! @} */
8706 
8707 /* The count of LPIT_CVAL */
8708 #define LPIT_CVAL_COUNT (4U)
8709 
8710 /*! @name TCTRL - Timer Control Register */
8711 /*! @{ */
8712 #define LPIT_TCTRL_T_EN_MASK (0x1U)
8713 #define LPIT_TCTRL_T_EN_SHIFT (0U)
8714 /*! T_EN - Timer Enable
8715  *  0b0..Timer Channel is disabled
8716  *  0b1..Timer Channel is enabled
8717  */
8718 #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
8719 #define LPIT_TCTRL_CHAIN_MASK (0x2U)
8720 #define LPIT_TCTRL_CHAIN_SHIFT (1U)
8721 /*! CHAIN - Chain Channel
8722  *  0b0..Channel Chaining is disabled. Channel Timer runs independently.
8723  *  0b1..Channel Chaining is enabled. Timer decrements on previous channel's timeout
8724  */
8725 #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
8726 #define LPIT_TCTRL_MODE_MASK (0xCU)
8727 #define LPIT_TCTRL_MODE_SHIFT (2U)
8728 /*! MODE - Timer Operation Mode
8729  *  0b00..32-bit Periodic Counter
8730  *  0b01..Dual 16-bit Periodic Counter
8731  *  0b10..32-bit Trigger Accumulator
8732  *  0b11..32-bit Trigger Input Capture
8733  */
8734 #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
8735 #define LPIT_TCTRL_TSOT_MASK (0x10000U)
8736 #define LPIT_TCTRL_TSOT_SHIFT (16U)
8737 /*! TSOT - Timer Start On Trigger
8738  *  0b0..Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)
8739  *  0b1..Timer starts to decrement when rising edge on selected trigger is detected
8740  */
8741 #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
8742 #define LPIT_TCTRL_TSOI_MASK (0x20000U)
8743 #define LPIT_TCTRL_TSOI_SHIFT (17U)
8744 /*! TSOI - Timer Stop On Interrupt
8745  *  0b0..Timer does not stop after timeout
8746  *  0b1..Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer
8747  *       channel is disabled and then enabled)
8748  */
8749 #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
8750 #define LPIT_TCTRL_TROT_MASK (0x40000U)
8751 #define LPIT_TCTRL_TROT_SHIFT (18U)
8752 /*! TROT - Timer Reload On Trigger
8753  *  0b0..Timer will not reload on selected trigger
8754  *  0b1..Timer will reload on selected trigger
8755  */
8756 #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
8757 #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U)
8758 #define LPIT_TCTRL_TRG_SRC_SHIFT (23U)
8759 /*! TRG_SRC - Trigger Source
8760  *  0b0..Trigger source selected in external
8761  *  0b1..Trigger source selected is the internal trigger
8762  */
8763 #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
8764 #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U)
8765 #define LPIT_TCTRL_TRG_SEL_SHIFT (24U)
8766 /*! TRG_SEL - Trigger Select
8767  *  0b0000..Timer channel 0 trigger source is selected
8768  *  0b0001..Timer channel 1 trigger source is selected
8769  *  0b0010..Timer channel 2 trigger source is selected
8770  */
8771 #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
8772 /*! @} */
8773 
8774 /* The count of LPIT_TCTRL */
8775 #define LPIT_TCTRL_COUNT (4U)
8776 
8777 /*!
8778  * @}
8779  */ /* end of group LPIT_Register_Masks */
8780 
8781 /* LPIT - Peripheral instance base addresses */
8782 /** Peripheral LPIT0 base address */
8783 #define LPIT0_BASE (0x40030000u)
8784 /** Peripheral LPIT0 base pointer */
8785 #define LPIT0 ((LPIT_Type *)LPIT0_BASE)
8786 /** Array initializer of LPIT peripheral base addresses */
8787 #define LPIT_BASE_ADDRS \
8788     {                   \
8789         LPIT0_BASE      \
8790     }
8791 /** Array initializer of LPIT peripheral base pointers */
8792 #define LPIT_BASE_PTRS \
8793     {                  \
8794         LPIT0          \
8795     }
8796 /** Interrupt vectors for the LPIT peripheral type */
8797 #define LPIT_IRQS                                          \
8798     {                                                      \
8799         {                                                  \
8800             LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn \
8801         }                                                  \
8802     }
8803 
8804 /*!
8805  * @}
8806  */ /* end of group LPIT_Peripheral_Access_Layer */
8807 
8808 /* ----------------------------------------------------------------------------
8809    -- LPSPI Peripheral Access Layer
8810    ---------------------------------------------------------------------------- */
8811 
8812 /*!
8813  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
8814  * @{
8815  */
8816 
8817 /** LPSPI - Register Layout Typedef */
8818 typedef struct
8819 {
8820     __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
8821     __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
8822     uint8_t RESERVED_0[8];
8823     __IO uint32_t CR;    /**< Control Register, offset: 0x10 */
8824     __IO uint32_t SR;    /**< Status Register, offset: 0x14 */
8825     __IO uint32_t IER;   /**< Interrupt Enable Register, offset: 0x18 */
8826     __IO uint32_t DER;   /**< DMA Enable Register, offset: 0x1C */
8827     __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
8828     __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
8829     uint8_t RESERVED_1[8];
8830     __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
8831     __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
8832     uint8_t RESERVED_2[8];
8833     __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
8834     uint8_t RESERVED_3[20];
8835     __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
8836     __I uint32_t FSR;  /**< FIFO Status Register, offset: 0x5C */
8837     __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
8838     __O uint32_t TDR;  /**< Transmit Data Register, offset: 0x64 */
8839     uint8_t RESERVED_4[8];
8840     __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
8841     __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
8842 } LPSPI_Type;
8843 
8844 /* ----------------------------------------------------------------------------
8845    -- LPSPI Register Masks
8846    ---------------------------------------------------------------------------- */
8847 
8848 /*!
8849  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
8850  * @{
8851  */
8852 
8853 /*! @name VERID - Version ID Register */
8854 /*! @{ */
8855 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
8856 #define LPSPI_VERID_FEATURE_SHIFT (0U)
8857 /*! FEATURE - Module Identification Number
8858  *  0b0000000000000100..Standard feature set supporting 32-bit shift register.
8859  */
8860 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
8861 #define LPSPI_VERID_MINOR_MASK (0xFF0000U)
8862 #define LPSPI_VERID_MINOR_SHIFT (16U)
8863 /*! MINOR - Minor Version Number
8864  */
8865 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
8866 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
8867 #define LPSPI_VERID_MAJOR_SHIFT (24U)
8868 /*! MAJOR - Major Version Number
8869  */
8870 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
8871 /*! @} */
8872 
8873 /*! @name PARAM - Parameter Register */
8874 /*! @{ */
8875 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
8876 #define LPSPI_PARAM_TXFIFO_SHIFT (0U)
8877 /*! TXFIFO - Transmit FIFO Size
8878  */
8879 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
8880 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
8881 #define LPSPI_PARAM_RXFIFO_SHIFT (8U)
8882 /*! RXFIFO - Receive FIFO Size
8883  */
8884 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
8885 /*! @} */
8886 
8887 /*! @name CR - Control Register */
8888 /*! @{ */
8889 #define LPSPI_CR_MEN_MASK (0x1U)
8890 #define LPSPI_CR_MEN_SHIFT (0U)
8891 /*! MEN - Module Enable
8892  *  0b0..Module is disabled.
8893  *  0b1..Module is enabled.
8894  */
8895 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
8896 #define LPSPI_CR_RST_MASK (0x2U)
8897 #define LPSPI_CR_RST_SHIFT (1U)
8898 /*! RST - Software Reset
8899  *  0b0..Master logic is not reset.
8900  *  0b1..Master logic is reset.
8901  */
8902 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
8903 #define LPSPI_CR_DOZEN_MASK (0x4U)
8904 #define LPSPI_CR_DOZEN_SHIFT (2U)
8905 /*! DOZEN - Doze mode enable
8906  *  0b0..Module is enabled in Doze mode.
8907  *  0b1..Module is disabled in Doze mode.
8908  */
8909 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
8910 #define LPSPI_CR_DBGEN_MASK (0x8U)
8911 #define LPSPI_CR_DBGEN_SHIFT (3U)
8912 /*! DBGEN - Debug Enable
8913  *  0b0..Module is disabled in debug mode.
8914  *  0b1..Module is enabled in debug mode.
8915  */
8916 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
8917 #define LPSPI_CR_RTF_MASK (0x100U)
8918 #define LPSPI_CR_RTF_SHIFT (8U)
8919 /*! RTF - Reset Transmit FIFO
8920  *  0b0..No effect.
8921  *  0b1..Transmit FIFO is reset.
8922  */
8923 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
8924 #define LPSPI_CR_RRF_MASK (0x200U)
8925 #define LPSPI_CR_RRF_SHIFT (9U)
8926 /*! RRF - Reset Receive FIFO
8927  *  0b0..No effect.
8928  *  0b1..Receive FIFO is reset.
8929  */
8930 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
8931 /*! @} */
8932 
8933 /*! @name SR - Status Register */
8934 /*! @{ */
8935 #define LPSPI_SR_TDF_MASK (0x1U)
8936 #define LPSPI_SR_TDF_SHIFT (0U)
8937 /*! TDF - Transmit Data Flag
8938  *  0b0..Transmit data not requested.
8939  *  0b1..Transmit data is requested.
8940  */
8941 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
8942 #define LPSPI_SR_RDF_MASK (0x2U)
8943 #define LPSPI_SR_RDF_SHIFT (1U)
8944 /*! RDF - Receive Data Flag
8945  *  0b0..Receive Data is not ready.
8946  *  0b1..Receive data is ready.
8947  */
8948 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
8949 #define LPSPI_SR_WCF_MASK (0x100U)
8950 #define LPSPI_SR_WCF_SHIFT (8U)
8951 /*! WCF - Word Complete Flag
8952  *  0b0..Transfer word not completed.
8953  *  0b1..Transfer word completed.
8954  */
8955 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
8956 #define LPSPI_SR_FCF_MASK (0x200U)
8957 #define LPSPI_SR_FCF_SHIFT (9U)
8958 /*! FCF - Frame Complete Flag
8959  *  0b0..Frame transfer has not completed.
8960  *  0b1..Frame transfer has completed.
8961  */
8962 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
8963 #define LPSPI_SR_TCF_MASK (0x400U)
8964 #define LPSPI_SR_TCF_SHIFT (10U)
8965 /*! TCF - Transfer Complete Flag
8966  *  0b0..All transfers have not completed.
8967  *  0b1..All transfers have completed.
8968  */
8969 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
8970 #define LPSPI_SR_TEF_MASK (0x800U)
8971 #define LPSPI_SR_TEF_SHIFT (11U)
8972 /*! TEF - Transmit Error Flag
8973  *  0b0..Transmit FIFO underrun has not occurred.
8974  *  0b1..Transmit FIFO underrun has occurred
8975  */
8976 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
8977 #define LPSPI_SR_REF_MASK (0x1000U)
8978 #define LPSPI_SR_REF_SHIFT (12U)
8979 /*! REF - Receive Error Flag
8980  *  0b0..Receive FIFO has not overflowed.
8981  *  0b1..Receive FIFO has overflowed.
8982  */
8983 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
8984 #define LPSPI_SR_DMF_MASK (0x2000U)
8985 #define LPSPI_SR_DMF_SHIFT (13U)
8986 /*! DMF - Data Match Flag
8987  *  0b0..Have not received matching data.
8988  *  0b1..Have received matching data.
8989  */
8990 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
8991 #define LPSPI_SR_MBF_MASK (0x1000000U)
8992 #define LPSPI_SR_MBF_SHIFT (24U)
8993 /*! MBF - Module Busy Flag
8994  *  0b0..LPSPI is idle.
8995  *  0b1..LPSPI is busy.
8996  */
8997 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
8998 /*! @} */
8999 
9000 /*! @name IER - Interrupt Enable Register */
9001 /*! @{ */
9002 #define LPSPI_IER_TDIE_MASK (0x1U)
9003 #define LPSPI_IER_TDIE_SHIFT (0U)
9004 /*! TDIE - Transmit Data Interrupt Enable
9005  *  0b0..Interrupt disabled.
9006  *  0b1..Interrupt enabled
9007  */
9008 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
9009 #define LPSPI_IER_RDIE_MASK (0x2U)
9010 #define LPSPI_IER_RDIE_SHIFT (1U)
9011 /*! RDIE - Receive Data Interrupt Enable
9012  *  0b0..Interrupt disabled.
9013  *  0b1..Interrupt enabled.
9014  */
9015 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
9016 #define LPSPI_IER_WCIE_MASK (0x100U)
9017 #define LPSPI_IER_WCIE_SHIFT (8U)
9018 /*! WCIE - Word Complete Interrupt Enable
9019  *  0b0..Interrupt disabled.
9020  *  0b1..Interrupt enabled.
9021  */
9022 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
9023 #define LPSPI_IER_FCIE_MASK (0x200U)
9024 #define LPSPI_IER_FCIE_SHIFT (9U)
9025 /*! FCIE - Frame Complete Interrupt Enable
9026  *  0b0..Interrupt disabled.
9027  *  0b1..Interrupt enabled.
9028  */
9029 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
9030 #define LPSPI_IER_TCIE_MASK (0x400U)
9031 #define LPSPI_IER_TCIE_SHIFT (10U)
9032 /*! TCIE - Transfer Complete Interrupt Enable
9033  *  0b0..Interrupt disabled.
9034  *  0b1..Interrupt enabled.
9035  */
9036 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
9037 #define LPSPI_IER_TEIE_MASK (0x800U)
9038 #define LPSPI_IER_TEIE_SHIFT (11U)
9039 /*! TEIE - Transmit Error Interrupt Enable
9040  *  0b0..Interrupt disabled.
9041  *  0b1..Interrupt enabled.
9042  */
9043 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
9044 #define LPSPI_IER_REIE_MASK (0x1000U)
9045 #define LPSPI_IER_REIE_SHIFT (12U)
9046 /*! REIE - Receive Error Interrupt Enable
9047  *  0b0..Interrupt disabled.
9048  *  0b1..Interrupt enabled.
9049  */
9050 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
9051 #define LPSPI_IER_DMIE_MASK (0x2000U)
9052 #define LPSPI_IER_DMIE_SHIFT (13U)
9053 /*! DMIE - Data Match Interrupt Enable
9054  *  0b0..Interrupt disabled.
9055  *  0b1..Interrupt enabled.
9056  */
9057 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
9058 /*! @} */
9059 
9060 /*! @name DER - DMA Enable Register */
9061 /*! @{ */
9062 #define LPSPI_DER_TDDE_MASK (0x1U)
9063 #define LPSPI_DER_TDDE_SHIFT (0U)
9064 /*! TDDE - Transmit Data DMA Enable
9065  *  0b0..DMA request disabled.
9066  *  0b1..DMA request enabled
9067  */
9068 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
9069 #define LPSPI_DER_RDDE_MASK (0x2U)
9070 #define LPSPI_DER_RDDE_SHIFT (1U)
9071 /*! RDDE - Receive Data DMA Enable
9072  *  0b0..DMA request disabled.
9073  *  0b1..DMA request enabled.
9074  */
9075 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
9076 /*! @} */
9077 
9078 /*! @name CFGR0 - Configuration Register 0 */
9079 /*! @{ */
9080 #define LPSPI_CFGR0_HREN_MASK (0x1U)
9081 #define LPSPI_CFGR0_HREN_SHIFT (0U)
9082 /*! HREN - Host Request Enable
9083  *  0b0..Host request is disabled.
9084  *  0b1..Host request is enabled.
9085  */
9086 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
9087 #define LPSPI_CFGR0_HRPOL_MASK (0x2U)
9088 #define LPSPI_CFGR0_HRPOL_SHIFT (1U)
9089 /*! HRPOL - Host Request Polarity
9090  *  0b0..Active low.
9091  *  0b1..Active high.
9092  */
9093 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
9094 #define LPSPI_CFGR0_HRSEL_MASK (0x4U)
9095 #define LPSPI_CFGR0_HRSEL_SHIFT (2U)
9096 /*! HRSEL - Host Request Select
9097  *  0b0..Host request input is pin LPSPI_HREQ.
9098  *  0b1..Host request input is input trigger.
9099  */
9100 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
9101 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
9102 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
9103 /*! CIRFIFO - Circular FIFO Enable
9104  *  0b0..Circular FIFO is disabled.
9105  *  0b1..Circular FIFO is enabled.
9106  */
9107 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
9108 #define LPSPI_CFGR0_RDMO_MASK (0x200U)
9109 #define LPSPI_CFGR0_RDMO_SHIFT (9U)
9110 /*! RDMO - Receive Data Match Only
9111  *  0b0..Received data is stored in the receive FIFO as normal.
9112  *  0b1..Received data is discarded unless the DMF is set.
9113  */
9114 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
9115 /*! @} */
9116 
9117 /*! @name CFGR1 - Configuration Register 1 */
9118 /*! @{ */
9119 #define LPSPI_CFGR1_MASTER_MASK (0x1U)
9120 #define LPSPI_CFGR1_MASTER_SHIFT (0U)
9121 /*! MASTER - Master Mode
9122  *  0b0..Slave mode.
9123  *  0b1..Master mode.
9124  */
9125 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
9126 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
9127 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
9128 /*! SAMPLE - Sample Point
9129  *  0b0..Input data sampled on SCK edge.
9130  *  0b1..Input data sampled on delayed SCK edge.
9131  */
9132 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
9133 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
9134 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
9135 /*! AUTOPCS - Automatic PCS
9136  *  0b0..Automatic PCS generation disabled.
9137  *  0b1..Automatic PCS generation enabled.
9138  */
9139 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
9140 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
9141 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
9142 /*! NOSTALL - No Stall
9143  *  0b0..Transfers will stall when transmit FIFO is empty or receive FIFO is full.
9144  *  0b1..Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur.
9145  */
9146 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
9147 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
9148 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
9149 /*! PCSPOL - Peripheral Chip Select Polarity
9150  *  0b0000..The PCSx is active low.
9151  *  0b0001..The PCSx is active high.
9152  */
9153 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
9154 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
9155 #define LPSPI_CFGR1_MATCFG_SHIFT (16U)
9156 /*! MATCFG - Match Configuration
9157  *  0b000..Match disabled.
9158  *  0b001..Reserved
9159  *  0b010..Match enabled (1st data word equals MATCH0 OR MATCH1).
9160  *  0b011..Match enabled (any data word equals MATCH0 OR MATCH1).
9161  *  0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).
9162  *  0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)
9163  *  0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
9164  *  0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).
9165  */
9166 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
9167 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
9168 #define LPSPI_CFGR1_PINCFG_SHIFT (24U)
9169 /*! PINCFG - Pin Configuration
9170  *  0b00..SIN is used for input data and SOUT for output data.
9171  *  0b01..SIN is used for both input and output data.
9172  *  0b10..SOUT is used for both input and output data.
9173  *  0b11..SOUT is used for input data and SIN for output data.
9174  */
9175 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
9176 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
9177 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
9178 /*! OUTCFG - Output Config
9179  *  0b0..Output data retains last value when chip select is negated.
9180  *  0b1..Output data is tristated when chip select is negated.
9181  */
9182 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
9183 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
9184 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
9185 /*! PCSCFG - Peripheral Chip Select Configuration
9186  *  0b0..PCS[3:2] are enabled.
9187  *  0b1..PCS[3:2] are disabled.
9188  */
9189 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
9190 /*! @} */
9191 
9192 /*! @name DMR0 - Data Match Register 0 */
9193 /*! @{ */
9194 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
9195 #define LPSPI_DMR0_MATCH0_SHIFT (0U)
9196 /*! MATCH0 - Match 0 Value
9197  */
9198 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
9199 /*! @} */
9200 
9201 /*! @name DMR1 - Data Match Register 1 */
9202 /*! @{ */
9203 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
9204 #define LPSPI_DMR1_MATCH1_SHIFT (0U)
9205 /*! MATCH1 - Match 1 Value
9206  */
9207 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
9208 /*! @} */
9209 
9210 /*! @name CCR - Clock Configuration Register */
9211 /*! @{ */
9212 #define LPSPI_CCR_SCKDIV_MASK (0xFFU)
9213 #define LPSPI_CCR_SCKDIV_SHIFT (0U)
9214 /*! SCKDIV - SCK Divider
9215  */
9216 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
9217 #define LPSPI_CCR_DBT_MASK (0xFF00U)
9218 #define LPSPI_CCR_DBT_SHIFT (8U)
9219 /*! DBT - Delay Between Transfers
9220  */
9221 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
9222 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
9223 #define LPSPI_CCR_PCSSCK_SHIFT (16U)
9224 /*! PCSSCK - PCS to SCK Delay
9225  */
9226 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
9227 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
9228 #define LPSPI_CCR_SCKPCS_SHIFT (24U)
9229 /*! SCKPCS - SCK to PCS Delay
9230  */
9231 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
9232 /*! @} */
9233 
9234 /*! @name FCR - FIFO Control Register */
9235 /*! @{ */
9236 #define LPSPI_FCR_TXWATER_MASK (0xFFU)
9237 #define LPSPI_FCR_TXWATER_SHIFT (0U)
9238 /*! TXWATER - Transmit FIFO Watermark
9239  */
9240 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
9241 #define LPSPI_FCR_RXWATER_MASK (0xFF0000U)
9242 #define LPSPI_FCR_RXWATER_SHIFT (16U)
9243 /*! RXWATER - Receive FIFO Watermark
9244  */
9245 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
9246 /*! @} */
9247 
9248 /*! @name FSR - FIFO Status Register */
9249 /*! @{ */
9250 #define LPSPI_FSR_TXCOUNT_MASK (0xFFU)
9251 #define LPSPI_FSR_TXCOUNT_SHIFT (0U)
9252 /*! TXCOUNT - Transmit FIFO Count
9253  */
9254 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
9255 #define LPSPI_FSR_RXCOUNT_MASK (0xFF0000U)
9256 #define LPSPI_FSR_RXCOUNT_SHIFT (16U)
9257 /*! RXCOUNT - Receive FIFO Count
9258  */
9259 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
9260 /*! @} */
9261 
9262 /*! @name TCR - Transmit Command Register */
9263 /*! @{ */
9264 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
9265 #define LPSPI_TCR_FRAMESZ_SHIFT (0U)
9266 /*! FRAMESZ - Frame Size
9267  */
9268 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
9269 #define LPSPI_TCR_WIDTH_MASK (0x30000U)
9270 #define LPSPI_TCR_WIDTH_SHIFT (16U)
9271 /*! WIDTH - Transfer Width
9272  *  0b00..Single bit transfer.
9273  *  0b01..Two bit transfer.
9274  *  0b10..Four bit transfer.
9275  *  0b11..Reserved.
9276  */
9277 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
9278 #define LPSPI_TCR_TXMSK_MASK (0x40000U)
9279 #define LPSPI_TCR_TXMSK_SHIFT (18U)
9280 /*! TXMSK - Transmit Data Mask
9281  *  0b0..Normal transfer.
9282  *  0b1..Mask transmit data.
9283  */
9284 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
9285 #define LPSPI_TCR_RXMSK_MASK (0x80000U)
9286 #define LPSPI_TCR_RXMSK_SHIFT (19U)
9287 /*! RXMSK - Receive Data Mask
9288  *  0b0..Normal transfer.
9289  *  0b1..Receive data is masked.
9290  */
9291 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
9292 #define LPSPI_TCR_CONTC_MASK (0x100000U)
9293 #define LPSPI_TCR_CONTC_SHIFT (20U)
9294 /*! CONTC - Continuing Command
9295  *  0b0..Command word for start of new transfer.
9296  *  0b1..Command word for continuing transfer.
9297  */
9298 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
9299 #define LPSPI_TCR_CONT_MASK (0x200000U)
9300 #define LPSPI_TCR_CONT_SHIFT (21U)
9301 /*! CONT - Continuous Transfer
9302  *  0b0..Continuous transfer disabled.
9303  *  0b1..Continuous transfer enabled.
9304  */
9305 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
9306 #define LPSPI_TCR_BYSW_MASK (0x400000U)
9307 #define LPSPI_TCR_BYSW_SHIFT (22U)
9308 /*! BYSW - Byte Swap
9309  *  0b0..Byte swap disabled.
9310  *  0b1..Byte swap enabled.
9311  */
9312 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
9313 #define LPSPI_TCR_LSBF_MASK (0x800000U)
9314 #define LPSPI_TCR_LSBF_SHIFT (23U)
9315 /*! LSBF - LSB First
9316  *  0b0..Data is transferred MSB first.
9317  *  0b1..Data is transferred LSB first.
9318  */
9319 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
9320 #define LPSPI_TCR_PCS_MASK (0x3000000U)
9321 #define LPSPI_TCR_PCS_SHIFT (24U)
9322 /*! PCS - Peripheral Chip Select
9323  *  0b00..Transfer using LPSPI_PCS[0]
9324  *  0b01..Transfer using LPSPI_PCS[1]
9325  *  0b10..Transfer using LPSPI_PCS[2]
9326  *  0b11..Transfer using LPSPI_PCS[3]
9327  */
9328 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
9329 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
9330 #define LPSPI_TCR_PRESCALE_SHIFT (27U)
9331 /*! PRESCALE - Prescaler Value
9332  *  0b000..Divide by 1.
9333  *  0b001..Divide by 2.
9334  *  0b010..Divide by 4.
9335  *  0b011..Divide by 8.
9336  *  0b100..Divide by 16.
9337  *  0b101..Divide by 32.
9338  *  0b110..Divide by 64.
9339  *  0b111..Divide by 128.
9340  */
9341 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
9342 #define LPSPI_TCR_CPHA_MASK (0x40000000U)
9343 #define LPSPI_TCR_CPHA_SHIFT (30U)
9344 /*! CPHA - Clock Phase
9345  *  0b0..Data is captured on the leading edge of SCK and changed on the following edge.
9346  *  0b1..Data is changed on the leading edge of SCK and captured on the following edge.
9347  */
9348 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
9349 #define LPSPI_TCR_CPOL_MASK (0x80000000U)
9350 #define LPSPI_TCR_CPOL_SHIFT (31U)
9351 /*! CPOL - Clock Polarity
9352  *  0b0..The inactive state value of SCK is low.
9353  *  0b1..The inactive state value of SCK is high.
9354  */
9355 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
9356 /*! @} */
9357 
9358 /*! @name TDR - Transmit Data Register */
9359 /*! @{ */
9360 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
9361 #define LPSPI_TDR_DATA_SHIFT (0U)
9362 /*! DATA - Transmit Data
9363  */
9364 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
9365 /*! @} */
9366 
9367 /*! @name RSR - Receive Status Register */
9368 /*! @{ */
9369 #define LPSPI_RSR_SOF_MASK (0x1U)
9370 #define LPSPI_RSR_SOF_SHIFT (0U)
9371 /*! SOF - Start Of Frame
9372  *  0b0..Subsequent data word received after LPSPI_PCS assertion.
9373  *  0b1..First data word received after LPSPI_PCS assertion.
9374  */
9375 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
9376 #define LPSPI_RSR_RXEMPTY_MASK (0x2U)
9377 #define LPSPI_RSR_RXEMPTY_SHIFT (1U)
9378 /*! RXEMPTY - RX FIFO Empty
9379  *  0b0..RX FIFO is not empty.
9380  *  0b1..RX FIFO is empty.
9381  */
9382 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
9383 /*! @} */
9384 
9385 /*! @name RDR - Receive Data Register */
9386 /*! @{ */
9387 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
9388 #define LPSPI_RDR_DATA_SHIFT (0U)
9389 /*! DATA - Receive Data
9390  */
9391 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
9392 /*! @} */
9393 
9394 /*!
9395  * @}
9396  */ /* end of group LPSPI_Register_Masks */
9397 
9398 /* LPSPI - Peripheral instance base addresses */
9399 /** Peripheral LPSPI0 base address */
9400 #define LPSPI0_BASE (0x400BC000u)
9401 /** Peripheral LPSPI0 base pointer */
9402 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
9403 /** Peripheral LPSPI1 base address */
9404 #define LPSPI1_BASE (0x400BD000u)
9405 /** Peripheral LPSPI1 base pointer */
9406 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
9407 /** Peripheral LPSPI2 base address */
9408 #define LPSPI2_BASE (0x4003E000u)
9409 /** Peripheral LPSPI2 base pointer */
9410 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
9411 /** Array initializer of LPSPI peripheral base addresses */
9412 #define LPSPI_BASE_ADDRS                      \
9413     {                                         \
9414         LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE \
9415     }
9416 /** Array initializer of LPSPI peripheral base pointers */
9417 #define LPSPI_BASE_PTRS        \
9418     {                          \
9419         LPSPI0, LPSPI1, LPSPI2 \
9420     }
9421 /** Interrupt vectors for the LPSPI peripheral type */
9422 #define LPSPI_IRQS                            \
9423     {                                         \
9424         LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn \
9425     }
9426 
9427 /*!
9428  * @}
9429  */ /* end of group LPSPI_Peripheral_Access_Layer */
9430 
9431 /* ----------------------------------------------------------------------------
9432    -- LPTMR Peripheral Access Layer
9433    ---------------------------------------------------------------------------- */
9434 
9435 /*!
9436  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
9437  * @{
9438  */
9439 
9440 /** LPTMR - Register Layout Typedef */
9441 typedef struct
9442 {
9443     __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
9444     __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
9445     __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
9446     __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
9447 } LPTMR_Type;
9448 
9449 /* ----------------------------------------------------------------------------
9450    -- LPTMR Register Masks
9451    ---------------------------------------------------------------------------- */
9452 
9453 /*!
9454  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
9455  * @{
9456  */
9457 
9458 /*! @name CSR - Low Power Timer Control Status Register */
9459 /*! @{ */
9460 #define LPTMR_CSR_TEN_MASK (0x1U)
9461 #define LPTMR_CSR_TEN_SHIFT (0U)
9462 /*! TEN - Timer Enable
9463  *  0b0..LPTMR is disabled and internal logic is reset.
9464  *  0b1..LPTMR is enabled.
9465  */
9466 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
9467 #define LPTMR_CSR_TMS_MASK (0x2U)
9468 #define LPTMR_CSR_TMS_SHIFT (1U)
9469 /*! TMS - Timer Mode Select
9470  *  0b0..Time Counter mode.
9471  *  0b1..Pulse Counter mode.
9472  */
9473 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
9474 #define LPTMR_CSR_TFC_MASK (0x4U)
9475 #define LPTMR_CSR_TFC_SHIFT (2U)
9476 /*! TFC - Timer Free-Running Counter
9477  *  0b0..CNR is reset whenever TCF is set.
9478  *  0b1..CNR is reset on overflow.
9479  */
9480 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
9481 #define LPTMR_CSR_TPP_MASK (0x8U)
9482 #define LPTMR_CSR_TPP_SHIFT (3U)
9483 /*! TPP - Timer Pin Polarity
9484  *  0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
9485  *  0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
9486  */
9487 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
9488 #define LPTMR_CSR_TPS_MASK (0x30U)
9489 #define LPTMR_CSR_TPS_SHIFT (4U)
9490 /*! TPS - Timer Pin Select
9491  *  0b00..Pulse counter input 0 is selected.
9492  *  0b01..Pulse counter input 1 is selected.
9493  *  0b10..Pulse counter input 2 is selected.
9494  *  0b11..Pulse counter input 3 is selected.
9495  */
9496 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
9497 #define LPTMR_CSR_TIE_MASK (0x40U)
9498 #define LPTMR_CSR_TIE_SHIFT (6U)
9499 /*! TIE - Timer Interrupt Enable
9500  *  0b0..Timer interrupt disabled.
9501  *  0b1..Timer interrupt enabled.
9502  */
9503 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
9504 #define LPTMR_CSR_TCF_MASK (0x80U)
9505 #define LPTMR_CSR_TCF_SHIFT (7U)
9506 /*! TCF - Timer Compare Flag
9507  *  0b0..The value of CNR is not equal to CMR and increments.
9508  *  0b1..The value of CNR is equal to CMR and increments.
9509  */
9510 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
9511 #define LPTMR_CSR_TDRE_MASK (0x100U)
9512 #define LPTMR_CSR_TDRE_SHIFT (8U)
9513 /*! TDRE - Timer DMA Request Enable
9514  *  0b0..Timer DMA Request disabled.
9515  *  0b1..Timer DMA Request enabled.
9516  */
9517 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
9518 /*! @} */
9519 
9520 /*! @name PSR - Low Power Timer Prescale Register */
9521 /*! @{ */
9522 #define LPTMR_PSR_PCS_MASK (0x3U)
9523 #define LPTMR_PSR_PCS_SHIFT (0U)
9524 /*! PCS - Prescaler Clock Select
9525  *  0b00..Prescaler/glitch filter clock 0 selected.
9526  *  0b01..Prescaler/glitch filter clock 1 selected.
9527  *  0b10..Prescaler/glitch filter clock 2 selected.
9528  *  0b11..Prescaler/glitch filter clock 3 selected.
9529  */
9530 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
9531 #define LPTMR_PSR_PBYP_MASK (0x4U)
9532 #define LPTMR_PSR_PBYP_SHIFT (2U)
9533 /*! PBYP - Prescaler Bypass
9534  *  0b0..Prescaler/glitch filter is enabled.
9535  *  0b1..Prescaler/glitch filter is bypassed.
9536  */
9537 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
9538 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
9539 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
9540 /*! PRESCALE - Prescale Value
9541  *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
9542  *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising
9543  * clock edges. 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4
9544  * rising clock edges. 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin
9545  * after 8 rising clock edges. 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on
9546  * input pin after 16 rising clock edges. 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes
9547  * change on input pin after 32 rising clock edges. 0b0110..Prescaler divides the prescaler clock by 128; glitch filter
9548  * recognizes change on input pin after 64 rising clock edges. 0b0111..Prescaler divides the prescaler clock by 256;
9549  * glitch filter recognizes change on input pin after 128 rising clock edges. 0b1000..Prescaler divides the prescaler
9550  * clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0b1001..Prescaler divides
9551  * the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
9552  *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024
9553  * rising clock edges. 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input
9554  * pin after 2048 rising clock edges. 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes
9555  * change on input pin after 4096 rising clock edges. 0b1101..Prescaler divides the prescaler clock by 16,384; glitch
9556  * filter recognizes change on input pin after 8192 rising clock edges. 0b1110..Prescaler divides the prescaler clock by
9557  * 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0b1111..Prescaler divides the
9558  * prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
9559  */
9560 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
9561 /*! @} */
9562 
9563 /*! @name CMR - Low Power Timer Compare Register */
9564 /*! @{ */
9565 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
9566 #define LPTMR_CMR_COMPARE_SHIFT (0U)
9567 /*! COMPARE - Compare Value
9568  */
9569 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
9570 /*! @} */
9571 
9572 /*! @name CNR - Low Power Timer Counter Register */
9573 /*! @{ */
9574 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
9575 #define LPTMR_CNR_COUNTER_SHIFT (0U)
9576 /*! COUNTER - Counter Value
9577  */
9578 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
9579 /*! @} */
9580 
9581 /*!
9582  * @}
9583  */ /* end of group LPTMR_Register_Masks */
9584 
9585 /* LPTMR - Peripheral instance base addresses */
9586 /** Peripheral LPTMR0 base address */
9587 #define LPTMR0_BASE (0x40034000u)
9588 /** Peripheral LPTMR0 base pointer */
9589 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
9590 /** Peripheral LPTMR1 base address */
9591 #define LPTMR1_BASE (0x400B5000u)
9592 /** Peripheral LPTMR1 base pointer */
9593 #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE)
9594 /** Array initializer of LPTMR peripheral base addresses */
9595 #define LPTMR_BASE_ADDRS         \
9596     {                            \
9597         LPTMR0_BASE, LPTMR1_BASE \
9598     }
9599 /** Array initializer of LPTMR peripheral base pointers */
9600 #define LPTMR_BASE_PTRS \
9601     {                   \
9602         LPTMR0, LPTMR1  \
9603     }
9604 /** Interrupt vectors for the LPTMR peripheral type */
9605 #define LPTMR_IRQS               \
9606     {                            \
9607         LPTMR0_IRQn, LPTMR1_IRQn \
9608     }
9609 
9610 /*!
9611  * @}
9612  */ /* end of group LPTMR_Peripheral_Access_Layer */
9613 
9614 /* ----------------------------------------------------------------------------
9615    -- LPUART Peripheral Access Layer
9616    ---------------------------------------------------------------------------- */
9617 
9618 /*!
9619  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
9620  * @{
9621  */
9622 
9623 /** LPUART - Register Layout Typedef */
9624 typedef struct
9625 {
9626     __I uint32_t VERID;   /**< Version ID Register, offset: 0x0 */
9627     __I uint32_t PARAM;   /**< Parameter Register, offset: 0x4 */
9628     __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
9629     __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
9630     __IO uint32_t BAUD;   /**< LPUART Baud Rate Register, offset: 0x10 */
9631     __IO uint32_t STAT;   /**< LPUART Status Register, offset: 0x14 */
9632     __IO uint32_t CTRL;   /**< LPUART Control Register, offset: 0x18 */
9633     __IO uint32_t DATA;   /**< LPUART Data Register, offset: 0x1C */
9634     __IO uint32_t MATCH;  /**< LPUART Match Address Register, offset: 0x20 */
9635     __IO uint32_t MODIR;  /**< LPUART Modem IrDA Register, offset: 0x24 */
9636     __IO uint32_t FIFO;   /**< LPUART FIFO Register, offset: 0x28 */
9637     __IO uint32_t WATER;  /**< LPUART Watermark Register, offset: 0x2C */
9638 } LPUART_Type;
9639 
9640 /* ----------------------------------------------------------------------------
9641    -- LPUART Register Masks
9642    ---------------------------------------------------------------------------- */
9643 
9644 /*!
9645  * @addtogroup LPUART_Register_Masks LPUART Register Masks
9646  * @{
9647  */
9648 
9649 /*! @name VERID - Version ID Register */
9650 /*! @{ */
9651 #define LPUART_VERID_FEATURE_MASK (0xFFFFU)
9652 #define LPUART_VERID_FEATURE_SHIFT (0U)
9653 /*! FEATURE - Feature Identification Number
9654  *  0b0000000000000001..Standard feature set.
9655  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
9656  */
9657 #define LPUART_VERID_FEATURE(x) \
9658     (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
9659 #define LPUART_VERID_MINOR_MASK (0xFF0000U)
9660 #define LPUART_VERID_MINOR_SHIFT (16U)
9661 /*! MINOR - Minor Version Number
9662  */
9663 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
9664 #define LPUART_VERID_MAJOR_MASK (0xFF000000U)
9665 #define LPUART_VERID_MAJOR_SHIFT (24U)
9666 /*! MAJOR - Major Version Number
9667  */
9668 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
9669 /*! @} */
9670 
9671 /*! @name PARAM - Parameter Register */
9672 /*! @{ */
9673 #define LPUART_PARAM_TXFIFO_MASK (0xFFU)
9674 #define LPUART_PARAM_TXFIFO_SHIFT (0U)
9675 /*! TXFIFO - Transmit FIFO Size
9676  */
9677 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
9678 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
9679 #define LPUART_PARAM_RXFIFO_SHIFT (8U)
9680 /*! RXFIFO - Receive FIFO Size
9681  */
9682 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
9683 /*! @} */
9684 
9685 /*! @name GLOBAL - LPUART Global Register */
9686 /*! @{ */
9687 #define LPUART_GLOBAL_RST_MASK (0x2U)
9688 #define LPUART_GLOBAL_RST_SHIFT (1U)
9689 /*! RST - Software Reset
9690  *  0b0..Module is not reset.
9691  *  0b1..Module is reset.
9692  */
9693 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
9694 /*! @} */
9695 
9696 /*! @name PINCFG - LPUART Pin Configuration Register */
9697 /*! @{ */
9698 #define LPUART_PINCFG_TRGSEL_MASK (0x3U)
9699 #define LPUART_PINCFG_TRGSEL_SHIFT (0U)
9700 /*! TRGSEL - Trigger Select
9701  *  0b00..Input trigger is disabled.
9702  *  0b01..Input trigger is used instead of RXD pin input.
9703  *  0b10..Input trigger is used instead of CTS pin input.
9704  *  0b11..Input trigger is used to modulate the TXD pin output.
9705  */
9706 #define LPUART_PINCFG_TRGSEL(x) \
9707     (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
9708 /*! @} */
9709 
9710 /*! @name BAUD - LPUART Baud Rate Register */
9711 /*! @{ */
9712 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
9713 #define LPUART_BAUD_SBR_SHIFT (0U)
9714 /*! SBR - Baud Rate Modulo Divisor.
9715  */
9716 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
9717 #define LPUART_BAUD_SBNS_MASK (0x2000U)
9718 #define LPUART_BAUD_SBNS_SHIFT (13U)
9719 /*! SBNS - Stop Bit Number Select
9720  *  0b0..One stop bit.
9721  *  0b1..Two stop bits.
9722  */
9723 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
9724 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
9725 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
9726 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
9727  *  0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
9728  *  0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
9729  */
9730 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
9731 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
9732 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
9733 /*! LBKDIE - LIN Break Detect Interrupt Enable
9734  *  0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
9735  *  0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
9736  */
9737 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
9738 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
9739 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
9740 /*! RESYNCDIS - Resynchronization Disable
9741  *  0b0..Resynchronization during received data word is supported
9742  *  0b1..Resynchronization during received data word is disabled
9743  */
9744 #define LPUART_BAUD_RESYNCDIS(x) \
9745     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
9746 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
9747 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
9748 /*! BOTHEDGE - Both Edge Sampling
9749  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
9750  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
9751  */
9752 #define LPUART_BAUD_BOTHEDGE(x) \
9753     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
9754 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
9755 #define LPUART_BAUD_MATCFG_SHIFT (18U)
9756 /*! MATCFG - Match Configuration
9757  *  0b00..Address Match Wakeup
9758  *  0b01..Idle Match Wakeup
9759  *  0b10..Match On and Match Off
9760  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
9761  */
9762 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
9763 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
9764 #define LPUART_BAUD_RDMAE_SHIFT (21U)
9765 /*! RDMAE - Receiver Full DMA Enable
9766  *  0b0..DMA request disabled.
9767  *  0b1..DMA request enabled.
9768  */
9769 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
9770 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
9771 #define LPUART_BAUD_TDMAE_SHIFT (23U)
9772 /*! TDMAE - Transmitter DMA Enable
9773  *  0b0..DMA request disabled.
9774  *  0b1..DMA request enabled.
9775  */
9776 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
9777 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
9778 #define LPUART_BAUD_OSR_SHIFT (24U)
9779 /*! OSR - Oversampling Ratio
9780  */
9781 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
9782 #define LPUART_BAUD_M10_MASK (0x20000000U)
9783 #define LPUART_BAUD_M10_SHIFT (29U)
9784 /*! M10 - 10-bit Mode select
9785  *  0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
9786  *  0b1..Receiver and transmitter use 10-bit data characters.
9787  */
9788 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
9789 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
9790 #define LPUART_BAUD_MAEN2_SHIFT (30U)
9791 /*! MAEN2 - Match Address Mode Enable 2
9792  *  0b0..Normal operation.
9793  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
9794  */
9795 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
9796 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
9797 #define LPUART_BAUD_MAEN1_SHIFT (31U)
9798 /*! MAEN1 - Match Address Mode Enable 1
9799  *  0b0..Normal operation.
9800  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
9801  */
9802 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
9803 /*! @} */
9804 
9805 /*! @name STAT - LPUART Status Register */
9806 /*! @{ */
9807 #define LPUART_STAT_MA2F_MASK (0x4000U)
9808 #define LPUART_STAT_MA2F_SHIFT (14U)
9809 /*! MA2F - Match 2 Flag
9810  *  0b0..Received data is not equal to MA2
9811  *  0b1..Received data is equal to MA2
9812  */
9813 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
9814 #define LPUART_STAT_MA1F_MASK (0x8000U)
9815 #define LPUART_STAT_MA1F_SHIFT (15U)
9816 /*! MA1F - Match 1 Flag
9817  *  0b0..Received data is not equal to MA1
9818  *  0b1..Received data is equal to MA1
9819  */
9820 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
9821 #define LPUART_STAT_PF_MASK (0x10000U)
9822 #define LPUART_STAT_PF_SHIFT (16U)
9823 /*! PF - Parity Error Flag
9824  *  0b0..No parity error.
9825  *  0b1..Parity error.
9826  */
9827 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
9828 #define LPUART_STAT_FE_MASK (0x20000U)
9829 #define LPUART_STAT_FE_SHIFT (17U)
9830 /*! FE - Framing Error Flag
9831  *  0b0..No framing error detected. This does not guarantee the framing is correct.
9832  *  0b1..Framing error.
9833  */
9834 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
9835 #define LPUART_STAT_NF_MASK (0x40000U)
9836 #define LPUART_STAT_NF_SHIFT (18U)
9837 /*! NF - Noise Flag
9838  *  0b0..No noise detected.
9839  *  0b1..Noise detected in the received character in LPUART_DATA.
9840  */
9841 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
9842 #define LPUART_STAT_OR_MASK (0x80000U)
9843 #define LPUART_STAT_OR_SHIFT (19U)
9844 /*! OR - Receiver Overrun Flag
9845  *  0b0..No overrun.
9846  *  0b1..Receive overrun (new LPUART data lost).
9847  */
9848 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
9849 #define LPUART_STAT_IDLE_MASK (0x100000U)
9850 #define LPUART_STAT_IDLE_SHIFT (20U)
9851 /*! IDLE - Idle Line Flag
9852  *  0b0..No idle line detected.
9853  *  0b1..Idle line was detected.
9854  */
9855 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
9856 #define LPUART_STAT_RDRF_MASK (0x200000U)
9857 #define LPUART_STAT_RDRF_SHIFT (21U)
9858 /*! RDRF - Receive Data Register Full Flag
9859  *  0b0..Receive data buffer empty.
9860  *  0b1..Receive data buffer full.
9861  */
9862 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
9863 #define LPUART_STAT_TC_MASK (0x400000U)
9864 #define LPUART_STAT_TC_SHIFT (22U)
9865 /*! TC - Transmission Complete Flag
9866  *  0b0..Transmitter active (sending data, a preamble, or a break).
9867  *  0b1..Transmitter idle (transmission activity complete).
9868  */
9869 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
9870 #define LPUART_STAT_TDRE_MASK (0x800000U)
9871 #define LPUART_STAT_TDRE_SHIFT (23U)
9872 /*! TDRE - Transmit Data Register Empty Flag
9873  *  0b0..Transmit data buffer full.
9874  *  0b1..Transmit data buffer empty.
9875  */
9876 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
9877 #define LPUART_STAT_RAF_MASK (0x1000000U)
9878 #define LPUART_STAT_RAF_SHIFT (24U)
9879 /*! RAF - Receiver Active Flag
9880  *  0b0..LPUART receiver idle waiting for a start bit.
9881  *  0b1..LPUART receiver active (LPUART_RX input not idle).
9882  */
9883 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
9884 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
9885 #define LPUART_STAT_LBKDE_SHIFT (25U)
9886 /*! LBKDE - LIN Break Detection Enable
9887  *  0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M =
9888  *       0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
9889  *  0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M
9890  *       = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
9891  */
9892 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
9893 #define LPUART_STAT_BRK13_MASK (0x4000000U)
9894 #define LPUART_STAT_BRK13_SHIFT (26U)
9895 /*! BRK13 - Break Character Generation Length
9896  *  0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0
9897  *       or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
9898  *  0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0
9899  *       or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
9900  */
9901 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
9902 #define LPUART_STAT_RWUID_MASK (0x8000000U)
9903 #define LPUART_STAT_RWUID_SHIFT (27U)
9904 /*! RWUID - Receive Wake Up Idle Detect
9905  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
9906  *       character. During address match wakeup, the IDLE bit does not get set when an address does not match.
9907  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
9908  *       address match wakeup, the IDLE bit does get set when an address does not match.
9909  */
9910 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
9911 #define LPUART_STAT_RXINV_MASK (0x10000000U)
9912 #define LPUART_STAT_RXINV_SHIFT (28U)
9913 /*! RXINV - Receive Data Inversion
9914  *  0b0..Receive data not inverted.
9915  *  0b1..Receive data inverted.
9916  */
9917 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
9918 #define LPUART_STAT_MSBF_MASK (0x20000000U)
9919 #define LPUART_STAT_MSBF_SHIFT (29U)
9920 /*! MSBF - MSB First
9921  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
9922  *       after the start bit is identified as bit0.
9923  *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
9924  *       the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
9925  *       identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
9926  */
9927 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
9928 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
9929 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
9930 /*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
9931  *  0b0..No active edge on the receive pin has occurred.
9932  *  0b1..An active edge on the receive pin has occurred.
9933  */
9934 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
9935 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
9936 #define LPUART_STAT_LBKDIF_SHIFT (31U)
9937 /*! LBKDIF - LIN Break Detect Interrupt Flag
9938  *  0b0..No LIN break character has been detected.
9939  *  0b1..LIN break character has been detected.
9940  */
9941 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
9942 /*! @} */
9943 
9944 /*! @name CTRL - LPUART Control Register */
9945 /*! @{ */
9946 #define LPUART_CTRL_PT_MASK (0x1U)
9947 #define LPUART_CTRL_PT_SHIFT (0U)
9948 /*! PT - Parity Type
9949  *  0b0..Even parity.
9950  *  0b1..Odd parity.
9951  */
9952 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
9953 #define LPUART_CTRL_PE_MASK (0x2U)
9954 #define LPUART_CTRL_PE_SHIFT (1U)
9955 /*! PE - Parity Enable
9956  *  0b0..No hardware parity generation or checking.
9957  *  0b1..Parity enabled.
9958  */
9959 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
9960 #define LPUART_CTRL_ILT_MASK (0x4U)
9961 #define LPUART_CTRL_ILT_SHIFT (2U)
9962 /*! ILT - Idle Line Type Select
9963  *  0b0..Idle character bit count starts after start bit.
9964  *  0b1..Idle character bit count starts after stop bit.
9965  */
9966 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
9967 #define LPUART_CTRL_WAKE_MASK (0x8U)
9968 #define LPUART_CTRL_WAKE_SHIFT (3U)
9969 /*! WAKE - Receiver Wakeup Method Select
9970  *  0b0..Configures RWU for idle-line wakeup.
9971  *  0b1..Configures RWU with address-mark wakeup.
9972  */
9973 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
9974 #define LPUART_CTRL_M_MASK (0x10U)
9975 #define LPUART_CTRL_M_SHIFT (4U)
9976 /*! M - 9-Bit or 8-Bit Mode Select
9977  *  0b0..Receiver and transmitter use 8-bit data characters.
9978  *  0b1..Receiver and transmitter use 9-bit data characters.
9979  */
9980 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
9981 #define LPUART_CTRL_RSRC_MASK (0x20U)
9982 #define LPUART_CTRL_RSRC_SHIFT (5U)
9983 /*! RSRC - Receiver Source Select
9984  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the
9985  * LPUART_RX pin. 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and
9986  * receiver input.
9987  */
9988 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
9989 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
9990 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
9991 /*! DOZEEN - Doze Enable
9992  *  0b0..LPUART is enabled in Doze mode.
9993  *  0b1..LPUART is disabled in Doze mode.
9994  */
9995 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
9996 #define LPUART_CTRL_LOOPS_MASK (0x80U)
9997 #define LPUART_CTRL_LOOPS_SHIFT (7U)
9998 /*! LOOPS - Loop Mode Select
9999  *  0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
10000  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC
10001  * bit).
10002  */
10003 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
10004 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
10005 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
10006 /*! IDLECFG - Idle Configuration
10007  *  0b000..1 idle character
10008  *  0b001..2 idle characters
10009  *  0b010..4 idle characters
10010  *  0b011..8 idle characters
10011  *  0b100..16 idle characters
10012  *  0b101..32 idle characters
10013  *  0b110..64 idle characters
10014  *  0b111..128 idle characters
10015  */
10016 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
10017 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
10018 #define LPUART_CTRL_MA2IE_SHIFT (14U)
10019 /*! MA2IE - Match 2 Interrupt Enable
10020  *  0b0..MA2F interrupt disabled
10021  *  0b1..MA2F interrupt enabled
10022  */
10023 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
10024 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
10025 #define LPUART_CTRL_MA1IE_SHIFT (15U)
10026 /*! MA1IE - Match 1 Interrupt Enable
10027  *  0b0..MA1F interrupt disabled
10028  *  0b1..MA1F interrupt enabled
10029  */
10030 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
10031 #define LPUART_CTRL_SBK_MASK (0x10000U)
10032 #define LPUART_CTRL_SBK_SHIFT (16U)
10033 /*! SBK - Send Break
10034  *  0b0..Normal transmitter operation.
10035  *  0b1..Queue break character(s) to be sent.
10036  */
10037 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
10038 #define LPUART_CTRL_RWU_MASK (0x20000U)
10039 #define LPUART_CTRL_RWU_SHIFT (17U)
10040 /*! RWU - Receiver Wakeup Control
10041  *  0b0..Normal receiver operation.
10042  *  0b1..LPUART receiver in standby waiting for wakeup condition.
10043  */
10044 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
10045 #define LPUART_CTRL_RE_MASK (0x40000U)
10046 #define LPUART_CTRL_RE_SHIFT (18U)
10047 /*! RE - Receiver Enable
10048  *  0b0..Receiver disabled.
10049  *  0b1..Receiver enabled.
10050  */
10051 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
10052 #define LPUART_CTRL_TE_MASK (0x80000U)
10053 #define LPUART_CTRL_TE_SHIFT (19U)
10054 /*! TE - Transmitter Enable
10055  *  0b0..Transmitter disabled.
10056  *  0b1..Transmitter enabled.
10057  */
10058 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
10059 #define LPUART_CTRL_ILIE_MASK (0x100000U)
10060 #define LPUART_CTRL_ILIE_SHIFT (20U)
10061 /*! ILIE - Idle Line Interrupt Enable
10062  *  0b0..Hardware interrupts from IDLE disabled; use polling.
10063  *  0b1..Hardware interrupt requested when IDLE flag is 1.
10064  */
10065 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
10066 #define LPUART_CTRL_RIE_MASK (0x200000U)
10067 #define LPUART_CTRL_RIE_SHIFT (21U)
10068 /*! RIE - Receiver Interrupt Enable
10069  *  0b0..Hardware interrupts from RDRF disabled; use polling.
10070  *  0b1..Hardware interrupt requested when RDRF flag is 1.
10071  */
10072 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
10073 #define LPUART_CTRL_TCIE_MASK (0x400000U)
10074 #define LPUART_CTRL_TCIE_SHIFT (22U)
10075 /*! TCIE - Transmission Complete Interrupt Enable for
10076  *  0b0..Hardware interrupts from TC disabled; use polling.
10077  *  0b1..Hardware interrupt requested when TC flag is 1.
10078  */
10079 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
10080 #define LPUART_CTRL_TIE_MASK (0x800000U)
10081 #define LPUART_CTRL_TIE_SHIFT (23U)
10082 /*! TIE - Transmit Interrupt Enable
10083  *  0b0..Hardware interrupts from TDRE disabled; use polling.
10084  *  0b1..Hardware interrupt requested when TDRE flag is 1.
10085  */
10086 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
10087 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
10088 #define LPUART_CTRL_PEIE_SHIFT (24U)
10089 /*! PEIE - Parity Error Interrupt Enable
10090  *  0b0..PF interrupts disabled; use polling).
10091  *  0b1..Hardware interrupt requested when PF is set.
10092  */
10093 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
10094 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
10095 #define LPUART_CTRL_FEIE_SHIFT (25U)
10096 /*! FEIE - Framing Error Interrupt Enable
10097  *  0b0..FE interrupts disabled; use polling.
10098  *  0b1..Hardware interrupt requested when FE is set.
10099  */
10100 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
10101 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
10102 #define LPUART_CTRL_NEIE_SHIFT (26U)
10103 /*! NEIE - Noise Error Interrupt Enable
10104  *  0b0..NF interrupts disabled; use polling.
10105  *  0b1..Hardware interrupt requested when NF is set.
10106  */
10107 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
10108 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
10109 #define LPUART_CTRL_ORIE_SHIFT (27U)
10110 /*! ORIE - Overrun Interrupt Enable
10111  *  0b0..OR interrupts disabled; use polling.
10112  *  0b1..Hardware interrupt requested when OR is set.
10113  */
10114 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
10115 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
10116 #define LPUART_CTRL_TXINV_SHIFT (28U)
10117 /*! TXINV - Transmit Data Inversion
10118  *  0b0..Transmit data not inverted.
10119  *  0b1..Transmit data inverted.
10120  */
10121 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
10122 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
10123 #define LPUART_CTRL_TXDIR_SHIFT (29U)
10124 /*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
10125  *  0b0..LPUART_TX pin is an input in single-wire mode.
10126  *  0b1..LPUART_TX pin is an output in single-wire mode.
10127  */
10128 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
10129 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
10130 #define LPUART_CTRL_R9T8_SHIFT (30U)
10131 /*! R9T8 - Receive Bit 9 / Transmit Bit 8
10132  */
10133 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
10134 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
10135 #define LPUART_CTRL_R8T9_SHIFT (31U)
10136 /*! R8T9 - Receive Bit 8 / Transmit Bit 9
10137  */
10138 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
10139 /*! @} */
10140 
10141 /*! @name DATA - LPUART Data Register */
10142 /*! @{ */
10143 #define LPUART_DATA_R0T0_MASK (0x1U)
10144 #define LPUART_DATA_R0T0_SHIFT (0U)
10145 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
10146 #define LPUART_DATA_R1T1_MASK (0x2U)
10147 #define LPUART_DATA_R1T1_SHIFT (1U)
10148 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
10149 #define LPUART_DATA_R2T2_MASK (0x4U)
10150 #define LPUART_DATA_R2T2_SHIFT (2U)
10151 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
10152 #define LPUART_DATA_R3T3_MASK (0x8U)
10153 #define LPUART_DATA_R3T3_SHIFT (3U)
10154 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
10155 #define LPUART_DATA_R4T4_MASK (0x10U)
10156 #define LPUART_DATA_R4T4_SHIFT (4U)
10157 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
10158 #define LPUART_DATA_R5T5_MASK (0x20U)
10159 #define LPUART_DATA_R5T5_SHIFT (5U)
10160 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
10161 #define LPUART_DATA_R6T6_MASK (0x40U)
10162 #define LPUART_DATA_R6T6_SHIFT (6U)
10163 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
10164 #define LPUART_DATA_R7T7_MASK (0x80U)
10165 #define LPUART_DATA_R7T7_SHIFT (7U)
10166 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
10167 #define LPUART_DATA_R8T8_MASK (0x100U)
10168 #define LPUART_DATA_R8T8_SHIFT (8U)
10169 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
10170 #define LPUART_DATA_R9T9_MASK (0x200U)
10171 #define LPUART_DATA_R9T9_SHIFT (9U)
10172 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
10173 #define LPUART_DATA_IDLINE_MASK (0x800U)
10174 #define LPUART_DATA_IDLINE_SHIFT (11U)
10175 /*! IDLINE - Idle Line
10176  *  0b0..Receiver was not idle before receiving this character.
10177  *  0b1..Receiver was idle before receiving this character.
10178  */
10179 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
10180 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
10181 #define LPUART_DATA_RXEMPT_SHIFT (12U)
10182 /*! RXEMPT - Receive Buffer Empty
10183  *  0b0..Receive buffer contains valid data.
10184  *  0b1..Receive buffer is empty, data returned on read is not valid.
10185  */
10186 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
10187 #define LPUART_DATA_FRETSC_MASK (0x2000U)
10188 #define LPUART_DATA_FRETSC_SHIFT (13U)
10189 /*! FRETSC - Frame Error / Transmit Special Character
10190  *  0b0..The dataword was received without a frame error on read, transmit a normal character on write.
10191  *  0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
10192  */
10193 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
10194 #define LPUART_DATA_PARITYE_MASK (0x4000U)
10195 #define LPUART_DATA_PARITYE_SHIFT (14U)
10196 /*! PARITYE
10197  *  0b0..The dataword was received without a parity error.
10198  *  0b1..The dataword was received with a parity error.
10199  */
10200 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
10201 #define LPUART_DATA_NOISY_MASK (0x8000U)
10202 #define LPUART_DATA_NOISY_SHIFT (15U)
10203 /*! NOISY
10204  *  0b0..The dataword was received without noise.
10205  *  0b1..The data was received with noise.
10206  */
10207 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
10208 /*! @} */
10209 
10210 /*! @name MATCH - LPUART Match Address Register */
10211 /*! @{ */
10212 #define LPUART_MATCH_MA1_MASK (0x3FFU)
10213 #define LPUART_MATCH_MA1_SHIFT (0U)
10214 /*! MA1 - Match Address 1
10215  */
10216 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
10217 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
10218 #define LPUART_MATCH_MA2_SHIFT (16U)
10219 /*! MA2 - Match Address 2
10220  */
10221 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
10222 /*! @} */
10223 
10224 /*! @name MODIR - LPUART Modem IrDA Register */
10225 /*! @{ */
10226 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
10227 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
10228 /*! TXCTSE - Transmitter clear-to-send enable
10229  *  0b0..CTS has no effect on the transmitter.
10230  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
10231  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
10232  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
10233  *       do not affect its transmission.
10234  */
10235 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
10236 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
10237 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
10238 /*! TXRTSE - Transmitter request-to-send enable
10239  *  0b0..The transmitter has no effect on RTS.
10240  *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
10241  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and
10242  *       shift register are completely sent, including the last stop bit.
10243  */
10244 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
10245 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
10246 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
10247 /*! TXRTSPOL - Transmitter request-to-send polarity
10248  *  0b0..Transmitter RTS is active low.
10249  *  0b1..Transmitter RTS is active high.
10250  */
10251 #define LPUART_MODIR_TXRTSPOL(x) \
10252     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
10253 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
10254 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
10255 /*! RXRTSE - Receiver request-to-send enable
10256  *  0b0..The receiver has no effect on RTS.
10257  *  0b1..RTS assertion is configured by the RTSWATER field
10258  */
10259 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
10260 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
10261 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
10262 /*! TXCTSC - Transmit CTS Configuration
10263  *  0b0..CTS input is sampled at the start of each character.
10264  *  0b1..CTS input is sampled when the transmitter is idle.
10265  */
10266 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
10267 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
10268 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
10269 /*! TXCTSSRC - Transmit CTS Source
10270  *  0b0..CTS input is the LPUART_CTS pin.
10271  *  0b1..CTS input is the inverted Receiver Match result.
10272  */
10273 #define LPUART_MODIR_TXCTSSRC(x) \
10274     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
10275 #define LPUART_MODIR_RTSWATER_MASK (0xFF00U)
10276 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
10277 /*! RTSWATER - Receive RTS Configuration
10278  *  0b00000000..RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full.
10279  *  0b00000001..RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates
10280  *              when the receive FIFO is greater than the RXWATER configuration.
10281  */
10282 #define LPUART_MODIR_RTSWATER(x) \
10283     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
10284 #define LPUART_MODIR_TNP_MASK (0x30000U)
10285 #define LPUART_MODIR_TNP_SHIFT (16U)
10286 /*! TNP - Transmitter narrow pulse
10287  *  0b00..1/OSR.
10288  *  0b01..2/OSR.
10289  *  0b10..3/OSR.
10290  *  0b11..4/OSR.
10291  */
10292 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
10293 #define LPUART_MODIR_IREN_MASK (0x40000U)
10294 #define LPUART_MODIR_IREN_SHIFT (18U)
10295 /*! IREN - Infrared enable
10296  *  0b0..IR disabled.
10297  *  0b1..IR enabled.
10298  */
10299 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
10300 /*! @} */
10301 
10302 /*! @name FIFO - LPUART FIFO Register */
10303 /*! @{ */
10304 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
10305 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
10306 /*! RXFIFOSIZE - Receive FIFO. Buffer Depth
10307  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
10308  */
10309 #define LPUART_FIFO_RXFIFOSIZE(x) \
10310     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
10311 #define LPUART_FIFO_RXFE_MASK (0x8U)
10312 #define LPUART_FIFO_RXFE_SHIFT (3U)
10313 /*! RXFE - Receive FIFO Enable
10314  *  0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
10315  *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
10316  */
10317 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
10318 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
10319 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
10320 /*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
10321  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
10322  */
10323 #define LPUART_FIFO_TXFIFOSIZE(x) \
10324     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
10325 #define LPUART_FIFO_TXFE_MASK (0x80U)
10326 #define LPUART_FIFO_TXFE_SHIFT (7U)
10327 /*! TXFE - Transmit FIFO Enable
10328  *  0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
10329  *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
10330  */
10331 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
10332 #define LPUART_FIFO_RXUFE_MASK (0x100U)
10333 #define LPUART_FIFO_RXUFE_SHIFT (8U)
10334 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
10335  *  0b0..RXUF flag does not generate an interrupt to the host.
10336  *  0b1..RXUF flag generates an interrupt to the host.
10337  */
10338 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
10339 #define LPUART_FIFO_TXOFE_MASK (0x200U)
10340 #define LPUART_FIFO_TXOFE_SHIFT (9U)
10341 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
10342  *  0b0..TXOF flag does not generate an interrupt to the host.
10343  *  0b1..TXOF flag generates an interrupt to the host.
10344  */
10345 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
10346 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
10347 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
10348 /*! RXIDEN - Receiver Idle Empty Enable
10349  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
10350  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
10351  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
10352  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
10353  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
10354  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
10355  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
10356  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
10357  */
10358 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
10359 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
10360 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
10361 /*! RXFLUSH - Receive FIFO/Buffer Flush
10362  *  0b0..No flush operation occurs.
10363  *  0b1..All data in the receive FIFO/buffer is cleared out.
10364  */
10365 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
10366 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
10367 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
10368 /*! TXFLUSH - Transmit FIFO/Buffer Flush
10369  *  0b0..No flush operation occurs.
10370  *  0b1..All data in the transmit FIFO/Buffer is cleared out.
10371  */
10372 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
10373 #define LPUART_FIFO_RXUF_MASK (0x10000U)
10374 #define LPUART_FIFO_RXUF_SHIFT (16U)
10375 /*! RXUF - Receiver Buffer Underflow Flag
10376  *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
10377  *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
10378  */
10379 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
10380 #define LPUART_FIFO_TXOF_MASK (0x20000U)
10381 #define LPUART_FIFO_TXOF_SHIFT (17U)
10382 /*! TXOF - Transmitter Buffer Overflow Flag
10383  *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
10384  *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
10385  */
10386 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
10387 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
10388 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
10389 /*! RXEMPT - Receive Buffer/FIFO Empty
10390  *  0b0..Receive buffer is not empty.
10391  *  0b1..Receive buffer is empty.
10392  */
10393 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
10394 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
10395 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
10396 /*! TXEMPT - Transmit Buffer/FIFO Empty
10397  *  0b0..Transmit buffer is not empty.
10398  *  0b1..Transmit buffer is empty.
10399  */
10400 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
10401 /*! @} */
10402 
10403 /*! @name WATER - LPUART Watermark Register */
10404 /*! @{ */
10405 #define LPUART_WATER_TXWATER_MASK (0xFFU)
10406 #define LPUART_WATER_TXWATER_SHIFT (0U)
10407 /*! TXWATER - Transmit Watermark
10408  */
10409 #define LPUART_WATER_TXWATER(x) \
10410     (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
10411 #define LPUART_WATER_TXCOUNT_MASK (0xFF00U)
10412 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
10413 /*! TXCOUNT - Transmit Counter
10414  */
10415 #define LPUART_WATER_TXCOUNT(x) \
10416     (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
10417 #define LPUART_WATER_RXWATER_MASK (0xFF0000U)
10418 #define LPUART_WATER_RXWATER_SHIFT (16U)
10419 /*! RXWATER - Receive Watermark
10420  */
10421 #define LPUART_WATER_RXWATER(x) \
10422     (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
10423 #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U)
10424 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
10425 /*! RXCOUNT - Receive Counter
10426  */
10427 #define LPUART_WATER_RXCOUNT(x) \
10428     (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
10429 /*! @} */
10430 
10431 /*!
10432  * @}
10433  */ /* end of group LPUART_Register_Masks */
10434 
10435 /* LPUART - Peripheral instance base addresses */
10436 /** Peripheral LPUART0 base address */
10437 #define LPUART0_BASE (0x400C4000u)
10438 /** Peripheral LPUART0 base pointer */
10439 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
10440 /** Peripheral LPUART1 base address */
10441 #define LPUART1_BASE (0x400C5000u)
10442 /** Peripheral LPUART1 base pointer */
10443 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
10444 /** Peripheral LPUART2 base address */
10445 #define LPUART2_BASE (0x40046000u)
10446 /** Peripheral LPUART2 base pointer */
10447 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
10448 /** Array initializer of LPUART peripheral base addresses */
10449 #define LPUART_BASE_ADDRS                        \
10450     {                                            \
10451         LPUART0_BASE, LPUART1_BASE, LPUART2_BASE \
10452     }
10453 /** Array initializer of LPUART peripheral base pointers */
10454 #define LPUART_BASE_PTRS          \
10455     {                             \
10456         LPUART0, LPUART1, LPUART2 \
10457     }
10458 /** Interrupt vectors for the LPUART peripheral type */
10459 #define LPUART_RX_TX_IRQS                        \
10460     {                                            \
10461         LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn \
10462     }
10463 #define LPUART_ERR_IRQS                          \
10464     {                                            \
10465         LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn \
10466     }
10467 
10468 /*!
10469  * @}
10470  */ /* end of group LPUART_Peripheral_Access_Layer */
10471 
10472 /* ----------------------------------------------------------------------------
10473    -- MCM Peripheral Access Layer
10474    ---------------------------------------------------------------------------- */
10475 
10476 /*!
10477  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
10478  * @{
10479  */
10480 
10481 /** MCM - Register Layout Typedef */
10482 typedef struct
10483 {
10484     uint8_t RESERVED_0[8];
10485     __I uint16_t PLASC;  /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
10486     __I uint16_t PLAMC;  /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
10487     __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
10488     uint8_t RESERVED_1[48];
10489     __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
10490 } MCM_Type;
10491 
10492 /* ----------------------------------------------------------------------------
10493    -- MCM Register Masks
10494    ---------------------------------------------------------------------------- */
10495 
10496 /*!
10497  * @addtogroup MCM_Register_Masks MCM Register Masks
10498  * @{
10499  */
10500 
10501 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
10502 /*! @{ */
10503 #define MCM_PLASC_ASC_MASK (0xFFU)
10504 #define MCM_PLASC_ASC_SHIFT (0U)
10505 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the
10506  *    crossbar switch's slave input port.
10507  *  0b00000000..A bus slave connection to AXBS input port n is absent.
10508  *  0b00000001..A bus slave connection to AXBS input port n is present.
10509  */
10510 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
10511 /*! @} */
10512 
10513 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
10514 /*! @{ */
10515 #define MCM_PLAMC_AMC_MASK (0xFFU)
10516 #define MCM_PLAMC_AMC_SHIFT (0U)
10517 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
10518  *  0b00000000..A bus master connection to AXBS input port n is absent
10519  *  0b00000001..A bus master connection to AXBS input port n is present
10520  */
10521 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
10522 /*! @} */
10523 
10524 /*! @name PLACR - Platform Control Register */
10525 /*! @{ */
10526 #define MCM_PLACR_MMCAU_MASK (0x100U)
10527 #define MCM_PLACR_MMCAU_SHIFT (8U)
10528 /*! MMCAU - MMCAU Present
10529  *  0b0..MMCAU is disabled
10530  *  0b1..MMCAU is enabled
10531  */
10532 #define MCM_PLACR_MMCAU(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_MMCAU_SHIFT)) & MCM_PLACR_MMCAU_MASK)
10533 #define MCM_PLACR_ARB_MASK (0x200U)
10534 #define MCM_PLACR_ARB_SHIFT (9U)
10535 /*! ARB - Arbitration select
10536  *  0b0..Fixed-priority arbitration for the crossbar masters
10537  *  0b1..Round-robin arbitration for the crossbar masters
10538  */
10539 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
10540 #define MCM_PLACR_CFCC_MASK (0x400U)
10541 #define MCM_PLACR_CFCC_SHIFT (10U)
10542 /*! CFCC - Clear Flash Controller Cache
10543  */
10544 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
10545 #define MCM_PLACR_DFCDA_MASK (0x800U)
10546 #define MCM_PLACR_DFCDA_SHIFT (11U)
10547 /*! DFCDA - Disable Flash Controller Data Caching
10548  *  0b0..Enable flash controller data caching
10549  *  0b1..Disable flash controller data caching.
10550  */
10551 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
10552 #define MCM_PLACR_DFCIC_MASK (0x1000U)
10553 #define MCM_PLACR_DFCIC_SHIFT (12U)
10554 /*! DFCIC - Disable Flash Controller Instruction Caching
10555  *  0b0..Enable flash controller instruction caching.
10556  *  0b1..Disable flash controller instruction caching.
10557  */
10558 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
10559 #define MCM_PLACR_DFCC_MASK (0x2000U)
10560 #define MCM_PLACR_DFCC_SHIFT (13U)
10561 /*! DFCC - Disable Flash Controller Cache
10562  *  0b0..Enable flash controller cache.
10563  *  0b1..Disable flash controller cache.
10564  */
10565 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
10566 #define MCM_PLACR_EFDS_MASK (0x4000U)
10567 #define MCM_PLACR_EFDS_SHIFT (14U)
10568 /*! EFDS - Enable Flash Data Speculation
10569  *  0b0..Disable flash data speculation.
10570  *  0b1..Enable flash data speculation.
10571  */
10572 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
10573 #define MCM_PLACR_DFCS_MASK (0x8000U)
10574 #define MCM_PLACR_DFCS_SHIFT (15U)
10575 /*! DFCS - Disable Flash Controller Speculation
10576  *  0b0..Enable flash controller speculation.
10577  *  0b1..Disable flash controller speculation.
10578  */
10579 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
10580 #define MCM_PLACR_ESFC_MASK (0x10000U)
10581 #define MCM_PLACR_ESFC_SHIFT (16U)
10582 /*! ESFC - Enable Stalling Flash Controller
10583  *  0b0..Disable stalling flash controller when flash is busy.
10584  *  0b1..Enable stalling flash controller when flash is busy.
10585  */
10586 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
10587 /*! @} */
10588 
10589 /*! @name CPO - Compute Operation Control Register */
10590 /*! @{ */
10591 #define MCM_CPO_CPOREQ_MASK (0x1U)
10592 #define MCM_CPO_CPOREQ_SHIFT (0U)
10593 /*! CPOREQ - Compute Operation Request
10594  *  0b0..Request is cleared.
10595  *  0b1..Request Compute Operation.
10596  */
10597 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
10598 #define MCM_CPO_CPOACK_MASK (0x2U)
10599 #define MCM_CPO_CPOACK_SHIFT (1U)
10600 /*! CPOACK - Compute Operation Acknowledge
10601  *  0b0..Compute operation entry has not completed or compute operation exit has completed.
10602  *  0b1..Compute operation entry has completed or compute operation exit has not completed.
10603  */
10604 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
10605 #define MCM_CPO_CPOWOI_MASK (0x4U)
10606 #define MCM_CPO_CPOWOI_SHIFT (2U)
10607 /*! CPOWOI - Compute Operation Wake-up on Interrupt
10608  *  0b0..No effect.
10609  *  0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
10610  */
10611 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
10612 /*! @} */
10613 
10614 /*!
10615  * @}
10616  */ /* end of group MCM_Register_Masks */
10617 
10618 /* MCM - Peripheral instance base addresses */
10619 /** Peripheral MCM0 base address */
10620 #define MCM0_BASE (0xF0003008u)
10621 /** Peripheral MCM0 base pointer */
10622 #define MCM0 ((MCM_Type *)MCM0_BASE)
10623 /** Array initializer of MCM peripheral base addresses */
10624 #define MCM_BASE_ADDRS \
10625     {                  \
10626         MCM0_BASE      \
10627     }
10628 /** Array initializer of MCM peripheral base pointers */
10629 #define MCM_BASE_PTRS \
10630     {                 \
10631         MCM0          \
10632     }
10633 
10634 /*!
10635  * @}
10636  */ /* end of group MCM_Peripheral_Access_Layer */
10637 
10638 /* ----------------------------------------------------------------------------
10639    -- MMDVSQ Peripheral Access Layer
10640    ---------------------------------------------------------------------------- */
10641 
10642 /*!
10643  * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer
10644  * @{
10645  */
10646 
10647 /** MMDVSQ - Register Layout Typedef */
10648 typedef struct
10649 {
10650     __IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */
10651     __IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */
10652     __IO uint32_t CSR;  /**< Control/Status Register, offset: 0x8 */
10653     __IO uint32_t RES;  /**< Result Register, offset: 0xC */
10654     __O uint32_t RCND;  /**< Radicand Register, offset: 0x10 */
10655 } MMDVSQ_Type;
10656 
10657 /* ----------------------------------------------------------------------------
10658    -- MMDVSQ Register Masks
10659    ---------------------------------------------------------------------------- */
10660 
10661 /*!
10662  * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks
10663  * @{
10664  */
10665 
10666 /*! @name DEND - Dividend Register */
10667 /*! @{ */
10668 #define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU)
10669 #define MMDVSQ_DEND_DIVIDEND_SHIFT (0U)
10670 /*! DIVIDEND - Dividend
10671  */
10672 #define MMDVSQ_DEND_DIVIDEND(x) \
10673     (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK)
10674 /*! @} */
10675 
10676 /*! @name DSOR - Divisor Register */
10677 /*! @{ */
10678 #define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU)
10679 #define MMDVSQ_DSOR_DIVISOR_SHIFT (0U)
10680 /*! DIVISOR - Divisor
10681  */
10682 #define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK)
10683 /*! @} */
10684 
10685 /*! @name CSR - Control/Status Register */
10686 /*! @{ */
10687 #define MMDVSQ_CSR_SRT_MASK (0x1U)
10688 #define MMDVSQ_CSR_SRT_SHIFT (0U)
10689 /*! SRT - Start
10690  *  0b0..No operation initiated
10691  *  0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore
10692  */
10693 #define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK)
10694 #define MMDVSQ_CSR_USGN_MASK (0x2U)
10695 #define MMDVSQ_CSR_USGN_SHIFT (1U)
10696 /*! USGN - Unsigned calculation
10697  *  0b0..Perform a signed divide
10698  *  0b1..Perform an unsigned divide
10699  */
10700 #define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK)
10701 #define MMDVSQ_CSR_REM_MASK (0x4U)
10702 #define MMDVSQ_CSR_REM_SHIFT (2U)
10703 /*! REM - REMainder calculation
10704  *  0b0..Return the quotient in the RES for the divide calculation
10705  *  0b1..Return the remainder in the RES for the divide calculation
10706  */
10707 #define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK)
10708 #define MMDVSQ_CSR_DZE_MASK (0x8U)
10709 #define MMDVSQ_CSR_DZE_SHIFT (3U)
10710 /*! DZE - Divide-by-Zero-Enable
10711  *  0b0..Reads of the RES register return the register contents
10712  *  0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the
10713  * register contents are returned
10714  */
10715 #define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK)
10716 #define MMDVSQ_CSR_DZ_MASK (0x10U)
10717 #define MMDVSQ_CSR_DZ_SHIFT (4U)
10718 /*! DZ - Divide-by-Zero
10719  *  0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0
10720  *  0b1..The last divide operation had a zero divisor, that is, DSOR = 0
10721  */
10722 #define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK)
10723 #define MMDVSQ_CSR_DFS_MASK (0x20U)
10724 #define MMDVSQ_CSR_DFS_SHIFT (5U)
10725 /*! DFS - Disable Fast Start
10726  *  0b0..A divide operation is initiated by a write to the DSOR register
10727  *  0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1
10728  */
10729 #define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK)
10730 #define MMDVSQ_CSR_SQRT_MASK (0x20000000U)
10731 #define MMDVSQ_CSR_SQRT_SHIFT (29U)
10732 /*! SQRT - SQUARE ROOT
10733  *  0b0..Current or last MMDVSQ operation was not a square root
10734  *  0b1..Current or last MMDVSQ operation was a square root
10735  */
10736 #define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK)
10737 #define MMDVSQ_CSR_DIV_MASK (0x40000000U)
10738 #define MMDVSQ_CSR_DIV_SHIFT (30U)
10739 /*! DIV - DIVIDE
10740  *  0b0..Current or last MMDVSQ operation was not a divide
10741  *  0b1..Current or last MMDVSQ operation was a divide
10742  */
10743 #define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK)
10744 #define MMDVSQ_CSR_BUSY_MASK (0x80000000U)
10745 #define MMDVSQ_CSR_BUSY_SHIFT (31U)
10746 /*! BUSY - BUSY
10747  *  0b0..MMDVSQ is idle
10748  *  0b1..MMDVSQ is busy performing a divide or square root calculation
10749  */
10750 #define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK)
10751 /*! @} */
10752 
10753 /*! @name RES - Result Register */
10754 /*! @{ */
10755 #define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU)
10756 #define MMDVSQ_RES_RESULT_SHIFT (0U)
10757 /*! RESULT - Result
10758  */
10759 #define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK)
10760 /*! @} */
10761 
10762 /*! @name RCND - Radicand Register */
10763 /*! @{ */
10764 #define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU)
10765 #define MMDVSQ_RCND_RADICAND_SHIFT (0U)
10766 /*! RADICAND - Radicand
10767  */
10768 #define MMDVSQ_RCND_RADICAND(x) \
10769     (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK)
10770 /*! @} */
10771 
10772 /*!
10773  * @}
10774  */ /* end of group MMDVSQ_Register_Masks */
10775 
10776 /* MMDVSQ - Peripheral instance base addresses */
10777 /** Peripheral MMDVSQ0 base address */
10778 #define MMDVSQ0_BASE (0xF0004000u)
10779 /** Peripheral MMDVSQ0 base pointer */
10780 #define MMDVSQ0 ((MMDVSQ_Type *)MMDVSQ0_BASE)
10781 /** Array initializer of MMDVSQ peripheral base addresses */
10782 #define MMDVSQ_BASE_ADDRS \
10783     {                     \
10784         MMDVSQ0_BASE      \
10785     }
10786 /** Array initializer of MMDVSQ peripheral base pointers */
10787 #define MMDVSQ_BASE_PTRS \
10788     {                    \
10789         MMDVSQ0          \
10790     }
10791 
10792 /*!
10793  * @}
10794  */ /* end of group MMDVSQ_Peripheral_Access_Layer */
10795 
10796 /* ----------------------------------------------------------------------------
10797    -- MSCM Peripheral Access Layer
10798    ---------------------------------------------------------------------------- */
10799 
10800 /*!
10801  * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
10802  * @{
10803  */
10804 
10805 /** MSCM - Register Layout Typedef */
10806 typedef struct
10807 {
10808     __I uint32_t CPxTYPE;   /**< Processor X Type Register, offset: 0x0 */
10809     __I uint32_t CPxNUM;    /**< Processor X Number Register, offset: 0x4 */
10810     __I uint32_t CPxMASTER; /**< Processor X Master Register, offset: 0x8 */
10811     __I uint32_t CPxCOUNT;  /**< Processor X Count Register, offset: 0xC */
10812     __I uint32_t CPxCFG0;   /**< Processor X Configuration Register, offset: 0x10 */
10813     __I uint32_t CPxCFG1;   /**< Processor X Configuration Register, offset: 0x14 */
10814     __I uint32_t CPxCFG2;   /**< Processor X Configuration Register, offset: 0x18 */
10815     __I uint32_t CPxCFG3;   /**< Processor X Configuration Register, offset: 0x1C */
10816     struct
10817     {                        /* offset: 0x20, array step: 0x20 */
10818         __I uint32_t TYPE;   /**< Processor 0 Type Register, array offset: 0x20, array step: 0x20 */
10819         __I uint32_t NUM;    /**< Processor 0 Number Register, array offset: 0x24, array step: 0x20 */
10820         __I uint32_t MASTER; /**< Processor 0 Master Register, array offset: 0x28, array step: 0x20 */
10821         __I uint32_t COUNT;  /**< Processor 0 Count Register, array offset: 0x2C, array step: 0x20 */
10822         __I uint32_t CFG0;   /**< Processor 0 Configuration Register, array offset: 0x30, array step: 0x20 */
10823         __I uint32_t CFG1;   /**< Processor 0 Configuration Register, array offset: 0x34, array step: 0x20 */
10824         __I uint32_t CFG2;   /**< Processor 0 Configuration Register, array offset: 0x38, array step: 0x20 */
10825         __I uint32_t CFG3;   /**< Processor 0 Configuration Register, array offset: 0x3C, array step: 0x20 */
10826     } CP[1];
10827     uint8_t RESERVED_0[960];
10828     __I uint32_t OCMDR[3]; /**< On-Chip Memory Descriptor Register, array offset: 0x400, array step: 0x4 */
10829 } MSCM_Type;
10830 
10831 /* ----------------------------------------------------------------------------
10832    -- MSCM Register Masks
10833    ---------------------------------------------------------------------------- */
10834 
10835 /*!
10836  * @addtogroup MSCM_Register_Masks MSCM Register Masks
10837  * @{
10838  */
10839 
10840 /*! @name CPxTYPE - Processor X Type Register */
10841 /*! @{ */
10842 #define MSCM_CPxTYPE_RYPZ_MASK (0xFFU)
10843 #define MSCM_CPxTYPE_RYPZ_SHIFT (0U)
10844 /*! RYPZ - Processor x Revision
10845  */
10846 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_RYPZ_SHIFT)) & MSCM_CPxTYPE_RYPZ_MASK)
10847 #define MSCM_CPxTYPE_PERSONALITY_MASK (0xFFFFFF00U)
10848 #define MSCM_CPxTYPE_PERSONALITY_SHIFT (8U)
10849 /*! PERSONALITY - Processor x Personality
10850  */
10851 #define MSCM_CPxTYPE_PERSONALITY(x) \
10852     (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_PERSONALITY_SHIFT)) & MSCM_CPxTYPE_PERSONALITY_MASK)
10853 /*! @} */
10854 
10855 /*! @name CPxNUM - Processor X Number Register */
10856 /*! @{ */
10857 #define MSCM_CPxNUM_CPN_MASK (0x1U)
10858 #define MSCM_CPxNUM_CPN_SHIFT (0U)
10859 /*! CPN - Processor x Number
10860  */
10861 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxNUM_CPN_SHIFT)) & MSCM_CPxNUM_CPN_MASK)
10862 /*! @} */
10863 
10864 /*! @name CPxMASTER - Processor X Master Register */
10865 /*! @{ */
10866 #define MSCM_CPxMASTER_PPN_MASK (0x3FU)
10867 #define MSCM_CPxMASTER_PPN_SHIFT (0U)
10868 /*! PPN - Processor x Physical Port Number
10869  */
10870 #define MSCM_CPxMASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxMASTER_PPN_SHIFT)) & MSCM_CPxMASTER_PPN_MASK)
10871 /*! @} */
10872 
10873 /*! @name CPxCOUNT - Processor X Count Register */
10874 /*! @{ */
10875 #define MSCM_CPxCOUNT_PCNT_MASK (0x3U)
10876 #define MSCM_CPxCOUNT_PCNT_SHIFT (0U)
10877 /*! PCNT - Processor Count
10878  */
10879 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCOUNT_PCNT_SHIFT)) & MSCM_CPxCOUNT_PCNT_MASK)
10880 /*! @} */
10881 
10882 /*! @name CPxCFG0 - Processor X Configuration Register */
10883 /*! @{ */
10884 #define MSCM_CPxCFG0_DCWY_MASK (0xFFU)
10885 #define MSCM_CPxCFG0_DCWY_SHIFT (0U)
10886 /*! DCWY - Level 1 Data Cache Ways
10887  */
10888 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCWY_SHIFT)) & MSCM_CPxCFG0_DCWY_MASK)
10889 #define MSCM_CPxCFG0_DCSZ_MASK (0xFF00U)
10890 #define MSCM_CPxCFG0_DCSZ_SHIFT (8U)
10891 /*! DCSZ - Level 1 Data Cache Size
10892  */
10893 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCSZ_SHIFT)) & MSCM_CPxCFG0_DCSZ_MASK)
10894 #define MSCM_CPxCFG0_ICWY_MASK (0xFF0000U)
10895 #define MSCM_CPxCFG0_ICWY_SHIFT (16U)
10896 /*! ICWY - Level 1 Instruction Cache Ways
10897  */
10898 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICWY_SHIFT)) & MSCM_CPxCFG0_ICWY_MASK)
10899 #define MSCM_CPxCFG0_ICSZ_MASK (0xFF000000U)
10900 #define MSCM_CPxCFG0_ICSZ_SHIFT (24U)
10901 /*! ICSZ - Level 1 Instruction Cache Size
10902  */
10903 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICSZ_SHIFT)) & MSCM_CPxCFG0_ICSZ_MASK)
10904 /*! @} */
10905 
10906 /*! @name CPxCFG1 - Processor X Configuration Register */
10907 /*! @{ */
10908 #define MSCM_CPxCFG1_DCWY_MASK (0xFFU)
10909 #define MSCM_CPxCFG1_DCWY_SHIFT (0U)
10910 /*! DCWY - Level 1 Data Cache Ways
10911  */
10912 #define MSCM_CPxCFG1_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_DCWY_SHIFT)) & MSCM_CPxCFG1_DCWY_MASK)
10913 #define MSCM_CPxCFG1_DCSZ_MASK (0xFF00U)
10914 #define MSCM_CPxCFG1_DCSZ_SHIFT (8U)
10915 /*! DCSZ - Level 1 Data Cache Size
10916  */
10917 #define MSCM_CPxCFG1_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_DCSZ_SHIFT)) & MSCM_CPxCFG1_DCSZ_MASK)
10918 #define MSCM_CPxCFG1_ICWY_MASK (0xFF0000U)
10919 #define MSCM_CPxCFG1_ICWY_SHIFT (16U)
10920 /*! ICWY - Level 1 Instruction Cache Ways
10921  */
10922 #define MSCM_CPxCFG1_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_ICWY_SHIFT)) & MSCM_CPxCFG1_ICWY_MASK)
10923 #define MSCM_CPxCFG1_ICSZ_MASK (0xFF000000U)
10924 #define MSCM_CPxCFG1_ICSZ_SHIFT (24U)
10925 /*! ICSZ - Level 1 Instruction Cache Size
10926  */
10927 #define MSCM_CPxCFG1_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_ICSZ_SHIFT)) & MSCM_CPxCFG1_ICSZ_MASK)
10928 /*! @} */
10929 
10930 /*! @name CPxCFG2 - Processor X Configuration Register */
10931 /*! @{ */
10932 #define MSCM_CPxCFG2_DCWY_MASK (0xFFU)
10933 #define MSCM_CPxCFG2_DCWY_SHIFT (0U)
10934 /*! DCWY - Level 1 Data Cache Ways
10935  */
10936 #define MSCM_CPxCFG2_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_DCWY_SHIFT)) & MSCM_CPxCFG2_DCWY_MASK)
10937 #define MSCM_CPxCFG2_DCSZ_MASK (0xFF00U)
10938 #define MSCM_CPxCFG2_DCSZ_SHIFT (8U)
10939 /*! DCSZ - Level 1 Data Cache Size
10940  */
10941 #define MSCM_CPxCFG2_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_DCSZ_SHIFT)) & MSCM_CPxCFG2_DCSZ_MASK)
10942 #define MSCM_CPxCFG2_ICWY_MASK (0xFF0000U)
10943 #define MSCM_CPxCFG2_ICWY_SHIFT (16U)
10944 /*! ICWY - Level 1 Instruction Cache Ways
10945  */
10946 #define MSCM_CPxCFG2_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_ICWY_SHIFT)) & MSCM_CPxCFG2_ICWY_MASK)
10947 #define MSCM_CPxCFG2_ICSZ_MASK (0xFF000000U)
10948 #define MSCM_CPxCFG2_ICSZ_SHIFT (24U)
10949 /*! ICSZ - Level 1 Instruction Cache Size
10950  */
10951 #define MSCM_CPxCFG2_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_ICSZ_SHIFT)) & MSCM_CPxCFG2_ICSZ_MASK)
10952 /*! @} */
10953 
10954 /*! @name CPxCFG3 - Processor X Configuration Register */
10955 /*! @{ */
10956 #define MSCM_CPxCFG3_DCWY_MASK (0xFFU)
10957 #define MSCM_CPxCFG3_DCWY_SHIFT (0U)
10958 /*! DCWY - Level 1 Data Cache Ways
10959  */
10960 #define MSCM_CPxCFG3_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_DCWY_SHIFT)) & MSCM_CPxCFG3_DCWY_MASK)
10961 #define MSCM_CPxCFG3_DCSZ_MASK (0xFF00U)
10962 #define MSCM_CPxCFG3_DCSZ_SHIFT (8U)
10963 /*! DCSZ - Level 1 Data Cache Size
10964  */
10965 #define MSCM_CPxCFG3_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_DCSZ_SHIFT)) & MSCM_CPxCFG3_DCSZ_MASK)
10966 #define MSCM_CPxCFG3_ICWY_MASK (0xFF0000U)
10967 #define MSCM_CPxCFG3_ICWY_SHIFT (16U)
10968 /*! ICWY - Level 1 Instruction Cache Ways
10969  */
10970 #define MSCM_CPxCFG3_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_ICWY_SHIFT)) & MSCM_CPxCFG3_ICWY_MASK)
10971 #define MSCM_CPxCFG3_ICSZ_MASK (0xFF000000U)
10972 #define MSCM_CPxCFG3_ICSZ_SHIFT (24U)
10973 /*! ICSZ - Level 1 Instruction Cache Size
10974  */
10975 #define MSCM_CPxCFG3_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_ICSZ_SHIFT)) & MSCM_CPxCFG3_ICSZ_MASK)
10976 /*! @} */
10977 
10978 /*! @name TYPE - Processor 0 Type Register */
10979 /*! @{ */
10980 #define MSCM_TYPE_RYPZ_MASK (0xFFU)
10981 #define MSCM_TYPE_RYPZ_SHIFT (0U)
10982 /*! RYPZ - Processor x Revision
10983  */
10984 #define MSCM_TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK)
10985 #define MSCM_TYPE_PERSONALITY_MASK (0xFFFFFF00U)
10986 #define MSCM_TYPE_PERSONALITY_SHIFT (8U)
10987 /*! PERSONALITY - Processor x Personality
10988  */
10989 #define MSCM_TYPE_PERSONALITY(x) \
10990     (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK)
10991 /*! @} */
10992 
10993 /* The count of MSCM_TYPE */
10994 #define MSCM_TYPE_COUNT (1U)
10995 
10996 /*! @name NUM - Processor 0 Number Register */
10997 /*! @{ */
10998 #define MSCM_NUM_CPN_MASK (0x1U)
10999 #define MSCM_NUM_CPN_SHIFT (0U)
11000 /*! CPN - Processor x Number
11001  */
11002 #define MSCM_NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK)
11003 /*! @} */
11004 
11005 /* The count of MSCM_NUM */
11006 #define MSCM_NUM_COUNT (1U)
11007 
11008 /*! @name MASTER - Processor 0 Master Register */
11009 /*! @{ */
11010 #define MSCM_MASTER_PPN_MASK (0x3FU)
11011 #define MSCM_MASTER_PPN_SHIFT (0U)
11012 /*! PPN - Processor x Physical Port Number
11013  */
11014 #define MSCM_MASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPN_SHIFT)) & MSCM_MASTER_PPN_MASK)
11015 /*! @} */
11016 
11017 /* The count of MSCM_MASTER */
11018 #define MSCM_MASTER_COUNT (1U)
11019 
11020 /*! @name COUNT - Processor 0 Count Register */
11021 /*! @{ */
11022 #define MSCM_COUNT_PCNT_MASK (0x3U)
11023 #define MSCM_COUNT_PCNT_SHIFT (0U)
11024 /*! PCNT - Processor Count
11025  */
11026 #define MSCM_COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK)
11027 /*! @} */
11028 
11029 /* The count of MSCM_COUNT */
11030 #define MSCM_COUNT_COUNT (1U)
11031 
11032 /*! @name CFG0 - Processor 0 Configuration Register */
11033 /*! @{ */
11034 #define MSCM_CFG0_DCWY_MASK (0xFFU)
11035 #define MSCM_CFG0_DCWY_SHIFT (0U)
11036 /*! DCWY - Level 1 Data Cache Ways
11037  */
11038 #define MSCM_CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCWY_SHIFT)) & MSCM_CFG0_DCWY_MASK)
11039 #define MSCM_CFG0_DCSZ_MASK (0xFF00U)
11040 #define MSCM_CFG0_DCSZ_SHIFT (8U)
11041 /*! DCSZ - Level 1 Data Cache Size
11042  */
11043 #define MSCM_CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCSZ_SHIFT)) & MSCM_CFG0_DCSZ_MASK)
11044 #define MSCM_CFG0_ICWY_MASK (0xFF0000U)
11045 #define MSCM_CFG0_ICWY_SHIFT (16U)
11046 /*! ICWY - Level 1 Instruction Cache Ways
11047  */
11048 #define MSCM_CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICWY_SHIFT)) & MSCM_CFG0_ICWY_MASK)
11049 #define MSCM_CFG0_ICSZ_MASK (0xFF000000U)
11050 #define MSCM_CFG0_ICSZ_SHIFT (24U)
11051 /*! ICSZ - Level 1 Instruction Cache Size
11052  */
11053 #define MSCM_CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICSZ_SHIFT)) & MSCM_CFG0_ICSZ_MASK)
11054 /*! @} */
11055 
11056 /* The count of MSCM_CFG0 */
11057 #define MSCM_CFG0_COUNT (1U)
11058 
11059 /*! @name CFG1 - Processor 0 Configuration Register */
11060 /*! @{ */
11061 #define MSCM_CFG1_DCWY_MASK (0xFFU)
11062 #define MSCM_CFG1_DCWY_SHIFT (0U)
11063 /*! DCWY - Level 1 Data Cache Ways
11064  */
11065 #define MSCM_CFG1_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_DCWY_SHIFT)) & MSCM_CFG1_DCWY_MASK)
11066 #define MSCM_CFG1_DCSZ_MASK (0xFF00U)
11067 #define MSCM_CFG1_DCSZ_SHIFT (8U)
11068 /*! DCSZ - Level 1 Data Cache Size
11069  */
11070 #define MSCM_CFG1_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_DCSZ_SHIFT)) & MSCM_CFG1_DCSZ_MASK)
11071 #define MSCM_CFG1_ICWY_MASK (0xFF0000U)
11072 #define MSCM_CFG1_ICWY_SHIFT (16U)
11073 /*! ICWY - Level 1 Instruction Cache Ways
11074  */
11075 #define MSCM_CFG1_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_ICWY_SHIFT)) & MSCM_CFG1_ICWY_MASK)
11076 #define MSCM_CFG1_ICSZ_MASK (0xFF000000U)
11077 #define MSCM_CFG1_ICSZ_SHIFT (24U)
11078 /*! ICSZ - Level 1 Instruction Cache Size
11079  */
11080 #define MSCM_CFG1_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_ICSZ_SHIFT)) & MSCM_CFG1_ICSZ_MASK)
11081 /*! @} */
11082 
11083 /* The count of MSCM_CFG1 */
11084 #define MSCM_CFG1_COUNT (1U)
11085 
11086 /*! @name CFG2 - Processor 0 Configuration Register */
11087 /*! @{ */
11088 #define MSCM_CFG2_DCWY_MASK (0xFFU)
11089 #define MSCM_CFG2_DCWY_SHIFT (0U)
11090 /*! DCWY - Level 1 Data Cache Ways
11091  */
11092 #define MSCM_CFG2_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_DCWY_SHIFT)) & MSCM_CFG2_DCWY_MASK)
11093 #define MSCM_CFG2_DCSZ_MASK (0xFF00U)
11094 #define MSCM_CFG2_DCSZ_SHIFT (8U)
11095 /*! DCSZ - Level 1 Data Cache Size
11096  */
11097 #define MSCM_CFG2_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_DCSZ_SHIFT)) & MSCM_CFG2_DCSZ_MASK)
11098 #define MSCM_CFG2_ICWY_MASK (0xFF0000U)
11099 #define MSCM_CFG2_ICWY_SHIFT (16U)
11100 /*! ICWY - Level 1 Instruction Cache Ways
11101  */
11102 #define MSCM_CFG2_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_ICWY_SHIFT)) & MSCM_CFG2_ICWY_MASK)
11103 #define MSCM_CFG2_ICSZ_MASK (0xFF000000U)
11104 #define MSCM_CFG2_ICSZ_SHIFT (24U)
11105 /*! ICSZ - Level 1 Instruction Cache Size
11106  */
11107 #define MSCM_CFG2_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_ICSZ_SHIFT)) & MSCM_CFG2_ICSZ_MASK)
11108 /*! @} */
11109 
11110 /* The count of MSCM_CFG2 */
11111 #define MSCM_CFG2_COUNT (1U)
11112 
11113 /*! @name CFG3 - Processor 0 Configuration Register */
11114 /*! @{ */
11115 #define MSCM_CFG3_DCWY_MASK (0xFFU)
11116 #define MSCM_CFG3_DCWY_SHIFT (0U)
11117 /*! DCWY - Level 1 Data Cache Ways
11118  */
11119 #define MSCM_CFG3_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_DCWY_SHIFT)) & MSCM_CFG3_DCWY_MASK)
11120 #define MSCM_CFG3_DCSZ_MASK (0xFF00U)
11121 #define MSCM_CFG3_DCSZ_SHIFT (8U)
11122 /*! DCSZ - Level 1 Data Cache Size
11123  */
11124 #define MSCM_CFG3_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_DCSZ_SHIFT)) & MSCM_CFG3_DCSZ_MASK)
11125 #define MSCM_CFG3_ICWY_MASK (0xFF0000U)
11126 #define MSCM_CFG3_ICWY_SHIFT (16U)
11127 /*! ICWY - Level 1 Instruction Cache Ways
11128  */
11129 #define MSCM_CFG3_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_ICWY_SHIFT)) & MSCM_CFG3_ICWY_MASK)
11130 #define MSCM_CFG3_ICSZ_MASK (0xFF000000U)
11131 #define MSCM_CFG3_ICSZ_SHIFT (24U)
11132 /*! ICSZ - Level 1 Instruction Cache Size
11133  */
11134 #define MSCM_CFG3_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_ICSZ_SHIFT)) & MSCM_CFG3_ICSZ_MASK)
11135 /*! @} */
11136 
11137 /* The count of MSCM_CFG3 */
11138 #define MSCM_CFG3_COUNT (1U)
11139 
11140 /*! @name OCMDR - On-Chip Memory Descriptor Register */
11141 /*! @{ */
11142 #define MSCM_OCMDR_OCMPU_MASK (0x1000U)
11143 #define MSCM_OCMDR_OCMPU_SHIFT (12U)
11144 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMPU_SHIFT)) & MSCM_OCMDR_OCMPU_MASK)
11145 #define MSCM_OCMDR_OCMT_MASK (0xE000U)
11146 #define MSCM_OCMDR_OCMT_SHIFT (13U)
11147 /*! OCMT
11148  *  0b000..OCMEMn is a system RAM.
11149  *  0b001..OCMEMn is a graphics RAM.
11150  *  0b010..Reserved
11151  *  0b011..OCMEMn is a ROM.
11152  *  0b100..Reserved
11153  *  0b101..Reserved
11154  *  0b110..Reserved
11155  *  0b111..Reserved
11156  */
11157 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMT_SHIFT)) & MSCM_OCMDR_OCMT_MASK)
11158 #define MSCM_OCMDR_RO_MASK (0x10000U)
11159 #define MSCM_OCMDR_RO_SHIFT (16U)
11160 /*! RO
11161  *  0b0..Writes to the OCMDRn[11:0] are allowed
11162  *  0b1..Writes to the OCMDRn[11:0] are ignored
11163  */
11164 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_RO_SHIFT)) & MSCM_OCMDR_RO_MASK)
11165 #define MSCM_OCMDR_OCMW_MASK (0xE0000U)
11166 #define MSCM_OCMDR_OCMW_SHIFT (17U)
11167 /*! OCMW
11168  *  0b010..OCMEMn 32-bits wide
11169  *  0b011..OCMEMn 64-bits wide
11170  */
11171 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMW_SHIFT)) & MSCM_OCMDR_OCMW_MASK)
11172 #define MSCM_OCMDR_OCMSZ_MASK (0xF000000U)
11173 #define MSCM_OCMDR_OCMSZ_SHIFT (24U)
11174 /*! OCMSZ
11175  *  0b0000..no OCMEMn
11176  *  0b0100..4KB OCMEMn
11177  *  0b0101..8KB OCMEMn
11178  *  0b0110..16KB OCMEMn
11179  *  0b0111..32KB OCMEMn
11180  *  0b1111..8192KB OCMEMn
11181  */
11182 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZ_SHIFT)) & MSCM_OCMDR_OCMSZ_MASK)
11183 #define MSCM_OCMDR_OCMSZH_MASK (0x10000000U)
11184 #define MSCM_OCMDR_OCMSZH_SHIFT (28U)
11185 /*! OCMSZH
11186  *  0b0..OCMEMn is a power-of-2 capacity.
11187  *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
11188  */
11189 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZH_SHIFT)) & MSCM_OCMDR_OCMSZH_MASK)
11190 #define MSCM_OCMDR_V_MASK (0x80000000U)
11191 #define MSCM_OCMDR_V_SHIFT (31U)
11192 /*! V
11193  *  0b0..OCMEMn is not present.
11194  *  0b1..OCMEMn is present.
11195  */
11196 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_V_SHIFT)) & MSCM_OCMDR_V_MASK)
11197 /*! @} */
11198 
11199 /* The count of MSCM_OCMDR */
11200 #define MSCM_OCMDR_COUNT (3U)
11201 
11202 /*!
11203  * @}
11204  */ /* end of group MSCM_Register_Masks */
11205 
11206 /* MSCM - Peripheral instance base addresses */
11207 /** Peripheral MSCM base address */
11208 #define MSCM_BASE (0x40001000u)
11209 /** Peripheral MSCM base pointer */
11210 #define MSCM ((MSCM_Type *)MSCM_BASE)
11211 /** Array initializer of MSCM peripheral base addresses */
11212 #define MSCM_BASE_ADDRS \
11213     {                   \
11214         MSCM_BASE       \
11215     }
11216 /** Array initializer of MSCM peripheral base pointers */
11217 #define MSCM_BASE_PTRS \
11218     {                  \
11219         MSCM           \
11220     }
11221 
11222 /*!
11223  * @}
11224  */ /* end of group MSCM_Peripheral_Access_Layer */
11225 
11226 /* ----------------------------------------------------------------------------
11227    -- MTB Peripheral Access Layer
11228    ---------------------------------------------------------------------------- */
11229 
11230 /*!
11231  * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
11232  * @{
11233  */
11234 
11235 /** MTB - Register Layout Typedef */
11236 typedef struct
11237 {
11238     __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
11239     __IO uint32_t MASTER;   /**< MTB Master Register, offset: 0x4 */
11240     __IO uint32_t FLOW;     /**< MTB Flow Register, offset: 0x8 */
11241     __I uint32_t BASE;      /**< MTB Base Register, offset: 0xC */
11242     uint8_t RESERVED_0[3824];
11243     __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
11244     uint8_t RESERVED_1[156];
11245     __I uint32_t TAGSET;   /**< Claim TAG Set Register, offset: 0xFA0 */
11246     __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
11247     uint8_t RESERVED_2[8];
11248     __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
11249     __I uint32_t LOCKSTAT;   /**< Lock Status Register, offset: 0xFB4 */
11250     __I uint32_t AUTHSTAT;   /**< Authentication Status Register, offset: 0xFB8 */
11251     __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
11252     uint8_t RESERVED_3[8];
11253     __I uint32_t DEVICECFG;   /**< Device Configuration Register, offset: 0xFC8 */
11254     __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
11255     __I uint32_t PERIPHID4;   /**< Peripheral ID Register, offset: 0xFD0 */
11256     __I uint32_t PERIPHID5;   /**< Peripheral ID Register, offset: 0xFD4 */
11257     __I uint32_t PERIPHID6;   /**< Peripheral ID Register, offset: 0xFD8 */
11258     __I uint32_t PERIPHID7;   /**< Peripheral ID Register, offset: 0xFDC */
11259     __I uint32_t PERIPHID0;   /**< Peripheral ID Register, offset: 0xFE0 */
11260     __I uint32_t PERIPHID1;   /**< Peripheral ID Register, offset: 0xFE4 */
11261     __I uint32_t PERIPHID2;   /**< Peripheral ID Register, offset: 0xFE8 */
11262     __I uint32_t PERIPHID3;   /**< Peripheral ID Register, offset: 0xFEC */
11263     __I uint32_t COMPID[4];   /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
11264 } MTB_Type;
11265 
11266 /* ----------------------------------------------------------------------------
11267    -- MTB Register Masks
11268    ---------------------------------------------------------------------------- */
11269 
11270 /*!
11271  * @addtogroup MTB_Register_Masks MTB Register Masks
11272  * @{
11273  */
11274 
11275 /*! @name POSITION - MTB Position Register */
11276 /*! @{ */
11277 #define MTB_POSITION_WRAP_MASK (0x4U)
11278 #define MTB_POSITION_WRAP_SHIFT (2U)
11279 /*! WRAP - WRAP
11280  */
11281 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
11282 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
11283 #define MTB_POSITION_POINTER_SHIFT (3U)
11284 /*! POINTER - Trace Packet Address Pointer[28:0]
11285  */
11286 #define MTB_POSITION_POINTER(x) \
11287     (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
11288 /*! @} */
11289 
11290 /*! @name MASTER - MTB Master Register */
11291 /*! @{ */
11292 #define MTB_MASTER_MASK_MASK (0x1FU)
11293 #define MTB_MASTER_MASK_SHIFT (0U)
11294 /*! MASK - Mask
11295  */
11296 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
11297 #define MTB_MASTER_TSTARTEN_MASK (0x20U)
11298 #define MTB_MASTER_TSTARTEN_SHIFT (5U)
11299 /*! TSTARTEN - Trace Start Input Enable
11300  */
11301 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
11302 #define MTB_MASTER_TSTOPEN_MASK (0x40U)
11303 #define MTB_MASTER_TSTOPEN_SHIFT (6U)
11304 /*! TSTOPEN - Trace Stop Input Enable
11305  */
11306 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
11307 #define MTB_MASTER_SFRWPRIV_MASK (0x80U)
11308 #define MTB_MASTER_SFRWPRIV_SHIFT (7U)
11309 /*! SFRWPRIV - Special Function Register Write Privilege
11310  */
11311 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
11312 #define MTB_MASTER_RAMPRIV_MASK (0x100U)
11313 #define MTB_MASTER_RAMPRIV_SHIFT (8U)
11314 /*! RAMPRIV - RAM Privilege
11315  */
11316 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
11317 #define MTB_MASTER_HALTREQ_MASK (0x200U)
11318 #define MTB_MASTER_HALTREQ_SHIFT (9U)
11319 /*! HALTREQ - Halt Request
11320  */
11321 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
11322 #define MTB_MASTER_EN_MASK (0x80000000U)
11323 #define MTB_MASTER_EN_SHIFT (31U)
11324 /*! EN - Main Trace Enable
11325  */
11326 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
11327 /*! @} */
11328 
11329 /*! @name FLOW - MTB Flow Register */
11330 /*! @{ */
11331 #define MTB_FLOW_AUTOSTOP_MASK (0x1U)
11332 #define MTB_FLOW_AUTOSTOP_SHIFT (0U)
11333 /*! AUTOSTOP - AUTOSTOP
11334  */
11335 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
11336 #define MTB_FLOW_AUTOHALT_MASK (0x2U)
11337 #define MTB_FLOW_AUTOHALT_SHIFT (1U)
11338 /*! AUTOHALT - AUTOHALT
11339  */
11340 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
11341 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
11342 #define MTB_FLOW_WATERMARK_SHIFT (3U)
11343 /*! WATERMARK - WATERMARK[28:0]
11344  */
11345 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
11346 /*! @} */
11347 
11348 /*! @name BASE - MTB Base Register */
11349 /*! @{ */
11350 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
11351 #define MTB_BASE_BASEADDR_SHIFT (0U)
11352 /*! BASEADDR - BASEADDR
11353  */
11354 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
11355 /*! @} */
11356 
11357 /*! @name MODECTRL - Integration Mode Control Register */
11358 /*! @{ */
11359 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
11360 #define MTB_MODECTRL_MODECTRL_SHIFT (0U)
11361 /*! MODECTRL - MODECTRL
11362  */
11363 #define MTB_MODECTRL_MODECTRL(x) \
11364     (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
11365 /*! @} */
11366 
11367 /*! @name TAGSET - Claim TAG Set Register */
11368 /*! @{ */
11369 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
11370 #define MTB_TAGSET_TAGSET_SHIFT (0U)
11371 /*! TAGSET - TAGSET
11372  */
11373 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
11374 /*! @} */
11375 
11376 /*! @name TAGCLEAR - Claim TAG Clear Register */
11377 /*! @{ */
11378 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
11379 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
11380 /*! TAGCLEAR - TAGCLEAR
11381  */
11382 #define MTB_TAGCLEAR_TAGCLEAR(x) \
11383     (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
11384 /*! @} */
11385 
11386 /*! @name LOCKACCESS - Lock Access Register */
11387 /*! @{ */
11388 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
11389 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
11390 #define MTB_LOCKACCESS_LOCKACCESS(x) \
11391     (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
11392 /*! @} */
11393 
11394 /*! @name LOCKSTAT - Lock Status Register */
11395 /*! @{ */
11396 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
11397 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
11398 /*! LOCKSTAT - LOCKSTAT
11399  */
11400 #define MTB_LOCKSTAT_LOCKSTAT(x) \
11401     (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
11402 /*! @} */
11403 
11404 /*! @name AUTHSTAT - Authentication Status Register */
11405 /*! @{ */
11406 #define MTB_AUTHSTAT_BIT0_MASK (0x1U)
11407 #define MTB_AUTHSTAT_BIT0_SHIFT (0U)
11408 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
11409 #define MTB_AUTHSTAT_BIT1_MASK (0x2U)
11410 #define MTB_AUTHSTAT_BIT1_SHIFT (1U)
11411 /*! BIT1 - BIT1
11412  */
11413 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
11414 #define MTB_AUTHSTAT_BIT2_MASK (0x4U)
11415 #define MTB_AUTHSTAT_BIT2_SHIFT (2U)
11416 /*! BIT2 - BIT2
11417  */
11418 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
11419 #define MTB_AUTHSTAT_BIT3_MASK (0x8U)
11420 #define MTB_AUTHSTAT_BIT3_SHIFT (3U)
11421 /*! BIT3 - BIT3
11422  */
11423 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
11424 /*! @} */
11425 
11426 /*! @name DEVICEARCH - Device Architecture Register */
11427 /*! @{ */
11428 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
11429 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
11430 /*! DEVICEARCH - DEVICEARCH
11431  */
11432 #define MTB_DEVICEARCH_DEVICEARCH(x) \
11433     (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
11434 /*! @} */
11435 
11436 /*! @name DEVICECFG - Device Configuration Register */
11437 /*! @{ */
11438 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
11439 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
11440 /*! DEVICECFG - DEVICECFG
11441  */
11442 #define MTB_DEVICECFG_DEVICECFG(x) \
11443     (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
11444 /*! @} */
11445 
11446 /*! @name DEVICETYPID - Device Type Identifier Register */
11447 /*! @{ */
11448 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
11449 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
11450 /*! DEVICETYPID - DEVICETYPID
11451  */
11452 #define MTB_DEVICETYPID_DEVICETYPID(x) \
11453     (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
11454 /*! @} */
11455 
11456 /*! @name PERIPHID4 - Peripheral ID Register */
11457 /*! @{ */
11458 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
11459 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
11460 /*! PERIPHID - PERIPHID
11461  */
11462 #define MTB_PERIPHID4_PERIPHID(x) \
11463     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
11464 /*! @} */
11465 
11466 /*! @name PERIPHID5 - Peripheral ID Register */
11467 /*! @{ */
11468 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
11469 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
11470 /*! PERIPHID - PERIPHID
11471  */
11472 #define MTB_PERIPHID5_PERIPHID(x) \
11473     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
11474 /*! @} */
11475 
11476 /*! @name PERIPHID6 - Peripheral ID Register */
11477 /*! @{ */
11478 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
11479 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
11480 /*! PERIPHID - PERIPHID
11481  */
11482 #define MTB_PERIPHID6_PERIPHID(x) \
11483     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
11484 /*! @} */
11485 
11486 /*! @name PERIPHID7 - Peripheral ID Register */
11487 /*! @{ */
11488 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
11489 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
11490 /*! PERIPHID - PERIPHID
11491  */
11492 #define MTB_PERIPHID7_PERIPHID(x) \
11493     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
11494 /*! @} */
11495 
11496 /*! @name PERIPHID0 - Peripheral ID Register */
11497 /*! @{ */
11498 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
11499 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
11500 /*! PERIPHID - PERIPHID
11501  */
11502 #define MTB_PERIPHID0_PERIPHID(x) \
11503     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
11504 /*! @} */
11505 
11506 /*! @name PERIPHID1 - Peripheral ID Register */
11507 /*! @{ */
11508 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
11509 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
11510 /*! PERIPHID - PERIPHID
11511  */
11512 #define MTB_PERIPHID1_PERIPHID(x) \
11513     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
11514 /*! @} */
11515 
11516 /*! @name PERIPHID2 - Peripheral ID Register */
11517 /*! @{ */
11518 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
11519 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
11520 /*! PERIPHID - PERIPHID
11521  */
11522 #define MTB_PERIPHID2_PERIPHID(x) \
11523     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
11524 /*! @} */
11525 
11526 /*! @name PERIPHID3 - Peripheral ID Register */
11527 /*! @{ */
11528 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
11529 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
11530 /*! PERIPHID - PERIPHID
11531  */
11532 #define MTB_PERIPHID3_PERIPHID(x) \
11533     (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
11534 /*! @} */
11535 
11536 /*! @name COMPID - Component ID Register */
11537 /*! @{ */
11538 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
11539 #define MTB_COMPID_COMPID_SHIFT (0U)
11540 /*! COMPID - Component ID
11541  */
11542 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
11543 /*! @} */
11544 
11545 /* The count of MTB_COMPID */
11546 #define MTB_COMPID_COUNT (4U)
11547 
11548 /*!
11549  * @}
11550  */ /* end of group MTB_Register_Masks */
11551 
11552 /* MTB - Peripheral instance base addresses */
11553 /** Peripheral MTB0 base address */
11554 #define MTB0_BASE (0xF0000000u)
11555 /** Peripheral MTB0 base pointer */
11556 #define MTB0 ((MTB_Type *)MTB0_BASE)
11557 /** Array initializer of MTB peripheral base addresses */
11558 #define MTB_BASE_ADDRS \
11559     {                  \
11560         MTB0_BASE      \
11561     }
11562 /** Array initializer of MTB peripheral base pointers */
11563 #define MTB_BASE_PTRS \
11564     {                 \
11565         MTB0          \
11566     }
11567 
11568 /*!
11569  * @}
11570  */ /* end of group MTB_Peripheral_Access_Layer */
11571 
11572 /* ----------------------------------------------------------------------------
11573    -- MTB_DWT Peripheral Access Layer
11574    ---------------------------------------------------------------------------- */
11575 
11576 /*!
11577  * @addtogroup MTB_DWT_Peripheral_Access_Layer MTB_DWT Peripheral Access Layer
11578  * @{
11579  */
11580 
11581 /** MTB_DWT - Register Layout Typedef */
11582 typedef struct
11583 {
11584     __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
11585     uint8_t RESERVED_0[28];
11586     struct
11587     {                       /* offset: 0x20, array step: 0x10 */
11588         __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
11589         __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
11590         __IO uint32_t FCT;  /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array
11591                                offset: 0x28, array step: 0x10 */
11592         uint8_t RESERVED_0[4];
11593     } COMPARATOR[2];
11594     uint8_t RESERVED_1[448];
11595     __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
11596     uint8_t RESERVED_2[3524];
11597     __I uint32_t DEVICECFG;   /**< Device Configuration Register, offset: 0xFC8 */
11598     __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
11599     __I uint32_t PERIPHID4;   /**< Peripheral ID Register, offset: 0xFD0 */
11600     __I uint32_t PERIPHID5;   /**< Peripheral ID Register, offset: 0xFD4 */
11601     __I uint32_t PERIPHID6;   /**< Peripheral ID Register, offset: 0xFD8 */
11602     __I uint32_t PERIPHID7;   /**< Peripheral ID Register, offset: 0xFDC */
11603     __I uint32_t PERIPHID0;   /**< Peripheral ID Register, offset: 0xFE0 */
11604     __I uint32_t PERIPHID1;   /**< Peripheral ID Register, offset: 0xFE4 */
11605     __I uint32_t PERIPHID2;   /**< Peripheral ID Register, offset: 0xFE8 */
11606     __I uint32_t PERIPHID3;   /**< Peripheral ID Register, offset: 0xFEC */
11607     __I uint32_t COMPID[4];   /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
11608 } MTB_DWT_Type;
11609 
11610 /* ----------------------------------------------------------------------------
11611    -- MTB_DWT Register Masks
11612    ---------------------------------------------------------------------------- */
11613 
11614 /*!
11615  * @addtogroup MTB_DWT_Register_Masks MTB_DWT Register Masks
11616  * @{
11617  */
11618 
11619 /*! @name CTRL - MTB DWT Control Register */
11620 /*! @{ */
11621 #define MTB_DWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
11622 #define MTB_DWT_CTRL_DWTCFGCTRL_SHIFT (0U)
11623 /*! DWTCFGCTRL - DWT configuration controls
11624  */
11625 #define MTB_DWT_CTRL_DWTCFGCTRL(x) \
11626     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_CTRL_DWTCFGCTRL_SHIFT)) & MTB_DWT_CTRL_DWTCFGCTRL_MASK)
11627 #define MTB_DWT_CTRL_NUMCMP_MASK (0xF0000000U)
11628 #define MTB_DWT_CTRL_NUMCMP_SHIFT (28U)
11629 /*! NUMCMP - Number of comparators
11630  */
11631 #define MTB_DWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_CTRL_NUMCMP_SHIFT)) & MTB_DWT_CTRL_NUMCMP_MASK)
11632 /*! @} */
11633 
11634 /*! @name COMP - MTB_DWT Comparator Register */
11635 /*! @{ */
11636 #define MTB_DWT_COMP_COMP_MASK (0xFFFFFFFFU)
11637 #define MTB_DWT_COMP_COMP_SHIFT (0U)
11638 /*! COMP - Reference value for comparison
11639  */
11640 #define MTB_DWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_COMP_COMP_SHIFT)) & MTB_DWT_COMP_COMP_MASK)
11641 /*! @} */
11642 
11643 /* The count of MTB_DWT_COMP */
11644 #define MTB_DWT_COMP_COUNT (2U)
11645 
11646 /*! @name MASK - MTB_DWT Comparator Mask Register */
11647 /*! @{ */
11648 #define MTB_DWT_MASK_MASK_MASK (0x1FU)
11649 #define MTB_DWT_MASK_MASK_SHIFT (0U)
11650 /*! MASK - MASK
11651  */
11652 #define MTB_DWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_MASK_MASK_SHIFT)) & MTB_DWT_MASK_MASK_MASK)
11653 /*! @} */
11654 
11655 /* The count of MTB_DWT_MASK */
11656 #define MTB_DWT_MASK_COUNT (2U)
11657 
11658 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
11659 /*! @{ */
11660 #define MTB_DWT_FCT_FUNCTION_MASK (0xFU)
11661 #define MTB_DWT_FCT_FUNCTION_SHIFT (0U)
11662 /*! FUNCTION - Function
11663  *  0b0000..Disabled.
11664  *  0b0100..Instruction fetch.
11665  *  0b0101..Data operand read.
11666  *  0b0110..Data operand write.
11667  *  0b0111..Data operand (read + write).
11668  */
11669 #define MTB_DWT_FCT_FUNCTION(x) \
11670     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_FUNCTION_SHIFT)) & MTB_DWT_FCT_FUNCTION_MASK)
11671 #define MTB_DWT_FCT_DATAVMATCH_MASK (0x100U)
11672 #define MTB_DWT_FCT_DATAVMATCH_SHIFT (8U)
11673 /*! DATAVMATCH - Data Value Match
11674  *  0b0..Perform address comparison.
11675  *  0b1..Perform data value comparison.
11676  */
11677 #define MTB_DWT_FCT_DATAVMATCH(x) \
11678     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVMATCH_SHIFT)) & MTB_DWT_FCT_DATAVMATCH_MASK)
11679 #define MTB_DWT_FCT_DATAVSIZE_MASK (0xC00U)
11680 #define MTB_DWT_FCT_DATAVSIZE_SHIFT (10U)
11681 /*! DATAVSIZE - Data Value Size
11682  *  0b00..Byte.
11683  *  0b01..Halfword.
11684  *  0b10..Word.
11685  *  0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
11686  */
11687 #define MTB_DWT_FCT_DATAVSIZE(x) \
11688     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVSIZE_SHIFT)) & MTB_DWT_FCT_DATAVSIZE_MASK)
11689 #define MTB_DWT_FCT_DATAVADDR0_MASK (0xF000U)
11690 #define MTB_DWT_FCT_DATAVADDR0_SHIFT (12U)
11691 /*! DATAVADDR0 - Data Value Address 0
11692  */
11693 #define MTB_DWT_FCT_DATAVADDR0(x) \
11694     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_DATAVADDR0_SHIFT)) & MTB_DWT_FCT_DATAVADDR0_MASK)
11695 #define MTB_DWT_FCT_MATCHED_MASK (0x1000000U)
11696 #define MTB_DWT_FCT_MATCHED_SHIFT (24U)
11697 /*! MATCHED - Comparator match
11698  *  0b0..No match.
11699  *  0b1..Match occurred.
11700  */
11701 #define MTB_DWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTB_DWT_FCT_MATCHED_SHIFT)) & MTB_DWT_FCT_MATCHED_MASK)
11702 /*! @} */
11703 
11704 /* The count of MTB_DWT_FCT */
11705 #define MTB_DWT_FCT_COUNT (2U)
11706 
11707 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
11708 /*! @{ */
11709 #define MTB_DWT_TBCTRL_ACOMP0_MASK (0x1U)
11710 #define MTB_DWT_TBCTRL_ACOMP0_SHIFT (0U)
11711 /*! ACOMP0 - Action based on Comparator 0 match
11712  *  0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
11713  *  0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
11714  */
11715 #define MTB_DWT_TBCTRL_ACOMP0(x) \
11716     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_ACOMP0_SHIFT)) & MTB_DWT_TBCTRL_ACOMP0_MASK)
11717 #define MTB_DWT_TBCTRL_ACOMP1_MASK (0x2U)
11718 #define MTB_DWT_TBCTRL_ACOMP1_SHIFT (1U)
11719 /*! ACOMP1 - Action based on Comparator 1 match
11720  *  0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
11721  *  0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
11722  */
11723 #define MTB_DWT_TBCTRL_ACOMP1(x) \
11724     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_ACOMP1_SHIFT)) & MTB_DWT_TBCTRL_ACOMP1_MASK)
11725 #define MTB_DWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
11726 #define MTB_DWT_TBCTRL_NUMCOMP_SHIFT (28U)
11727 /*! NUMCOMP - Number of Comparators
11728  */
11729 #define MTB_DWT_TBCTRL_NUMCOMP(x) \
11730     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_TBCTRL_NUMCOMP_SHIFT)) & MTB_DWT_TBCTRL_NUMCOMP_MASK)
11731 /*! @} */
11732 
11733 /*! @name DEVICECFG - Device Configuration Register */
11734 /*! @{ */
11735 #define MTB_DWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
11736 #define MTB_DWT_DEVICECFG_DEVICECFG_SHIFT (0U)
11737 /*! DEVICECFG - DEVICECFG
11738  */
11739 #define MTB_DWT_DEVICECFG_DEVICECFG(x) \
11740     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DWT_DEVICECFG_DEVICECFG_MASK)
11741 /*! @} */
11742 
11743 /*! @name DEVICETYPID - Device Type Identifier Register */
11744 /*! @{ */
11745 #define MTB_DWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
11746 #define MTB_DWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
11747 /*! DEVICETYPID - DEVICETYPID
11748  */
11749 #define MTB_DWT_DEVICETYPID_DEVICETYPID(x) \
11750     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DWT_DEVICETYPID_DEVICETYPID_MASK)
11751 /*! @} */
11752 
11753 /*! @name PERIPHID4 - Peripheral ID Register */
11754 /*! @{ */
11755 #define MTB_DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
11756 #define MTB_DWT_PERIPHID4_PERIPHID_SHIFT (0U)
11757 /*! PERIPHID - PERIPHID
11758  */
11759 #define MTB_DWT_PERIPHID4_PERIPHID(x) \
11760     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID4_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID4_PERIPHID_MASK)
11761 /*! @} */
11762 
11763 /*! @name PERIPHID5 - Peripheral ID Register */
11764 /*! @{ */
11765 #define MTB_DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
11766 #define MTB_DWT_PERIPHID5_PERIPHID_SHIFT (0U)
11767 /*! PERIPHID - PERIPHID
11768  */
11769 #define MTB_DWT_PERIPHID5_PERIPHID(x) \
11770     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID5_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID5_PERIPHID_MASK)
11771 /*! @} */
11772 
11773 /*! @name PERIPHID6 - Peripheral ID Register */
11774 /*! @{ */
11775 #define MTB_DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
11776 #define MTB_DWT_PERIPHID6_PERIPHID_SHIFT (0U)
11777 /*! PERIPHID - PERIPHID
11778  */
11779 #define MTB_DWT_PERIPHID6_PERIPHID(x) \
11780     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID6_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID6_PERIPHID_MASK)
11781 /*! @} */
11782 
11783 /*! @name PERIPHID7 - Peripheral ID Register */
11784 /*! @{ */
11785 #define MTB_DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
11786 #define MTB_DWT_PERIPHID7_PERIPHID_SHIFT (0U)
11787 /*! PERIPHID - PERIPHID
11788  */
11789 #define MTB_DWT_PERIPHID7_PERIPHID(x) \
11790     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID7_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID7_PERIPHID_MASK)
11791 /*! @} */
11792 
11793 /*! @name PERIPHID0 - Peripheral ID Register */
11794 /*! @{ */
11795 #define MTB_DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
11796 #define MTB_DWT_PERIPHID0_PERIPHID_SHIFT (0U)
11797 /*! PERIPHID - PERIPHID
11798  */
11799 #define MTB_DWT_PERIPHID0_PERIPHID(x) \
11800     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID0_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID0_PERIPHID_MASK)
11801 /*! @} */
11802 
11803 /*! @name PERIPHID1 - Peripheral ID Register */
11804 /*! @{ */
11805 #define MTB_DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
11806 #define MTB_DWT_PERIPHID1_PERIPHID_SHIFT (0U)
11807 /*! PERIPHID - PERIPHID
11808  */
11809 #define MTB_DWT_PERIPHID1_PERIPHID(x) \
11810     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID1_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID1_PERIPHID_MASK)
11811 /*! @} */
11812 
11813 /*! @name PERIPHID2 - Peripheral ID Register */
11814 /*! @{ */
11815 #define MTB_DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
11816 #define MTB_DWT_PERIPHID2_PERIPHID_SHIFT (0U)
11817 /*! PERIPHID - PERIPHID
11818  */
11819 #define MTB_DWT_PERIPHID2_PERIPHID(x) \
11820     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID2_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID2_PERIPHID_MASK)
11821 /*! @} */
11822 
11823 /*! @name PERIPHID3 - Peripheral ID Register */
11824 /*! @{ */
11825 #define MTB_DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
11826 #define MTB_DWT_PERIPHID3_PERIPHID_SHIFT (0U)
11827 /*! PERIPHID - PERIPHID
11828  */
11829 #define MTB_DWT_PERIPHID3_PERIPHID(x) \
11830     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_PERIPHID3_PERIPHID_SHIFT)) & MTB_DWT_PERIPHID3_PERIPHID_MASK)
11831 /*! @} */
11832 
11833 /*! @name COMPID - Component ID Register */
11834 /*! @{ */
11835 #define MTB_DWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
11836 #define MTB_DWT_COMPID_COMPID_SHIFT (0U)
11837 /*! COMPID - Component ID
11838  */
11839 #define MTB_DWT_COMPID_COMPID(x) \
11840     (((uint32_t)(((uint32_t)(x)) << MTB_DWT_COMPID_COMPID_SHIFT)) & MTB_DWT_COMPID_COMPID_MASK)
11841 /*! @} */
11842 
11843 /* The count of MTB_DWT_COMPID */
11844 #define MTB_DWT_COMPID_COUNT (4U)
11845 
11846 /*!
11847  * @}
11848  */ /* end of group MTB_DWT_Register_Masks */
11849 
11850 /* MTB_DWT - Peripheral instance base addresses */
11851 /** Peripheral MTB0_DWT base address */
11852 #define MTB0_DWT_BASE (0xF0001000u)
11853 /** Peripheral MTB0_DWT base pointer */
11854 #define MTB0_DWT ((MTB_DWT_Type *)MTB0_DWT_BASE)
11855 /** Array initializer of MTB_DWT peripheral base addresses */
11856 #define MTB_DWT_BASE_ADDRS \
11857     {                      \
11858         MTB0_DWT_BASE      \
11859     }
11860 /** Array initializer of MTB_DWT peripheral base pointers */
11861 #define MTB_DWT_BASE_PTRS \
11862     {                     \
11863         MTB0_DWT          \
11864     }
11865 
11866 /*!
11867  * @}
11868  */ /* end of group MTB_DWT_Peripheral_Access_Layer */
11869 
11870 /* ----------------------------------------------------------------------------
11871    -- MTB_ROM Peripheral Access Layer
11872    ---------------------------------------------------------------------------- */
11873 
11874 /*!
11875  * @addtogroup MTB_ROM_Peripheral_Access_Layer MTB_ROM Peripheral Access Layer
11876  * @{
11877  */
11878 
11879 /** MTB_ROM - Register Layout Typedef */
11880 typedef struct
11881 {
11882     __I uint32_t ENTRY[4];  /**< Entry, array offset: 0x0, array step: 0x4 */
11883     __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0x10 */
11884     uint8_t RESERVED_0[4024];
11885     __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
11886     __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
11887     __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
11888     __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
11889     __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
11890     __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
11891     __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
11892     __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
11893     __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
11894     __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
11895 } MTB_ROM_Type;
11896 
11897 /* ----------------------------------------------------------------------------
11898    -- MTB_ROM Register Masks
11899    ---------------------------------------------------------------------------- */
11900 
11901 /*!
11902  * @addtogroup MTB_ROM_Register_Masks MTB_ROM Register Masks
11903  * @{
11904  */
11905 
11906 /*! @name ENTRY - Entry */
11907 /*! @{ */
11908 #define MTB_ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
11909 #define MTB_ROM_ENTRY_ENTRY_SHIFT (0U)
11910 /*! ENTRY - ENTRY
11911  */
11912 #define MTB_ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << MTB_ROM_ENTRY_ENTRY_SHIFT)) & MTB_ROM_ENTRY_ENTRY_MASK)
11913 /*! @} */
11914 
11915 /* The count of MTB_ROM_ENTRY */
11916 #define MTB_ROM_ENTRY_COUNT (4U)
11917 
11918 /*! @name TABLEMARK - End of Table Marker Register */
11919 /*! @{ */
11920 #define MTB_ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
11921 #define MTB_ROM_TABLEMARK_MARK_SHIFT (0U)
11922 /*! MARK - MARK
11923  */
11924 #define MTB_ROM_TABLEMARK_MARK(x) \
11925     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_TABLEMARK_MARK_SHIFT)) & MTB_ROM_TABLEMARK_MARK_MASK)
11926 /*! @} */
11927 
11928 /*! @name SYSACCESS - System Access Register */
11929 /*! @{ */
11930 #define MTB_ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
11931 #define MTB_ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
11932 /*! SYSACCESS - SYSACCESS
11933  */
11934 #define MTB_ROM_SYSACCESS_SYSACCESS(x) \
11935     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_SYSACCESS_SYSACCESS_SHIFT)) & MTB_ROM_SYSACCESS_SYSACCESS_MASK)
11936 /*! @} */
11937 
11938 /*! @name PERIPHID4 - Peripheral ID Register */
11939 /*! @{ */
11940 #define MTB_ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
11941 #define MTB_ROM_PERIPHID4_PERIPHID_SHIFT (0U)
11942 /*! PERIPHID - PERIPHID
11943  */
11944 #define MTB_ROM_PERIPHID4_PERIPHID(x) \
11945     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID4_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID4_PERIPHID_MASK)
11946 /*! @} */
11947 
11948 /*! @name PERIPHID5 - Peripheral ID Register */
11949 /*! @{ */
11950 #define MTB_ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
11951 #define MTB_ROM_PERIPHID5_PERIPHID_SHIFT (0U)
11952 /*! PERIPHID - PERIPHID
11953  */
11954 #define MTB_ROM_PERIPHID5_PERIPHID(x) \
11955     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID5_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID5_PERIPHID_MASK)
11956 /*! @} */
11957 
11958 /*! @name PERIPHID6 - Peripheral ID Register */
11959 /*! @{ */
11960 #define MTB_ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
11961 #define MTB_ROM_PERIPHID6_PERIPHID_SHIFT (0U)
11962 /*! PERIPHID - PERIPHID
11963  */
11964 #define MTB_ROM_PERIPHID6_PERIPHID(x) \
11965     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID6_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID6_PERIPHID_MASK)
11966 /*! @} */
11967 
11968 /*! @name PERIPHID7 - Peripheral ID Register */
11969 /*! @{ */
11970 #define MTB_ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
11971 #define MTB_ROM_PERIPHID7_PERIPHID_SHIFT (0U)
11972 /*! PERIPHID - PERIPHID
11973  */
11974 #define MTB_ROM_PERIPHID7_PERIPHID(x) \
11975     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID7_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID7_PERIPHID_MASK)
11976 /*! @} */
11977 
11978 /*! @name PERIPHID0 - Peripheral ID Register */
11979 /*! @{ */
11980 #define MTB_ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
11981 #define MTB_ROM_PERIPHID0_PERIPHID_SHIFT (0U)
11982 /*! PERIPHID - PERIPHID
11983  */
11984 #define MTB_ROM_PERIPHID0_PERIPHID(x) \
11985     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID0_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID0_PERIPHID_MASK)
11986 /*! @} */
11987 
11988 /*! @name PERIPHID1 - Peripheral ID Register */
11989 /*! @{ */
11990 #define MTB_ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
11991 #define MTB_ROM_PERIPHID1_PERIPHID_SHIFT (0U)
11992 /*! PERIPHID - PERIPHID
11993  */
11994 #define MTB_ROM_PERIPHID1_PERIPHID(x) \
11995     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID1_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID1_PERIPHID_MASK)
11996 /*! @} */
11997 
11998 /*! @name PERIPHID2 - Peripheral ID Register */
11999 /*! @{ */
12000 #define MTB_ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
12001 #define MTB_ROM_PERIPHID2_PERIPHID_SHIFT (0U)
12002 /*! PERIPHID - PERIPHID
12003  */
12004 #define MTB_ROM_PERIPHID2_PERIPHID(x) \
12005     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID2_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID2_PERIPHID_MASK)
12006 /*! @} */
12007 
12008 /*! @name PERIPHID3 - Peripheral ID Register */
12009 /*! @{ */
12010 #define MTB_ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
12011 #define MTB_ROM_PERIPHID3_PERIPHID_SHIFT (0U)
12012 /*! PERIPHID - PERIPHID
12013  */
12014 #define MTB_ROM_PERIPHID3_PERIPHID(x) \
12015     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_PERIPHID3_PERIPHID_SHIFT)) & MTB_ROM_PERIPHID3_PERIPHID_MASK)
12016 /*! @} */
12017 
12018 /*! @name COMPID - Component ID Register */
12019 /*! @{ */
12020 #define MTB_ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
12021 #define MTB_ROM_COMPID_COMPID_SHIFT (0U)
12022 /*! COMPID - Component ID
12023  */
12024 #define MTB_ROM_COMPID_COMPID(x) \
12025     (((uint32_t)(((uint32_t)(x)) << MTB_ROM_COMPID_COMPID_SHIFT)) & MTB_ROM_COMPID_COMPID_MASK)
12026 /*! @} */
12027 
12028 /* The count of MTB_ROM_COMPID */
12029 #define MTB_ROM_COMPID_COUNT (4U)
12030 
12031 /*!
12032  * @}
12033  */ /* end of group MTB_ROM_Register_Masks */
12034 
12035 /* MTB_ROM - Peripheral instance base addresses */
12036 /** Peripheral MTB0_ROM base address */
12037 #define MTB0_ROM_BASE (0xF0002000u)
12038 /** Peripheral MTB0_ROM base pointer */
12039 #define MTB0_ROM ((MTB_ROM_Type *)MTB0_ROM_BASE)
12040 /** Array initializer of MTB_ROM peripheral base addresses */
12041 #define MTB_ROM_BASE_ADDRS \
12042     {                      \
12043         MTB0_ROM_BASE      \
12044     }
12045 /** Array initializer of MTB_ROM peripheral base pointers */
12046 #define MTB_ROM_BASE_PTRS \
12047     {                     \
12048         MTB0_ROM          \
12049     }
12050 
12051 /*!
12052  * @}
12053  */ /* end of group MTB_ROM_Peripheral_Access_Layer */
12054 
12055 /* ----------------------------------------------------------------------------
12056    -- NV Peripheral Access Layer
12057    ---------------------------------------------------------------------------- */
12058 
12059 /*!
12060  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
12061  * @{
12062  */
12063 
12064 /** NV - Register Layout Typedef */
12065 typedef struct
12066 {
12067     __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
12068     __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
12069     __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
12070     __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
12071     __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
12072     __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
12073     __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
12074     __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
12075     __I uint8_t FPROT3;   /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
12076     __I uint8_t FPROT2;   /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
12077     __I uint8_t FPROT1;   /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
12078     __I uint8_t FPROT0;   /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
12079     __I uint8_t FSEC;     /**< Non-volatile Flash Security Register, offset: 0xC */
12080     __I uint8_t FOPT;     /**< Non-volatile Flash Option Register, offset: 0xD */
12081 } NV_Type;
12082 
12083 /* ----------------------------------------------------------------------------
12084    -- NV Register Masks
12085    ---------------------------------------------------------------------------- */
12086 
12087 /*!
12088  * @addtogroup NV_Register_Masks NV Register Masks
12089  * @{
12090  */
12091 
12092 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
12093 /*! @{ */
12094 #define NV_BACKKEY3_KEY_MASK (0xFFU)
12095 #define NV_BACKKEY3_KEY_SHIFT (0U)
12096 /*! KEY - Backdoor Comparison Key.
12097  */
12098 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
12099 /*! @} */
12100 
12101 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
12102 /*! @{ */
12103 #define NV_BACKKEY2_KEY_MASK (0xFFU)
12104 #define NV_BACKKEY2_KEY_SHIFT (0U)
12105 /*! KEY - Backdoor Comparison Key.
12106  */
12107 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
12108 /*! @} */
12109 
12110 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
12111 /*! @{ */
12112 #define NV_BACKKEY1_KEY_MASK (0xFFU)
12113 #define NV_BACKKEY1_KEY_SHIFT (0U)
12114 /*! KEY - Backdoor Comparison Key.
12115  */
12116 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
12117 /*! @} */
12118 
12119 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
12120 /*! @{ */
12121 #define NV_BACKKEY0_KEY_MASK (0xFFU)
12122 #define NV_BACKKEY0_KEY_SHIFT (0U)
12123 /*! KEY - Backdoor Comparison Key.
12124  */
12125 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
12126 /*! @} */
12127 
12128 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
12129 /*! @{ */
12130 #define NV_BACKKEY7_KEY_MASK (0xFFU)
12131 #define NV_BACKKEY7_KEY_SHIFT (0U)
12132 /*! KEY - Backdoor Comparison Key.
12133  */
12134 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
12135 /*! @} */
12136 
12137 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
12138 /*! @{ */
12139 #define NV_BACKKEY6_KEY_MASK (0xFFU)
12140 #define NV_BACKKEY6_KEY_SHIFT (0U)
12141 /*! KEY - Backdoor Comparison Key.
12142  */
12143 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
12144 /*! @} */
12145 
12146 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
12147 /*! @{ */
12148 #define NV_BACKKEY5_KEY_MASK (0xFFU)
12149 #define NV_BACKKEY5_KEY_SHIFT (0U)
12150 /*! KEY - Backdoor Comparison Key.
12151  */
12152 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
12153 /*! @} */
12154 
12155 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
12156 /*! @{ */
12157 #define NV_BACKKEY4_KEY_MASK (0xFFU)
12158 #define NV_BACKKEY4_KEY_SHIFT (0U)
12159 /*! KEY - Backdoor Comparison Key.
12160  */
12161 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
12162 /*! @} */
12163 
12164 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
12165 /*! @{ */
12166 #define NV_FPROT3_PROT_MASK (0xFFU)
12167 #define NV_FPROT3_PROT_SHIFT (0U)
12168 /*! PROT - P-Flash Region Protect
12169  */
12170 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
12171 /*! @} */
12172 
12173 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
12174 /*! @{ */
12175 #define NV_FPROT2_PROT_MASK (0xFFU)
12176 #define NV_FPROT2_PROT_SHIFT (0U)
12177 /*! PROT - P-Flash Region Protect
12178  */
12179 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
12180 /*! @} */
12181 
12182 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
12183 /*! @{ */
12184 #define NV_FPROT1_PROT_MASK (0xFFU)
12185 #define NV_FPROT1_PROT_SHIFT (0U)
12186 /*! PROT - P-Flash Region Protect
12187  */
12188 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
12189 /*! @} */
12190 
12191 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
12192 /*! @{ */
12193 #define NV_FPROT0_PROT_MASK (0xFFU)
12194 #define NV_FPROT0_PROT_SHIFT (0U)
12195 /*! PROT - P-Flash Region Protect
12196  */
12197 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
12198 /*! @} */
12199 
12200 /*! @name FSEC - Non-volatile Flash Security Register */
12201 /*! @{ */
12202 #define NV_FSEC_SEC_MASK (0x3U)
12203 #define NV_FSEC_SEC_SHIFT (0U)
12204 /*! SEC - Flash Security
12205  *  0b10..MCU security status is unsecure
12206  *  0b11..MCU security status is secure
12207  */
12208 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
12209 #define NV_FSEC_FSLACC_MASK (0xCU)
12210 #define NV_FSEC_FSLACC_SHIFT (2U)
12211 /*! FSLACC - Freescale Failure Analysis Access Code
12212  *  0b10..Freescale factory access denied
12213  *  0b11..Freescale factory access granted
12214  */
12215 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
12216 #define NV_FSEC_MEEN_MASK (0x30U)
12217 #define NV_FSEC_MEEN_SHIFT (4U)
12218 /*! MEEN
12219  *  0b10..Mass erase is disabled
12220  *  0b11..Mass erase is enabled
12221  */
12222 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
12223 #define NV_FSEC_KEYEN_MASK (0xC0U)
12224 #define NV_FSEC_KEYEN_SHIFT (6U)
12225 /*! KEYEN - Backdoor Key Security Enable
12226  *  0b10..Backdoor key access enabled
12227  *  0b11..Backdoor key access disabled
12228  */
12229 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
12230 /*! @} */
12231 
12232 /*! @name FOPT - Non-volatile Flash Option Register */
12233 /*! @{ */
12234 #define NV_FOPT_LPBOOT0_MASK (0x1U)
12235 #define NV_FOPT_LPBOOT0_SHIFT (0U)
12236 /*! LPBOOT0
12237  *  0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when
12238  * LPBOOT1=1. 0b1..Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when
12239  * LPBOOT1=1.
12240  */
12241 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
12242 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
12243 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
12244 /*! BOOTPIN_OPT
12245  *  0b0..Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI
12246  * pin 0b1..Boot source configured by FOPT (BOOTSRC_SEL) bits
12247  */
12248 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
12249 #define NV_FOPT_NMI_DIS_MASK (0x4U)
12250 #define NV_FOPT_NMI_DIS_SHIFT (2U)
12251 /*! NMI_DIS
12252  *  0b0..NMI interrupts are always blocked
12253  *  0b1..NMI_b pin/interrupts reset default to enabled
12254  */
12255 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
12256 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
12257 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
12258 /*! RESET_PIN_CFG
12259  *  0b0..RESET pin is disabled following a POR and cannot be enabled as reset function
12260  *  0b1..RESET_b pin is dedicated
12261  */
12262 #define NV_FOPT_RESET_PIN_CFG(x) \
12263     (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
12264 #define NV_FOPT_LPBOOT1_MASK (0x10U)
12265 #define NV_FOPT_LPBOOT1_SHIFT (4U)
12266 /*! LPBOOT1
12267  *  0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when
12268  * LPBOOT0=1. 0b1..Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when
12269  * LPBOOT0=1.
12270  */
12271 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
12272 #define NV_FOPT_FAST_INIT_MASK (0x20U)
12273 #define NV_FOPT_FAST_INIT_SHIFT (5U)
12274 /*! FAST_INIT
12275  *  0b0..Slower initialization
12276  *  0b1..Fast Initialization
12277  */
12278 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
12279 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
12280 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
12281 /*! BOOTSRC_SEL - Boot source selection
12282  *  0b00..Boot from Flash
12283  *  0b10..Boot from ROM
12284  *  0b11..Boot from ROM
12285  */
12286 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
12287 /*! @} */
12288 
12289 /*!
12290  * @}
12291  */ /* end of group NV_Register_Masks */
12292 
12293 /* NV - Peripheral instance base addresses */
12294 /** Peripheral FTFA_FlashConfig base address */
12295 #define FTFA_FlashConfig_BASE (0x400u)
12296 /** Peripheral FTFA_FlashConfig base pointer */
12297 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
12298 /** Array initializer of NV peripheral base addresses */
12299 #define NV_BASE_ADDRS         \
12300     {                         \
12301         FTFA_FlashConfig_BASE \
12302     }
12303 /** Array initializer of NV peripheral base pointers */
12304 #define NV_BASE_PTRS     \
12305     {                    \
12306         FTFA_FlashConfig \
12307     }
12308 
12309 /*!
12310  * @}
12311  */ /* end of group NV_Peripheral_Access_Layer */
12312 
12313 /* ----------------------------------------------------------------------------
12314    -- PCC Peripheral Access Layer
12315    ---------------------------------------------------------------------------- */
12316 
12317 /*!
12318  * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer
12319  * @{
12320  */
12321 
12322 /** PCC - Register Layout Typedef */
12323 typedef struct
12324 {
12325     __IO uint32_t CLKCFG[121]; /**< PCC CLKCFG Register, array offset: 0x0, array step: 0x4 */
12326 } PCC_Type;
12327 
12328 /* ----------------------------------------------------------------------------
12329    -- PCC Register Masks
12330    ---------------------------------------------------------------------------- */
12331 
12332 /*!
12333  * @addtogroup PCC_Register_Masks PCC Register Masks
12334  * @{
12335  */
12336 
12337 /*! @name CLKCFG - PCC CLKCFG Register */
12338 /*! @{ */
12339 #define PCC_CLKCFG_PCD_MASK (0x7U)
12340 #define PCC_CLKCFG_PCD_SHIFT (0U)
12341 /*! PCD - Peripheral Clock Divider Select
12342  *  0b000..Divide by 1 (pass-through, no clock divide).
12343  *  0b001..Divide by 2.
12344  *  0b010..Divide by 3.
12345  *  0b011..Divide by 4.
12346  *  0b100..Divide by 5.
12347  *  0b101..Divide by 6.
12348  *  0b110..Divide by 7.
12349  *  0b111..Divide by 8.
12350  */
12351 #define PCC_CLKCFG_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK)
12352 #define PCC_CLKCFG_FRAC_MASK (0x8U)
12353 #define PCC_CLKCFG_FRAC_SHIFT (3U)
12354 /*! FRAC - Peripheral Clock Divider Fraction
12355  *  0b0..Fractional value is 0.
12356  *  0b1..Fractional value is 1.
12357  */
12358 #define PCC_CLKCFG_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK)
12359 #define PCC_CLKCFG_PCS_MASK (0x7000000U)
12360 #define PCC_CLKCFG_PCS_SHIFT (24U)
12361 /*! PCS - Peripheral Clock Source Select
12362  *  0b000..Clock is off (or test clock is enabled).
12363  *  0b001..OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
12364  *  0b010..SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
12365  *  0b011..SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
12366  *  0b100..Reserved.
12367  *  0b101..Reserved.
12368  *  0b110..SCGPCLK System PLL clock (scg_spll_slow_clk).
12369  *  0b111..Reserved.
12370  */
12371 #define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK)
12372 #define PCC_CLKCFG_INUSE_MASK (0x20000000U)
12373 #define PCC_CLKCFG_INUSE_SHIFT (29U)
12374 /*! INUSE - Clock Gate Control
12375  *  0b0..Another core is not using this peripheral.
12376  *  0b1..Another core is using this peripheral. Software cannot modify the existing clocking configuration.
12377  */
12378 #define PCC_CLKCFG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK)
12379 #define PCC_CLKCFG_CGC_MASK (0x40000000U)
12380 #define PCC_CLKCFG_CGC_SHIFT (30U)
12381 /*! CGC - Clock Gate Control
12382  *  0b0..Clock disabled
12383  *  0b1..Clock enabled
12384  */
12385 #define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK)
12386 #define PCC_CLKCFG_PR_MASK (0x80000000U)
12387 #define PCC_CLKCFG_PR_SHIFT (31U)
12388 /*! PR - Enable
12389  *  0b0..Peripheral is not present.
12390  *  0b1..Peripheral is present.
12391  */
12392 #define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK)
12393 /*! @} */
12394 
12395 /* The count of PCC_CLKCFG */
12396 #define PCC_CLKCFG_COUNT (121U)
12397 
12398 /*!
12399  * @}
12400  */ /* end of group PCC_Register_Masks */
12401 
12402 /* PCC - Peripheral instance base addresses */
12403 /** Peripheral PCC0 base address */
12404 #define PCC0_BASE (0x4007A000u)
12405 /** Peripheral PCC0 base pointer */
12406 #define PCC0 ((PCC_Type *)PCC0_BASE)
12407 /** Peripheral PCC1 base address */
12408 #define PCC1_BASE (0x400FA000u)
12409 /** Peripheral PCC1 base pointer */
12410 #define PCC1 ((PCC_Type *)PCC1_BASE)
12411 /** Array initializer of PCC peripheral base addresses */
12412 #define PCC_BASE_ADDRS       \
12413     {                        \
12414         PCC0_BASE, PCC1_BASE \
12415     }
12416 /** Array initializer of PCC peripheral base pointers */
12417 #define PCC_BASE_PTRS \
12418     {                 \
12419         PCC0, PCC1    \
12420     }
12421 #define PCC_INSTANCE_MASK 0xF
12422 #define PCC_INSTANCE_SHIFT 12
12423 #define PCC_PERIPHERAL_MASK 0xFFF
12424 #define PCC_PERIPHERAL_SHIFT 0
12425 #define PCC_INSTANCE_0 0
12426 #define PCC_INSTANCE_1 1
12427 
12428 #define PCC_DMA0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8)
12429 #define PCC_FLASH_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 32)
12430 #define PCC_DMAMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33)
12431 #define PCC_INTMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36)
12432 #define PCC_TPM2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46)
12433 #define PCC_LPIT0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48)
12434 #define PCC_LPTMR0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 52)
12435 #define PCC_RTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56)
12436 #define PCC_LPSPI2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62)
12437 #define PCC_LPI2C2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66)
12438 #define PCC_LPUART2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70)
12439 #define PCC_EMVSIM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 78)
12440 #define PCC_USB0FS_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 85)
12441 #define PCC_PORTA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 90)
12442 #define PCC_PORTB_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 91)
12443 #define PCC_PORTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 92)
12444 #define PCC_PORTD_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 93)
12445 #define PCC_PORTE_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 94)
12446 #define PCC_TSI0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 98)
12447 #define PCC_ADC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 102)
12448 #define PCC_DAC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 106)
12449 #define PCC_CMP0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 110)
12450 #define PCC_VREF_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 114)
12451 #define PCC_CRC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 120)
12452 #define PCC_DMA0 (PCC0->CLKCFG[8])
12453 #define PCC_FLASH (PCC0->CLKCFG[32])
12454 #define PCC_DMAMUX0 (PCC0->CLKCFG[33])
12455 #define PCC_INTMUX0 (PCC0->CLKCFG[36])
12456 #define PCC_TPM2 (PCC0->CLKCFG[46])
12457 #define PCC_LPIT0 (PCC0->CLKCFG[48])
12458 #define PCC_LPTMR0 (PCC0->CLKCFG[52])
12459 #define PCC_RTC (PCC0->CLKCFG[56])
12460 #define PCC_LPSPI2 (PCC0->CLKCFG[62])
12461 #define PCC_LPI2C2 (PCC0->CLKCFG[66])
12462 #define PCC_LPUART2 (PCC0->CLKCFG[70])
12463 #define PCC_EMVSIM0 (PCC0->CLKCFG[78])
12464 #define PCC_USB0FS (PCC0->CLKCFG[85])
12465 #define PCC_PORTA (PCC0->CLKCFG[90])
12466 #define PCC_PORTB (PCC0->CLKCFG[91])
12467 #define PCC_PORTC (PCC0->CLKCFG[92])
12468 #define PCC_PORTD (PCC0->CLKCFG[93])
12469 #define PCC_PORTE (PCC0->CLKCFG[94])
12470 #define PCC_TSI0 (PCC0->CLKCFG[98])
12471 #define PCC_ADC0 (PCC0->CLKCFG[102])
12472 #define PCC_DAC0 (PCC0->CLKCFG[106])
12473 #define PCC_CMP0 (PCC0->CLKCFG[110])
12474 #define PCC_VREF (PCC0->CLKCFG[114])
12475 #define PCC_CRC (PCC0->CLKCFG[120])
12476 
12477 #define PCC_TRNG_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37)
12478 #define PCC_TPM0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 44)
12479 #define PCC_TPM1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45)
12480 #define PCC_LPTMR1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53)
12481 #define PCC_LPSPI0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60)
12482 #define PCC_LPSPI1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61)
12483 #define PCC_LPI2C0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64)
12484 #define PCC_LPI2C1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65)
12485 #define PCC_LPUART0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68)
12486 #define PCC_LPUART1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69)
12487 #define PCC_FLEXIO0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74)
12488 #define PCC_PORTM_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 96)
12489 #define PCC_CMP1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 111)
12490 #define PCC_TRNG (PCC1->CLKCFG[37])
12491 #define PCC_TPM0 (PCC1->CLKCFG[44])
12492 #define PCC_TPM1 (PCC1->CLKCFG[45])
12493 #define PCC_LPTMR1 (PCC1->CLKCFG[53])
12494 #define PCC_LPSPI0 (PCC1->CLKCFG[60])
12495 #define PCC_LPSPI1 (PCC1->CLKCFG[61])
12496 #define PCC_LPI2C0 (PCC1->CLKCFG[64])
12497 #define PCC_LPI2C1 (PCC1->CLKCFG[65])
12498 #define PCC_LPUART0 (PCC1->CLKCFG[68])
12499 #define PCC_LPUART1 (PCC1->CLKCFG[69])
12500 #define PCC_FLEXIO0 (PCC1->CLKCFG[74])
12501 #define PCC_CMP1 (PCC1->CLKCFG[111])
12502 
12503 /*!
12504  * @}
12505  */ /* end of group PCC_Peripheral_Access_Layer */
12506 
12507 /* ----------------------------------------------------------------------------
12508    -- PMC Peripheral Access Layer
12509    ---------------------------------------------------------------------------- */
12510 
12511 /*!
12512  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
12513  * @{
12514  */
12515 
12516 /** PMC - Register Layout Typedef */
12517 typedef struct
12518 {
12519     __I uint32_t VERID;   /**< Version ID register, offset: 0x0 */
12520     __I uint32_t PARAM;   /**< Parameter register, offset: 0x4 */
12521     __IO uint32_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x8 */
12522     __IO uint32_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0xC */
12523     __IO uint32_t REGSC;  /**< Regulator Status And Control register, offset: 0x10 */
12524     uint8_t RESERVED_0[32];
12525     __IO uint32_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0x34 */
12526 } PMC_Type;
12527 
12528 /* ----------------------------------------------------------------------------
12529    -- PMC Register Masks
12530    ---------------------------------------------------------------------------- */
12531 
12532 /*!
12533  * @addtogroup PMC_Register_Masks PMC Register Masks
12534  * @{
12535  */
12536 
12537 /*! @name VERID - Version ID register */
12538 /*! @{ */
12539 #define PMC_VERID_FEATURE_MASK (0xFFFFU)
12540 #define PMC_VERID_FEATURE_SHIFT (0U)
12541 /*! FEATURE - Feature Specification Number
12542  *  0b0000000000000000..Standard features implemented
12543  */
12544 #define PMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_FEATURE_SHIFT)) & PMC_VERID_FEATURE_MASK)
12545 #define PMC_VERID_MINOR_MASK (0xFF0000U)
12546 #define PMC_VERID_MINOR_SHIFT (16U)
12547 /*! MINOR - Minor Version Number
12548  */
12549 #define PMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MINOR_SHIFT)) & PMC_VERID_MINOR_MASK)
12550 #define PMC_VERID_MAJOR_MASK (0xFF000000U)
12551 #define PMC_VERID_MAJOR_SHIFT (24U)
12552 /*! MAJOR - Major Version Number
12553  */
12554 #define PMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MAJOR_SHIFT)) & PMC_VERID_MAJOR_MASK)
12555 /*! @} */
12556 
12557 /*! @name PARAM - Parameter register */
12558 /*! @{ */
12559 #define PMC_PARAM_VLPOE_MASK (0x1U)
12560 #define PMC_PARAM_VLPOE_SHIFT (0U)
12561 /*! VLPOE - VLPO Enable
12562  */
12563 #define PMC_PARAM_VLPOE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PARAM_VLPOE_SHIFT)) & PMC_PARAM_VLPOE_MASK)
12564 #define PMC_PARAM_HVDE_MASK (0x2U)
12565 #define PMC_PARAM_HVDE_SHIFT (1U)
12566 /*! HVDE - HVD Enabled
12567  */
12568 #define PMC_PARAM_HVDE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PARAM_HVDE_SHIFT)) & PMC_PARAM_HVDE_MASK)
12569 /*! @} */
12570 
12571 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
12572 /*! @{ */
12573 #define PMC_LVDSC1_LVDV_MASK (0x3U)
12574 #define PMC_LVDSC1_LVDV_SHIFT (0U)
12575 /*! LVDV - Low-Voltage Detect Voltage Select
12576  *  0b00..Low trip point selected (V LVD = V LVDL )
12577  *  0b01..High trip point selected (V LVD = V LVDH )
12578  *  0b10..Reserved
12579  *  0b11..Reserved
12580  */
12581 #define PMC_LVDSC1_LVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
12582 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
12583 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
12584 /*! LVDRE - Low-Voltage Detect Reset Enable
12585  *  0b0..LVDF does not generate hardware resets
12586  *  0b1..Force an MCU reset when LVDF = 1
12587  */
12588 #define PMC_LVDSC1_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
12589 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
12590 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
12591 /*! LVDIE - Low-Voltage Detect Interrupt Enable
12592  *  0b0..Hardware interrupt disabled (use polling)
12593  *  0b1..Request a hardware interrupt when LVDF = 1
12594  */
12595 #define PMC_LVDSC1_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
12596 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
12597 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
12598 /*! LVDACK - Low-Voltage Detect Acknowledge
12599  */
12600 #define PMC_LVDSC1_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
12601 #define PMC_LVDSC1_LVDF_MASK (0x80U)
12602 #define PMC_LVDSC1_LVDF_SHIFT (7U)
12603 /*! LVDF - Low-Voltage Detect Flag
12604  *  0b0..Low-voltage event not detected
12605  *  0b1..Low-voltage event detected
12606  */
12607 #define PMC_LVDSC1_LVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
12608 /*! @} */
12609 
12610 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
12611 /*! @{ */
12612 #define PMC_LVDSC2_LVWV_MASK (0x3U)
12613 #define PMC_LVDSC2_LVWV_SHIFT (0U)
12614 /*! LVWV - Low-Voltage Warning Voltage Select
12615  *  0b00..Low trip point selected (VLVW = VLVW1)
12616  *  0b01..Mid 1 trip point selected (VLVW = VLVW2)
12617  *  0b10..Mid 2 trip point selected (VLVW = VLVW3)
12618  *  0b11..High trip point selected (VLVW = VLVW4)
12619  */
12620 #define PMC_LVDSC2_LVWV(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
12621 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
12622 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
12623 /*! LVWIE - Low-Voltage Warning Interrupt Enable
12624  *  0b0..Hardware interrupt disabled (use polling)
12625  *  0b1..Request a hardware interrupt when LVWF = 1
12626  */
12627 #define PMC_LVDSC2_LVWIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
12628 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
12629 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
12630 /*! LVWACK - Low-Voltage Warning Acknowledge
12631  */
12632 #define PMC_LVDSC2_LVWACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
12633 #define PMC_LVDSC2_LVWF_MASK (0x80U)
12634 #define PMC_LVDSC2_LVWF_SHIFT (7U)
12635 /*! LVWF - Low-Voltage Warning Flag
12636  *  0b0..Low-voltage warning event not detected
12637  *  0b1..Low-voltage warning event detected
12638  */
12639 #define PMC_LVDSC2_LVWF(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
12640 /*! @} */
12641 
12642 /*! @name REGSC - Regulator Status And Control register */
12643 /*! @{ */
12644 #define PMC_REGSC_BGBE_MASK (0x1U)
12645 #define PMC_REGSC_BGBE_SHIFT (0U)
12646 /*! BGBE - Bandgap Buffer Enable
12647  *  0b0..Bandgap buffer not enabled
12648  *  0b1..Bandgap buffer enabled
12649  */
12650 #define PMC_REGSC_BGBE(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
12651 #define PMC_REGSC_REGONS_MASK (0x4U)
12652 #define PMC_REGSC_REGONS_SHIFT (2U)
12653 /*! REGONS - Regulator In Run Regulation Status
12654  *  0b0..Regulator is in stop regulation or in transition to/from it
12655  *  0b1..Regulator is in run regulation
12656  */
12657 #define PMC_REGSC_REGONS(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
12658 #define PMC_REGSC_ACKISO_MASK (0x8U)
12659 #define PMC_REGSC_ACKISO_SHIFT (3U)
12660 /*! ACKISO - Acknowledge Isolation
12661  *  0b0..Peripherals and I/O pads are in normal run state.
12662  *  0b1..Certain peripherals and I/O pads are in an isolated and latched state.
12663  */
12664 #define PMC_REGSC_ACKISO(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
12665 #define PMC_REGSC_BGEN_MASK (0x10U)
12666 #define PMC_REGSC_BGEN_SHIFT (4U)
12667 /*! BGEN - Bandgap Enable In VLPx Operation
12668  *  0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
12669  *  0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
12670  */
12671 #define PMC_REGSC_BGEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
12672 #define PMC_REGSC_VLPO_MASK (0x40U)
12673 #define PMC_REGSC_VLPO_SHIFT (6U)
12674 /*! VLPO - VLPx Option
12675  *  0b0..Operating frequencies and SCG clocking modes are restricted during VLPx modes as listed in the Power Management
12676  * chapter. 0b1..If BGEN is also set, operating frequencies and SCG clocking modes are unrestricted during VLPx modes.
12677  *       Note that flash access frequency is still restricted however.
12678  */
12679 #define PMC_REGSC_VLPO(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
12680 /*! @} */
12681 
12682 /*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
12683 /*! @{ */
12684 #define PMC_HVDSC1_HVDV_MASK (0x1U)
12685 #define PMC_HVDSC1_HVDV_SHIFT (0U)
12686 /*! HVDV - High-Voltage Detect Voltage Select
12687  *  0b0..Low trip point selected (V HVD = V HVDL )
12688  *  0b1..High trip point selected (V HVD = V HVDH )
12689  */
12690 #define PMC_HVDSC1_HVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
12691 #define PMC_HVDSC1_HVDRE_MASK (0x10U)
12692 #define PMC_HVDSC1_HVDRE_SHIFT (4U)
12693 /*! HVDRE - High-Voltage Detect Reset Enable
12694  *  0b0..HVDF does not generate hardware resets
12695  *  0b1..Force an MCU reset when HVDF = 1
12696  */
12697 #define PMC_HVDSC1_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
12698 #define PMC_HVDSC1_HVDIE_MASK (0x20U)
12699 #define PMC_HVDSC1_HVDIE_SHIFT (5U)
12700 /*! HVDIE - High-Voltage Detect Interrupt Enable
12701  *  0b0..Hardware interrupt disabled (use polling)
12702  *  0b1..Request a hardware interrupt when HVDF = 1
12703  */
12704 #define PMC_HVDSC1_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
12705 #define PMC_HVDSC1_HVDACK_MASK (0x40U)
12706 #define PMC_HVDSC1_HVDACK_SHIFT (6U)
12707 /*! HVDACK - High-Voltage Detect Acknowledge
12708  */
12709 #define PMC_HVDSC1_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
12710 #define PMC_HVDSC1_HVDF_MASK (0x80U)
12711 #define PMC_HVDSC1_HVDF_SHIFT (7U)
12712 /*! HVDF - High-Voltage Detect Flag
12713  *  0b0..High-voltage event not detected
12714  *  0b1..High-voltage event detected
12715  */
12716 #define PMC_HVDSC1_HVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
12717 /*! @} */
12718 
12719 /*!
12720  * @}
12721  */ /* end of group PMC_Register_Masks */
12722 
12723 /* PMC - Peripheral instance base addresses */
12724 /** Peripheral PMC base address */
12725 #define PMC_BASE (0x4007D000u)
12726 /** Peripheral PMC base pointer */
12727 #define PMC ((PMC_Type *)PMC_BASE)
12728 /** Array initializer of PMC peripheral base addresses */
12729 #define PMC_BASE_ADDRS \
12730     {                  \
12731         PMC_BASE       \
12732     }
12733 /** Array initializer of PMC peripheral base pointers */
12734 #define PMC_BASE_PTRS \
12735     {                 \
12736         PMC           \
12737     }
12738 /** Interrupt vectors for the PMC peripheral type */
12739 #define PMC_IRQS \
12740     {            \
12741         PMC_IRQn \
12742     }
12743 
12744 /*!
12745  * @}
12746  */ /* end of group PMC_Peripheral_Access_Layer */
12747 
12748 /* ----------------------------------------------------------------------------
12749    -- PORT Peripheral Access Layer
12750    ---------------------------------------------------------------------------- */
12751 
12752 /*!
12753  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
12754  * @{
12755  */
12756 
12757 /** PORT - Register Layout Typedef */
12758 typedef struct
12759 {
12760     __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
12761     __O uint32_t GPCLR;    /**< Global Pin Control Low Register, offset: 0x80 */
12762     __O uint32_t GPCHR;    /**< Global Pin Control High Register, offset: 0x84 */
12763     __O uint32_t GICLR;    /**< Global Interrupt Control Low Register, offset: 0x88 */
12764     __O uint32_t GICHR;    /**< Global Interrupt Control High Register, offset: 0x8C */
12765     uint8_t RESERVED_0[16];
12766     __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
12767 } PORT_Type;
12768 
12769 /* ----------------------------------------------------------------------------
12770    -- PORT Register Masks
12771    ---------------------------------------------------------------------------- */
12772 
12773 /*!
12774  * @addtogroup PORT_Register_Masks PORT Register Masks
12775  * @{
12776  */
12777 
12778 /*! @name PCR - Pin Control Register n */
12779 /*! @{ */
12780 #define PORT_PCR_PS_MASK (0x1U)
12781 #define PORT_PCR_PS_SHIFT (0U)
12782 /*! PS - Pull Select
12783  *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
12784  *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
12785  */
12786 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
12787 #define PORT_PCR_PE_MASK (0x2U)
12788 #define PORT_PCR_PE_SHIFT (1U)
12789 /*! PE - Pull Enable
12790  *  0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
12791  *  0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital
12792  * input.
12793  */
12794 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
12795 #define PORT_PCR_SRE_MASK (0x4U)
12796 #define PORT_PCR_SRE_SHIFT (2U)
12797 /*! SRE - Slew Rate Enable
12798  *  0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
12799  *  0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
12800  */
12801 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
12802 #define PORT_PCR_PFE_MASK (0x10U)
12803 #define PORT_PCR_PFE_SHIFT (4U)
12804 /*! PFE - Passive Filter Enable
12805  *  0b0..Passive input filter is disabled on the corresponding pin.
12806  *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input.
12807  *       Refer to the device data sheet for filter characteristics.
12808  */
12809 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
12810 #define PORT_PCR_ODE_MASK (0x20U)
12811 #define PORT_PCR_ODE_SHIFT (5U)
12812 /*! ODE - Open Drain Enable
12813  *  0b0..Open drain output is disabled on the corresponding pin.
12814  *  0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
12815  */
12816 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
12817 #define PORT_PCR_DSE_MASK (0x40U)
12818 #define PORT_PCR_DSE_SHIFT (6U)
12819 /*! DSE - Drive Strength Enable
12820  *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
12821  *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
12822  */
12823 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
12824 #define PORT_PCR_MUX_MASK (0x700U)
12825 #define PORT_PCR_MUX_SHIFT (8U)
12826 /*! MUX - Pin Mux Control
12827  *  0b000..Pin disabled (Alternative 0) (analog).
12828  *  0b001..Alternative 1 (GPIO).
12829  *  0b010..Alternative 2 (chip-specific).
12830  *  0b011..Alternative 3 (chip-specific).
12831  *  0b100..Alternative 4 (chip-specific).
12832  *  0b101..Alternative 5 (chip-specific).
12833  *  0b110..Alternative 6 (chip-specific).
12834  *  0b111..Alternative 7 (chip-specific).
12835  */
12836 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
12837 #define PORT_PCR_LK_MASK (0x8000U)
12838 #define PORT_PCR_LK_SHIFT (15U)
12839 /*! LK - Lock Register
12840  *  0b0..Pin Control Register fields [15:0] are not locked.
12841  *  0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
12842  */
12843 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
12844 #define PORT_PCR_IRQC_MASK (0xF0000U)
12845 #define PORT_PCR_IRQC_SHIFT (16U)
12846 /*! IRQC - Interrupt Configuration
12847  *  0b0000..Interrupt Status Flag (ISF) is disabled.
12848  *  0b0001..ISF flag and DMA request on rising edge.
12849  *  0b0010..ISF flag and DMA request on falling edge.
12850  *  0b0011..ISF flag and DMA request on either edge.
12851  *  0b0100..Reserved.
12852  *  0b0101..Flag sets on rising edge.
12853  *  0b0110..Flag sets on falling edge.
12854  *  0b0111..Flag sets on either edge.
12855  *  0b1000..ISF flag and Interrupt when logic 0.
12856  *  0b1001..ISF flag and Interrupt on rising-edge.
12857  *  0b1010..ISF flag and Interrupt on falling-edge.
12858  *  0b1011..ISF flag and Interrupt on either edge.
12859  *  0b1100..ISF flag and Interrupt when logic 1.
12860  *  0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux,
12861  *          which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are
12862  *          configured, then they are ORed together to create the trigger)]
12863  *  0b1110..Enable active low trigger output, flag is disabled.
12864  *  0b1111..Reserved.
12865  */
12866 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
12867 #define PORT_PCR_ISF_MASK (0x1000000U)
12868 #define PORT_PCR_ISF_SHIFT (24U)
12869 /*! ISF - Interrupt Status Flag
12870  *  0b0..Configured interrupt is not detected.
12871  *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
12872  *       corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise,
12873  * the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt
12874  * and the pin remains asserted, then the flag is set again immediately after it is cleared.
12875  */
12876 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
12877 /*! @} */
12878 
12879 /* The count of PORT_PCR */
12880 #define PORT_PCR_COUNT (32U)
12881 
12882 /*! @name GPCLR - Global Pin Control Low Register */
12883 /*! @{ */
12884 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
12885 #define PORT_GPCLR_GPWD_SHIFT (0U)
12886 /*! GPWD - Global Pin Write Data
12887  */
12888 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
12889 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
12890 #define PORT_GPCLR_GPWE_SHIFT (16U)
12891 /*! GPWE - Global Pin Write Enable
12892  *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
12893  *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
12894  */
12895 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
12896 /*! @} */
12897 
12898 /*! @name GPCHR - Global Pin Control High Register */
12899 /*! @{ */
12900 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
12901 #define PORT_GPCHR_GPWD_SHIFT (0U)
12902 /*! GPWD - Global Pin Write Data
12903  */
12904 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
12905 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
12906 #define PORT_GPCHR_GPWE_SHIFT (16U)
12907 /*! GPWE - Global Pin Write Enable
12908  *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
12909  *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
12910  */
12911 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
12912 /*! @} */
12913 
12914 /*! @name GICLR - Global Interrupt Control Low Register */
12915 /*! @{ */
12916 #define PORT_GICLR_GIWE_MASK (0xFFFFU)
12917 #define PORT_GICLR_GIWE_SHIFT (0U)
12918 /*! GIWE - Global Interrupt Write Enable
12919  *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
12920  *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
12921  */
12922 #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK)
12923 #define PORT_GICLR_GIWD_MASK (0xFFFF0000U)
12924 #define PORT_GICLR_GIWD_SHIFT (16U)
12925 /*! GIWD - Global Interrupt Write Data
12926  */
12927 #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK)
12928 /*! @} */
12929 
12930 /*! @name GICHR - Global Interrupt Control High Register */
12931 /*! @{ */
12932 #define PORT_GICHR_GIWE_MASK (0xFFFFU)
12933 #define PORT_GICHR_GIWE_SHIFT (0U)
12934 /*! GIWE - Global Interrupt Write Enable
12935  *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
12936  *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
12937  */
12938 #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK)
12939 #define PORT_GICHR_GIWD_MASK (0xFFFF0000U)
12940 #define PORT_GICHR_GIWD_SHIFT (16U)
12941 /*! GIWD - Global Interrupt Write Data
12942  */
12943 #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK)
12944 /*! @} */
12945 
12946 /*! @name ISFR - Interrupt Status Flag Register */
12947 /*! @{ */
12948 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
12949 #define PORT_ISFR_ISF_SHIFT (0U)
12950 /*! ISF - Interrupt Status Flag
12951  *  0b00000000000000000000000000000000..Configured interrupt is not detected.
12952  *  0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a
12953  *                                      DMA request, then the corresponding flag will be cleared automatically at
12954  *                                      the completion of the requested DMA transfer. Otherwise, the flag remains set
12955  *                                      until a logic 1 is written to the flag. If the pin is configured for a
12956  *                                      level sensitive interrupt and the pin remains asserted, then the flag is set
12957  *                                      again immediately after it is cleared.
12958  */
12959 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
12960 /*! @} */
12961 
12962 /*!
12963  * @}
12964  */ /* end of group PORT_Register_Masks */
12965 
12966 /* PORT - Peripheral instance base addresses */
12967 /** Peripheral PORTA base address */
12968 #define PORTA_BASE (0x4005A000u)
12969 /** Peripheral PORTA base pointer */
12970 #define PORTA ((PORT_Type *)PORTA_BASE)
12971 /** Peripheral PORTB base address */
12972 #define PORTB_BASE (0x4005B000u)
12973 /** Peripheral PORTB base pointer */
12974 #define PORTB ((PORT_Type *)PORTB_BASE)
12975 /** Peripheral PORTC base address */
12976 #define PORTC_BASE (0x4005C000u)
12977 /** Peripheral PORTC base pointer */
12978 #define PORTC ((PORT_Type *)PORTC_BASE)
12979 /** Peripheral PORTD base address */
12980 #define PORTD_BASE (0x4005D000u)
12981 /** Peripheral PORTD base pointer */
12982 #define PORTD ((PORT_Type *)PORTD_BASE)
12983 /** Peripheral PORTE base address */
12984 #define PORTE_BASE (0x4005E000u)
12985 /** Peripheral PORTE base pointer */
12986 #define PORTE ((PORT_Type *)PORTE_BASE)
12987 /** Array initializer of PORT peripheral base addresses */
12988 #define PORT_BASE_ADDRS                                            \
12989     {                                                              \
12990         PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE \
12991     }
12992 /** Array initializer of PORT peripheral base pointers */
12993 #define PORT_BASE_PTRS                    \
12994     {                                     \
12995         PORTA, PORTB, PORTC, PORTD, PORTE \
12996     }
12997 /** Interrupt vectors for the PORT peripheral type */
12998 #define PORT_IRQS                                                  \
12999     {                                                              \
13000         PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn \
13001     }
13002 
13003 /*!
13004  * @}
13005  */ /* end of group PORT_Peripheral_Access_Layer */
13006 
13007 /* ----------------------------------------------------------------------------
13008    -- RCM Peripheral Access Layer
13009    ---------------------------------------------------------------------------- */
13010 
13011 /*!
13012  * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
13013  * @{
13014  */
13015 
13016 /** RCM - Register Layout Typedef */
13017 typedef struct
13018 {
13019     __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
13020     __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
13021     __I uint32_t SRS;   /**< System Reset Status Register, offset: 0x8 */
13022     __IO uint32_t RPC;  /**< Reset Pin Control register, offset: 0xC */
13023     __IO uint32_t MR;   /**< Mode Register, offset: 0x10 */
13024     __IO uint32_t FM;   /**< Force Mode Register, offset: 0x14 */
13025     __IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */
13026     __IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */
13027 } RCM_Type;
13028 
13029 /* ----------------------------------------------------------------------------
13030    -- RCM Register Masks
13031    ---------------------------------------------------------------------------- */
13032 
13033 /*!
13034  * @addtogroup RCM_Register_Masks RCM Register Masks
13035  * @{
13036  */
13037 
13038 /*! @name VERID - Version ID Register */
13039 /*! @{ */
13040 #define RCM_VERID_FEATURE_MASK (0xFFFFU)
13041 #define RCM_VERID_FEATURE_SHIFT (0U)
13042 /*! FEATURE - Feature Specification Number
13043  *  0b0000000000000011..Standard feature set.
13044  */
13045 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_FEATURE_SHIFT)) & RCM_VERID_FEATURE_MASK)
13046 #define RCM_VERID_MINOR_MASK (0xFF0000U)
13047 #define RCM_VERID_MINOR_SHIFT (16U)
13048 /*! MINOR - Minor Version Number
13049  */
13050 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MINOR_SHIFT)) & RCM_VERID_MINOR_MASK)
13051 #define RCM_VERID_MAJOR_MASK (0xFF000000U)
13052 #define RCM_VERID_MAJOR_SHIFT (24U)
13053 /*! MAJOR - Major Version Number
13054  */
13055 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MAJOR_SHIFT)) & RCM_VERID_MAJOR_MASK)
13056 /*! @} */
13057 
13058 /*! @name PARAM - Parameter Register */
13059 /*! @{ */
13060 #define RCM_PARAM_EWAKEUP_MASK (0x1U)
13061 #define RCM_PARAM_EWAKEUP_SHIFT (0U)
13062 /*! EWAKEUP - Existence of SRS[WAKEUP] status indication feature
13063  *  0b0..The feature is not available.
13064  *  0b1..The feature is available.
13065  */
13066 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EWAKEUP_SHIFT)) & RCM_PARAM_EWAKEUP_MASK)
13067 #define RCM_PARAM_ELVD_MASK (0x2U)
13068 #define RCM_PARAM_ELVD_SHIFT (1U)
13069 /*! ELVD - Existence of SRS[LVD] status indication feature
13070  *  0b0..The feature is not available.
13071  *  0b1..The feature is available.
13072  */
13073 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELVD_SHIFT)) & RCM_PARAM_ELVD_MASK)
13074 #define RCM_PARAM_ELOC_MASK (0x4U)
13075 #define RCM_PARAM_ELOC_SHIFT (2U)
13076 /*! ELOC - Existence of SRS[LOC] status indication feature
13077  *  0b0..The feature is not available.
13078  *  0b1..The feature is available.
13079  */
13080 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOC_SHIFT)) & RCM_PARAM_ELOC_MASK)
13081 #define RCM_PARAM_ELOL_MASK (0x8U)
13082 #define RCM_PARAM_ELOL_SHIFT (3U)
13083 /*! ELOL - Existence of SRS[LOL] status indication feature
13084  *  0b0..The feature is not available.
13085  *  0b1..The feature is available.
13086  */
13087 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOL_SHIFT)) & RCM_PARAM_ELOL_MASK)
13088 #define RCM_PARAM_ECMU_LOC_MASK (0x10U)
13089 #define RCM_PARAM_ECMU_LOC_SHIFT (4U)
13090 /*! ECMU_LOC - Existence of SRS[CMU_LOC] status indication feature
13091  *  0b0..The feature is not available.
13092  *  0b1..The feature is available.
13093  */
13094 #define RCM_PARAM_ECMU_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ECMU_LOC_SHIFT)) & RCM_PARAM_ECMU_LOC_MASK)
13095 #define RCM_PARAM_EWDOG_MASK (0x20U)
13096 #define RCM_PARAM_EWDOG_SHIFT (5U)
13097 /*! EWDOG - Existence of SRS[WDOG] status indication feature
13098  *  0b0..The feature is not available.
13099  *  0b1..The feature is available.
13100  */
13101 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EWDOG_SHIFT)) & RCM_PARAM_EWDOG_MASK)
13102 #define RCM_PARAM_EPIN_MASK (0x40U)
13103 #define RCM_PARAM_EPIN_SHIFT (6U)
13104 /*! EPIN - Existence of SRS[PIN] status indication feature
13105  *  0b0..The feature is not available.
13106  *  0b1..The feature is available.
13107  */
13108 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPIN_SHIFT)) & RCM_PARAM_EPIN_MASK)
13109 #define RCM_PARAM_EPOR_MASK (0x80U)
13110 #define RCM_PARAM_EPOR_SHIFT (7U)
13111 /*! EPOR - Existence of SRS[POR] status indication feature
13112  *  0b0..The feature is not available.
13113  *  0b1..The feature is available.
13114  */
13115 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPOR_SHIFT)) & RCM_PARAM_EPOR_MASK)
13116 #define RCM_PARAM_EJTAG_MASK (0x100U)
13117 #define RCM_PARAM_EJTAG_SHIFT (8U)
13118 /*! EJTAG - Existence of SRS[JTAG] status indication feature
13119  *  0b0..The feature is not available.
13120  *  0b1..The feature is available.
13121  */
13122 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EJTAG_SHIFT)) & RCM_PARAM_EJTAG_MASK)
13123 #define RCM_PARAM_ELOCKUP_MASK (0x200U)
13124 #define RCM_PARAM_ELOCKUP_SHIFT (9U)
13125 /*! ELOCKUP - Existence of SRS[LOCKUP] status indication feature
13126  *  0b0..The feature is not available.
13127  *  0b1..The feature is available.
13128  */
13129 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOCKUP_SHIFT)) & RCM_PARAM_ELOCKUP_MASK)
13130 #define RCM_PARAM_ESW_MASK (0x400U)
13131 #define RCM_PARAM_ESW_SHIFT (10U)
13132 /*! ESW - Existence of SRS[SW] status indication feature
13133  *  0b0..The feature is not available.
13134  *  0b1..The feature is available.
13135  */
13136 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESW_SHIFT)) & RCM_PARAM_ESW_MASK)
13137 #define RCM_PARAM_EMDM_AP_MASK (0x800U)
13138 #define RCM_PARAM_EMDM_AP_SHIFT (11U)
13139 /*! EMDM_AP - Existence of SRS[MDM_AP] status indication feature
13140  *  0b0..The feature is not available.
13141  *  0b1..The feature is available.
13142  */
13143 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EMDM_AP_SHIFT)) & RCM_PARAM_EMDM_AP_MASK)
13144 #define RCM_PARAM_ESACKERR_MASK (0x2000U)
13145 #define RCM_PARAM_ESACKERR_SHIFT (13U)
13146 /*! ESACKERR - Existence of SRS[SACKERR] status indication feature
13147  *  0b0..The feature is not available.
13148  *  0b1..The feature is available.
13149  */
13150 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESACKERR_SHIFT)) & RCM_PARAM_ESACKERR_MASK)
13151 #define RCM_PARAM_ETAMPER_MASK (0x8000U)
13152 #define RCM_PARAM_ETAMPER_SHIFT (15U)
13153 /*! ETAMPER - Existence of SRS[TAMPER] status indication feature
13154  *  0b0..The feature is not available.
13155  *  0b1..The feature is available.
13156  */
13157 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ETAMPER_SHIFT)) & RCM_PARAM_ETAMPER_MASK)
13158 #define RCM_PARAM_ECORE1_MASK (0x10000U)
13159 #define RCM_PARAM_ECORE1_SHIFT (16U)
13160 /*! ECORE1 - Existence of SRS[CORE1] status indication feature
13161  *  0b0..The feature is not available.
13162  *  0b1..The feature is available.
13163  */
13164 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ECORE1_SHIFT)) & RCM_PARAM_ECORE1_MASK)
13165 /*! @} */
13166 
13167 /*! @name SRS - System Reset Status Register */
13168 /*! @{ */
13169 #define RCM_SRS_WAKEUP_MASK (0x1U)
13170 #define RCM_SRS_WAKEUP_SHIFT (0U)
13171 /*! WAKEUP - VLLS Wakeup Reset
13172  *  0b0..Reset not caused by wakeup from VLLS mode.
13173  *  0b1..Reset caused by wakeup from VLLS mode.
13174  */
13175 #define RCM_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WAKEUP_SHIFT)) & RCM_SRS_WAKEUP_MASK)
13176 #define RCM_SRS_LVD_MASK (0x2U)
13177 #define RCM_SRS_LVD_SHIFT (1U)
13178 /*! LVD - Low-Voltage Detect Reset or High-Voltage Detect Reset
13179  *  0b0..Reset not caused by LVD trip, HVD trip or POR
13180  *  0b1..Reset caused by LVD trip, HVD trip or POR
13181  */
13182 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LVD_SHIFT)) & RCM_SRS_LVD_MASK)
13183 #define RCM_SRS_LOC_MASK (0x4U)
13184 #define RCM_SRS_LOC_SHIFT (2U)
13185 /*! LOC - Loss-of-Clock Reset
13186  *  0b0..Reset not caused by a loss of external clock.
13187  *  0b1..Reset caused by a loss of external clock.
13188  */
13189 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOC_SHIFT)) & RCM_SRS_LOC_MASK)
13190 #define RCM_SRS_LOL_MASK (0x8U)
13191 #define RCM_SRS_LOL_SHIFT (3U)
13192 /*! LOL - Loss-of-Lock Reset
13193  *  0b0..Reset not caused by a loss of lock in the PLL/FLL
13194  *  0b1..Reset caused by a loss of lock in the PLL/FLL
13195  */
13196 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOL_SHIFT)) & RCM_SRS_LOL_MASK)
13197 #define RCM_SRS_WDOG_MASK (0x20U)
13198 #define RCM_SRS_WDOG_SHIFT (5U)
13199 /*! WDOG - Watchdog
13200  *  0b0..Reset not caused by watchdog timeout
13201  *  0b1..Reset caused by watchdog timeout
13202  */
13203 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WDOG_SHIFT)) & RCM_SRS_WDOG_MASK)
13204 #define RCM_SRS_PIN_MASK (0x40U)
13205 #define RCM_SRS_PIN_SHIFT (6U)
13206 /*! PIN - External Reset Pin
13207  *  0b0..Reset not caused by external reset pin
13208  *  0b1..Reset caused by external reset pin
13209  */
13210 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_PIN_SHIFT)) & RCM_SRS_PIN_MASK)
13211 #define RCM_SRS_POR_MASK (0x80U)
13212 #define RCM_SRS_POR_SHIFT (7U)
13213 /*! POR - Power-On Reset
13214  *  0b0..Reset not caused by POR
13215  *  0b1..Reset caused by POR
13216  */
13217 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_POR_SHIFT)) & RCM_SRS_POR_MASK)
13218 #define RCM_SRS_LOCKUP_MASK (0x200U)
13219 #define RCM_SRS_LOCKUP_SHIFT (9U)
13220 /*! LOCKUP - Core Lockup
13221  *  0b0..Reset not caused by core LOCKUP event
13222  *  0b1..Reset caused by core LOCKUP event
13223  */
13224 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOCKUP_SHIFT)) & RCM_SRS_LOCKUP_MASK)
13225 #define RCM_SRS_SW_MASK (0x400U)
13226 #define RCM_SRS_SW_SHIFT (10U)
13227 /*! SW - Software
13228  *  0b0..Reset not caused by software setting of SYSRESETREQ bit
13229  *  0b1..Reset caused by software setting of SYSRESETREQ bit
13230  */
13231 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SW_SHIFT)) & RCM_SRS_SW_MASK)
13232 #define RCM_SRS_MDM_AP_MASK (0x800U)
13233 #define RCM_SRS_MDM_AP_SHIFT (11U)
13234 /*! MDM_AP - MDM-AP System Reset Request
13235  *  0b0..Reset was not caused by host debugger system setting of the System Reset Request bit
13236  *  0b1..Reset was caused by host debugger system setting of the System Reset Request bit
13237  */
13238 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_MDM_AP_SHIFT)) & RCM_SRS_MDM_AP_MASK)
13239 #define RCM_SRS_SACKERR_MASK (0x2000U)
13240 #define RCM_SRS_SACKERR_SHIFT (13U)
13241 /*! SACKERR - Stop Acknowledge Error
13242  *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
13243  *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
13244  */
13245 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SACKERR_SHIFT)) & RCM_SRS_SACKERR_MASK)
13246 /*! @} */
13247 
13248 /*! @name RPC - Reset Pin Control register */
13249 /*! @{ */
13250 #define RCM_RPC_RSTFLTSRW_MASK (0x3U)
13251 #define RCM_RPC_RSTFLTSRW_SHIFT (0U)
13252 /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
13253  *  0b00..All filtering disabled
13254  *  0b01..Bus clock filter enabled for normal operation
13255  *  0b10..LPO clock filter enabled for normal operation
13256  *  0b11..Reserved
13257  */
13258 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSRW_SHIFT)) & RCM_RPC_RSTFLTSRW_MASK)
13259 #define RCM_RPC_RSTFLTSS_MASK (0x4U)
13260 #define RCM_RPC_RSTFLTSS_SHIFT (2U)
13261 /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
13262  *  0b0..All filtering disabled
13263  *  0b1..LPO clock filter enabled
13264  */
13265 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSS_SHIFT)) & RCM_RPC_RSTFLTSS_MASK)
13266 #define RCM_RPC_RSTFLTSEL_MASK (0x1F00U)
13267 #define RCM_RPC_RSTFLTSEL_SHIFT (8U)
13268 /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
13269  */
13270 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSEL_SHIFT)) & RCM_RPC_RSTFLTSEL_MASK)
13271 /*! @} */
13272 
13273 /*! @name MR - Mode Register */
13274 /*! @{ */
13275 #define RCM_MR_BOOTROM_MASK (0x6U)
13276 #define RCM_MR_BOOTROM_SHIFT (1U)
13277 /*! BOOTROM - Boot ROM Configuration
13278  *  0b00..Boot from Flash
13279  *  0b01..Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin
13280  *  0b10..Boot form ROM due to FOPT[7] configuration
13281  *  0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
13282  */
13283 #define RCM_MR_BOOTROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
13284 /*! @} */
13285 
13286 /*! @name FM - Force Mode Register */
13287 /*! @{ */
13288 #define RCM_FM_FORCEROM_MASK (0x6U)
13289 #define RCM_FM_FORCEROM_SHIFT (1U)
13290 /*! FORCEROM - Force ROM Boot
13291  *  0b00..No effect
13292  *  0b01..Force boot from ROM with RCM_MR[1] set.
13293  *  0b10..Force boot from ROM with RCM_MR[2] set.
13294  *  0b11..Force boot from ROM with RCM_MR[2:1] set.
13295  */
13296 #define RCM_FM_FORCEROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
13297 /*! @} */
13298 
13299 /*! @name SSRS - Sticky System Reset Status Register */
13300 /*! @{ */
13301 #define RCM_SSRS_SWAKEUP_MASK (0x1U)
13302 #define RCM_SSRS_SWAKEUP_SHIFT (0U)
13303 /*! SWAKEUP - Sticky VLLS Wakeup Reset
13304  *  0b0..Reset not caused by wakeup from VLLS mode.
13305  *  0b1..Reset caused by wakeup from VLLS mode.
13306  */
13307 #define RCM_SSRS_SWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWAKEUP_SHIFT)) & RCM_SSRS_SWAKEUP_MASK)
13308 #define RCM_SSRS_SLVD_MASK (0x2U)
13309 #define RCM_SSRS_SLVD_SHIFT (1U)
13310 /*! SLVD - Sticky Low-Voltage Detect Reset
13311  *  0b0..Reset not caused by LVD trip or POR
13312  *  0b1..Reset caused by LVD trip or POR
13313  */
13314 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLVD_SHIFT)) & RCM_SSRS_SLVD_MASK)
13315 #define RCM_SSRS_SLOC_MASK (0x4U)
13316 #define RCM_SSRS_SLOC_SHIFT (2U)
13317 /*! SLOC - Sticky Loss-of-Clock Reset
13318  *  0b0..Reset not caused by a loss of external clock.
13319  *  0b1..Reset caused by a loss of external clock.
13320  */
13321 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOC_SHIFT)) & RCM_SSRS_SLOC_MASK)
13322 #define RCM_SSRS_SLOL_MASK (0x8U)
13323 #define RCM_SSRS_SLOL_SHIFT (3U)
13324 /*! SLOL - Sticky Loss-of-Lock Reset
13325  *  0b0..Reset not caused by a loss of lock in the PLL/FLL
13326  *  0b1..Reset caused by a loss of lock in the PLL/FLL
13327  */
13328 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOL_SHIFT)) & RCM_SSRS_SLOL_MASK)
13329 #define RCM_SSRS_SWDOG_MASK (0x20U)
13330 #define RCM_SSRS_SWDOG_SHIFT (5U)
13331 /*! SWDOG - Sticky Watchdog
13332  *  0b0..Reset not caused by watchdog timeout
13333  *  0b1..Reset caused by watchdog timeout
13334  */
13335 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWDOG_SHIFT)) & RCM_SSRS_SWDOG_MASK)
13336 #define RCM_SSRS_SPIN_MASK (0x40U)
13337 #define RCM_SSRS_SPIN_SHIFT (6U)
13338 /*! SPIN - Sticky External Reset Pin
13339  *  0b0..Reset not caused by external reset pin
13340  *  0b1..Reset caused by external reset pin
13341  */
13342 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPIN_SHIFT)) & RCM_SSRS_SPIN_MASK)
13343 #define RCM_SSRS_SPOR_MASK (0x80U)
13344 #define RCM_SSRS_SPOR_SHIFT (7U)
13345 /*! SPOR - Sticky Power-On Reset
13346  *  0b0..Reset not caused by POR
13347  *  0b1..Reset caused by POR
13348  */
13349 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPOR_SHIFT)) & RCM_SSRS_SPOR_MASK)
13350 #define RCM_SSRS_SLOCKUP_MASK (0x200U)
13351 #define RCM_SSRS_SLOCKUP_SHIFT (9U)
13352 /*! SLOCKUP - Sticky Core Lockup
13353  *  0b0..Reset not caused by core LOCKUP event
13354  *  0b1..Reset caused by core LOCKUP event
13355  */
13356 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOCKUP_SHIFT)) & RCM_SSRS_SLOCKUP_MASK)
13357 #define RCM_SSRS_SSW_MASK (0x400U)
13358 #define RCM_SSRS_SSW_SHIFT (10U)
13359 /*! SSW - Sticky Software
13360  *  0b0..Reset not caused by software setting of SYSRESETREQ bit
13361  *  0b1..Reset caused by software setting of SYSRESETREQ bit
13362  */
13363 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSW_SHIFT)) & RCM_SSRS_SSW_MASK)
13364 #define RCM_SSRS_SMDM_AP_MASK (0x800U)
13365 #define RCM_SSRS_SMDM_AP_SHIFT (11U)
13366 /*! SMDM_AP - Sticky MDM-AP System Reset Request
13367  *  0b0..Reset was not caused by host debugger system setting of the System Reset Request bit
13368  *  0b1..Reset was caused by host debugger system setting of the System Reset Request bit
13369  */
13370 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SMDM_AP_SHIFT)) & RCM_SSRS_SMDM_AP_MASK)
13371 #define RCM_SSRS_SSACKERR_MASK (0x2000U)
13372 #define RCM_SSRS_SSACKERR_SHIFT (13U)
13373 /*! SSACKERR - Sticky Stop Acknowledge Error
13374  *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
13375  *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
13376  */
13377 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSACKERR_SHIFT)) & RCM_SSRS_SSACKERR_MASK)
13378 /*! @} */
13379 
13380 /*! @name SRIE - System Reset Interrupt Enable Register */
13381 /*! @{ */
13382 #define RCM_SRIE_DELAY_MASK (0x3U)
13383 #define RCM_SRIE_DELAY_SHIFT (0U)
13384 /*! DELAY - Reset Delay Time
13385  *  0b00..10 LPO cycles
13386  *  0b01..34 LPO cycles
13387  *  0b10..130 LPO cycles
13388  *  0b11..514 LPO cycles
13389  */
13390 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_DELAY_SHIFT)) & RCM_SRIE_DELAY_MASK)
13391 #define RCM_SRIE_LOC_MASK (0x4U)
13392 #define RCM_SRIE_LOC_SHIFT (2U)
13393 /*! LOC - Loss-of-Clock Interrupt
13394  *  0b0..Interrupt disabled.
13395  *  0b1..Interrupt enabled.
13396  */
13397 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOC_SHIFT)) & RCM_SRIE_LOC_MASK)
13398 #define RCM_SRIE_LOL_MASK (0x8U)
13399 #define RCM_SRIE_LOL_SHIFT (3U)
13400 /*! LOL - Loss-of-Lock Interrupt
13401  *  0b0..Interrupt disabled.
13402  *  0b1..Interrupt enabled.
13403  */
13404 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOL_SHIFT)) & RCM_SRIE_LOL_MASK)
13405 #define RCM_SRIE_WDOG_MASK (0x20U)
13406 #define RCM_SRIE_WDOG_SHIFT (5U)
13407 /*! WDOG - Watchdog Interrupt
13408  *  0b0..Interrupt disabled.
13409  *  0b1..Interrupt enabled.
13410  */
13411 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_WDOG_SHIFT)) & RCM_SRIE_WDOG_MASK)
13412 #define RCM_SRIE_PIN_MASK (0x40U)
13413 #define RCM_SRIE_PIN_SHIFT (6U)
13414 /*! PIN - External Reset Pin Interrupt
13415  *  0b0..Reset not caused by external reset pin
13416  *  0b1..Reset caused by external reset pin
13417  */
13418 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_PIN_SHIFT)) & RCM_SRIE_PIN_MASK)
13419 #define RCM_SRIE_GIE_MASK (0x80U)
13420 #define RCM_SRIE_GIE_SHIFT (7U)
13421 /*! GIE - Global Interrupt Enable
13422  *  0b0..All interrupt sources disabled.
13423  *  0b1..All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate
13424  * interrupts.
13425  */
13426 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_GIE_SHIFT)) & RCM_SRIE_GIE_MASK)
13427 #define RCM_SRIE_LOCKUP_MASK (0x200U)
13428 #define RCM_SRIE_LOCKUP_SHIFT (9U)
13429 /*! LOCKUP - Core Lockup Interrupt
13430  *  0b0..Interrupt disabled.
13431  *  0b1..Interrupt enabled.
13432  */
13433 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOCKUP_SHIFT)) & RCM_SRIE_LOCKUP_MASK)
13434 #define RCM_SRIE_SW_MASK (0x400U)
13435 #define RCM_SRIE_SW_SHIFT (10U)
13436 /*! SW - Software Interrupt
13437  *  0b0..Interrupt disabled.
13438  *  0b1..Interrupt enabled.
13439  */
13440 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SW_SHIFT)) & RCM_SRIE_SW_MASK)
13441 #define RCM_SRIE_MDM_AP_MASK (0x800U)
13442 #define RCM_SRIE_MDM_AP_SHIFT (11U)
13443 /*! MDM_AP - MDM-AP System Reset Request
13444  *  0b0..Interrupt disabled.
13445  *  0b1..Interrupt enabled.
13446  */
13447 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_MDM_AP_SHIFT)) & RCM_SRIE_MDM_AP_MASK)
13448 #define RCM_SRIE_SACKERR_MASK (0x2000U)
13449 #define RCM_SRIE_SACKERR_SHIFT (13U)
13450 /*! SACKERR - Stop Acknowledge Error Interrupt
13451  *  0b0..Interrupt disabled.
13452  *  0b1..Interrupt enabled.
13453  */
13454 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SACKERR_SHIFT)) & RCM_SRIE_SACKERR_MASK)
13455 /*! @} */
13456 
13457 /*!
13458  * @}
13459  */ /* end of group RCM_Register_Masks */
13460 
13461 /* RCM - Peripheral instance base addresses */
13462 /** Peripheral RCM base address */
13463 #define RCM_BASE (0x4007F000u)
13464 /** Peripheral RCM base pointer */
13465 #define RCM ((RCM_Type *)RCM_BASE)
13466 /** Array initializer of RCM peripheral base addresses */
13467 #define RCM_BASE_ADDRS \
13468     {                  \
13469         RCM_BASE       \
13470     }
13471 /** Array initializer of RCM peripheral base pointers */
13472 #define RCM_BASE_PTRS \
13473     {                 \
13474         RCM           \
13475     }
13476 /** Interrupt vectors for the RCM peripheral type */
13477 #define RCM_IRQS \
13478     {            \
13479         RCM_IRQn \
13480     }
13481 
13482 /*!
13483  * @}
13484  */ /* end of group RCM_Peripheral_Access_Layer */
13485 
13486 /* ----------------------------------------------------------------------------
13487    -- RFSYS Peripheral Access Layer
13488    ---------------------------------------------------------------------------- */
13489 
13490 /*!
13491  * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
13492  * @{
13493  */
13494 
13495 /** RFSYS - Register Layout Typedef */
13496 typedef struct
13497 {
13498     __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
13499 } RFSYS_Type;
13500 
13501 /* ----------------------------------------------------------------------------
13502    -- RFSYS Register Masks
13503    ---------------------------------------------------------------------------- */
13504 
13505 /*!
13506  * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
13507  * @{
13508  */
13509 
13510 /*! @name REG - Register file register */
13511 /*! @{ */
13512 #define RFSYS_REG_LL_MASK (0xFFU)
13513 #define RFSYS_REG_LL_SHIFT (0U)
13514 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
13515 #define RFSYS_REG_LH_MASK (0xFF00U)
13516 #define RFSYS_REG_LH_SHIFT (8U)
13517 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
13518 #define RFSYS_REG_HL_MASK (0xFF0000U)
13519 #define RFSYS_REG_HL_SHIFT (16U)
13520 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
13521 #define RFSYS_REG_HH_MASK (0xFF000000U)
13522 #define RFSYS_REG_HH_SHIFT (24U)
13523 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
13524 /*! @} */
13525 
13526 /* The count of RFSYS_REG */
13527 #define RFSYS_REG_COUNT (8U)
13528 
13529 /*!
13530  * @}
13531  */ /* end of group RFSYS_Register_Masks */
13532 
13533 /* RFSYS - Peripheral instance base addresses */
13534 /** Peripheral RFSYS base address */
13535 #define RFSYS_BASE (0x4007C000u)
13536 /** Peripheral RFSYS base pointer */
13537 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
13538 /** Array initializer of RFSYS peripheral base addresses */
13539 #define RFSYS_BASE_ADDRS \
13540     {                    \
13541         RFSYS_BASE       \
13542     }
13543 /** Array initializer of RFSYS peripheral base pointers */
13544 #define RFSYS_BASE_PTRS \
13545     {                   \
13546         RFSYS           \
13547     }
13548 
13549 /*!
13550  * @}
13551  */ /* end of group RFSYS_Peripheral_Access_Layer */
13552 
13553 /* ----------------------------------------------------------------------------
13554    -- RTC Peripheral Access Layer
13555    ---------------------------------------------------------------------------- */
13556 
13557 /*!
13558  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
13559  * @{
13560  */
13561 
13562 /** RTC - Register Layout Typedef */
13563 typedef struct
13564 {
13565     __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
13566     __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
13567     __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
13568     __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
13569     __IO uint32_t CR;  /**< RTC Control Register, offset: 0x10 */
13570     __IO uint32_t SR;  /**< RTC Status Register, offset: 0x14 */
13571     __IO uint32_t LR;  /**< RTC Lock Register, offset: 0x18 */
13572     __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
13573 } RTC_Type;
13574 
13575 /* ----------------------------------------------------------------------------
13576    -- RTC Register Masks
13577    ---------------------------------------------------------------------------- */
13578 
13579 /*!
13580  * @addtogroup RTC_Register_Masks RTC Register Masks
13581  * @{
13582  */
13583 
13584 /*! @name TSR - RTC Time Seconds Register */
13585 /*! @{ */
13586 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
13587 #define RTC_TSR_TSR_SHIFT (0U)
13588 /*! TSR - Time Seconds Register
13589  */
13590 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
13591 /*! @} */
13592 
13593 /*! @name TPR - RTC Time Prescaler Register */
13594 /*! @{ */
13595 #define RTC_TPR_TPR_MASK (0xFFFFU)
13596 #define RTC_TPR_TPR_SHIFT (0U)
13597 /*! TPR - Time Prescaler Register
13598  */
13599 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
13600 /*! @} */
13601 
13602 /*! @name TAR - RTC Time Alarm Register */
13603 /*! @{ */
13604 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
13605 #define RTC_TAR_TAR_SHIFT (0U)
13606 /*! TAR - Time Alarm Register
13607  */
13608 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
13609 /*! @} */
13610 
13611 /*! @name TCR - RTC Time Compensation Register */
13612 /*! @{ */
13613 #define RTC_TCR_TCR_MASK (0xFFU)
13614 #define RTC_TCR_TCR_SHIFT (0U)
13615 /*! TCR - Time Compensation Register
13616  *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
13617  *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
13618  *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
13619  *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
13620  *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
13621  */
13622 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
13623 #define RTC_TCR_CIR_MASK (0xFF00U)
13624 #define RTC_TCR_CIR_SHIFT (8U)
13625 /*! CIR - Compensation Interval Register
13626  */
13627 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
13628 #define RTC_TCR_TCV_MASK (0xFF0000U)
13629 #define RTC_TCR_TCV_SHIFT (16U)
13630 /*! TCV - Time Compensation Value
13631  */
13632 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
13633 #define RTC_TCR_CIC_MASK (0xFF000000U)
13634 #define RTC_TCR_CIC_SHIFT (24U)
13635 /*! CIC - Compensation Interval Counter
13636  */
13637 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
13638 /*! @} */
13639 
13640 /*! @name CR - RTC Control Register */
13641 /*! @{ */
13642 #define RTC_CR_SWR_MASK (0x1U)
13643 #define RTC_CR_SWR_SHIFT (0U)
13644 /*! SWR - Software Reset
13645  *  0b0..No effect.
13646  *  0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly
13647  * clearing it.
13648  */
13649 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
13650 #define RTC_CR_WPE_MASK (0x2U)
13651 #define RTC_CR_WPE_SHIFT (1U)
13652 /*! WPE - Wakeup Pin Enable
13653  *  0b0..Wakeup pin is disabled.
13654  *  0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
13655  */
13656 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
13657 #define RTC_CR_SUP_MASK (0x4U)
13658 #define RTC_CR_SUP_SHIFT (2U)
13659 /*! SUP - Supervisor Access
13660  *  0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
13661  *  0b1..Non-supervisor mode write accesses are supported.
13662  */
13663 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
13664 #define RTC_CR_UM_MASK (0x8U)
13665 #define RTC_CR_UM_SHIFT (3U)
13666 /*! UM - Update Mode
13667  *  0b0..Registers cannot be written when locked.
13668  *  0b1..Registers can be written when locked under limited conditions.
13669  */
13670 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
13671 #define RTC_CR_WPS_MASK (0x10U)
13672 #define RTC_CR_WPS_SHIFT (4U)
13673 /*! WPS - Wakeup Pin Select
13674  *  0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
13675  *  0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is
13676  * output to other peripherals.
13677  */
13678 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
13679 #define RTC_CR_CPS_MASK (0x20U)
13680 #define RTC_CR_CPS_SHIFT (5U)
13681 /*! CPS - Clock Pin Select
13682  *  0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
13683  *  0b1..The RTC 32kHz crystal clock is output on RTC_CLKOUT.
13684  */
13685 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)
13686 #define RTC_CR_LPOS_MASK (0x80U)
13687 #define RTC_CR_LPOS_SHIFT (7U)
13688 /*! LPOS - LPO Select
13689  *  0b0..RTC prescaler increments using 32kHz crystal.
13690  *  0b1..RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are bypassed.
13691  */
13692 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
13693 #define RTC_CR_OSCE_MASK (0x100U)
13694 #define RTC_CR_OSCE_SHIFT (8U)
13695 /*! OSCE - Oscillator Enable
13696  *  0b0..32.768 kHz oscillator is disabled.
13697  *  0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before
13698  *       enabling the time counter to allow the 32.768 kHz clock time to stabilize.
13699  */
13700 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
13701 #define RTC_CR_CLKO_MASK (0x200U)
13702 #define RTC_CR_CLKO_SHIFT (9U)
13703 /*! CLKO - Clock Output
13704  *  0b0..The 32 kHz clock is output to other peripherals.
13705  *  0b1..The 32 kHz clock is not output to other peripherals.
13706  */
13707 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
13708 #define RTC_CR_SC16P_MASK (0x400U)
13709 #define RTC_CR_SC16P_SHIFT (10U)
13710 /*! SC16P - Oscillator 16pF Load Configure
13711  *  0b0..Disable the load.
13712  *  0b1..Enable the additional load.
13713  */
13714 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
13715 #define RTC_CR_SC8P_MASK (0x800U)
13716 #define RTC_CR_SC8P_SHIFT (11U)
13717 /*! SC8P - Oscillator 8pF Load Configure
13718  *  0b0..Disable the load.
13719  *  0b1..Enable the additional load.
13720  */
13721 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
13722 #define RTC_CR_SC4P_MASK (0x1000U)
13723 #define RTC_CR_SC4P_SHIFT (12U)
13724 /*! SC4P - Oscillator 4pF Load Configure
13725  *  0b0..Disable the load.
13726  *  0b1..Enable the additional load.
13727  */
13728 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
13729 #define RTC_CR_SC2P_MASK (0x2000U)
13730 #define RTC_CR_SC2P_SHIFT (13U)
13731 /*! SC2P - Oscillator 2pF Load Configure
13732  *  0b0..Disable the load.
13733  *  0b1..Enable the additional load.
13734  */
13735 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
13736 #define RTC_CR_CPE_MASK (0x3000000U)
13737 #define RTC_CR_CPE_SHIFT (24U)
13738 /*! CPE - Clock Pin Enable
13739  *  0b00..RTC_CLKOUT is disabled.
13740  *  0b01..RTC_CLKOUT is enabled on pin PTE0.
13741  *  0b10..RTC_CLKOUT is enabled on pin PTE26.
13742  *  0b11..Reserved.
13743  */
13744 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
13745 /*! @} */
13746 
13747 /*! @name SR - RTC Status Register */
13748 /*! @{ */
13749 #define RTC_SR_TIF_MASK (0x1U)
13750 #define RTC_SR_TIF_SHIFT (0U)
13751 /*! TIF - Time Invalid Flag
13752  *  0b0..Time is valid.
13753  *  0b1..Time is invalid and time counter is read as zero.
13754  */
13755 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
13756 #define RTC_SR_TOF_MASK (0x2U)
13757 #define RTC_SR_TOF_SHIFT (1U)
13758 /*! TOF - Time Overflow Flag
13759  *  0b0..Time overflow has not occurred.
13760  *  0b1..Time overflow has occurred and time counter is read as zero.
13761  */
13762 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
13763 #define RTC_SR_TAF_MASK (0x4U)
13764 #define RTC_SR_TAF_SHIFT (2U)
13765 /*! TAF - Time Alarm Flag
13766  *  0b0..Time alarm has not occurred.
13767  *  0b1..Time alarm has occurred.
13768  */
13769 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
13770 #define RTC_SR_TCE_MASK (0x10U)
13771 #define RTC_SR_TCE_SHIFT (4U)
13772 /*! TCE - Time Counter Enable
13773  *  0b0..Time counter is disabled.
13774  *  0b1..Time counter is enabled.
13775  */
13776 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
13777 /*! @} */
13778 
13779 /*! @name LR - RTC Lock Register */
13780 /*! @{ */
13781 #define RTC_LR_TCL_MASK (0x8U)
13782 #define RTC_LR_TCL_SHIFT (3U)
13783 /*! TCL - Time Compensation Lock
13784  *  0b0..Time Compensation Register is locked and writes are ignored.
13785  *  0b1..Time Compensation Register is not locked and writes complete as normal.
13786  */
13787 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
13788 #define RTC_LR_CRL_MASK (0x10U)
13789 #define RTC_LR_CRL_SHIFT (4U)
13790 /*! CRL - Control Register Lock
13791  *  0b0..Control Register is locked and writes are ignored.
13792  *  0b1..Control Register is not locked and writes complete as normal.
13793  */
13794 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
13795 #define RTC_LR_SRL_MASK (0x20U)
13796 #define RTC_LR_SRL_SHIFT (5U)
13797 /*! SRL - Status Register Lock
13798  *  0b0..Status Register is locked and writes are ignored.
13799  *  0b1..Status Register is not locked and writes complete as normal.
13800  */
13801 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
13802 #define RTC_LR_LRL_MASK (0x40U)
13803 #define RTC_LR_LRL_SHIFT (6U)
13804 /*! LRL - Lock Register Lock
13805  *  0b0..Lock Register is locked and writes are ignored.
13806  *  0b1..Lock Register is not locked and writes complete as normal.
13807  */
13808 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
13809 /*! @} */
13810 
13811 /*! @name IER - RTC Interrupt Enable Register */
13812 /*! @{ */
13813 #define RTC_IER_TIIE_MASK (0x1U)
13814 #define RTC_IER_TIIE_SHIFT (0U)
13815 /*! TIIE - Time Invalid Interrupt Enable
13816  *  0b0..Time invalid flag does not generate an interrupt.
13817  *  0b1..Time invalid flag does generate an interrupt.
13818  */
13819 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
13820 #define RTC_IER_TOIE_MASK (0x2U)
13821 #define RTC_IER_TOIE_SHIFT (1U)
13822 /*! TOIE - Time Overflow Interrupt Enable
13823  *  0b0..Time overflow flag does not generate an interrupt.
13824  *  0b1..Time overflow flag does generate an interrupt.
13825  */
13826 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
13827 #define RTC_IER_TAIE_MASK (0x4U)
13828 #define RTC_IER_TAIE_SHIFT (2U)
13829 /*! TAIE - Time Alarm Interrupt Enable
13830  *  0b0..Time alarm flag does not generate an interrupt.
13831  *  0b1..Time alarm flag does generate an interrupt.
13832  */
13833 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
13834 #define RTC_IER_TSIE_MASK (0x10U)
13835 #define RTC_IER_TSIE_SHIFT (4U)
13836 /*! TSIE - Time Seconds Interrupt Enable
13837  *  0b0..Seconds interrupt is disabled.
13838  *  0b1..Seconds interrupt is enabled.
13839  */
13840 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
13841 #define RTC_IER_WPON_MASK (0x80U)
13842 #define RTC_IER_WPON_SHIFT (7U)
13843 /*! WPON - Wakeup Pin On
13844  *  0b0..No effect.
13845  *  0b1..If the wakeup pin is enabled, then the wakeup pin will assert.
13846  */
13847 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
13848 #define RTC_IER_TSIC_MASK (0x70000U)
13849 #define RTC_IER_TSIC_SHIFT (16U)
13850 /*! TSIC - Timer Seconds Interrupt Configuration
13851  *  0b000..1 Hz.
13852  *  0b001..2 Hz.
13853  *  0b010..4 Hz.
13854  *  0b011..8 Hz.
13855  *  0b100..16 Hz.
13856  *  0b101..32 Hz.
13857  *  0b110..64 Hz.
13858  *  0b111..128 Hz.
13859  */
13860 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
13861 /*! @} */
13862 
13863 /*!
13864  * @}
13865  */ /* end of group RTC_Register_Masks */
13866 
13867 /* RTC - Peripheral instance base addresses */
13868 /** Peripheral RTC base address */
13869 #define RTC_BASE (0x40038000u)
13870 /** Peripheral RTC base pointer */
13871 #define RTC ((RTC_Type *)RTC_BASE)
13872 /** Array initializer of RTC peripheral base addresses */
13873 #define RTC_BASE_ADDRS \
13874     {                  \
13875         RTC_BASE       \
13876     }
13877 /** Array initializer of RTC peripheral base pointers */
13878 #define RTC_BASE_PTRS \
13879     {                 \
13880         RTC           \
13881     }
13882 /** Interrupt vectors for the RTC peripheral type */
13883 #define RTC_IRQS \
13884     {            \
13885         RTC_IRQn \
13886     }
13887 #define RTC_SECONDS_IRQS \
13888     {                    \
13889         RTC_Seconds_IRQn \
13890     }
13891 
13892 /*!
13893  * @}
13894  */ /* end of group RTC_Peripheral_Access_Layer */
13895 
13896 /* ----------------------------------------------------------------------------
13897    -- SCG Peripheral Access Layer
13898    ---------------------------------------------------------------------------- */
13899 
13900 /*!
13901  * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
13902  * @{
13903  */
13904 
13905 /** SCG - Register Layout Typedef */
13906 typedef struct
13907 {
13908     __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
13909     __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
13910     uint8_t RESERVED_0[8];
13911     __I uint32_t CSR;         /**< Clock Status Register, offset: 0x10 */
13912     __IO uint32_t RCCR;       /**< Run Clock Control Register, offset: 0x14 */
13913     __IO uint32_t VCCR;       /**< VLPR Clock Control Register, offset: 0x18 */
13914     __IO uint32_t HCCR;       /**< HSRUN Clock Control Register, offset: 0x1C */
13915     __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */
13916     uint8_t RESERVED_1[220];
13917     __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */
13918     __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */
13919     __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */
13920     uint8_t RESERVED_2[244];
13921     __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */
13922     __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */
13923     __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */
13924     uint8_t RESERVED_3[244];
13925     __IO uint32_t FIRCCSR;  /**< Fast IRC Control Status Register, offset: 0x300 */
13926     __IO uint32_t FIRCDIV;  /**< Fast IRC Divide Register, offset: 0x304 */
13927     __IO uint32_t FIRCCFG;  /**< Fast IRC Configuration Register, offset: 0x308 */
13928     __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */
13929     uint8_t RESERVED_4[8];
13930     __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */
13931     uint8_t RESERVED_5[740];
13932     __IO uint32_t SPLLCSR; /**< System PLL Control Status Register, offset: 0x600 */
13933     __IO uint32_t SPLLDIV; /**< System PLL Divide Register, offset: 0x604 */
13934     __IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0x608 */
13935 } SCG_Type;
13936 
13937 /* ----------------------------------------------------------------------------
13938    -- SCG Register Masks
13939    ---------------------------------------------------------------------------- */
13940 
13941 /*!
13942  * @addtogroup SCG_Register_Masks SCG Register Masks
13943  * @{
13944  */
13945 
13946 /*! @name VERID - Version ID Register */
13947 /*! @{ */
13948 #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU)
13949 #define SCG_VERID_VERSION_SHIFT (0U)
13950 /*! VERSION - SCG Version Number
13951  */
13952 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
13953 /*! @} */
13954 
13955 /*! @name PARAM - Parameter Register */
13956 /*! @{ */
13957 #define SCG_PARAM_CLKPRES_MASK (0xFFU)
13958 #define SCG_PARAM_CLKPRES_SHIFT (0U)
13959 /*! CLKPRES - Clock Present
13960  */
13961 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK)
13962 #define SCG_PARAM_DIVPRES_MASK (0xF8000000U)
13963 #define SCG_PARAM_DIVPRES_SHIFT (27U)
13964 /*! DIVPRES - Divider Present
13965  */
13966 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK)
13967 /*! @} */
13968 
13969 /*! @name CSR - Clock Status Register */
13970 /*! @{ */
13971 #define SCG_CSR_DIVSLOW_MASK (0xFU)
13972 #define SCG_CSR_DIVSLOW_SHIFT (0U)
13973 /*! DIVSLOW - Slow Clock Divide Ratio
13974  *  0b0000..Divide-by-1
13975  *  0b0001..Divide-by-2
13976  *  0b0010..Divide-by-3
13977  *  0b0011..Divide-by-4
13978  *  0b0100..Divide-by-5
13979  *  0b0101..Divide-by-6
13980  *  0b0110..Divide-by-7
13981  *  0b0111..Divide-by-8
13982  *  0b1000..Divide-by-9
13983  *  0b1001..Divide-by-10
13984  *  0b1010..Divide-by-11
13985  *  0b1011..Divide-by-12
13986  *  0b1100..Divide-by-13
13987  *  0b1101..Divide-by-14
13988  *  0b1110..Divide-by-15
13989  *  0b1111..Divide-by-16
13990  */
13991 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
13992 #define SCG_CSR_DIVCORE_MASK (0xF0000U)
13993 #define SCG_CSR_DIVCORE_SHIFT (16U)
13994 /*! DIVCORE - Core Clock Divide Ratio
13995  *  0b0000..Divide-by-1
13996  *  0b0001..Divide-by-2
13997  *  0b0010..Divide-by-3
13998  *  0b0011..Divide-by-4
13999  *  0b0100..Divide-by-5
14000  *  0b0101..Divide-by-6
14001  *  0b0110..Divide-by-7
14002  *  0b0111..Divide-by-8
14003  *  0b1000..Divide-by-9
14004  *  0b1001..Divide-by-10
14005  *  0b1010..Divide-by-11
14006  *  0b1011..Divide-by-12
14007  *  0b1100..Divide-by-13
14008  *  0b1101..Divide-by-14
14009  *  0b1110..Divide-by-15
14010  *  0b1111..Divide-by-16
14011  */
14012 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK)
14013 #define SCG_CSR_SCS_MASK (0xF000000U)
14014 #define SCG_CSR_SCS_SHIFT (24U)
14015 /*! SCS - System Clock Source
14016  *  0b0000..Reserved
14017  *  0b0001..System OSC (SOSC_CLK)
14018  *  0b0010..Slow IRC (SIRC_CLK)
14019  *  0b0011..Fast IRC (FIRC_CLK)
14020  *  0b0100..Reserved
14021  *  0b0101..Reserved
14022  *  0b0110..System PLL (SPLL_CLK)
14023  *  0b0111..Reserved
14024  */
14025 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
14026 /*! @} */
14027 
14028 /*! @name RCCR - Run Clock Control Register */
14029 /*! @{ */
14030 #define SCG_RCCR_DIVSLOW_MASK (0xFU)
14031 #define SCG_RCCR_DIVSLOW_SHIFT (0U)
14032 /*! DIVSLOW - Slow Clock Divide Ratio
14033  *  0b0000..Divide-by-1
14034  *  0b0001..Divide-by-2
14035  *  0b0010..Divide-by-3
14036  *  0b0011..Divide-by-4
14037  *  0b0100..Divide-by-5
14038  *  0b0101..Divide-by-6
14039  *  0b0110..Divide-by-7
14040  *  0b0111..Divide-by-8
14041  *  0b1000..Divide-by-9
14042  *  0b1001..Divide-by-10
14043  *  0b1010..Divide-by-11
14044  *  0b1011..Divide-by-12
14045  *  0b1100..Divide-by-13
14046  *  0b1101..Divide-by-14
14047  *  0b1110..Divide-by-15
14048  *  0b1111..Divide-by-16
14049  */
14050 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK)
14051 #define SCG_RCCR_DIVCORE_MASK (0xF0000U)
14052 #define SCG_RCCR_DIVCORE_SHIFT (16U)
14053 /*! DIVCORE - Core Clock Divide Ratio
14054  *  0b0000..Divide-by-1
14055  *  0b0001..Divide-by-2
14056  *  0b0010..Divide-by-3
14057  *  0b0011..Divide-by-4
14058  *  0b0100..Divide-by-5
14059  *  0b0101..Divide-by-6
14060  *  0b0110..Divide-by-7
14061  *  0b0111..Divide-by-8
14062  *  0b1000..Divide-by-9
14063  *  0b1001..Divide-by-10
14064  *  0b1010..Divide-by-11
14065  *  0b1011..Divide-by-12
14066  *  0b1100..Divide-by-13
14067  *  0b1101..Divide-by-14
14068  *  0b1110..Divide-by-15
14069  *  0b1111..Divide-by-16
14070  */
14071 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK)
14072 #define SCG_RCCR_SCS_MASK (0xF000000U)
14073 #define SCG_RCCR_SCS_SHIFT (24U)
14074 /*! SCS - System Clock Source
14075  *  0b0000..Reserved
14076  *  0b0001..System OSC (SOSC_CLK)
14077  *  0b0010..Slow IRC (SIRC_CLK)
14078  *  0b0011..Fast IRC (FIRC_CLK)
14079  *  0b0100..Reserved
14080  *  0b0101..Reserved
14081  *  0b0110..System PLL (SPLL_CLK)
14082  *  0b0111..Reserved
14083  */
14084 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
14085 /*! @} */
14086 
14087 /*! @name VCCR - VLPR Clock Control Register */
14088 /*! @{ */
14089 #define SCG_VCCR_DIVSLOW_MASK (0xFU)
14090 #define SCG_VCCR_DIVSLOW_SHIFT (0U)
14091 /*! DIVSLOW - Slow Clock Divide Ratio
14092  *  0b0000..Divide-by-1
14093  *  0b0001..Divide-by-2
14094  *  0b0010..Divide-by-3
14095  *  0b0011..Divide-by-4
14096  *  0b0100..Divide-by-5
14097  *  0b0101..Divide-by-6
14098  *  0b0110..Divide-by-7
14099  *  0b0111..Divide-by-8
14100  *  0b1000..Divide-by-9
14101  *  0b1001..Divide-by-10
14102  *  0b1010..Divide-by-11
14103  *  0b1011..Divide-by-12
14104  *  0b1100..Divide-by-13
14105  *  0b1101..Divide-by-14
14106  *  0b1110..Divide-by-15
14107  *  0b1111..Divide-by-16
14108  */
14109 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)
14110 #define SCG_VCCR_DIVCORE_MASK (0xF0000U)
14111 #define SCG_VCCR_DIVCORE_SHIFT (16U)
14112 /*! DIVCORE - Core Clock Divide Ratio
14113  *  0b0000..Divide-by-1
14114  *  0b0001..Divide-by-2
14115  *  0b0010..Divide-by-3
14116  *  0b0011..Divide-by-4
14117  *  0b0100..Divide-by-5
14118  *  0b0101..Divide-by-6
14119  *  0b0110..Divide-by-7
14120  *  0b0111..Divide-by-8
14121  *  0b1000..Divide-by-9
14122  *  0b1001..Divide-by-10
14123  *  0b1010..Divide-by-11
14124  *  0b1011..Divide-by-12
14125  *  0b1100..Divide-by-13
14126  *  0b1101..Divide-by-14
14127  *  0b1110..Divide-by-15
14128  *  0b1111..Divide-by-16
14129  */
14130 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)
14131 #define SCG_VCCR_SCS_MASK (0xF000000U)
14132 #define SCG_VCCR_SCS_SHIFT (24U)
14133 /*! SCS - System Clock Source
14134  *  0b0000..Reserved
14135  *  0b0001..System OSC (SOSC_CLK)
14136  *  0b0010..Slow IRC (SIRC_CLK)
14137  *  0b0011..Reserved
14138  *  0b0100..Reserved
14139  *  0b0101..Reserved
14140  *  0b0110..Reserved
14141  *  0b0111..Reserved
14142  */
14143 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK)
14144 /*! @} */
14145 
14146 /*! @name HCCR - HSRUN Clock Control Register */
14147 /*! @{ */
14148 #define SCG_HCCR_DIVSLOW_MASK (0xFU)
14149 #define SCG_HCCR_DIVSLOW_SHIFT (0U)
14150 /*! DIVSLOW - Slow Clock Divide Ratio
14151  *  0b0000..Divide-by-1
14152  *  0b0001..Divide-by-2
14153  *  0b0010..Divide-by-3
14154  *  0b0011..Divide-by-4
14155  *  0b0100..Divide-by-5
14156  *  0b0101..Divide-by-6
14157  *  0b0110..Divide-by-7
14158  *  0b0111..Divide-by-8
14159  *  0b1000..Divide-by-9
14160  *  0b1001..Divide-by-10
14161  *  0b1010..Divide-by-11
14162  *  0b1011..Divide-by-12
14163  *  0b1100..Divide-by-13
14164  *  0b1101..Divide-by-14
14165  *  0b1110..Divide-by-15
14166  *  0b1111..Divide-by-16
14167  */
14168 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK)
14169 #define SCG_HCCR_DIVCORE_MASK (0xF0000U)
14170 #define SCG_HCCR_DIVCORE_SHIFT (16U)
14171 /*! DIVCORE - Core Clock Divide Ratio
14172  *  0b0000..Divide-by-1
14173  *  0b0001..Divide-by-2
14174  *  0b0010..Divide-by-3
14175  *  0b0011..Divide-by-4
14176  *  0b0100..Divide-by-5
14177  *  0b0101..Divide-by-6
14178  *  0b0110..Divide-by-7
14179  *  0b0111..Divide-by-8
14180  *  0b1000..Divide-by-9
14181  *  0b1001..Divide-by-10
14182  *  0b1010..Divide-by-11
14183  *  0b1011..Divide-by-12
14184  *  0b1100..Divide-by-13
14185  *  0b1101..Divide-by-14
14186  *  0b1110..Divide-by-15
14187  *  0b1111..Divide-by-16
14188  */
14189 #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
14190 #define SCG_HCCR_SCS_MASK (0xF000000U)
14191 #define SCG_HCCR_SCS_SHIFT (24U)
14192 /*! SCS - System Clock Source
14193  *  0b0000..Reserved
14194  *  0b0001..System OSC (SOSC_CLK)
14195  *  0b0010..Slow IRC (SIRC_CLK)
14196  *  0b0011..Fast IRC (FIRC_CLK)
14197  *  0b0100..Reserved
14198  *  0b0101..Reserved
14199  *  0b0110..System PLL (SPLL_CLK)
14200  *  0b0111..Reserved
14201  */
14202 #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK)
14203 /*! @} */
14204 
14205 /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
14206 /*! @{ */
14207 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U)
14208 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U)
14209 /*! CLKOUTSEL - SCG Clkout Select
14210  *  0b0000..SCG SLOW Clock
14211  *  0b0001..System OSC (SOSC_CLK)
14212  *  0b0010..Slow IRC (SIRC_CLK)
14213  *  0b0011..Fast IRC (FIRC_CLK)
14214  *  0b0100..Reserved
14215  *  0b0101..Reserved
14216  *  0b0110..System PLL (SPLL_CLK)
14217  *  0b0111..Reserved
14218  *  0b1111..Reserved
14219  */
14220 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) \
14221     (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
14222 /*! @} */
14223 
14224 /*! @name SOSCCSR - System OSC Control Status Register */
14225 /*! @{ */
14226 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U)
14227 #define SCG_SOSCCSR_SOSCEN_SHIFT (0U)
14228 /*! SOSCEN - System OSC Enable
14229  *  0b0..System OSC is disabled
14230  *  0b1..System OSC is enabled
14231  */
14232 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
14233 #define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U)
14234 #define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U)
14235 /*! SOSCSTEN - System OSC Stop Enable
14236  *  0b0..System OSC is disabled in Stop modes
14237  *  0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and
14238  * SOSCEN=1.
14239  */
14240 #define SCG_SOSCCSR_SOSCSTEN(x) \
14241     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
14242 #define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U)
14243 #define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U)
14244 /*! SOSCLPEN - System OSC Low Power Enable
14245  *  0b0..System OSC is disabled in VLP modes
14246  *  0b1..System OSC is enabled in VLP modes
14247  */
14248 #define SCG_SOSCCSR_SOSCLPEN(x) \
14249     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK)
14250 #define SCG_SOSCCSR_SOSCERCLKEN_MASK (0x8U)
14251 #define SCG_SOSCCSR_SOSCERCLKEN_SHIFT (3U)
14252 /*! SOSCERCLKEN - System OSC 3V ERCLK Enable
14253  *  0b0..System OSC 3V ERCLK output clock is disabled.
14254  *  0b1..System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled.
14255  */
14256 #define SCG_SOSCCSR_SOSCERCLKEN(x) \
14257     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERCLKEN_SHIFT)) & SCG_SOSCCSR_SOSCERCLKEN_MASK)
14258 #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U)
14259 #define SCG_SOSCCSR_SOSCCM_SHIFT (16U)
14260 /*! SOSCCM - System OSC Clock Monitor
14261  *  0b0..System OSC Clock Monitor is disabled
14262  *  0b1..System OSC Clock Monitor is enabled
14263  */
14264 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
14265 #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U)
14266 #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U)
14267 /*! SOSCCMRE - System OSC Clock Monitor Reset Enable
14268  *  0b0..Clock Monitor generates interrupt when error detected
14269  *  0b1..Clock Monitor generates reset when error detected
14270  */
14271 #define SCG_SOSCCSR_SOSCCMRE(x) \
14272     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
14273 #define SCG_SOSCCSR_LK_MASK (0x800000U)
14274 #define SCG_SOSCCSR_LK_SHIFT (23U)
14275 /*! LK - Lock Register
14276  *  0b0..This Control Status Register can be written.
14277  *  0b1..This Control Status Register cannot be written.
14278  */
14279 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
14280 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U)
14281 #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U)
14282 /*! SOSCVLD - System OSC Valid
14283  *  0b0..System OSC is not enabled or clock is not valid
14284  *  0b1..System OSC is enabled and output clock is valid
14285  */
14286 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
14287 #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U)
14288 #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U)
14289 /*! SOSCSEL - System OSC Selected
14290  *  0b0..System OSC is not the system clock source
14291  *  0b1..System OSC is the system clock source
14292  */
14293 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
14294 #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U)
14295 #define SCG_SOSCCSR_SOSCERR_SHIFT (26U)
14296 /*! SOSCERR - System OSC Clock Error
14297  *  0b0..System OSC Clock Monitor is disabled or has not detected an error
14298  *  0b1..System OSC Clock Monitor is enabled and detected an error
14299  */
14300 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
14301 /*! @} */
14302 
14303 /*! @name SOSCDIV - System OSC Divide Register */
14304 /*! @{ */
14305 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U)
14306 #define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U)
14307 /*! SOSCDIV1 - System OSC Clock Divide 1
14308  *  0b000..Output disabled
14309  *  0b001..Divide by 1
14310  *  0b010..Divide by 2
14311  *  0b011..Divide by 4
14312  *  0b100..Divide by 8
14313  *  0b101..Divide by 16
14314  *  0b110..Divide by 32
14315  *  0b111..Divide by 64
14316  */
14317 #define SCG_SOSCDIV_SOSCDIV1(x) \
14318     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
14319 #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U)
14320 #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U)
14321 /*! SOSCDIV2 - System OSC Clock Divide 2
14322  *  0b000..Output disabled
14323  *  0b001..Divide by 1
14324  *  0b010..Divide by 2
14325  *  0b011..Divide by 4
14326  *  0b100..Divide by 8
14327  *  0b101..Divide by 16
14328  *  0b110..Divide by 32
14329  *  0b111..Divide by 64
14330  */
14331 #define SCG_SOSCDIV_SOSCDIV2(x) \
14332     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK)
14333 #define SCG_SOSCDIV_SOSCDIV3_MASK (0x70000U)
14334 #define SCG_SOSCDIV_SOSCDIV3_SHIFT (16U)
14335 /*! SOSCDIV3 - System OSC Clock Divide 3
14336  *  0b000..Output disabled
14337  *  0b001..Divide by 1
14338  *  0b010..Divide by 2
14339  *  0b011..Divide by 4
14340  *  0b100..Divide by 8
14341  *  0b101..Divide by 16
14342  *  0b110..Divide by 32
14343  *  0b111..Divide by 64
14344  */
14345 #define SCG_SOSCDIV_SOSCDIV3(x) \
14346     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK)
14347 /*! @} */
14348 
14349 /*! @name SOSCCFG - System Oscillator Configuration Register */
14350 /*! @{ */
14351 #define SCG_SOSCCFG_EREFS_MASK (0x4U)
14352 #define SCG_SOSCCFG_EREFS_SHIFT (2U)
14353 /*! EREFS - External Reference Select
14354  *  0b0..External reference clock selected
14355  *  0b1..Internal crystal oscillator of OSC selected. In VLLS0, the internal oscillator of OSC is disabled even if
14356  * SOSCEN=1 and SOSCSTEN=1.
14357  */
14358 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK)
14359 #define SCG_SOSCCFG_HGO_MASK (0x8U)
14360 #define SCG_SOSCCFG_HGO_SHIFT (3U)
14361 /*! HGO - High Gain Oscillator Select
14362  *  0b0..Configure crystal oscillator for low-gain operation
14363  *  0b1..Configure crystal oscillator for high-gain operation
14364  */
14365 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK)
14366 #define SCG_SOSCCFG_RANGE_MASK (0x30U)
14367 #define SCG_SOSCCFG_RANGE_SHIFT (4U)
14368 /*! RANGE - System OSC Range Select
14369  *  0b00..Reserved
14370  *  0b01..Low frequency range selected for the crystal oscillator
14371  *  0b10..Medium frequency range selected for the crytstal oscillator
14372  *  0b11..High frequency range selected for the crystal oscillator
14373  */
14374 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK)
14375 #define SCG_SOSCCFG_SC16P_MASK (0x100U)
14376 #define SCG_SOSCCFG_SC16P_SHIFT (8U)
14377 /*! SC16P - Oscillator 16 pF Capacitor Load
14378  */
14379 #define SCG_SOSCCFG_SC16P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC16P_SHIFT)) & SCG_SOSCCFG_SC16P_MASK)
14380 #define SCG_SOSCCFG_SC8P_MASK (0x200U)
14381 #define SCG_SOSCCFG_SC8P_SHIFT (9U)
14382 /*! SC8P - Oscillator 8 pF Capacitor Load Configure
14383  */
14384 #define SCG_SOSCCFG_SC8P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC8P_SHIFT)) & SCG_SOSCCFG_SC8P_MASK)
14385 #define SCG_SOSCCFG_SC4P_MASK (0x400U)
14386 #define SCG_SOSCCFG_SC4P_SHIFT (10U)
14387 /*! SC4P - Oscillator 4 pF Capacitor Load
14388  */
14389 #define SCG_SOSCCFG_SC4P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC4P_SHIFT)) & SCG_SOSCCFG_SC4P_MASK)
14390 #define SCG_SOSCCFG_SC2P_MASK (0x800U)
14391 #define SCG_SOSCCFG_SC2P_SHIFT (11U)
14392 /*! SC2P - Oscillator 2 pF Capacitor Load
14393  */
14394 #define SCG_SOSCCFG_SC2P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC2P_SHIFT)) & SCG_SOSCCFG_SC2P_MASK)
14395 /*! @} */
14396 
14397 /*! @name SIRCCSR - Slow IRC Control Status Register */
14398 /*! @{ */
14399 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U)
14400 #define SCG_SIRCCSR_SIRCEN_SHIFT (0U)
14401 /*! SIRCEN - Slow IRC Enable
14402  *  0b0..Slow IRC is disabled
14403  *  0b1..Slow IRC is enabled
14404  */
14405 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)
14406 #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U)
14407 #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U)
14408 /*! SIRCSTEN - Slow IRC Stop Enable
14409  *  0b0..Slow IRC is disabled in supported Stop modes
14410  *  0b1..Slow IRC is enabled in supported Stop modes
14411  */
14412 #define SCG_SIRCCSR_SIRCSTEN(x) \
14413     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
14414 #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U)
14415 #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U)
14416 /*! SIRCLPEN - Slow IRC Low Power Enable
14417  *  0b0..Slow IRC is disabled in VLP modes
14418  *  0b1..Slow IRC is enabled in VLP modes
14419  */
14420 #define SCG_SIRCCSR_SIRCLPEN(x) \
14421     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK)
14422 #define SCG_SIRCCSR_LK_MASK (0x800000U)
14423 #define SCG_SIRCCSR_LK_SHIFT (23U)
14424 /*! LK - Lock Register
14425  *  0b0..Control Status Register can be written.
14426  *  0b1..Control Status Register cannot be written.
14427  */
14428 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
14429 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U)
14430 #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U)
14431 /*! SIRCVLD - Slow IRC Valid
14432  *  0b0..Slow IRC is not enabled or clock is not valid
14433  *  0b1..Slow IRC is enabled and output clock is valid
14434  */
14435 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
14436 #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U)
14437 #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U)
14438 /*! SIRCSEL - Slow IRC Selected
14439  *  0b0..Slow IRC is not the system clock source
14440  *  0b1..Slow IRC is the system clock source
14441  */
14442 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
14443 /*! @} */
14444 
14445 /*! @name SIRCDIV - Slow IRC Divide Register */
14446 /*! @{ */
14447 #define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U)
14448 #define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U)
14449 /*! SIRCDIV1 - Slow IRC Clock Divide 1
14450  *  0b000..Output disabled
14451  *  0b001..Divide by 1
14452  *  0b010..Divide by 2
14453  *  0b011..Divide by 4
14454  *  0b100..Divide by 8
14455  *  0b101..Divide by 16
14456  *  0b110..Divide by 32
14457  *  0b111..Divide by 64
14458  */
14459 #define SCG_SIRCDIV_SIRCDIV1(x) \
14460     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK)
14461 #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U)
14462 #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U)
14463 /*! SIRCDIV2 - Slow IRC Clock Divide 2
14464  *  0b000..Output disabled
14465  *  0b001..Divide by 1
14466  *  0b010..Divide by 2
14467  *  0b011..Divide by 4
14468  *  0b100..Divide by 8
14469  *  0b101..Divide by 16
14470  *  0b110..Divide by 32
14471  *  0b111..Divide by 64
14472  */
14473 #define SCG_SIRCDIV_SIRCDIV2(x) \
14474     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK)
14475 #define SCG_SIRCDIV_SIRCDIV3_MASK (0x70000U)
14476 #define SCG_SIRCDIV_SIRCDIV3_SHIFT (16U)
14477 /*! SIRCDIV3 - Slow IRC Clock Divider 3
14478  *  0b000..Output disabled
14479  *  0b001..Divide by 1
14480  *  0b010..Divide by 2
14481  *  0b011..Divide by 4
14482  *  0b100..Divide by 8
14483  *  0b101..Divide by 16
14484  *  0b110..Divide by 32
14485  *  0b111..Divide by 64
14486  */
14487 #define SCG_SIRCDIV_SIRCDIV3(x) \
14488     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK)
14489 /*! @} */
14490 
14491 /*! @name SIRCCFG - Slow IRC Configuration Register */
14492 /*! @{ */
14493 #define SCG_SIRCCFG_RANGE_MASK (0x1U)
14494 #define SCG_SIRCCFG_RANGE_SHIFT (0U)
14495 /*! RANGE - Frequency Range
14496  *  0b0..Slow IRC low range clock (2 MHz)
14497  *  0b1..Slow IRC high range clock (8 MHz )
14498  */
14499 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK)
14500 /*! @} */
14501 
14502 /*! @name FIRCCSR - Fast IRC Control Status Register */
14503 /*! @{ */
14504 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U)
14505 #define SCG_FIRCCSR_FIRCEN_SHIFT (0U)
14506 /*! FIRCEN - Fast IRC Enable
14507  *  0b0..Fast IRC is disabled
14508  *  0b1..Fast IRC is enabled
14509  */
14510 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
14511 #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U)
14512 #define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U)
14513 /*! FIRCSTEN - Fast IRC Stop Enable
14514  *  0b0..Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if the
14515  *       System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0.
14516  *  0b1..Fast IRC is enabled in Stop modes
14517  */
14518 #define SCG_FIRCCSR_FIRCSTEN(x) \
14519     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
14520 #define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U)
14521 #define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U)
14522 /*! FIRCLPEN - Fast IRC Low Power Enable
14523  *  0b0..Fast IRC is disabled in VLP modes
14524  *  0b1..Fast IRC is enabled in VLP modes
14525  */
14526 #define SCG_FIRCCSR_FIRCLPEN(x) \
14527     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK)
14528 #define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U)
14529 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U)
14530 /*! FIRCREGOFF - Fast IRC Regulator Enable
14531  *  0b0..Fast IRC Regulator is enabled.
14532  *  0b1..Fast IRC Regulator is disabled.
14533  */
14534 #define SCG_FIRCCSR_FIRCREGOFF(x) \
14535     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK)
14536 #define SCG_FIRCCSR_FIRCTREN_MASK (0x100U)
14537 #define SCG_FIRCCSR_FIRCTREN_SHIFT (8U)
14538 /*! FIRCTREN - Fast IRC Trim Enable
14539  *  0b0..Disable trimming Fast IRC to an external clock source
14540  *  0b1..Enable trimming Fast IRC to an external clock source
14541  */
14542 #define SCG_FIRCCSR_FIRCTREN(x) \
14543     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
14544 #define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U)
14545 #define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U)
14546 /*! FIRCTRUP - Fast IRC Trim Update
14547  *  0b0..Disable Fast IRC trimming updates
14548  *  0b1..Enable Fast IRC trimming updates
14549  */
14550 #define SCG_FIRCCSR_FIRCTRUP(x) \
14551     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
14552 #define SCG_FIRCCSR_LK_MASK (0x800000U)
14553 #define SCG_FIRCCSR_LK_SHIFT (23U)
14554 /*! LK - Lock Register
14555  *  0b0..Control Status Register can be written.
14556  *  0b1..Control Status Register cannot be written.
14557  */
14558 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
14559 #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U)
14560 #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U)
14561 /*! FIRCVLD - Fast IRC Valid status
14562  *  0b0..Fast IRC is not enabled or clock is not valid.
14563  *  0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC
14564  * analog.
14565  */
14566 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
14567 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U)
14568 #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U)
14569 /*! FIRCSEL - Fast IRC Selected status
14570  *  0b0..Fast IRC is not the system clock source
14571  *  0b1..Fast IRC is the system clock source
14572  */
14573 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
14574 #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U)
14575 #define SCG_FIRCCSR_FIRCERR_SHIFT (26U)
14576 /*! FIRCERR - Fast IRC Clock Error
14577  *  0b0..Error not detected with the Fast IRC trimming.
14578  *  0b1..Error detected with the Fast IRC trimming.
14579  */
14580 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
14581 /*! @} */
14582 
14583 /*! @name FIRCDIV - Fast IRC Divide Register */
14584 /*! @{ */
14585 #define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U)
14586 #define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U)
14587 /*! FIRCDIV1 - Fast IRC Clock Divide 1
14588  *  0b000..Output disabled
14589  *  0b001..Divide by 1
14590  *  0b010..Divide by 2
14591  *  0b011..Divide by 4
14592  *  0b100..Divide by 8
14593  *  0b101..Divide by 16
14594  *  0b110..Divide by 32
14595  *  0b111..Divide by 64
14596  */
14597 #define SCG_FIRCDIV_FIRCDIV1(x) \
14598     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK)
14599 #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U)
14600 #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U)
14601 /*! FIRCDIV2 - Fast IRC Clock Divide 2
14602  *  0b000..Output disabled
14603  *  0b001..Divide by 1
14604  *  0b010..Divide by 2
14605  *  0b011..Divide by 4
14606  *  0b100..Divide by 8
14607  *  0b101..Divide by 16
14608  *  0b110..Divide by 32
14609  *  0b111..Divide by 64
14610  */
14611 #define SCG_FIRCDIV_FIRCDIV2(x) \
14612     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK)
14613 #define SCG_FIRCDIV_FIRCDIV3_MASK (0x70000U)
14614 #define SCG_FIRCDIV_FIRCDIV3_SHIFT (16U)
14615 /*! FIRCDIV3 - Fast IRC Clock Divider 3
14616  *  0b000..Clock disabled
14617  *  0b001..Divide by 1
14618  *  0b010..Divide by 2
14619  *  0b011..Divide by 4
14620  *  0b100..Divide by 8
14621  *  0b101..Divide by 16
14622  *  0b110..Divide by 32
14623  *  0b111..Divide by 64
14624  */
14625 #define SCG_FIRCDIV_FIRCDIV3(x) \
14626     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK)
14627 /*! @} */
14628 
14629 /*! @name FIRCCFG - Fast IRC Configuration Register */
14630 /*! @{ */
14631 #define SCG_FIRCCFG_RANGE_MASK (0x3U)
14632 #define SCG_FIRCCFG_RANGE_SHIFT (0U)
14633 /*! RANGE - Frequency Range
14634  *  0b00..Fast IRC is trimmed to 48 MHz
14635  *  0b01..Fast IRC is trimmed to 52 MHz
14636  *  0b10..Fast IRC is trimmed to 56 MHz
14637  *  0b11..Fast IRC is trimmed to 60 MHz
14638  */
14639 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
14640 /*! @} */
14641 
14642 /*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
14643 /*! @{ */
14644 #define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U)
14645 #define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U)
14646 /*! TRIMSRC - Trim Source
14647  *  0b00..USB0 Start of Frame (1 kHz)
14648  *  0b01..Reserved
14649  *  0b10..System OSC
14650  *  0b11..Reserved
14651  */
14652 #define SCG_FIRCTCFG_TRIMSRC(x) \
14653     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
14654 #define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U)
14655 #define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U)
14656 /*! TRIMDIV - Fast IRC Trim Predivide
14657  *  0b000..Divide by 1
14658  *  0b001..Divide by 128
14659  *  0b010..Divide by 256
14660  *  0b011..Divide by 512
14661  *  0b100..Divide by 1024
14662  *  0b101..Divide by 2048
14663  *  0b110..Reserved. Writing this value will result in Divide by 1.
14664  *  0b111..Reserved. Writing this value will result in a Divide by 1.
14665  */
14666 #define SCG_FIRCTCFG_TRIMDIV(x) \
14667     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
14668 /*! @} */
14669 
14670 /*! @name FIRCSTAT - Fast IRC Status Register */
14671 /*! @{ */
14672 #define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU)
14673 #define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U)
14674 /*! TRIMFINE - Trim Fine Status
14675  */
14676 #define SCG_FIRCSTAT_TRIMFINE(x) \
14677     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
14678 #define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U)
14679 #define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U)
14680 /*! TRIMCOAR - Trim Coarse
14681  */
14682 #define SCG_FIRCSTAT_TRIMCOAR(x) \
14683     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
14684 /*! @} */
14685 
14686 /*! @name SPLLCSR - System PLL Control Status Register */
14687 /*! @{ */
14688 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U)
14689 #define SCG_SPLLCSR_SPLLEN_SHIFT (0U)
14690 /*! SPLLEN - System PLL Enable
14691  *  0b0..System PLL is disabled
14692  *  0b1..System PLL is enabled
14693  */
14694 #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
14695 #define SCG_SPLLCSR_SPLLSTEN_MASK (0x2U)
14696 #define SCG_SPLLCSR_SPLLSTEN_SHIFT (1U)
14697 /*! SPLLSTEN - System PLL Stop Enable
14698  *  0b0..System PLL is disabled in Stop modes
14699  *  0b1..System PLL is enabled in Stop modes
14700  */
14701 #define SCG_SPLLCSR_SPLLSTEN(x) \
14702     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK)
14703 #define SCG_SPLLCSR_SPLLCM_MASK (0x10000U)
14704 #define SCG_SPLLCSR_SPLLCM_SHIFT (16U)
14705 /*! SPLLCM - System PLL Clock Monitor
14706  *  0b0..System PLL Clock Monitor is disabled
14707  *  0b1..System PLL Clock Monitor is enabled
14708  */
14709 #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK)
14710 #define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U)
14711 #define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U)
14712 /*! SPLLCMRE - System PLL Clock Monitor Reset Enable
14713  *  0b0..Clock Monitor generates interrupt when error detected
14714  *  0b1..Clock Monitor generates reset when error detected
14715  */
14716 #define SCG_SPLLCSR_SPLLCMRE(x) \
14717     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK)
14718 #define SCG_SPLLCSR_LK_MASK (0x800000U)
14719 #define SCG_SPLLCSR_LK_SHIFT (23U)
14720 /*! LK - Lock Register
14721  *  0b0..Control Status Register can be written.
14722  *  0b1..Control Status Register cannot be written.
14723  */
14724 #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK)
14725 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U)
14726 #define SCG_SPLLCSR_SPLLVLD_SHIFT (24U)
14727 /*! SPLLVLD - System PLL Valid
14728  *  0b0..System PLL is not enabled or clock is not valid
14729  *  0b1..System PLL is enabled and output clock is valid
14730  */
14731 #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
14732 #define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U)
14733 #define SCG_SPLLCSR_SPLLSEL_SHIFT (25U)
14734 /*! SPLLSEL - System PLL Selected
14735  *  0b0..System PLL is not the system clock source
14736  *  0b1..System PLL is the system clock source
14737  */
14738 #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK)
14739 #define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U)
14740 #define SCG_SPLLCSR_SPLLERR_SHIFT (26U)
14741 /*! SPLLERR - System PLL Clock Error
14742  *  0b0..System PLL Clock Monitor is disabled or has not detected an error
14743  *  0b1..System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when
14744  *       System OSC is selected as its source and SOSCERR has set.
14745  */
14746 #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK)
14747 /*! @} */
14748 
14749 /*! @name SPLLDIV - System PLL Divide Register */
14750 /*! @{ */
14751 #define SCG_SPLLDIV_SPLLDIV1_MASK (0x7U)
14752 #define SCG_SPLLDIV_SPLLDIV1_SHIFT (0U)
14753 /*! SPLLDIV1 - System PLL Clock Divide 1
14754  *  0b000..Clock disabled
14755  *  0b001..Divide by 1
14756  *  0b010..Divide by 2
14757  *  0b011..Divide by 4
14758  *  0b100..Divide by 8
14759  *  0b101..Divide by 16
14760  *  0b110..Divide by 32
14761  *  0b111..Divide by 64
14762  */
14763 #define SCG_SPLLDIV_SPLLDIV1(x) \
14764     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV1_SHIFT)) & SCG_SPLLDIV_SPLLDIV1_MASK)
14765 #define SCG_SPLLDIV_SPLLDIV2_MASK (0x700U)
14766 #define SCG_SPLLDIV_SPLLDIV2_SHIFT (8U)
14767 /*! SPLLDIV2 - System PLL Clock Divide 2
14768  *  0b000..Clock disabled
14769  *  0b001..Divide by 1
14770  *  0b010..Divide by 2
14771  *  0b011..Divide by 4
14772  *  0b100..Divide by 8
14773  *  0b101..Divide by 16
14774  *  0b110..Divide by 32
14775  *  0b111..Divide by 64
14776  */
14777 #define SCG_SPLLDIV_SPLLDIV2(x) \
14778     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV2_SHIFT)) & SCG_SPLLDIV_SPLLDIV2_MASK)
14779 #define SCG_SPLLDIV_SPLLDIV3_MASK (0x70000U)
14780 #define SCG_SPLLDIV_SPLLDIV3_SHIFT (16U)
14781 /*! SPLLDIV3 - System PLL Clock Divide 3
14782  *  0b000..Clock disabled
14783  *  0b001..Divide by 1
14784  *  0b010..Divide by 2
14785  *  0b011..Divide by 4
14786  *  0b100..Divide by 8
14787  *  0b101..Divide by 16
14788  *  0b110..Divide by 32
14789  *  0b111..Divide by 64
14790  */
14791 #define SCG_SPLLDIV_SPLLDIV3(x) \
14792     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV3_SHIFT)) & SCG_SPLLDIV_SPLLDIV3_MASK)
14793 /*! @} */
14794 
14795 /*! @name SPLLCFG - System PLL Configuration Register */
14796 /*! @{ */
14797 #define SCG_SPLLCFG_SOURCE_MASK (0x1U)
14798 #define SCG_SPLLCFG_SOURCE_SHIFT (0U)
14799 /*! SOURCE - Clock Source
14800  *  0b0..System OSC (SOSC)
14801  *  0b1..Fast IRC (FIRC)
14802  */
14803 #define SCG_SPLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_SOURCE_SHIFT)) & SCG_SPLLCFG_SOURCE_MASK)
14804 #define SCG_SPLLCFG_PREDIV_MASK (0x700U)
14805 #define SCG_SPLLCFG_PREDIV_SHIFT (8U)
14806 /*! PREDIV - PLL Reference Clock Divider
14807  */
14808 #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PREDIV_SHIFT)) & SCG_SPLLCFG_PREDIV_MASK)
14809 #define SCG_SPLLCFG_MULT_MASK (0x1F0000U)
14810 #define SCG_SPLLCFG_MULT_SHIFT (16U)
14811 /*! MULT - System PLL Multiplier
14812  */
14813 #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_MULT_SHIFT)) & SCG_SPLLCFG_MULT_MASK)
14814 /*! @} */
14815 
14816 /*!
14817  * @}
14818  */ /* end of group SCG_Register_Masks */
14819 
14820 /* SCG - Peripheral instance base addresses */
14821 /** Peripheral SCG base address */
14822 #define SCG_BASE (0x4007B000u)
14823 /** Peripheral SCG base pointer */
14824 #define SCG ((SCG_Type *)SCG_BASE)
14825 /** Array initializer of SCG peripheral base addresses */
14826 #define SCG_BASE_ADDRS \
14827     {                  \
14828         SCG_BASE       \
14829     }
14830 /** Array initializer of SCG peripheral base pointers */
14831 #define SCG_BASE_PTRS \
14832     {                 \
14833         SCG           \
14834     }
14835 /** Interrupt vectors for the SCG peripheral type */
14836 #define SCG_IRQS \
14837     {            \
14838         SCG_IRQn \
14839     }
14840 
14841 /*!
14842  * @}
14843  */ /* end of group SCG_Peripheral_Access_Layer */
14844 
14845 /* ----------------------------------------------------------------------------
14846    -- SIM Peripheral Access Layer
14847    ---------------------------------------------------------------------------- */
14848 
14849 /*!
14850  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
14851  * @{
14852  */
14853 
14854 /** SIM - Register Layout Typedef */
14855 typedef struct
14856 {
14857     __IO uint32_t SOPT1;    /**< System Options Register 1, offset: 0x0 */
14858     __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
14859     uint8_t RESERVED_0[4124];
14860     __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
14861     uint8_t RESERVED_1[36];
14862     __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
14863     __I uint32_t FCFG2;  /**< Flash Configuration Register 2, offset: 0x1050 */
14864     uint8_t RESERVED_2[4];
14865     __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
14866     __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
14867     __I uint32_t UIDL;  /**< Unique Identification Register Low, offset: 0x1060 */
14868     uint8_t RESERVED_3[136];
14869     __I uint32_t PCSR; /**< Peripheral Clock Status Register, offset: 0x10EC */
14870 } SIM_Type;
14871 
14872 /* ----------------------------------------------------------------------------
14873    -- SIM Register Masks
14874    ---------------------------------------------------------------------------- */
14875 
14876 /*!
14877  * @addtogroup SIM_Register_Masks SIM Register Masks
14878  * @{
14879  */
14880 
14881 /*! @name SOPT1 - System Options Register 1 */
14882 /*! @{ */
14883 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
14884 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
14885 /*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes
14886  *  0b0..USB voltage regulator not in standby during VLPR and VLPW modes.
14887  *  0b1..USB voltage regulator in standby during VLPR and VLPW modes.
14888  */
14889 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
14890 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
14891 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
14892 /*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
14893  *  0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
14894  *  0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
14895  */
14896 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
14897 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
14898 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
14899 /*! USBREGEN - USB voltage regulator enable
14900  *  0b0..USB voltage regulator is disabled.
14901  *  0b1..USB voltage regulator is enabled.
14902  */
14903 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
14904 /*! @} */
14905 
14906 /*! @name SOPT1CFG - SOPT1 Configuration Register */
14907 /*! @{ */
14908 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
14909 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
14910 /*! URWE - USB voltage regulator enable write enable
14911  *  0b0..SOPT1 USBREGEN cannot be written.
14912  *  0b1..SOPT1 USBREGEN can be written.
14913  */
14914 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
14915 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
14916 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
14917 /*! UVSWE - USB voltage regulator VLP standby write enable
14918  *  0b0..SOPT1 USBVSTB cannot be written.
14919  *  0b1..SOPT1 USBVSTB can be written.
14920  */
14921 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
14922 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
14923 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
14924 /*! USSWE - USB voltage regulator stop standby write enable
14925  *  0b0..SOPT1 USBSSTB cannot be written.
14926  *  0b1..SOPT1 USBSSTB can be written.
14927  */
14928 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
14929 /*! @} */
14930 
14931 /*! @name SDID - System Device Identification Register */
14932 /*! @{ */
14933 #define SIM_SDID_PINID_MASK (0xFU)
14934 #define SIM_SDID_PINID_SHIFT (0U)
14935 /*! PINID - Pin count identification
14936  *  0b0000..Reserved
14937  *  0b0001..Reserved
14938  *  0b0010..Reserved
14939  *  0b0011..Reserved
14940  *  0b0100..Reserved
14941  *  0b0101..Reserved
14942  *  0b0110..Reserved
14943  *  0b0111..Reserved
14944  *  0b1000..100-pin
14945  *  0b1001..121-pin
14946  *  0b1010..Reserved
14947  *  0b1011..Reserved
14948  *  0b1100..Reserved
14949  *  0b1101..Reserved
14950  *  0b1110..Reserved
14951  *  0b1111..Reserved
14952  */
14953 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
14954 #define SIM_SDID_KEYATT_MASK (0x70U)
14955 #define SIM_SDID_KEYATT_SHIFT (4U)
14956 /*! KEYATT - Core configuration of the device.
14957  *  0b000..Cortex CM0+ Core
14958  *  0b001..Reserved
14959  *  0b010..Reserved
14960  *  0b011..Reserved
14961  *  0b100..Reserved
14962  *  0b101..Reserved
14963  *  0b110..Reserved
14964  *  0b111..Reserved
14965  */
14966 #define SIM_SDID_KEYATT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_KEYATT_SHIFT)) & SIM_SDID_KEYATT_MASK)
14967 #define SIM_SDID_DIEID_MASK (0xF80U)
14968 #define SIM_SDID_DIEID_SHIFT (7U)
14969 /*! DIEID - Device Die Number
14970  */
14971 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
14972 #define SIM_SDID_REVID_MASK (0xF000U)
14973 #define SIM_SDID_REVID_SHIFT (12U)
14974 /*! REVID - Device Revision Number
14975  *  0b0001..Revision 1.1
14976  */
14977 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
14978 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
14979 #define SIM_SDID_SRAMSIZE_SHIFT (16U)
14980 /*! SRAMSIZE - System SRAM Size
14981  *  0b1000..96 KB
14982  *  0b1001..128 KB
14983  */
14984 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
14985 #define SIM_SDID_SERIESID_MASK (0xF00000U)
14986 #define SIM_SDID_SERIESID_SHIFT (20U)
14987 /*! SERIESID - Kinetis Series ID
14988  *  0b0001..KL family
14989  */
14990 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
14991 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
14992 #define SIM_SDID_SUBFAMID_SHIFT (24U)
14993 /*! SUBFAMID - Kinetis Sub-Family ID
14994  *  0b0010..KLx2 Subfamily
14995  *  0b0011..KLx3 Subfamily
14996  *  0b0100..KLx4 Subfamily
14997  *  0b0101..KLx5 Subfamily
14998  *  0b0110..KLx6 Subfamily
14999  *  0b0111..KLx7 Subfamily
15000  *  0b1000..KLx8 Subfamily
15001  *  0b1001..KLx9 Subfamily
15002  */
15003 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
15004 #define SIM_SDID_FAMID_MASK (0xF0000000U)
15005 #define SIM_SDID_FAMID_SHIFT (28U)
15006 /*! FAMID - Kinetis family ID
15007  *  0b0010..KL2x Family (USB)
15008  */
15009 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
15010 /*! @} */
15011 
15012 /*! @name FCFG1 - Flash Configuration Register 1 */
15013 /*! @{ */
15014 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
15015 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
15016 /*! FLASHDIS - Flash Disable
15017  *  0b0..Flash is enabled.
15018  *  0b1..Flash is disabled.
15019  */
15020 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
15021 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
15022 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
15023 /*! FLASHDOZE - Flash Doze
15024  *  0b0..Flash remains enabled during Doze mode.
15025  *  0b1..Flash is disabled for the duration of Doze mode.
15026  */
15027 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
15028 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
15029 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
15030 /*! PFSIZE - Program Flash Size
15031  *  0b0101..64 KB of program flash memory, 2 KB protection region
15032  *  0b0111..128 KB of program flash memory, 4 KB protection region
15033  *  0b1001..256 KB of program flash memory, 8 KB protection region
15034  *  0b1011..512 KB of program flash memory, 16 KB protection region
15035  */
15036 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
15037 /*! @} */
15038 
15039 /*! @name FCFG2 - Flash Configuration Register 2 */
15040 /*! @{ */
15041 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
15042 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
15043 /*! MAXADDR0 - Max Address lock
15044  */
15045 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
15046 /*! @} */
15047 
15048 /*! @name UIDMH - Unique Identification Register Mid-High */
15049 /*! @{ */
15050 #define SIM_UIDMH_UID_MASK (0xFFFFU)
15051 #define SIM_UIDMH_UID_SHIFT (0U)
15052 /*! UID - Unique Identification
15053  */
15054 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
15055 /*! @} */
15056 
15057 /*! @name UIDML - Unique Identification Register Mid Low */
15058 /*! @{ */
15059 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
15060 #define SIM_UIDML_UID_SHIFT (0U)
15061 /*! UID - Unique Identification
15062  */
15063 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
15064 /*! @} */
15065 
15066 /*! @name UIDL - Unique Identification Register Low */
15067 /*! @{ */
15068 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
15069 #define SIM_UIDL_UID_SHIFT (0U)
15070 /*! UID - Unique Identification
15071  */
15072 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
15073 /*! @} */
15074 
15075 /*! @name PCSR - Peripheral Clock Status Register */
15076 /*! @{ */
15077 #define SIM_PCSR_CS1_MASK (0x2U)
15078 #define SIM_PCSR_CS1_SHIFT (1U)
15079 /*! CS1 - Clock Source 1
15080  *  0b0..Clock not ready.
15081  *  0b1..Clock ready.
15082  */
15083 #define SIM_PCSR_CS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS1_SHIFT)) & SIM_PCSR_CS1_MASK)
15084 #define SIM_PCSR_CS2_MASK (0x4U)
15085 #define SIM_PCSR_CS2_SHIFT (2U)
15086 /*! CS2 - Clock Source 2
15087  *  0b0..Clock not ready.
15088  *  0b1..Clock ready.
15089  */
15090 #define SIM_PCSR_CS2(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS2_SHIFT)) & SIM_PCSR_CS2_MASK)
15091 #define SIM_PCSR_CS3_MASK (0x8U)
15092 #define SIM_PCSR_CS3_SHIFT (3U)
15093 /*! CS3 - Clock Source 3
15094  *  0b0..Clock not ready.
15095  *  0b1..Clock ready.
15096  */
15097 #define SIM_PCSR_CS3(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS3_SHIFT)) & SIM_PCSR_CS3_MASK)
15098 #define SIM_PCSR_CS4_MASK (0x10U)
15099 #define SIM_PCSR_CS4_SHIFT (4U)
15100 /*! CS4 - Clock Source 4
15101  *  0b0..Clock not ready.
15102  *  0b1..Clock ready.
15103  */
15104 #define SIM_PCSR_CS4(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS4_SHIFT)) & SIM_PCSR_CS4_MASK)
15105 #define SIM_PCSR_CS5_MASK (0x20U)
15106 #define SIM_PCSR_CS5_SHIFT (5U)
15107 /*! CS5 - Clock Source 5
15108  *  0b0..Clock not ready.
15109  *  0b1..Clock ready.
15110  */
15111 #define SIM_PCSR_CS5(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS5_SHIFT)) & SIM_PCSR_CS5_MASK)
15112 #define SIM_PCSR_CS6_MASK (0x40U)
15113 #define SIM_PCSR_CS6_SHIFT (6U)
15114 /*! CS6 - Clock Source 6
15115  *  0b0..Clock not ready.
15116  *  0b1..Clock ready.
15117  */
15118 #define SIM_PCSR_CS6(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS6_SHIFT)) & SIM_PCSR_CS6_MASK)
15119 #define SIM_PCSR_CS7_MASK (0x80U)
15120 #define SIM_PCSR_CS7_SHIFT (7U)
15121 /*! CS7 - Clock Source 7
15122  *  0b0..Clock not ready.
15123  *  0b1..Clock ready.
15124  */
15125 #define SIM_PCSR_CS7(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS7_SHIFT)) & SIM_PCSR_CS7_MASK)
15126 /*! @} */
15127 
15128 /*!
15129  * @}
15130  */ /* end of group SIM_Register_Masks */
15131 
15132 /* SIM - Peripheral instance base addresses */
15133 /** Peripheral SIM base address */
15134 #define SIM_BASE (0x40074000u)
15135 /** Peripheral SIM base pointer */
15136 #define SIM ((SIM_Type *)SIM_BASE)
15137 /** Array initializer of SIM peripheral base addresses */
15138 #define SIM_BASE_ADDRS \
15139     {                  \
15140         SIM_BASE       \
15141     }
15142 /** Array initializer of SIM peripheral base pointers */
15143 #define SIM_BASE_PTRS \
15144     {                 \
15145         SIM           \
15146     }
15147 
15148 /*!
15149  * @}
15150  */ /* end of group SIM_Peripheral_Access_Layer */
15151 
15152 /* ----------------------------------------------------------------------------
15153    -- SMC Peripheral Access Layer
15154    ---------------------------------------------------------------------------- */
15155 
15156 /*!
15157  * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
15158  * @{
15159  */
15160 
15161 /** SMC - Register Layout Typedef */
15162 typedef struct
15163 {
15164     __I uint32_t VERID;     /**< SMC Version ID Register, offset: 0x0 */
15165     __I uint32_t PARAM;     /**< SMC Parameter Register, offset: 0x4 */
15166     __IO uint32_t PMPROT;   /**< Power Mode Protection register, offset: 0x8 */
15167     __IO uint32_t PMCTRL;   /**< Power Mode Control register, offset: 0xC */
15168     __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
15169     __I uint32_t PMSTAT;    /**< Power Mode Status register, offset: 0x14 */
15170 } SMC_Type;
15171 
15172 /* ----------------------------------------------------------------------------
15173    -- SMC Register Masks
15174    ---------------------------------------------------------------------------- */
15175 
15176 /*!
15177  * @addtogroup SMC_Register_Masks SMC Register Masks
15178  * @{
15179  */
15180 
15181 /*! @name VERID - SMC Version ID Register */
15182 /*! @{ */
15183 #define SMC_VERID_FEATURE_MASK (0xFFFFU)
15184 #define SMC_VERID_FEATURE_SHIFT (0U)
15185 /*! FEATURE - Feature Specification Number
15186  *  0b0000000000000000..Standard features implemented
15187  */
15188 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK)
15189 #define SMC_VERID_MINOR_MASK (0xFF0000U)
15190 #define SMC_VERID_MINOR_SHIFT (16U)
15191 /*! MINOR - Minor Version Number
15192  */
15193 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK)
15194 #define SMC_VERID_MAJOR_MASK (0xFF000000U)
15195 #define SMC_VERID_MAJOR_SHIFT (24U)
15196 /*! MAJOR - Major Version Number
15197  */
15198 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK)
15199 /*! @} */
15200 
15201 /*! @name PARAM - SMC Parameter Register */
15202 /*! @{ */
15203 #define SMC_PARAM_EHSRUN_MASK (0x1U)
15204 #define SMC_PARAM_EHSRUN_SHIFT (0U)
15205 /*! EHSRUN - Existence of HSRUN feature
15206  *  0b0..The feature is not available.
15207  *  0b1..The feature is available.
15208  */
15209 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK)
15210 #define SMC_PARAM_ELLS_MASK (0x8U)
15211 #define SMC_PARAM_ELLS_SHIFT (3U)
15212 /*! ELLS - Existence of LLS feature
15213  *  0b0..The feature is not available.
15214  *  0b1..The feature is available.
15215  */
15216 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK)
15217 #define SMC_PARAM_ELLS2_MASK (0x20U)
15218 #define SMC_PARAM_ELLS2_SHIFT (5U)
15219 /*! ELLS2 - Existence of LLS2 feature
15220  *  0b0..The feature is not available.
15221  *  0b1..The feature is available.
15222  */
15223 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK)
15224 #define SMC_PARAM_EVLLS0_MASK (0x40U)
15225 #define SMC_PARAM_EVLLS0_SHIFT (6U)
15226 /*! EVLLS0 - Existence of VLLS0 feature
15227  *  0b0..The feature is not available.
15228  *  0b1..The feature is available.
15229  */
15230 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK)
15231 /*! @} */
15232 
15233 /*! @name PMPROT - Power Mode Protection register */
15234 /*! @{ */
15235 #define SMC_PMPROT_AVLLS_MASK (0x2U)
15236 #define SMC_PMPROT_AVLLS_SHIFT (1U)
15237 /*! AVLLS - Allow Very-Low-Leakage Stop Mode
15238  *  0b0..Any VLLSx mode is not allowed
15239  *  0b1..Any VLLSx mode is allowed
15240  */
15241 #define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
15242 #define SMC_PMPROT_ALLS_MASK (0x8U)
15243 #define SMC_PMPROT_ALLS_SHIFT (3U)
15244 /*! ALLS - Allow Low-Leakage Stop Mode
15245  *  0b0..Any LLSx mode is not allowed
15246  *  0b1..Any LLSx mode is allowed
15247  */
15248 #define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
15249 #define SMC_PMPROT_AVLP_MASK (0x20U)
15250 #define SMC_PMPROT_AVLP_SHIFT (5U)
15251 /*! AVLP - Allow Very-Low-Power Modes
15252  *  0b0..VLPR, VLPW, and VLPS are not allowed.
15253  *  0b1..VLPR, VLPW, and VLPS are allowed.
15254  */
15255 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
15256 #define SMC_PMPROT_AHSRUN_MASK (0x80U)
15257 #define SMC_PMPROT_AHSRUN_SHIFT (7U)
15258 /*! AHSRUN - Allow High Speed Run mode
15259  *  0b0..HSRUN is not allowed
15260  *  0b1..HSRUN is allowed
15261  */
15262 #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
15263 /*! @} */
15264 
15265 /*! @name PMCTRL - Power Mode Control register */
15266 /*! @{ */
15267 #define SMC_PMCTRL_STOPM_MASK (0x7U)
15268 #define SMC_PMCTRL_STOPM_SHIFT (0U)
15269 /*! STOPM - Stop Mode Control
15270  *  0b000..Normal Stop (STOP)
15271  *  0b001..Reserved
15272  *  0b010..Very-Low-Power Stop (VLPS)
15273  *  0b011..Low-Leakage Stop (LLSx)
15274  *  0b100..Very-Low-Leakage Stop (VLLSx)
15275  *  0b101..Reserved
15276  *  0b110..Reseved
15277  *  0b111..Reserved
15278  */
15279 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
15280 #define SMC_PMCTRL_STOPA_MASK (0x8U)
15281 #define SMC_PMCTRL_STOPA_SHIFT (3U)
15282 /*! STOPA - Stop Aborted
15283  *  0b0..The previous stop mode entry was successful.
15284  *  0b1..The previous stop mode entry was aborted.
15285  */
15286 #define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
15287 #define SMC_PMCTRL_RUNM_MASK (0x60U)
15288 #define SMC_PMCTRL_RUNM_SHIFT (5U)
15289 /*! RUNM - Run Mode Control
15290  *  0b00..Normal Run mode (RUN)
15291  *  0b01..Reserved
15292  *  0b10..Very-Low-Power Run mode (VLPR)
15293  *  0b11..High Speed Run mode (HSRUN)
15294  */
15295 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
15296 /*! @} */
15297 
15298 /*! @name STOPCTRL - Stop Control Register */
15299 /*! @{ */
15300 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
15301 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
15302 /*! LLSM - LLS or VLLS Mode Control
15303  *  0b000..VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
15304  *  0b001..VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
15305  *  0b010..VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
15306  *  0b011..VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
15307  *  0b100..Reserved
15308  *  0b101..Reserved
15309  *  0b110..Reserved
15310  *  0b111..Reserved
15311  */
15312 #define SMC_STOPCTRL_LLSM(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
15313 #define SMC_STOPCTRL_LPOPO_MASK (0x8U)
15314 #define SMC_STOPCTRL_LPOPO_SHIFT (3U)
15315 /*! LPOPO - LPO Power Option
15316  *  0b0..LPO clock is enabled in LLS/VLLSx
15317  *  0b1..LPO clock is disabled in LLS/VLLSx
15318  */
15319 #define SMC_STOPCTRL_LPOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
15320 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
15321 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
15322 /*! PORPO - POR Power Option
15323  *  0b0..POR detect circuit is enabled in VLLS0
15324  *  0b1..POR detect circuit is disabled in VLLS0
15325  */
15326 #define SMC_STOPCTRL_PORPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
15327 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
15328 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
15329 /*! PSTOPO - Partial Stop Option
15330  *  0b00..STOP - Normal Stop mode
15331  *  0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
15332  *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
15333  *  0b11..Reserved
15334  */
15335 #define SMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
15336 /*! @} */
15337 
15338 /*! @name PMSTAT - Power Mode Status register */
15339 /*! @{ */
15340 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
15341 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
15342 /*! PMSTAT - Power Mode Status
15343  */
15344 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
15345 /*! @} */
15346 
15347 /*!
15348  * @}
15349  */ /* end of group SMC_Register_Masks */
15350 
15351 /* SMC - Peripheral instance base addresses */
15352 /** Peripheral SMC base address */
15353 #define SMC_BASE (0x4007E000u)
15354 /** Peripheral SMC base pointer */
15355 #define SMC ((SMC_Type *)SMC_BASE)
15356 /** Array initializer of SMC peripheral base addresses */
15357 #define SMC_BASE_ADDRS \
15358     {                  \
15359         SMC_BASE       \
15360     }
15361 /** Array initializer of SMC peripheral base pointers */
15362 #define SMC_BASE_PTRS \
15363     {                 \
15364         SMC           \
15365     }
15366 
15367 /*!
15368  * @}
15369  */ /* end of group SMC_Peripheral_Access_Layer */
15370 
15371 /* ----------------------------------------------------------------------------
15372    -- TPM Peripheral Access Layer
15373    ---------------------------------------------------------------------------- */
15374 
15375 /*!
15376  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
15377  * @{
15378  */
15379 
15380 /** TPM - Register Layout Typedef */
15381 typedef struct
15382 {
15383     __I uint32_t VERID;   /**< Version ID Register, offset: 0x0 */
15384     __I uint32_t PARAM;   /**< Parameter Register, offset: 0x4 */
15385     __IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */
15386     uint8_t RESERVED_0[4];
15387     __IO uint32_t SC;     /**< Status and Control, offset: 0x10 */
15388     __IO uint32_t CNT;    /**< Counter, offset: 0x14 */
15389     __IO uint32_t MOD;    /**< Modulo, offset: 0x18 */
15390     __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */
15391     struct
15392     {                       /* offset: 0x20, array step: 0x8 */
15393         __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
15394         __IO uint32_t CnV;  /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
15395     } CONTROLS[6];
15396     uint8_t RESERVED_1[20];
15397     __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
15398     uint8_t RESERVED_2[4];
15399     __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */
15400     __IO uint32_t POL;  /**< Channel Polarity, offset: 0x70 */
15401     uint8_t RESERVED_3[4];
15402     __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
15403     uint8_t RESERVED_4[4];
15404     __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
15405     __IO uint32_t CONF;   /**< Configuration, offset: 0x84 */
15406 } TPM_Type;
15407 
15408 /* ----------------------------------------------------------------------------
15409    -- TPM Register Masks
15410    ---------------------------------------------------------------------------- */
15411 
15412 /*!
15413  * @addtogroup TPM_Register_Masks TPM Register Masks
15414  * @{
15415  */
15416 
15417 /*! @name VERID - Version ID Register */
15418 /*! @{ */
15419 #define TPM_VERID_FEATURE_MASK (0xFFFFU)
15420 #define TPM_VERID_FEATURE_SHIFT (0U)
15421 /*! FEATURE - Feature Identification Number
15422  *  0b0000000000000001..Standard feature set.
15423  *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
15424  *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
15425  */
15426 #define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
15427 #define TPM_VERID_MINOR_MASK (0xFF0000U)
15428 #define TPM_VERID_MINOR_SHIFT (16U)
15429 /*! MINOR - Minor Version Number
15430  */
15431 #define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
15432 #define TPM_VERID_MAJOR_MASK (0xFF000000U)
15433 #define TPM_VERID_MAJOR_SHIFT (24U)
15434 /*! MAJOR - Major Version Number
15435  */
15436 #define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
15437 /*! @} */
15438 
15439 /*! @name PARAM - Parameter Register */
15440 /*! @{ */
15441 #define TPM_PARAM_CHAN_MASK (0xFFU)
15442 #define TPM_PARAM_CHAN_SHIFT (0U)
15443 /*! CHAN - Channel Count
15444  */
15445 #define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
15446 #define TPM_PARAM_TRIG_MASK (0xFF00U)
15447 #define TPM_PARAM_TRIG_SHIFT (8U)
15448 /*! TRIG - Trigger Count
15449  */
15450 #define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
15451 #define TPM_PARAM_WIDTH_MASK (0xFF0000U)
15452 #define TPM_PARAM_WIDTH_SHIFT (16U)
15453 /*! WIDTH - Counter Width
15454  */
15455 #define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
15456 /*! @} */
15457 
15458 /*! @name GLOBAL - TPM Global Register */
15459 /*! @{ */
15460 #define TPM_GLOBAL_RST_MASK (0x2U)
15461 #define TPM_GLOBAL_RST_SHIFT (1U)
15462 /*! RST - Software Reset
15463  *  0b0..Module is not reset.
15464  *  0b1..Module is reset.
15465  */
15466 #define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
15467 /*! @} */
15468 
15469 /*! @name SC - Status and Control */
15470 /*! @{ */
15471 #define TPM_SC_PS_MASK (0x7U)
15472 #define TPM_SC_PS_SHIFT (0U)
15473 /*! PS - Prescale Factor Selection
15474  *  0b000..Divide by 1
15475  *  0b001..Divide by 2
15476  *  0b010..Divide by 4
15477  *  0b011..Divide by 8
15478  *  0b100..Divide by 16
15479  *  0b101..Divide by 32
15480  *  0b110..Divide by 64
15481  *  0b111..Divide by 128
15482  */
15483 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
15484 #define TPM_SC_CMOD_MASK (0x18U)
15485 #define TPM_SC_CMOD_SHIFT (3U)
15486 /*! CMOD - Clock Mode Selection
15487  *  0b00..TPM counter is disabled
15488  *  0b01..TPM counter increments on every TPM counter clock
15489  *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
15490  *  0b11..TPM counter increments on rising edge of the selected external input trigger.
15491  */
15492 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
15493 #define TPM_SC_CPWMS_MASK (0x20U)
15494 #define TPM_SC_CPWMS_SHIFT (5U)
15495 /*! CPWMS - Center-Aligned PWM Select
15496  *  0b0..TPM counter operates in up counting mode.
15497  *  0b1..TPM counter operates in up-down counting mode.
15498  */
15499 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
15500 #define TPM_SC_TOIE_MASK (0x40U)
15501 #define TPM_SC_TOIE_SHIFT (6U)
15502 /*! TOIE - Timer Overflow Interrupt Enable
15503  *  0b0..Disable TOF interrupts. Use software polling or DMA request.
15504  *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
15505  */
15506 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
15507 #define TPM_SC_TOF_MASK (0x80U)
15508 #define TPM_SC_TOF_SHIFT (7U)
15509 /*! TOF - Timer Overflow Flag
15510  *  0b0..TPM counter has not overflowed.
15511  *  0b1..TPM counter has overflowed.
15512  */
15513 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
15514 #define TPM_SC_DMA_MASK (0x100U)
15515 #define TPM_SC_DMA_SHIFT (8U)
15516 /*! DMA - DMA Enable
15517  *  0b0..Disables DMA transfers.
15518  *  0b1..Enables DMA transfers.
15519  */
15520 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
15521 /*! @} */
15522 
15523 /*! @name CNT - Counter */
15524 /*! @{ */
15525 #define TPM_CNT_COUNT_MASK (0xFFFFU)
15526 #define TPM_CNT_COUNT_SHIFT (0U)
15527 /*! COUNT - Counter value
15528  */
15529 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
15530 /*! @} */
15531 
15532 /*! @name MOD - Modulo */
15533 /*! @{ */
15534 #define TPM_MOD_MOD_MASK (0xFFFFU)
15535 #define TPM_MOD_MOD_SHIFT (0U)
15536 /*! MOD - Modulo value
15537  */
15538 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
15539 /*! @} */
15540 
15541 /*! @name STATUS - Capture and Compare Status */
15542 /*! @{ */
15543 #define TPM_STATUS_CH0F_MASK (0x1U)
15544 #define TPM_STATUS_CH0F_SHIFT (0U)
15545 /*! CH0F - Channel 0 Flag
15546  *  0b0..No channel event has occurred.
15547  *  0b1..A channel event has occurred.
15548  */
15549 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
15550 #define TPM_STATUS_CH1F_MASK (0x2U)
15551 #define TPM_STATUS_CH1F_SHIFT (1U)
15552 /*! CH1F - Channel 1 Flag
15553  *  0b0..No channel event has occurred.
15554  *  0b1..A channel event has occurred.
15555  */
15556 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
15557 #define TPM_STATUS_CH2F_MASK (0x4U)
15558 #define TPM_STATUS_CH2F_SHIFT (2U)
15559 /*! CH2F - Channel 2 Flag
15560  *  0b0..No channel event has occurred.
15561  *  0b1..A channel event has occurred.
15562  */
15563 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
15564 #define TPM_STATUS_CH3F_MASK (0x8U)
15565 #define TPM_STATUS_CH3F_SHIFT (3U)
15566 /*! CH3F - Channel 3 Flag
15567  *  0b0..No channel event has occurred.
15568  *  0b1..A channel event has occurred.
15569  */
15570 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
15571 #define TPM_STATUS_CH4F_MASK (0x10U)
15572 #define TPM_STATUS_CH4F_SHIFT (4U)
15573 /*! CH4F - Channel 4 Flag
15574  *  0b0..No channel event has occurred.
15575  *  0b1..A channel event has occurred.
15576  */
15577 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
15578 #define TPM_STATUS_CH5F_MASK (0x20U)
15579 #define TPM_STATUS_CH5F_SHIFT (5U)
15580 /*! CH5F - Channel 5 Flag
15581  *  0b0..No channel event has occurred.
15582  *  0b1..A channel event has occurred.
15583  */
15584 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
15585 #define TPM_STATUS_TOF_MASK (0x100U)
15586 #define TPM_STATUS_TOF_SHIFT (8U)
15587 /*! TOF - Timer Overflow Flag
15588  *  0b0..TPM counter has not overflowed.
15589  *  0b1..TPM counter has overflowed.
15590  */
15591 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
15592 /*! @} */
15593 
15594 /*! @name CnSC - Channel (n) Status and Control */
15595 /*! @{ */
15596 #define TPM_CnSC_DMA_MASK (0x1U)
15597 #define TPM_CnSC_DMA_SHIFT (0U)
15598 /*! DMA - DMA Enable
15599  *  0b0..Disable DMA transfers.
15600  *  0b1..Enable DMA transfers.
15601  */
15602 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
15603 #define TPM_CnSC_ELSA_MASK (0x4U)
15604 #define TPM_CnSC_ELSA_SHIFT (2U)
15605 /*! ELSA - Edge or Level Select
15606  */
15607 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
15608 #define TPM_CnSC_ELSB_MASK (0x8U)
15609 #define TPM_CnSC_ELSB_SHIFT (3U)
15610 /*! ELSB - Edge or Level Select
15611  */
15612 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
15613 #define TPM_CnSC_MSA_MASK (0x10U)
15614 #define TPM_CnSC_MSA_SHIFT (4U)
15615 /*! MSA - Channel Mode Select
15616  */
15617 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
15618 #define TPM_CnSC_MSB_MASK (0x20U)
15619 #define TPM_CnSC_MSB_SHIFT (5U)
15620 /*! MSB - Channel Mode Select
15621  */
15622 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
15623 #define TPM_CnSC_CHIE_MASK (0x40U)
15624 #define TPM_CnSC_CHIE_SHIFT (6U)
15625 /*! CHIE - Channel Interrupt Enable
15626  *  0b0..Disable channel interrupts.
15627  *  0b1..Enable channel interrupts.
15628  */
15629 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
15630 #define TPM_CnSC_CHF_MASK (0x80U)
15631 #define TPM_CnSC_CHF_SHIFT (7U)
15632 /*! CHF - Channel Flag
15633  *  0b0..No channel event has occurred.
15634  *  0b1..A channel event has occurred.
15635  */
15636 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
15637 /*! @} */
15638 
15639 /* The count of TPM_CnSC */
15640 #define TPM_CnSC_COUNT (6U)
15641 
15642 /*! @name CnV - Channel (n) Value */
15643 /*! @{ */
15644 #define TPM_CnV_VAL_MASK (0xFFFFU)
15645 #define TPM_CnV_VAL_SHIFT (0U)
15646 /*! VAL - Channel Value
15647  */
15648 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
15649 /*! @} */
15650 
15651 /* The count of TPM_CnV */
15652 #define TPM_CnV_COUNT (6U)
15653 
15654 /*! @name COMBINE - Combine Channel Register */
15655 /*! @{ */
15656 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
15657 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
15658 /*! COMBINE0 - Combine Channels 0 and 1
15659  *  0b0..Channels 0 and 1 are independent.
15660  *  0b1..Channels 0 and 1 are combined.
15661  */
15662 #define TPM_COMBINE_COMBINE0(x) \
15663     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
15664 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
15665 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
15666 /*! COMSWAP0 - Combine Channel 0 and 1 Swap
15667  *  0b0..Even channel is used for input capture and 1st compare.
15668  *  0b1..Odd channel is used for input capture and 1st compare.
15669  */
15670 #define TPM_COMBINE_COMSWAP0(x) \
15671     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
15672 #define TPM_COMBINE_COMBINE1_MASK (0x100U)
15673 #define TPM_COMBINE_COMBINE1_SHIFT (8U)
15674 /*! COMBINE1 - Combine Channels 2 and 3
15675  *  0b0..Channels 2 and 3 are independent.
15676  *  0b1..Channels 2 and 3 are combined.
15677  */
15678 #define TPM_COMBINE_COMBINE1(x) \
15679     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
15680 #define TPM_COMBINE_COMSWAP1_MASK (0x200U)
15681 #define TPM_COMBINE_COMSWAP1_SHIFT (9U)
15682 /*! COMSWAP1 - Combine Channels 2 and 3 Swap
15683  *  0b0..Even channel is used for input capture and 1st compare.
15684  *  0b1..Odd channel is used for input capture and 1st compare.
15685  */
15686 #define TPM_COMBINE_COMSWAP1(x) \
15687     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
15688 #define TPM_COMBINE_COMBINE2_MASK (0x10000U)
15689 #define TPM_COMBINE_COMBINE2_SHIFT (16U)
15690 /*! COMBINE2 - Combine Channels 4 and 5
15691  *  0b0..Channels 4 and 5 are independent.
15692  *  0b1..Channels 4 and 5 are combined.
15693  */
15694 #define TPM_COMBINE_COMBINE2(x) \
15695     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
15696 #define TPM_COMBINE_COMSWAP2_MASK (0x20000U)
15697 #define TPM_COMBINE_COMSWAP2_SHIFT (17U)
15698 /*! COMSWAP2 - Combine Channels 4 and 5 Swap
15699  *  0b0..Even channel is used for input capture and 1st compare.
15700  *  0b1..Odd channel is used for input capture and 1st compare.
15701  */
15702 #define TPM_COMBINE_COMSWAP2(x) \
15703     (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
15704 /*! @} */
15705 
15706 /*! @name TRIG - Channel Trigger */
15707 /*! @{ */
15708 #define TPM_TRIG_TRIG0_MASK (0x1U)
15709 #define TPM_TRIG_TRIG0_SHIFT (0U)
15710 /*! TRIG0 - Channel 0 Trigger
15711  *  0b0..No effect.
15712  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15713  */
15714 #define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
15715 #define TPM_TRIG_TRIG1_MASK (0x2U)
15716 #define TPM_TRIG_TRIG1_SHIFT (1U)
15717 /*! TRIG1 - Channel 1 Trigger
15718  *  0b0..No effect.
15719  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15720  */
15721 #define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
15722 #define TPM_TRIG_TRIG2_MASK (0x4U)
15723 #define TPM_TRIG_TRIG2_SHIFT (2U)
15724 /*! TRIG2 - Channel 2 Trigger
15725  *  0b0..No effect.
15726  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15727  */
15728 #define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
15729 #define TPM_TRIG_TRIG3_MASK (0x8U)
15730 #define TPM_TRIG_TRIG3_SHIFT (3U)
15731 /*! TRIG3 - Channel 3 Trigger
15732  *  0b0..No effect.
15733  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15734  */
15735 #define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
15736 #define TPM_TRIG_TRIG4_MASK (0x10U)
15737 #define TPM_TRIG_TRIG4_SHIFT (4U)
15738 /*! TRIG4 - Channel 4 Trigger
15739  *  0b0..No effect.
15740  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15741  */
15742 #define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
15743 #define TPM_TRIG_TRIG5_MASK (0x20U)
15744 #define TPM_TRIG_TRIG5_SHIFT (5U)
15745 /*! TRIG5 - Channel 5 Trigger
15746  *  0b0..No effect.
15747  *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
15748  */
15749 #define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
15750 /*! @} */
15751 
15752 /*! @name POL - Channel Polarity */
15753 /*! @{ */
15754 #define TPM_POL_POL0_MASK (0x1U)
15755 #define TPM_POL_POL0_SHIFT (0U)
15756 /*! POL0 - Channel 0 Polarity
15757  *  0b0..The channel polarity is active high.
15758  *  0b1..The channel polarity is active low.
15759  */
15760 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
15761 #define TPM_POL_POL1_MASK (0x2U)
15762 #define TPM_POL_POL1_SHIFT (1U)
15763 /*! POL1 - Channel 1 Polarity
15764  *  0b0..The channel polarity is active high.
15765  *  0b1..The channel polarity is active low.
15766  */
15767 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
15768 #define TPM_POL_POL2_MASK (0x4U)
15769 #define TPM_POL_POL2_SHIFT (2U)
15770 /*! POL2 - Channel 2 Polarity
15771  *  0b0..The channel polarity is active high.
15772  *  0b1..The channel polarity is active low.
15773  */
15774 #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
15775 #define TPM_POL_POL3_MASK (0x8U)
15776 #define TPM_POL_POL3_SHIFT (3U)
15777 /*! POL3 - Channel 3 Polarity
15778  *  0b0..The channel polarity is active high.
15779  *  0b1..The channel polarity is active low.
15780  */
15781 #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
15782 #define TPM_POL_POL4_MASK (0x10U)
15783 #define TPM_POL_POL4_SHIFT (4U)
15784 /*! POL4 - Channel 4 Polarity
15785  *  0b0..The channel polarity is active high
15786  *  0b1..The channel polarity is active low.
15787  */
15788 #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
15789 #define TPM_POL_POL5_MASK (0x20U)
15790 #define TPM_POL_POL5_SHIFT (5U)
15791 /*! POL5 - Channel 5 Polarity
15792  *  0b0..The channel polarity is active high.
15793  *  0b1..The channel polarity is active low.
15794  */
15795 #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
15796 /*! @} */
15797 
15798 /*! @name FILTER - Filter Control */
15799 /*! @{ */
15800 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
15801 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
15802 /*! CH0FVAL - Channel 0 Filter Value
15803  */
15804 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
15805 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
15806 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
15807 /*! CH1FVAL - Channel 1 Filter Value
15808  */
15809 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
15810 #define TPM_FILTER_CH2FVAL_MASK (0xF00U)
15811 #define TPM_FILTER_CH2FVAL_SHIFT (8U)
15812 /*! CH2FVAL - Channel 2 Filter Value
15813  */
15814 #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
15815 #define TPM_FILTER_CH3FVAL_MASK (0xF000U)
15816 #define TPM_FILTER_CH3FVAL_SHIFT (12U)
15817 /*! CH3FVAL - Channel 3 Filter Value
15818  */
15819 #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
15820 #define TPM_FILTER_CH4FVAL_MASK (0xF0000U)
15821 #define TPM_FILTER_CH4FVAL_SHIFT (16U)
15822 /*! CH4FVAL - Channel 4 Filter Value
15823  */
15824 #define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
15825 #define TPM_FILTER_CH5FVAL_MASK (0xF00000U)
15826 #define TPM_FILTER_CH5FVAL_SHIFT (20U)
15827 /*! CH5FVAL - Channel 5 Filter Value
15828  */
15829 #define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
15830 /*! @} */
15831 
15832 /*! @name QDCTRL - Quadrature Decoder Control and Status */
15833 /*! @{ */
15834 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
15835 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
15836 /*! QUADEN
15837  *  0b0..Quadrature decoder mode is disabled.
15838  *  0b1..Quadrature decoder mode is enabled.
15839  */
15840 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
15841 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
15842 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
15843 /*! TOFDIR
15844  *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
15845  *       from its minimum value (zero) to its maximum value (MOD register).
15846  *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
15847  *       its maximum value (MOD register) to its minimum value (zero).
15848  */
15849 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
15850 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
15851 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
15852 /*! QUADIR - Counter Direction in Quadrature Decode Mode
15853  *  0b0..Counter direction is decreasing (counter decrement).
15854  *  0b1..Counter direction is increasing (counter increment).
15855  */
15856 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
15857 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
15858 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
15859 /*! QUADMODE - Quadrature Decoder Mode
15860  *  0b0..Phase encoding mode.
15861  *  0b1..Count and direction encoding mode.
15862  */
15863 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
15864 /*! @} */
15865 
15866 /*! @name CONF - Configuration */
15867 /*! @{ */
15868 #define TPM_CONF_DOZEEN_MASK (0x20U)
15869 #define TPM_CONF_DOZEEN_SHIFT (5U)
15870 /*! DOZEEN - Doze Enable
15871  *  0b0..Internal TPM counter continues in Doze mode.
15872  *  0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events
15873  * are also ignored.
15874  */
15875 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
15876 #define TPM_CONF_DBGMODE_MASK (0xC0U)
15877 #define TPM_CONF_DBGMODE_SHIFT (6U)
15878 /*! DBGMODE - Debug Mode
15879  *  0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are
15880  * also ignored. 0b11..TPM counter continues in debug mode.
15881  */
15882 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
15883 #define TPM_CONF_GTBSYNC_MASK (0x100U)
15884 #define TPM_CONF_GTBSYNC_SHIFT (8U)
15885 /*! GTBSYNC - Global Time Base Synchronization
15886  *  0b0..Global timebase synchronization disabled.
15887  *  0b1..Global timebase synchronization enabled.
15888  */
15889 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
15890 #define TPM_CONF_GTBEEN_MASK (0x200U)
15891 #define TPM_CONF_GTBEEN_SHIFT (9U)
15892 /*! GTBEEN - Global time base enable
15893  *  0b0..All channels use the internally generated TPM counter as their timebase
15894  *  0b1..All channels use an externally generated global timebase as their timebase
15895  */
15896 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
15897 #define TPM_CONF_CSOT_MASK (0x10000U)
15898 #define TPM_CONF_CSOT_SHIFT (16U)
15899 /*! CSOT - Counter Start on Trigger
15900  *  0b0..TPM counter starts to increment immediately, once it is enabled.
15901  *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
15902  *       after it has been enabled or after it has stopped due to overflow.
15903  */
15904 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
15905 #define TPM_CONF_CSOO_MASK (0x20000U)
15906 #define TPM_CONF_CSOO_SHIFT (17U)
15907 /*! CSOO - Counter Stop On Overflow
15908  *  0b0..TPM counter continues incrementing or decrementing after overflow
15909  *  0b1..TPM counter stops incrementing or decrementing after overflow.
15910  */
15911 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
15912 #define TPM_CONF_CROT_MASK (0x40000U)
15913 #define TPM_CONF_CROT_SHIFT (18U)
15914 /*! CROT - Counter Reload On Trigger
15915  *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
15916  *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
15917  */
15918 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
15919 #define TPM_CONF_CPOT_MASK (0x80000U)
15920 #define TPM_CONF_CPOT_SHIFT (19U)
15921 /*! CPOT - Counter Pause On Trigger
15922  */
15923 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
15924 #define TPM_CONF_TRGPOL_MASK (0x400000U)
15925 #define TPM_CONF_TRGPOL_SHIFT (22U)
15926 /*! TRGPOL - Trigger Polarity
15927  *  0b0..Trigger is active high.
15928  *  0b1..Trigger is active low.
15929  */
15930 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
15931 #define TPM_CONF_TRGSRC_MASK (0x800000U)
15932 #define TPM_CONF_TRGSRC_SHIFT (23U)
15933 /*! TRGSRC - Trigger Source
15934  *  0b0..Trigger source selected by TRGSEL is external.
15935  *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
15936  */
15937 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
15938 #define TPM_CONF_TRGSEL_MASK (0x3000000U)
15939 #define TPM_CONF_TRGSEL_SHIFT (24U)
15940 /*! TRGSEL - Trigger Select
15941  */
15942 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
15943 /*! @} */
15944 
15945 /*!
15946  * @}
15947  */ /* end of group TPM_Register_Masks */
15948 
15949 /* TPM - Peripheral instance base addresses */
15950 /** Peripheral TPM0 base address */
15951 #define TPM0_BASE (0x400AC000u)
15952 /** Peripheral TPM0 base pointer */
15953 #define TPM0 ((TPM_Type *)TPM0_BASE)
15954 /** Peripheral TPM1 base address */
15955 #define TPM1_BASE (0x400AD000u)
15956 /** Peripheral TPM1 base pointer */
15957 #define TPM1 ((TPM_Type *)TPM1_BASE)
15958 /** Peripheral TPM2 base address */
15959 #define TPM2_BASE (0x4002E000u)
15960 /** Peripheral TPM2 base pointer */
15961 #define TPM2 ((TPM_Type *)TPM2_BASE)
15962 /** Array initializer of TPM peripheral base addresses */
15963 #define TPM_BASE_ADDRS                  \
15964     {                                   \
15965         TPM0_BASE, TPM1_BASE, TPM2_BASE \
15966     }
15967 /** Array initializer of TPM peripheral base pointers */
15968 #define TPM_BASE_PTRS    \
15969     {                    \
15970         TPM0, TPM1, TPM2 \
15971     }
15972 /** Interrupt vectors for the TPM peripheral type */
15973 #define TPM_IRQS                        \
15974     {                                   \
15975         TPM0_IRQn, TPM1_IRQn, TPM2_IRQn \
15976     }
15977 
15978 /*!
15979  * @}
15980  */ /* end of group TPM_Peripheral_Access_Layer */
15981 
15982 /* ----------------------------------------------------------------------------
15983    -- TRGMUX Peripheral Access Layer
15984    ---------------------------------------------------------------------------- */
15985 
15986 /*!
15987  * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
15988  * @{
15989  */
15990 
15991 /** TRGMUX - Register Layout Typedef */
15992 typedef struct
15993 {
15994     __IO uint32_t TRGCFG[14]; /**< TRGMUX TRGCFG Register, array offset: 0x0, array step: 0x4 */
15995 } TRGMUX_Type;
15996 
15997 /* ----------------------------------------------------------------------------
15998    -- TRGMUX Register Masks
15999    ---------------------------------------------------------------------------- */
16000 
16001 /*!
16002  * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
16003  * @{
16004  */
16005 
16006 /*! @name TRGCFG - TRGMUX TRGCFG Register */
16007 /*! @{ */
16008 #define TRGMUX_TRGCFG_SEL0_MASK (0x3FU)
16009 #define TRGMUX_TRGCFG_SEL0_SHIFT (0U)
16010 /*! SEL0 - Trigger MUX Input 0 Source Select
16011  *  0b000000..Trigger function is disabled.
16012  *  0b000001..Port pin trigger input is selected.
16013  *  0b000010..FlexIO Timer 0 input is selected.
16014  *  0b000011..FlexIO Timer 1 input is selected.
16015  *  0b000100..FlexIO Timer 2 input is selected.
16016  *  0b000101..FlexIO Timer 3 input is selected.
16017  *  0b000110..FlexIO Timer 4 input is selected.
16018  *  0b000111..FlexIO Timer 5 input is selected.
16019  *  0b001000..FlexIO Timer 6 input is selected.
16020  *  0b001001..FlexIO Timer 7 input is selected.
16021  *  0b001010..TPM0 Overflow is selected
16022  *  0b001011..TPM0 Channel 0 is selected
16023  *  0b001100..TPM0 Channel 1 is selected
16024  *  0b001101..TPM1 Overflow is selected
16025  *  0b001110..TPM1 Channel 0 is selected
16026  *  0b001111..TPM1 Channel 1 is selected
16027  *  0b010000..LPIT1 Channel 0 is selected
16028  *  0b010001..LPIT1 Channel 1 is selected
16029  *  0b010010..LPIT1 Channel 2 is selected
16030  *  0b010011..LPIT1 Channel 3 is selected
16031  *  0b010100..LPUART0 RX Data is selected.
16032  *  0b010101..LPUART0 TX Data is selected.
16033  *  0b010110..LPUART0 RX Idle is selected.
16034  *  0b010111..LPUART1 RX Data is selected.
16035  *  0b011000..LPUART1 TX Data is selected.
16036  *  0b011001..LPUART1 RX Idle is selected.
16037  *  0b011010..LPI2C0 Master STOP is selected.
16038  *  0b011011..LPI2C0 Slave STOP is selected.
16039  *  0b011100..LPI2C1 Master STOP is selected.
16040  *  0b011101..LPI2C1 Slave STOP is selected.
16041  *  0b011110..LPSPI0 Frame is selected.
16042  *  0b011111..LPSPI0 RX data is selected.
16043  *  0b100000..LPSPI1 Frame is selected.
16044  *  0b100001..LPSPI1 RX data is selected.
16045  *  0b100010..RTC Seconds Counter is selected.
16046  *  0b100011..RTC Alarm is selected.
16047  *  0b100100..LPTMR0 Trigger is selected.
16048  *  0b100101..LPTMR1 Trigger is selected.
16049  *  0b100110..CMP0 Output is selected.
16050  *  0b100111..CMP1 Output is selected.
16051  *  0b101000..ADC0 Conversion A Complete is selected.
16052  *  0b101001..ADC0 Conversion B Complete is selected.
16053  *  0b101010..Port A Pin Trigger is selected.
16054  *  0b101011..Port B Pin Trigger is selected.
16055  *  0b101100..Port C Pin Trigger is selected.
16056  *  0b101101..Port D Pin Trigger is selected.
16057  *  0b101110..Port E Pin Trigger is selected.
16058  *  0b101111..TPM2 Overflow selected.
16059  *  0b110000..TPM2 Channel 0 is selected.
16060  *  0b110001..TPM2 Channel 1 is selected.
16061  *  0b110010..LPIT0 Channel 0 is selected.
16062  *  0b110011..LPIT0 Channel 1 is selected.
16063  *  0b110100..LPIT0 Channel 2 is selected.
16064  *  0b110101..LPIT0 Channel 3 is selected.
16065  *  0b110110..USB Start-of-Frame is selected.
16066  *  0b110111..LPUART2 RX Data is selected.
16067  *  0b111000..LPUART2 TX Data is selected.
16068  *  0b111001..LPUART2 RX Idle is selected.
16069  *  0b111010..LPI2C2 Master STOP is selected.
16070  *  0b111011..LPI2C2 Slave STOP is selected.
16071  *  0b111100..LPSPI2 Frame is selected.
16072  *  0b111101..LPSPI2 RX Data is selected.
16073  */
16074 #define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)
16075 #define TRGMUX_TRGCFG_SEL1_MASK (0x3F00U)
16076 #define TRGMUX_TRGCFG_SEL1_SHIFT (8U)
16077 /*! SEL1 - Trigger MUX Input 1 Source Select
16078  *  0b000000..Trigger function is disabled.
16079  *  0b000001..Port pin trigger input is selected.
16080  *  0b000010..FlexIO Timer 0 input is selected.
16081  *  0b000011..FlexIO Timer 1 input is selected.
16082  *  0b000100..FlexIO Timer 2 input is selected.
16083  *  0b000101..FlexIO Timer 3 input is selected.
16084  *  0b000110..FlexIO Timer 4 input is selected.
16085  *  0b000111..FlexIO Timer 5 input is selected.
16086  *  0b001000..FlexIO Timer 6 input is selected.
16087  *  0b001001..FlexIO Timer 7 input is selected.
16088  *  0b001010..TPM0 Overflow is selected
16089  *  0b001011..TPM0 Channel 0 is selected
16090  *  0b001100..TPM0 Channel 1 is selected
16091  *  0b001101..TPM1 Overflow is selected
16092  *  0b001110..TPM1 Channel 0 is selected
16093  *  0b001111..TPM1 Channel 1 is selected
16094  *  0b010000..LPIT1 Channel 0 is selected
16095  *  0b010001..LPIT1 Channel 1 is selected
16096  *  0b010010..LPIT1 Channel 2 is selected
16097  *  0b010011..LPIT1 Channel 3 is selected
16098  *  0b010100..LPUART0 RX Data is selected.
16099  *  0b010101..LPUART0 TX Data is selected.
16100  *  0b010110..LPUART0 RX Idle is selected.
16101  *  0b010111..LPUART1 RX Data is selected.
16102  *  0b011000..LPUART1 TX Data is selected.
16103  *  0b011001..LPUART1 RX Idle is selected.
16104  *  0b011010..LPI2C0 Master STOP is selected.
16105  *  0b011011..LPI2C0 Slave STOP is selected.
16106  *  0b011100..LPI2C1 Master STOP is selected.
16107  *  0b011101..LPI2C1 Slave STOP is selected.
16108  *  0b011110..LPSPI0 Frame is selected.
16109  *  0b011111..LPSPI0 RX data is selected.
16110  *  0b100000..LPSPI1 Frame is selected.
16111  *  0b100001..LPSPI1 RX data is selected.
16112  *  0b100010..RTC Seconds Counter is selected.
16113  *  0b100011..RTC Alarm is selected.
16114  *  0b100100..LPTMR0 Trigger is selected.
16115  *  0b100101..LPTMR1 Trigger is selected.
16116  *  0b100110..CMP0 Output is selected.
16117  *  0b100111..CMP1 Output is selected.
16118  *  0b101000..ADC0 Conversion A Complete is selected.
16119  *  0b101001..ADC0 Conversion B Complete is selected.
16120  *  0b101010..Port A Pin Trigger is selected.
16121  *  0b101011..Port B Pin Trigger is selected.
16122  *  0b101100..Port C Pin Trigger is selected.
16123  *  0b101101..Port D Pin Trigger is selected.
16124  *  0b101110..Port E Pin Trigger is selected.
16125  *  0b101111..TPM2 Overflow selected.
16126  *  0b110000..TPM2 Channel 0 is selected.
16127  *  0b110001..TPM2 Channel 1 is selected.
16128  *  0b110010..LPIT0 Channel 0 is selected.
16129  *  0b110011..LPIT0 Channel 1 is selected.
16130  *  0b110100..LPIT0 Channel 2 is selected.
16131  *  0b110101..LPIT0 Channel 3 is selected.
16132  *  0b110110..USB Start-of-Frame is selected.
16133  *  0b110111..LPUART2 RX Data is selected.
16134  *  0b111000..LPUART2 TX Data is selected.
16135  *  0b111001..LPUART2 RX Idle is selected.
16136  *  0b111010..LPI2C2 Master STOP is selected.
16137  *  0b111011..LPI2C2 Slave STOP is selected.
16138  *  0b111100..LPSPI2 Frame is selected.
16139  *  0b111101..LPSPI2 RX Data is selected.
16140  */
16141 #define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)
16142 #define TRGMUX_TRGCFG_SEL2_MASK (0x3F0000U)
16143 #define TRGMUX_TRGCFG_SEL2_SHIFT (16U)
16144 /*! SEL2 - Trigger MUX Input 2 Source Select
16145  *  0b000000..Trigger function is disabled.
16146  *  0b000001..Port pin trigger input is selected.
16147  *  0b000010..FlexIO Timer 0 input is selected.
16148  *  0b000011..FlexIO Timer 1 input is selected.
16149  *  0b000100..FlexIO Timer 2 input is selected.
16150  *  0b000101..FlexIO Timer 3 input is selected.
16151  *  0b000110..FlexIO Timer 4 input is selected.
16152  *  0b000111..FlexIO Timer 5 input is selected.
16153  *  0b001000..FlexIO Timer 6 input is selected.
16154  *  0b001001..FlexIO Timer 7 input is selected.
16155  *  0b001010..TPM0 Overflow is selected
16156  *  0b001011..TPM0 Channel 0 is selected
16157  *  0b001100..TPM0 Channel 1 is selected
16158  *  0b001101..TPM1 Overflow is selected
16159  *  0b001110..TPM1 Channel 0 is selected
16160  *  0b001111..TPM1 Channel 1 is selected
16161  *  0b010000..LPIT1 Channel 0 is selected
16162  *  0b010001..LPIT1 Channel 1 is selected
16163  *  0b010010..LPIT1 Channel 2 is selected
16164  *  0b010011..LPIT1 Channel 3 is selected
16165  *  0b010100..LPUART0 RX Data is selected.
16166  *  0b010101..LPUART0 TX Data is selected.
16167  *  0b010110..LPUART0 RX Idle is selected.
16168  *  0b010111..LPUART1 RX Data is selected.
16169  *  0b011000..LPUART1 TX Data is selected.
16170  *  0b011001..LPUART1 RX Idle is selected.
16171  *  0b011010..LPI2C0 Master STOP is selected.
16172  *  0b011011..LPI2C0 Slave STOP is selected.
16173  *  0b011100..LPI2C1 Master STOP is selected.
16174  *  0b011101..LPI2C1 Slave STOP is selected.
16175  *  0b011110..LPSPI0 Frame is selected.
16176  *  0b011111..LPSPI0 RX data is selected.
16177  *  0b100000..LPSPI1 Frame is selected.
16178  *  0b100001..LPSPI1 RX data is selected.
16179  *  0b100010..RTC Seconds Counter is selected.
16180  *  0b100011..RTC Alarm is selected.
16181  *  0b100100..LPTMR0 Trigger is selected.
16182  *  0b100101..LPTMR1 Trigger is selected.
16183  *  0b100110..CMP0 Output is selected.
16184  *  0b100111..CMP1 Output is selected.
16185  *  0b101000..ADC0 Conversion A Complete is selected.
16186  *  0b101001..ADC0 Conversion B Complete is selected.
16187  *  0b101010..Port A Pin Trigger is selected.
16188  *  0b101011..Port B Pin Trigger is selected.
16189  *  0b101100..Port C Pin Trigger is selected.
16190  *  0b101101..Port D Pin Trigger is selected.
16191  *  0b101110..Port E Pin Trigger is selected.
16192  *  0b101111..TPM2 Overflow selected.
16193  *  0b110000..TPM2 Channel 0 is selected.
16194  *  0b110001..TPM2 Channel 1 is selected.
16195  *  0b110010..LPIT0 Channel 0 is selected.
16196  *  0b110011..LPIT0 Channel 1 is selected.
16197  *  0b110100..LPIT0 Channel 2 is selected.
16198  *  0b110101..LPIT0 Channel 3 is selected.
16199  *  0b110110..USB Start-of-Frame is selected.
16200  *  0b110111..LPUART2 RX Data is selected.
16201  *  0b111000..LPUART2 TX Data is selected.
16202  *  0b111001..LPUART2 RX Idle is selected.
16203  *  0b111010..LPI2C2 Master STOP is selected.
16204  *  0b111011..LPI2C2 Slave STOP is selected.
16205  *  0b111100..LPSPI2 Frame is selected.
16206  *  0b111101..LPSPI2 RX Data is selected.
16207  */
16208 #define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)
16209 #define TRGMUX_TRGCFG_SEL3_MASK (0x3F000000U)
16210 #define TRGMUX_TRGCFG_SEL3_SHIFT (24U)
16211 /*! SEL3 - Trigger MUX Input 3 Source Select
16212  *  0b000000..Trigger function is disabled.
16213  *  0b000001..Port pin trigger input is selected.
16214  *  0b000010..FlexIO Timer 0 input is selected.
16215  *  0b000011..FlexIO Timer 1 input is selected.
16216  *  0b000100..FlexIO Timer 2 input is selected.
16217  *  0b000101..FlexIO Timer 3 input is selected.
16218  *  0b000110..FlexIO Timer 4 input is selected.
16219  *  0b000111..FlexIO Timer 5 input is selected.
16220  *  0b001000..FlexIO Timer 6 input is selected.
16221  *  0b001001..FlexIO Timer 7 input is selected.
16222  *  0b001010..TPM0 Overflow is selected
16223  *  0b001011..TPM0 Channel 0 is selected
16224  *  0b001100..TPM0 Channel 1 is selected
16225  *  0b001101..TPM1 Overflow is selected
16226  *  0b001110..TPM1 Channel 0 is selected
16227  *  0b001111..TPM1 Channel 1 is selected
16228  *  0b010000..LPIT1 Channel 0 is selected
16229  *  0b010001..LPIT1 Channel 1 is selected
16230  *  0b010010..LPIT1 Channel 2 is selected
16231  *  0b010011..LPIT1 Channel 3 is selected
16232  *  0b010100..LPUART0 RX Data is selected.
16233  *  0b010101..LPUART0 TX Data is selected.
16234  *  0b010110..LPUART0 RX Idle is selected.
16235  *  0b010111..LPUART1 RX Data is selected.
16236  *  0b011000..LPUART1 TX Data is selected.
16237  *  0b011001..LPUART1 RX Idle is selected.
16238  *  0b011010..LPI2C0 Master STOP is selected.
16239  *  0b011011..LPI2C0 Slave STOP is selected.
16240  *  0b011100..LPI2C1 Master STOP is selected.
16241  *  0b011101..LPI2C1 Slave STOP is selected.
16242  *  0b011110..LPSPI0 Frame is selected.
16243  *  0b011111..LPSPI0 RX data is selected.
16244  *  0b100000..LPSPI1 Frame is selected.
16245  *  0b100001..LPSPI1 RX data is selected.
16246  *  0b100010..RTC Seconds Counter is selected.
16247  *  0b100011..RTC Alarm is selected.
16248  *  0b100100..LPTMR0 Trigger is selected.
16249  *  0b100101..LPTMR1 Trigger is selected.
16250  *  0b100110..CMP0 Output is selected.
16251  *  0b100111..CMP1 Output is selected.
16252  *  0b101000..ADC0 Conversion A Complete is selected.
16253  *  0b101001..ADC0 Conversion B Complete is selected.
16254  *  0b101010..Port A Pin Trigger is selected.
16255  *  0b101011..Port B Pin Trigger is selected.
16256  *  0b101100..Port C Pin Trigger is selected.
16257  *  0b101101..Port D Pin Trigger is selected.
16258  *  0b101110..Port E Pin Trigger is selected.
16259  *  0b101111..TPM2 Overflow selected.
16260  *  0b110000..TPM2 Channel 0 is selected.
16261  *  0b110001..TPM2 Channel 1 is selected.
16262  *  0b110010..LPIT0 Channel 0 is selected.
16263  *  0b110011..LPIT0 Channel 1 is selected.
16264  *  0b110100..LPIT0 Channel 2 is selected.
16265  *  0b110101..LPIT0 Channel 3 is selected.
16266  *  0b110110..USB Start-of-Frame is selected.
16267  *  0b110111..LPUART2 RX Data is selected.
16268  *  0b111000..LPUART2 TX Data is selected.
16269  *  0b111001..LPUART2 RX Idle is selected.
16270  *  0b111010..LPI2C2 Master STOP is selected.
16271  *  0b111011..LPI2C2 Slave STOP is selected.
16272  *  0b111100..LPSPI2 Frame is selected.
16273  *  0b111101..LPSPI2 RX Data is selected.
16274  */
16275 #define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)
16276 #define TRGMUX_TRGCFG_LK_MASK (0x80000000U)
16277 #define TRGMUX_TRGCFG_LK_SHIFT (31U)
16278 /*! LK - Enable
16279  *  0b0..Register can be written.
16280  *  0b1..Register cannot be written until the next system Reset.
16281  */
16282 #define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
16283 /*! @} */
16284 
16285 /* The count of TRGMUX_TRGCFG */
16286 #define TRGMUX_TRGCFG_COUNT (14U)
16287 
16288 /*!
16289  * @}
16290  */ /* end of group TRGMUX_Register_Masks */
16291 
16292 /* TRGMUX - Peripheral instance base addresses */
16293 /** Peripheral TRGMUX0 base address */
16294 #define TRGMUX0_BASE (0x40027000u)
16295 /** Peripheral TRGMUX0 base pointer */
16296 #define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE)
16297 /** Peripheral TRGMUX1 base address */
16298 #define TRGMUX1_BASE (0x400A7000u)
16299 /** Peripheral TRGMUX1 base pointer */
16300 #define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE)
16301 /** Array initializer of TRGMUX peripheral base addresses */
16302 #define TRGMUX_BASE_ADDRS          \
16303     {                              \
16304         TRGMUX0_BASE, TRGMUX1_BASE \
16305     }
16306 /** Array initializer of TRGMUX peripheral base pointers */
16307 #define TRGMUX_BASE_PTRS \
16308     {                    \
16309         TRGMUX0, TRGMUX1 \
16310     }
16311 #define TRGMUX_INSTANCE_MASK 0xF
16312 #define TRGMUX_INSTANCE_SHIFT 12
16313 #define TRGMUX_PERIPHERAL_MASK 0xFFF
16314 #define TRGMUX_PERIPHERAL_SHIFT 0
16315 #define TRGMUX_INSTANCE_0 0
16316 #define TRGMUX_INSTANCE_1 1
16317 
16318 #define TRGMUX_DMAMUX0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0)
16319 #define TRGMUX_LPIT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1)
16320 #define TRGMUX_TPM2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 2)
16321 #define TRGMUX_ADC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 4)
16322 #define TRGMUX_LPUART2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 5)
16323 #define TRGMUX_LPI2C2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7)
16324 #define TRGMUX_LPSPI2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 9)
16325 #define TRGMUX_CMP0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 11)
16326 #define TRGMUX_CMP1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 12)
16327 #define TRGMUX_DAC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 13)
16328 #define TRGMUX_DMAMUX0 (TRGMUX0->TRGCFG[0])
16329 #define TRGMUX_LPIT0 (TRGMUX0->TRGCFG[1])
16330 #define TRGMUX_TPM2 (TRGMUX0->TRGCFG[2])
16331 #define TRGMUX_ADC0 (TRGMUX0->TRGCFG[4])
16332 #define TRGMUX_LPUART2 (TRGMUX0->TRGCFG[5])
16333 #define TRGMUX_LPI2C2 (TRGMUX0->TRGCFG[7])
16334 #define TRGMUX_LPSPI2 (TRGMUX0->TRGCFG[9])
16335 #define TRGMUX_CMP0 (TRGMUX0->TRGCFG[11])
16336 #define TRGMUX_CMP1 (TRGMUX0->TRGCFG[12])
16337 #define TRGMUX_DAC0 (TRGMUX0->TRGCFG[13])
16338 
16339 #define TRGMUX_TPM0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 2)
16340 #define TRGMUX_TPM1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 3)
16341 #define TRGMUX_FLEXIO_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 4)
16342 #define TRGMUX_LPUART0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 5)
16343 #define TRGMUX_LPUART1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 6)
16344 #define TRGMUX_LPI2C0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7)
16345 #define TRGMUX_LPI2C1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 8)
16346 #define TRGMUX_LPSPI0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 9)
16347 #define TRGMUX_LPSPI1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 10)
16348 #define TRGMUX_TPM0 (TRGMUX1->TRGCFG[2])
16349 #define TRGMUX_TPM1 (TRGMUX1->TRGCFG[3])
16350 #define TRGMUX_FLEXIO (TRGMUX1->TRGCFG[4])
16351 #define TRGMUX_LPUART0 (TRGMUX1->TRGCFG[5])
16352 #define TRGMUX_LPUART1 (TRGMUX1->TRGCFG[6])
16353 #define TRGMUX_LPI2C0 (TRGMUX1->TRGCFG[7])
16354 #define TRGMUX_LPI2C1 (TRGMUX1->TRGCFG[8])
16355 #define TRGMUX_LPSPI0 (TRGMUX1->TRGCFG[9])
16356 #define TRGMUX_LPSPI1 (TRGMUX1->TRGCFG[10])
16357 
16358 /*!
16359  * @}
16360  */ /* end of group TRGMUX_Peripheral_Access_Layer */
16361 
16362 /* ----------------------------------------------------------------------------
16363    -- TRNG Peripheral Access Layer
16364    ---------------------------------------------------------------------------- */
16365 
16366 /*!
16367  * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
16368  * @{
16369  */
16370 
16371 /** TRNG - Register Layout Typedef */
16372 typedef struct
16373 {
16374     __IO uint32_t MCTL;   /**< TRNG Miscellaneous Control Register, offset: 0x0 */
16375     __IO uint32_t SCMISC; /**< TRNG Statistical Check Miscellaneous Register, offset: 0x4 */
16376     __IO uint32_t PKRRNG; /**< TRNG Poker Range Register, offset: 0x8 */
16377     union
16378     {                         /* offset: 0xC */
16379         __IO uint32_t PKRMAX; /**< TRNG Poker Maximum Limit Register, offset: 0xC */
16380         __I uint32_t PKRSQ;   /**< TRNG Poker Square Calculation Result Register, offset: 0xC */
16381     };
16382     __IO uint32_t SDCTL; /**< TRNG Seed Control Register, offset: 0x10 */
16383     union
16384     {                        /* offset: 0x14 */
16385         __IO uint32_t SBLIM; /**< TRNG Sparse Bit Limit Register, offset: 0x14 */
16386         __I uint32_t TOTSAM; /**< TRNG Total Samples Register, offset: 0x14 */
16387     };
16388     __IO uint32_t FRQMIN; /**< TRNG Frequency Count Minimum Limit Register, offset: 0x18 */
16389     union
16390     {                         /* offset: 0x1C */
16391         __I uint32_t FRQCNT;  /**< TRNG Frequency Count Register, offset: 0x1C */
16392         __IO uint32_t FRQMAX; /**< TRNG Frequency Count Maximum Limit Register, offset: 0x1C */
16393     };
16394     union
16395     {                       /* offset: 0x20 */
16396         __I uint32_t SCMC;  /**< TRNG Statistical Check Monobit Count Register, offset: 0x20 */
16397         __IO uint32_t SCML; /**< TRNG Statistical Check Monobit Limit Register, offset: 0x20 */
16398     };
16399     union
16400     {                        /* offset: 0x24 */
16401         __I uint32_t SCR1C;  /**< TRNG Statistical Check Run Length 1 Count Register, offset: 0x24 */
16402         __IO uint32_t SCR1L; /**< TRNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */
16403     };
16404     union
16405     {                        /* offset: 0x28 */
16406         __I uint32_t SCR2C;  /**< TRNG Statistical Check Run Length 2 Count Register, offset: 0x28 */
16407         __IO uint32_t SCR2L; /**< TRNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */
16408     };
16409     union
16410     {                        /* offset: 0x2C */
16411         __I uint32_t SCR3C;  /**< TRNG Statistical Check Run Length 3 Count Register, offset: 0x2C */
16412         __IO uint32_t SCR3L; /**< TRNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */
16413     };
16414     union
16415     {                        /* offset: 0x30 */
16416         __I uint32_t SCR4C;  /**< TRNG Statistical Check Run Length 4 Count Register, offset: 0x30 */
16417         __IO uint32_t SCR4L; /**< TRNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */
16418     };
16419     union
16420     {                        /* offset: 0x34 */
16421         __I uint32_t SCR5C;  /**< TRNG Statistical Check Run Length 5 Count Register, offset: 0x34 */
16422         __IO uint32_t SCR5L; /**< TRNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */
16423     };
16424     union
16425     {                         /* offset: 0x38 */
16426         __I uint32_t SCR6PC;  /**< TRNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */
16427         __IO uint32_t SCR6PL; /**< TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
16428     };
16429     __I uint32_t STATUS;      /**< TRNG Status Register, offset: 0x3C */
16430     __I uint32_t ENT[16];     /**< TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */
16431     __I uint32_t PKRCNT10;    /**< TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
16432     __I uint32_t PKRCNT32;    /**< TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
16433     __I uint32_t PKRCNT54;    /**< TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
16434     __I uint32_t PKRCNT76;    /**< TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
16435     __I uint32_t PKRCNT98;    /**< TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
16436     __I uint32_t PKRCNTBA;    /**< TRNG Statistical Check Poker Count B and A Register, offset: 0x94 */
16437     __I uint32_t PKRCNTDC;    /**< TRNG Statistical Check Poker Count D and C Register, offset: 0x98 */
16438     __I uint32_t PKRCNTFE;    /**< TRNG Statistical Check Poker Count F and E Register, offset: 0x9C */
16439     __IO uint32_t SEC_CFG;    /**< TRNG Security Configuration Register, offset: 0xA0 */
16440     __IO uint32_t INT_CTRL;   /**< TRNG Interrupt Control Register, offset: 0xA4 */
16441     __IO uint32_t INT_MASK;   /**< TRNG Mask Register, offset: 0xA8 */
16442     __IO uint32_t INT_STATUS; /**< TRNG Interrupt Status Register, offset: 0xAC */
16443     uint8_t RESERVED_0[64];
16444     __I uint32_t VID1; /**< TRNG Version ID Register (MS), offset: 0xF0 */
16445     __I uint32_t VID2; /**< TRNG Version ID Register (LS), offset: 0xF4 */
16446 } TRNG_Type;
16447 
16448 /* ----------------------------------------------------------------------------
16449    -- TRNG Register Masks
16450    ---------------------------------------------------------------------------- */
16451 
16452 /*!
16453  * @addtogroup TRNG_Register_Masks TRNG Register Masks
16454  * @{
16455  */
16456 
16457 /*! @name MCTL - TRNG Miscellaneous Control Register */
16458 /*! @{ */
16459 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
16460 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
16461 /*! SAMP_MODE
16462  *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
16463  *  0b01..use raw data into both Entropy shifter and Statistical Checker
16464  *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
16465  *  0b11..undefined/reserved.
16466  */
16467 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
16468 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
16469 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
16470 /*! OSC_DIV
16471  *  0b00..use ring oscillator with no divide
16472  *  0b01..use ring oscillator divided-by-2
16473  *  0b10..use ring oscillator divided-by-4
16474  *  0b11..use ring oscillator divided-by-8
16475  */
16476 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
16477 #define TRNG_MCTL_UNUSED_MASK (0x10U)
16478 #define TRNG_MCTL_UNUSED_SHIFT (4U)
16479 #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
16480 #define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
16481 #define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
16482 #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
16483 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
16484 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
16485 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
16486 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
16487 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
16488 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
16489 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
16490 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
16491 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
16492 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
16493 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
16494 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
16495 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
16496 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
16497 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
16498 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
16499 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
16500 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
16501 #define TRNG_MCTL_ERR_MASK (0x1000U)
16502 #define TRNG_MCTL_ERR_SHIFT (12U)
16503 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
16504 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
16505 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
16506 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
16507 #define TRNG_MCTL_PRGM_MASK (0x10000U)
16508 #define TRNG_MCTL_PRGM_SHIFT (16U)
16509 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
16510 /*! @} */
16511 
16512 /*! @name SCMISC - TRNG Statistical Check Miscellaneous Register */
16513 /*! @{ */
16514 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
16515 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
16516 #define TRNG_SCMISC_LRUN_MAX(x) \
16517     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
16518 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
16519 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
16520 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
16521 /*! @} */
16522 
16523 /*! @name PKRRNG - TRNG Poker Range Register */
16524 /*! @{ */
16525 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
16526 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
16527 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
16528 /*! @} */
16529 
16530 /*! @name PKRMAX - TRNG Poker Maximum Limit Register */
16531 /*! @{ */
16532 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
16533 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
16534 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
16535 /*! @} */
16536 
16537 /*! @name PKRSQ - TRNG Poker Square Calculation Result Register */
16538 /*! @{ */
16539 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
16540 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
16541 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
16542 /*! @} */
16543 
16544 /*! @name SDCTL - TRNG Seed Control Register */
16545 /*! @{ */
16546 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
16547 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
16548 #define TRNG_SDCTL_SAMP_SIZE(x) \
16549     (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
16550 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
16551 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
16552 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
16553 /*! @} */
16554 
16555 /*! @name SBLIM - TRNG Sparse Bit Limit Register */
16556 /*! @{ */
16557 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
16558 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
16559 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
16560 /*! @} */
16561 
16562 /*! @name TOTSAM - TRNG Total Samples Register */
16563 /*! @{ */
16564 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
16565 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
16566 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
16567 /*! @} */
16568 
16569 /*! @name FRQMIN - TRNG Frequency Count Minimum Limit Register */
16570 /*! @{ */
16571 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
16572 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
16573 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
16574 /*! @} */
16575 
16576 /*! @name FRQCNT - TRNG Frequency Count Register */
16577 /*! @{ */
16578 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
16579 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
16580 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
16581 /*! @} */
16582 
16583 /*! @name FRQMAX - TRNG Frequency Count Maximum Limit Register */
16584 /*! @{ */
16585 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
16586 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
16587 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
16588 /*! @} */
16589 
16590 /*! @name SCMC - TRNG Statistical Check Monobit Count Register */
16591 /*! @{ */
16592 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
16593 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
16594 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
16595 /*! @} */
16596 
16597 /*! @name SCML - TRNG Statistical Check Monobit Limit Register */
16598 /*! @{ */
16599 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
16600 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
16601 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
16602 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
16603 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
16604 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
16605 /*! @} */
16606 
16607 /*! @name SCR1C - TRNG Statistical Check Run Length 1 Count Register */
16608 /*! @{ */
16609 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
16610 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
16611 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
16612 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
16613 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
16614 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
16615 /*! @} */
16616 
16617 /*! @name SCR1L - TRNG Statistical Check Run Length 1 Limit Register */
16618 /*! @{ */
16619 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
16620 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
16621 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
16622 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
16623 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
16624 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
16625 /*! @} */
16626 
16627 /*! @name SCR2C - TRNG Statistical Check Run Length 2 Count Register */
16628 /*! @{ */
16629 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
16630 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
16631 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
16632 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
16633 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
16634 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
16635 /*! @} */
16636 
16637 /*! @name SCR2L - TRNG Statistical Check Run Length 2 Limit Register */
16638 /*! @{ */
16639 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
16640 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
16641 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
16642 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
16643 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
16644 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
16645 /*! @} */
16646 
16647 /*! @name SCR3C - TRNG Statistical Check Run Length 3 Count Register */
16648 /*! @{ */
16649 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
16650 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
16651 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
16652 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
16653 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
16654 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
16655 /*! @} */
16656 
16657 /*! @name SCR3L - TRNG Statistical Check Run Length 3 Limit Register */
16658 /*! @{ */
16659 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
16660 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
16661 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
16662 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
16663 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
16664 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
16665 /*! @} */
16666 
16667 /*! @name SCR4C - TRNG Statistical Check Run Length 4 Count Register */
16668 /*! @{ */
16669 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
16670 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
16671 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
16672 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
16673 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
16674 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
16675 /*! @} */
16676 
16677 /*! @name SCR4L - TRNG Statistical Check Run Length 4 Limit Register */
16678 /*! @{ */
16679 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
16680 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
16681 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
16682 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
16683 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
16684 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
16685 /*! @} */
16686 
16687 /*! @name SCR5C - TRNG Statistical Check Run Length 5 Count Register */
16688 /*! @{ */
16689 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
16690 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
16691 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
16692 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
16693 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
16694 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
16695 /*! @} */
16696 
16697 /*! @name SCR5L - TRNG Statistical Check Run Length 5 Limit Register */
16698 /*! @{ */
16699 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
16700 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
16701 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
16702 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
16703 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
16704 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
16705 /*! @} */
16706 
16707 /*! @name SCR6PC - TRNG Statistical Check Run Length 6+ Count Register */
16708 /*! @{ */
16709 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
16710 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
16711 #define TRNG_SCR6PC_R6P_0_CT(x) \
16712     (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
16713 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
16714 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
16715 #define TRNG_SCR6PC_R6P_1_CT(x) \
16716     (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
16717 /*! @} */
16718 
16719 /*! @name SCR6PL - TRNG Statistical Check Run Length 6+ Limit Register */
16720 /*! @{ */
16721 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
16722 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
16723 #define TRNG_SCR6PL_RUN6P_MAX(x) \
16724     (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
16725 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
16726 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
16727 #define TRNG_SCR6PL_RUN6P_RNG(x) \
16728     (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
16729 /*! @} */
16730 
16731 /*! @name STATUS - TRNG Status Register */
16732 /*! @{ */
16733 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
16734 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
16735 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
16736 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
16737 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
16738 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
16739 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
16740 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
16741 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
16742 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
16743 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
16744 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
16745 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
16746 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
16747 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
16748 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
16749 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
16750 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
16751 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
16752 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
16753 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
16754 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
16755 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
16756 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
16757 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
16758 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
16759 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
16760 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
16761 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
16762 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
16763 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
16764 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
16765 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
16766 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
16767 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
16768 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
16769 #define TRNG_STATUS_TFSB_MASK (0x1000U)
16770 #define TRNG_STATUS_TFSB_SHIFT (12U)
16771 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
16772 #define TRNG_STATUS_TFLR_MASK (0x2000U)
16773 #define TRNG_STATUS_TFLR_SHIFT (13U)
16774 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
16775 #define TRNG_STATUS_TFP_MASK (0x4000U)
16776 #define TRNG_STATUS_TFP_SHIFT (14U)
16777 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
16778 #define TRNG_STATUS_TFMB_MASK (0x8000U)
16779 #define TRNG_STATUS_TFMB_SHIFT (15U)
16780 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
16781 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
16782 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
16783 #define TRNG_STATUS_RETRY_CT(x) \
16784     (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
16785 /*! @} */
16786 
16787 /*! @name ENT - TRNG Entropy Read Register */
16788 /*! @{ */
16789 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
16790 #define TRNG_ENT_ENT_SHIFT (0U)
16791 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
16792 /*! @} */
16793 
16794 /* The count of TRNG_ENT */
16795 #define TRNG_ENT_COUNT (16U)
16796 
16797 /*! @name PKRCNT10 - TRNG Statistical Check Poker Count 1 and 0 Register */
16798 /*! @{ */
16799 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
16800 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
16801 #define TRNG_PKRCNT10_PKR_0_CT(x) \
16802     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
16803 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
16804 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
16805 #define TRNG_PKRCNT10_PKR_1_CT(x) \
16806     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
16807 /*! @} */
16808 
16809 /*! @name PKRCNT32 - TRNG Statistical Check Poker Count 3 and 2 Register */
16810 /*! @{ */
16811 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
16812 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
16813 #define TRNG_PKRCNT32_PKR_2_CT(x) \
16814     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
16815 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
16816 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
16817 #define TRNG_PKRCNT32_PKR_3_CT(x) \
16818     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
16819 /*! @} */
16820 
16821 /*! @name PKRCNT54 - TRNG Statistical Check Poker Count 5 and 4 Register */
16822 /*! @{ */
16823 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
16824 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
16825 #define TRNG_PKRCNT54_PKR_4_CT(x) \
16826     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
16827 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
16828 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
16829 #define TRNG_PKRCNT54_PKR_5_CT(x) \
16830     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
16831 /*! @} */
16832 
16833 /*! @name PKRCNT76 - TRNG Statistical Check Poker Count 7 and 6 Register */
16834 /*! @{ */
16835 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
16836 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
16837 #define TRNG_PKRCNT76_PKR_6_CT(x) \
16838     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
16839 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
16840 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
16841 #define TRNG_PKRCNT76_PKR_7_CT(x) \
16842     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
16843 /*! @} */
16844 
16845 /*! @name PKRCNT98 - TRNG Statistical Check Poker Count 9 and 8 Register */
16846 /*! @{ */
16847 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
16848 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
16849 #define TRNG_PKRCNT98_PKR_8_CT(x) \
16850     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
16851 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
16852 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
16853 #define TRNG_PKRCNT98_PKR_9_CT(x) \
16854     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
16855 /*! @} */
16856 
16857 /*! @name PKRCNTBA - TRNG Statistical Check Poker Count B and A Register */
16858 /*! @{ */
16859 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
16860 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
16861 #define TRNG_PKRCNTBA_PKR_A_CT(x) \
16862     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
16863 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
16864 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
16865 #define TRNG_PKRCNTBA_PKR_B_CT(x) \
16866     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
16867 /*! @} */
16868 
16869 /*! @name PKRCNTDC - TRNG Statistical Check Poker Count D and C Register */
16870 /*! @{ */
16871 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
16872 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
16873 #define TRNG_PKRCNTDC_PKR_C_CT(x) \
16874     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
16875 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
16876 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
16877 #define TRNG_PKRCNTDC_PKR_D_CT(x) \
16878     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
16879 /*! @} */
16880 
16881 /*! @name PKRCNTFE - TRNG Statistical Check Poker Count F and E Register */
16882 /*! @{ */
16883 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
16884 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
16885 #define TRNG_PKRCNTFE_PKR_E_CT(x) \
16886     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
16887 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
16888 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
16889 #define TRNG_PKRCNTFE_PKR_F_CT(x) \
16890     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
16891 /*! @} */
16892 
16893 /*! @name SEC_CFG - TRNG Security Configuration Register */
16894 /*! @{ */
16895 #define TRNG_SEC_CFG_SH0_MASK (0x1U)
16896 #define TRNG_SEC_CFG_SH0_SHIFT (0U)
16897 /*! SH0
16898  *  0b0..See DRNG version.
16899  *  0b1..See DRNG version.
16900  */
16901 #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
16902 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
16903 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
16904 /*! NO_PRGM
16905  *  0b0..Programability of registers controlled only by the TRNG Miscellaneous Control Register's access mode bit.
16906  *  0b1..Overides TRNG Miscellaneous Control Register access mode and prevents TRNG register programming.
16907  */
16908 #define TRNG_SEC_CFG_NO_PRGM(x) \
16909     (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
16910 #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
16911 #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
16912 /*! SK_VAL
16913  *  0b0..See DRNG version.
16914  *  0b1..See DRNG version.
16915  */
16916 #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
16917 /*! @} */
16918 
16919 /*! @name INT_CTRL - TRNG Interrupt Control Register */
16920 /*! @{ */
16921 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
16922 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
16923 /*! HW_ERR
16924  *  0b0..Corresponding bit of INT_STATUS cleared.
16925  *  0b1..Corresponding bit of INT_STATUS active.
16926  */
16927 #define TRNG_INT_CTRL_HW_ERR(x) \
16928     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
16929 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
16930 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
16931 /*! ENT_VAL
16932  *  0b0..Same behavior as bit 0 above.
16933  *  0b1..Same behavior as bit 0 above.
16934  */
16935 #define TRNG_INT_CTRL_ENT_VAL(x) \
16936     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
16937 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
16938 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
16939 /*! FRQ_CT_FAIL
16940  *  0b0..Same behavior as bit 0 above.
16941  *  0b1..Same behavior as bit 0 above.
16942  */
16943 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) \
16944     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
16945 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
16946 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
16947 #define TRNG_INT_CTRL_UNUSED(x) \
16948     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
16949 /*! @} */
16950 
16951 /*! @name INT_MASK - TRNG Mask Register */
16952 /*! @{ */
16953 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
16954 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
16955 /*! HW_ERR
16956  *  0b0..Corresponding interrupt of INT_STATUS is masked.
16957  *  0b1..Corresponding bit of INT_STATUS is active.
16958  */
16959 #define TRNG_INT_MASK_HW_ERR(x) \
16960     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
16961 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
16962 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
16963 /*! ENT_VAL
16964  *  0b0..Same behavior as bit 0 above.
16965  *  0b1..Same behavior as bit 0 above.
16966  */
16967 #define TRNG_INT_MASK_ENT_VAL(x) \
16968     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
16969 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
16970 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
16971 /*! FRQ_CT_FAIL
16972  *  0b0..Same behavior as bit 0 above.
16973  *  0b1..Same behavior as bit 0 above.
16974  */
16975 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) \
16976     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
16977 /*! @} */
16978 
16979 /*! @name INT_STATUS - TRNG Interrupt Status Register */
16980 /*! @{ */
16981 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
16982 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
16983 /*! HW_ERR
16984  *  0b0..no error
16985  *  0b1..error detected.
16986  */
16987 #define TRNG_INT_STATUS_HW_ERR(x) \
16988     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
16989 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
16990 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
16991 /*! ENT_VAL
16992  *  0b0..Busy generation entropy. Any value read is invalid.
16993  *  0b1..TRNG can be stopped and entropy is valid if read.
16994  */
16995 #define TRNG_INT_STATUS_ENT_VAL(x) \
16996     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
16997 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
16998 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
16999 /*! FRQ_CT_FAIL
17000  *  0b0..No hardware nor self test frequency errors.
17001  *  0b1..The frequency counter has detected a failure.
17002  */
17003 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) \
17004     (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
17005 /*! @} */
17006 
17007 /*! @name VID1 - TRNG Version ID Register (MS) */
17008 /*! @{ */
17009 #define TRNG_VID1_MIN_REV_MASK (0xFFU)
17010 #define TRNG_VID1_MIN_REV_SHIFT (0U)
17011 /*! MIN_REV
17012  *  0b00000000..Minor revision number for TRNG.
17013  */
17014 #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
17015 #define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
17016 #define TRNG_VID1_MAJ_REV_SHIFT (8U)
17017 /*! MAJ_REV
17018  *  0b00000001..Major revision number for TRNG.
17019  */
17020 #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
17021 #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
17022 #define TRNG_VID1_IP_ID_SHIFT (16U)
17023 /*! IP_ID
17024  *  0b0000000000110000..ID for TRNG.
17025  */
17026 #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
17027 /*! @} */
17028 
17029 /*! @name VID2 - TRNG Version ID Register (LS) */
17030 /*! @{ */
17031 #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
17032 #define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
17033 /*! CONFIG_OPT
17034  *  0b00000000..TRNG_CONFIG_OPT for TRNG.
17035  */
17036 #define TRNG_VID2_CONFIG_OPT(x) \
17037     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
17038 #define TRNG_VID2_ECO_REV_MASK (0xFF00U)
17039 #define TRNG_VID2_ECO_REV_SHIFT (8U)
17040 /*! ECO_REV
17041  *  0b00000000..TRNG_ECO_REV for TRNG.
17042  */
17043 #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
17044 #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
17045 #define TRNG_VID2_INTG_OPT_SHIFT (16U)
17046 /*! INTG_OPT
17047  *  0b00000000..INTG_OPT for TRNG.
17048  */
17049 #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
17050 #define TRNG_VID2_ERA_MASK (0xFF000000U)
17051 #define TRNG_VID2_ERA_SHIFT (24U)
17052 /*! ERA
17053  *  0b00000000..COMPILE_OPT for TRNG.
17054  */
17055 #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
17056 /*! @} */
17057 
17058 /*!
17059  * @}
17060  */ /* end of group TRNG_Register_Masks */
17061 
17062 /* TRNG - Peripheral instance base addresses */
17063 /** Peripheral TRNG base address */
17064 #define TRNG_BASE (0x400A5000u)
17065 /** Peripheral TRNG base pointer */
17066 #define TRNG ((TRNG_Type *)TRNG_BASE)
17067 /** Array initializer of TRNG peripheral base addresses */
17068 #define TRNG_BASE_ADDRS \
17069     {                   \
17070         TRNG_BASE       \
17071     }
17072 /** Array initializer of TRNG peripheral base pointers */
17073 #define TRNG_BASE_PTRS \
17074     {                  \
17075         TRNG           \
17076     }
17077 /** Interrupt vectors for the TRNG peripheral type */
17078 #define TRNG_IRQS \
17079     {             \
17080         TRNG_IRQn \
17081     }
17082 
17083 /*!
17084  * @}
17085  */ /* end of group TRNG_Peripheral_Access_Layer */
17086 
17087 /* ----------------------------------------------------------------------------
17088    -- TSI Peripheral Access Layer
17089    ---------------------------------------------------------------------------- */
17090 
17091 /*!
17092  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
17093  * @{
17094  */
17095 
17096 /** TSI - Register Layout Typedef */
17097 typedef struct
17098 {
17099     __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
17100     __IO uint32_t DATA;  /**< TSI DATA Register, offset: 0x4 */
17101     __IO uint32_t TSHD;  /**< TSI Threshold Register, offset: 0x8 */
17102 } TSI_Type;
17103 
17104 /* ----------------------------------------------------------------------------
17105    -- TSI Register Masks
17106    ---------------------------------------------------------------------------- */
17107 
17108 /*!
17109  * @addtogroup TSI_Register_Masks TSI Register Masks
17110  * @{
17111  */
17112 
17113 /*! @name GENCS - TSI General Control and Status Register */
17114 /*! @{ */
17115 #define TSI_GENCS_EOSDMEO_MASK (0x1U)
17116 #define TSI_GENCS_EOSDMEO_SHIFT (0U)
17117 /*! EOSDMEO - End-of-Scan DMA Transfer Request Enable Only
17118  *  0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or
17119  *       End-of-Scan can trigger a DMA transfer request and interrupt.
17120  *  0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers
17121  * an interrupt if TSIIE is set.
17122  */
17123 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
17124 #define TSI_GENCS_CURSW_MASK (0x2U)
17125 #define TSI_GENCS_CURSW_SHIFT (1U)
17126 /*! CURSW - CURSW
17127  *  0b0..The current source pair are not swapped.
17128  *  0b1..The current source pair are swapped.
17129  */
17130 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
17131 #define TSI_GENCS_EOSF_MASK (0x4U)
17132 #define TSI_GENCS_EOSF_SHIFT (2U)
17133 /*! EOSF - End of Scan Flag
17134  *  0b0..Scan not complete.
17135  *  0b1..Scan complete.
17136  */
17137 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
17138 #define TSI_GENCS_SCNIP_MASK (0x8U)
17139 #define TSI_GENCS_SCNIP_SHIFT (3U)
17140 /*! SCNIP - Scan In Progress Status
17141  *  0b0..No scan in progress.
17142  *  0b1..Scan in progress.
17143  */
17144 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
17145 #define TSI_GENCS_STM_MASK (0x10U)
17146 #define TSI_GENCS_STM_SHIFT (4U)
17147 /*! STM - Scan Trigger Mode
17148  *  0b0..Software trigger scan.
17149  *  0b1..Hardware trigger scan.
17150  */
17151 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
17152 #define TSI_GENCS_STPE_MASK (0x20U)
17153 #define TSI_GENCS_STPE_SHIFT (5U)
17154 /*! STPE - TSI STOP Enable
17155  *  0b0..TSI is disabled when MCU goes into low power mode.
17156  *  0b1..Allows TSI to continue running in all low power modes.
17157  */
17158 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
17159 #define TSI_GENCS_TSIIEN_MASK (0x40U)
17160 #define TSI_GENCS_TSIIEN_SHIFT (6U)
17161 /*! TSIIEN - Touch Sensing Input Interrupt Enable
17162  *  0b0..TSI interrupt is disabled.
17163  *  0b1..TSI interrupt is enabled.
17164  */
17165 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
17166 #define TSI_GENCS_TSIEN_MASK (0x80U)
17167 #define TSI_GENCS_TSIEN_SHIFT (7U)
17168 /*! TSIEN - Touch Sensing Input Module Enable
17169  *  0b0..TSI module disabled.
17170  *  0b1..TSI module enabled.
17171  */
17172 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
17173 #define TSI_GENCS_NSCN_MASK (0x1F00U)
17174 #define TSI_GENCS_NSCN_SHIFT (8U)
17175 /*! NSCN - NSCN
17176  *  0b00000..Once per electrode
17177  *  0b00001..Twice per electrode
17178  *  0b00010..3 times per electrode
17179  *  0b00011..4 times per electrode
17180  *  0b00100..5 times per electrode
17181  *  0b00101..6 times per electrode
17182  *  0b00110..7 times per electrode
17183  *  0b00111..8 times per electrode
17184  *  0b01000..9 times per electrode
17185  *  0b01001..10 times per electrode
17186  *  0b01010..11 times per electrode
17187  *  0b01011..12 times per electrode
17188  *  0b01100..13 times per electrode
17189  *  0b01101..14 times per electrode
17190  *  0b01110..15 times per electrode
17191  *  0b01111..16 times per electrode
17192  *  0b10000..17 times per electrode
17193  *  0b10001..18 times per electrode
17194  *  0b10010..19 times per electrode
17195  *  0b10011..20 times per electrode
17196  *  0b10100..21 times per electrode
17197  *  0b10101..22 times per electrode
17198  *  0b10110..23 times per electrode
17199  *  0b10111..24 times per electrode
17200  *  0b11000..25 times per electrode
17201  *  0b11001..26 times per electrode
17202  *  0b11010..27 times per electrode
17203  *  0b11011..28 times per electrode
17204  *  0b11100..29 times per electrode
17205  *  0b11101..30 times per electrode
17206  *  0b11110..31 times per electrode
17207  *  0b11111..32 times per electrode
17208  */
17209 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
17210 #define TSI_GENCS_PS_MASK (0xE000U)
17211 #define TSI_GENCS_PS_SHIFT (13U)
17212 /*! PS - PS
17213  *  0b000..Electrode Oscillator Frequency divided by 1
17214  *  0b001..Electrode Oscillator Frequency divided by 2
17215  *  0b010..Electrode Oscillator Frequency divided by 4
17216  *  0b011..Electrode Oscillator Frequency divided by 8
17217  *  0b100..Electrode Oscillator Frequency divided by 16
17218  *  0b101..Electrode Oscillator Frequency divided by 32
17219  *  0b110..Electrode Oscillator Frequency divided by 64
17220  *  0b111..Electrode Oscillator Frequency divided by 128
17221  */
17222 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
17223 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
17224 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
17225 /*! EXTCHRG - EXTCHRG
17226  *  0b000..500 nA.
17227  *  0b001..1 uA.
17228  *  0b010..2 uA.
17229  *  0b011..4 uA.
17230  *  0b100..8 uA.
17231  *  0b101..16 uA.
17232  *  0b110..32 uA.
17233  *  0b111..64 uA.
17234  */
17235 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
17236 #define TSI_GENCS_DVOLT_MASK (0x180000U)
17237 #define TSI_GENCS_DVOLT_SHIFT (19U)
17238 /*! DVOLT - DVOLT
17239  *  0b00..DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V.
17240  *  0b01..DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V.
17241  *  0b10..DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V.
17242  *  0b11..DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.
17243  */
17244 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
17245 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
17246 #define TSI_GENCS_REFCHRG_SHIFT (21U)
17247 /*! REFCHRG - REFCHRG
17248  *  0b000..500 nA.
17249  *  0b001..1 uA.
17250  *  0b010..2 uA.
17251  *  0b011..4 uA.
17252  *  0b100..8 uA.
17253  *  0b101..16 uA.
17254  *  0b110..32 uA.
17255  *  0b111..64 uA.
17256  */
17257 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
17258 #define TSI_GENCS_MODE_MASK (0xF000000U)
17259 #define TSI_GENCS_MODE_SHIFT (24U)
17260 /*! MODE - TSI analog modes setup and status
17261  *  0b0000..Set TSI in capacitive sensing(non-noise detection) mode.
17262  *  0b0100..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is
17263  * disabled. 0b1000..Set TSI analog to work in single threshold noise detection mode and the frequency limitation
17264  * circuit is enabled to work in higher frequencies operations. 0b1100..Set TSI analog to work in automatic noise
17265  * detection mode.
17266  */
17267 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
17268 #define TSI_GENCS_ESOR_MASK (0x10000000U)
17269 #define TSI_GENCS_ESOR_SHIFT (28U)
17270 /*! ESOR - End-of-scan or Out-of-Range Interrupt Selection
17271  *  0b0..Out-of-range interrupt is allowed.
17272  *  0b1..End-of-scan interrupt is allowed.
17273  */
17274 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
17275 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
17276 #define TSI_GENCS_OUTRGF_SHIFT (31U)
17277 /*! OUTRGF - Out of Range Flag.
17278  */
17279 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
17280 /*! @} */
17281 
17282 /*! @name DATA - TSI DATA Register */
17283 /*! @{ */
17284 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
17285 #define TSI_DATA_TSICNT_SHIFT (0U)
17286 /*! TSICNT - TSI Conversion Counter Value
17287  */
17288 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
17289 #define TSI_DATA_SWTS_MASK (0x400000U)
17290 #define TSI_DATA_SWTS_SHIFT (22U)
17291 /*! SWTS - Software Trigger Start
17292  *  0b0..No effect.
17293  *  0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH].
17294  */
17295 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
17296 #define TSI_DATA_DMAEN_MASK (0x800000U)
17297 #define TSI_DATA_DMAEN_SHIFT (23U)
17298 /*! DMAEN - DMA Transfer Enabled
17299  *  0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
17300  *  0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
17301  */
17302 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
17303 #define TSI_DATA_TSICH_MASK (0xF0000000U)
17304 #define TSI_DATA_TSICH_SHIFT (28U)
17305 /*! TSICH - TSICH
17306  *  0b0000..Channel 0.
17307  *  0b0001..Channel 1.
17308  *  0b0010..Channel 2.
17309  *  0b0011..Channel 3.
17310  *  0b0100..Channel 4.
17311  *  0b0101..Channel 5.
17312  *  0b0110..Channel 6.
17313  *  0b0111..Channel 7.
17314  *  0b1000..Channel 8.
17315  *  0b1001..Channel 9.
17316  *  0b1010..Channel 10.
17317  *  0b1011..Channel 11.
17318  *  0b1100..Channel 12.
17319  *  0b1101..Channel 13.
17320  *  0b1110..Channel 14.
17321  *  0b1111..Channel 15.
17322  */
17323 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
17324 /*! @} */
17325 
17326 /*! @name TSHD - TSI Threshold Register */
17327 /*! @{ */
17328 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
17329 #define TSI_TSHD_THRESL_SHIFT (0U)
17330 /*! THRESL - TSI Wakeup Channel Low-threshold
17331  */
17332 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
17333 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
17334 #define TSI_TSHD_THRESH_SHIFT (16U)
17335 /*! THRESH - TSI Wakeup Channel High-threshold
17336  */
17337 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
17338 /*! @} */
17339 
17340 /*!
17341  * @}
17342  */ /* end of group TSI_Register_Masks */
17343 
17344 /* TSI - Peripheral instance base addresses */
17345 /** Peripheral TSI0 base address */
17346 #define TSI0_BASE (0x40062000u)
17347 /** Peripheral TSI0 base pointer */
17348 #define TSI0 ((TSI_Type *)TSI0_BASE)
17349 /** Array initializer of TSI peripheral base addresses */
17350 #define TSI_BASE_ADDRS \
17351     {                  \
17352         TSI0_BASE      \
17353     }
17354 /** Array initializer of TSI peripheral base pointers */
17355 #define TSI_BASE_PTRS \
17356     {                 \
17357         TSI0          \
17358     }
17359 /** Interrupt vectors for the TSI peripheral type */
17360 #define TSI_IRQS  \
17361     {             \
17362         TSI0_IRQn \
17363     }
17364 
17365 /*!
17366  * @}
17367  */ /* end of group TSI_Peripheral_Access_Layer */
17368 
17369 /* ----------------------------------------------------------------------------
17370    -- TSTMR Peripheral Access Layer
17371    ---------------------------------------------------------------------------- */
17372 
17373 /*!
17374  * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
17375  * @{
17376  */
17377 
17378 /** TSTMR - Register Layout Typedef */
17379 typedef struct
17380 {
17381     __I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */
17382     __I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */
17383 } TSTMR_Type;
17384 
17385 /* ----------------------------------------------------------------------------
17386    -- TSTMR Register Masks
17387    ---------------------------------------------------------------------------- */
17388 
17389 /*!
17390  * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
17391  * @{
17392  */
17393 
17394 /*! @name L - Time Stamp Timer Register Low */
17395 /*! @{ */
17396 #define TSTMR_L_VALUE_MASK (0xFFFFFFFFU)
17397 #define TSTMR_L_VALUE_SHIFT (0U)
17398 /*! VALUE - Time Stamp Timer Low
17399  */
17400 #define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
17401 /*! @} */
17402 
17403 /*! @name H - Time Stamp Timer Register High */
17404 /*! @{ */
17405 #define TSTMR_H_VALUE_MASK (0xFFFFFFU)
17406 #define TSTMR_H_VALUE_SHIFT (0U)
17407 /*! VALUE - Time Stamp Timer High
17408  */
17409 #define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
17410 /*! @} */
17411 
17412 /*!
17413  * @}
17414  */ /* end of group TSTMR_Register_Masks */
17415 
17416 /* TSTMR - Peripheral instance base addresses */
17417 /** Peripheral TSTMR0 base address */
17418 #define TSTMR0_BASE (0x400750F0u)
17419 /** Peripheral TSTMR0 base pointer */
17420 #define TSTMR0 ((TSTMR_Type *)TSTMR0_BASE)
17421 /** Array initializer of TSTMR peripheral base addresses */
17422 #define TSTMR_BASE_ADDRS \
17423     {                    \
17424         TSTMR0_BASE      \
17425     }
17426 /** Array initializer of TSTMR peripheral base pointers */
17427 #define TSTMR_BASE_PTRS \
17428     {                   \
17429         TSTMR0          \
17430     }
17431 
17432 /*!
17433  * @}
17434  */ /* end of group TSTMR_Peripheral_Access_Layer */
17435 
17436 /* ----------------------------------------------------------------------------
17437    -- USB Peripheral Access Layer
17438    ---------------------------------------------------------------------------- */
17439 
17440 /*!
17441  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
17442  * @{
17443  */
17444 
17445 /** USB - Register Layout Typedef */
17446 typedef struct
17447 {
17448     __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
17449     uint8_t RESERVED_0[3];
17450     __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
17451     uint8_t RESERVED_1[3];
17452     __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
17453     uint8_t RESERVED_2[3];
17454     __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
17455     uint8_t RESERVED_3[3];
17456     __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
17457     uint8_t RESERVED_4[3];
17458     __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
17459     uint8_t RESERVED_5[3];
17460     __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
17461     uint8_t RESERVED_6[3];
17462     __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
17463     uint8_t RESERVED_7[99];
17464     __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
17465     uint8_t RESERVED_8[3];
17466     __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
17467     uint8_t RESERVED_9[3];
17468     __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
17469     uint8_t RESERVED_10[3];
17470     __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
17471     uint8_t RESERVED_11[3];
17472     __I uint8_t STAT; /**< Status register, offset: 0x90 */
17473     uint8_t RESERVED_12[3];
17474     __IO uint8_t CTL; /**< Control register, offset: 0x94 */
17475     uint8_t RESERVED_13[3];
17476     __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
17477     uint8_t RESERVED_14[3];
17478     __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
17479     uint8_t RESERVED_15[3];
17480     __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
17481     uint8_t RESERVED_16[3];
17482     __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
17483     uint8_t RESERVED_17[3];
17484     __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
17485     uint8_t RESERVED_18[3];
17486     __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
17487     uint8_t RESERVED_19[3];
17488     __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
17489     uint8_t RESERVED_20[3];
17490     __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
17491     uint8_t RESERVED_21[11];
17492     struct
17493     {                       /* offset: 0xC0, array step: 0x4 */
17494         __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
17495         uint8_t RESERVED_0[3];
17496     } ENDPOINT[16];
17497     __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
17498     uint8_t RESERVED_22[3];
17499     __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
17500     uint8_t RESERVED_23[3];
17501     __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
17502     uint8_t RESERVED_24[3];
17503     __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
17504     uint8_t RESERVED_25[7];
17505     __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
17506     uint8_t RESERVED_26[23];
17507     __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
17508     uint8_t RESERVED_27[19];
17509     __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
17510     uint8_t RESERVED_28[19];
17511     __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
17512     uint8_t RESERVED_29[7];
17513     __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
17514 } USB_Type;
17515 
17516 /* ----------------------------------------------------------------------------
17517    -- USB Register Masks
17518    ---------------------------------------------------------------------------- */
17519 
17520 /*!
17521  * @addtogroup USB_Register_Masks USB Register Masks
17522  * @{
17523  */
17524 
17525 /*! @name PERID - Peripheral ID register */
17526 /*! @{ */
17527 #define USB_PERID_ID_MASK (0x3FU)
17528 #define USB_PERID_ID_SHIFT (0U)
17529 /*! ID - Peripheral Identification
17530  */
17531 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
17532 /*! @} */
17533 
17534 /*! @name IDCOMP - Peripheral ID Complement register */
17535 /*! @{ */
17536 #define USB_IDCOMP_NID_MASK (0x3FU)
17537 #define USB_IDCOMP_NID_SHIFT (0U)
17538 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
17539 /*! @} */
17540 
17541 /*! @name REV - Peripheral Revision register */
17542 /*! @{ */
17543 #define USB_REV_REV_MASK (0xFFU)
17544 #define USB_REV_REV_SHIFT (0U)
17545 /*! REV - Revision
17546  */
17547 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
17548 /*! @} */
17549 
17550 /*! @name ADDINFO - Peripheral Additional Info register */
17551 /*! @{ */
17552 #define USB_ADDINFO_IEHOST_MASK (0x1U)
17553 #define USB_ADDINFO_IEHOST_SHIFT (0U)
17554 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
17555 /*! @} */
17556 
17557 /*! @name OTGISTAT - OTG Interrupt Status register */
17558 /*! @{ */
17559 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
17560 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
17561 #define USB_OTGISTAT_LINE_STATE_CHG(x) \
17562     (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
17563 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
17564 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
17565 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
17566 /*! @} */
17567 
17568 /*! @name OTGICR - OTG Interrupt Control register */
17569 /*! @{ */
17570 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
17571 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
17572 /*! LINESTATEEN - Line State Change Interrupt Enable
17573  *  0b0..Disables the LINE_STAT_CHG interrupt.
17574  *  0b1..Enables the LINE_STAT_CHG interrupt.
17575  */
17576 #define USB_OTGICR_LINESTATEEN(x) \
17577     (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
17578 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
17579 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
17580 /*! ONEMSECEN - One Millisecond Interrupt Enable
17581  *  0b0..Diables the 1ms timer interrupt.
17582  *  0b1..Enables the 1ms timer interrupt.
17583  */
17584 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
17585 /*! @} */
17586 
17587 /*! @name OTGSTAT - OTG Status register */
17588 /*! @{ */
17589 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
17590 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
17591 /*! LINESTATESTABLE
17592  *  0b0..The LINE_STAT_CHG bit is not yet stable.
17593  *  0b1..The LINE_STAT_CHG bit has been debounced and is stable.
17594  */
17595 #define USB_OTGSTAT_LINESTATESTABLE(x) \
17596     (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
17597 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
17598 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
17599 #define USB_OTGSTAT_ONEMSECEN(x) \
17600     (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
17601 /*! @} */
17602 
17603 /*! @name OTGCTL - OTG Control register */
17604 /*! @{ */
17605 #define USB_OTGCTL_OTGEN_MASK (0x4U)
17606 #define USB_OTGCTL_OTGEN_SHIFT (2U)
17607 /*! OTGEN - On-The-Go pullup/pulldown resistor enable
17608  *  0b0..If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors
17609  *       are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
17610  *  0b1..The pull-up and pull-down controls in this register are used.
17611  */
17612 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
17613 #define USB_OTGCTL_DMLOW_MASK (0x10U)
17614 #define USB_OTGCTL_DMLOW_SHIFT (4U)
17615 /*! DMLOW - D- Data Line pull-down resistor enable
17616  *  0b0..D- pulldown resistor is not enabled.
17617  *  0b1..D- pulldown resistor is enabled.
17618  */
17619 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
17620 #define USB_OTGCTL_DPLOW_MASK (0x20U)
17621 #define USB_OTGCTL_DPLOW_SHIFT (5U)
17622 /*! DPLOW - D+ Data Line pull-down resistor enable
17623  *  0b0..D+ pulldown resistor is not enabled.
17624  *  0b1..D+ pulldown resistor is enabled.
17625  */
17626 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
17627 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
17628 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
17629 /*! DPHIGH - D+ Data Line pullup resistor enable
17630  *  0b0..D+ pullup resistor is not enabled
17631  *  0b1..D+ pullup resistor is enabled
17632  */
17633 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
17634 /*! @} */
17635 
17636 /*! @name ISTAT - Interrupt Status register */
17637 /*! @{ */
17638 #define USB_ISTAT_USBRST_MASK (0x1U)
17639 #define USB_ISTAT_USBRST_SHIFT (0U)
17640 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
17641 #define USB_ISTAT_ERROR_MASK (0x2U)
17642 #define USB_ISTAT_ERROR_SHIFT (1U)
17643 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
17644 #define USB_ISTAT_SOFTOK_MASK (0x4U)
17645 #define USB_ISTAT_SOFTOK_SHIFT (2U)
17646 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
17647 #define USB_ISTAT_TOKDNE_MASK (0x8U)
17648 #define USB_ISTAT_TOKDNE_SHIFT (3U)
17649 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
17650 #define USB_ISTAT_SLEEP_MASK (0x10U)
17651 #define USB_ISTAT_SLEEP_SHIFT (4U)
17652 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
17653 #define USB_ISTAT_RESUME_MASK (0x20U)
17654 #define USB_ISTAT_RESUME_SHIFT (5U)
17655 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
17656 #define USB_ISTAT_ATTACH_MASK (0x40U)
17657 #define USB_ISTAT_ATTACH_SHIFT (6U)
17658 /*! ATTACH - Attach Interrupt
17659  *  0b0..No Attach is detected since the last time the ATTACH bit was cleared.
17660  *  0b1..A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us).
17661  */
17662 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
17663 #define USB_ISTAT_STALL_MASK (0x80U)
17664 #define USB_ISTAT_STALL_SHIFT (7U)
17665 /*! STALL - Stall Interrupt
17666  */
17667 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
17668 /*! @} */
17669 
17670 /*! @name INTEN - Interrupt Enable register */
17671 /*! @{ */
17672 #define USB_INTEN_USBRSTEN_MASK (0x1U)
17673 #define USB_INTEN_USBRSTEN_SHIFT (0U)
17674 /*! USBRSTEN - USBRST Interrupt Enable
17675  *  0b0..Disables the USBRST interrupt.
17676  *  0b1..Enables the USBRST interrupt.
17677  */
17678 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
17679 #define USB_INTEN_ERROREN_MASK (0x2U)
17680 #define USB_INTEN_ERROREN_SHIFT (1U)
17681 /*! ERROREN - ERROR Interrupt Enable
17682  *  0b0..Disables the ERROR interrupt.
17683  *  0b1..Enables the ERROR interrupt.
17684  */
17685 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
17686 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
17687 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
17688 /*! SOFTOKEN - SOFTOK Interrupt Enable
17689  *  0b0..Disbles the SOFTOK interrupt.
17690  *  0b1..Enables the SOFTOK interrupt.
17691  */
17692 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
17693 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
17694 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
17695 /*! TOKDNEEN - TOKDNE Interrupt Enable
17696  *  0b0..Disables the TOKDNE interrupt.
17697  *  0b1..Enables the TOKDNE interrupt.
17698  */
17699 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
17700 #define USB_INTEN_SLEEPEN_MASK (0x10U)
17701 #define USB_INTEN_SLEEPEN_SHIFT (4U)
17702 /*! SLEEPEN - SLEEP Interrupt Enable
17703  *  0b0..Disables the SLEEP interrupt.
17704  *  0b1..Enables the SLEEP interrupt.
17705  */
17706 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
17707 #define USB_INTEN_RESUMEEN_MASK (0x20U)
17708 #define USB_INTEN_RESUMEEN_SHIFT (5U)
17709 /*! RESUMEEN - RESUME Interrupt Enable
17710  *  0b0..Disables the RESUME interrupt.
17711  *  0b1..Enables the RESUME interrupt.
17712  */
17713 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
17714 #define USB_INTEN_ATTACHEN_MASK (0x40U)
17715 #define USB_INTEN_ATTACHEN_SHIFT (6U)
17716 /*! ATTACHEN - ATTACH Interrupt Enable
17717  *  0b0..Disables the ATTACH interrupt.
17718  *  0b1..Enables the ATTACH interrupt.
17719  */
17720 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
17721 #define USB_INTEN_STALLEN_MASK (0x80U)
17722 #define USB_INTEN_STALLEN_SHIFT (7U)
17723 /*! STALLEN - STALL Interrupt Enable
17724  *  0b0..Diasbles the STALL interrupt.
17725  *  0b1..Enables the STALL interrupt.
17726  */
17727 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
17728 /*! @} */
17729 
17730 /*! @name ERRSTAT - Error Interrupt Status register */
17731 /*! @{ */
17732 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
17733 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
17734 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
17735 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
17736 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
17737 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
17738 #define USB_ERRSTAT_CRC16_MASK (0x4U)
17739 #define USB_ERRSTAT_CRC16_SHIFT (2U)
17740 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
17741 #define USB_ERRSTAT_DFN8_MASK (0x8U)
17742 #define USB_ERRSTAT_DFN8_SHIFT (3U)
17743 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
17744 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
17745 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
17746 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
17747 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
17748 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
17749 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
17750 #define USB_ERRSTAT_OWNERR_MASK (0x40U)
17751 #define USB_ERRSTAT_OWNERR_SHIFT (6U)
17752 #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
17753 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
17754 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
17755 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
17756 /*! @} */
17757 
17758 /*! @name ERREN - Error Interrupt Enable register */
17759 /*! @{ */
17760 #define USB_ERREN_PIDERREN_MASK (0x1U)
17761 #define USB_ERREN_PIDERREN_SHIFT (0U)
17762 /*! PIDERREN - PIDERR Interrupt Enable
17763  *  0b0..Disables the PIDERR interrupt.
17764  *  0b1..Enters the PIDERR interrupt.
17765  */
17766 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
17767 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
17768 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
17769 /*! CRC5EOFEN - CRC5/EOF Interrupt Enable
17770  *  0b0..Disables the CRC5/EOF interrupt.
17771  *  0b1..Enables the CRC5/EOF interrupt.
17772  */
17773 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
17774 #define USB_ERREN_CRC16EN_MASK (0x4U)
17775 #define USB_ERREN_CRC16EN_SHIFT (2U)
17776 /*! CRC16EN - CRC16 Interrupt Enable
17777  *  0b0..Disables the CRC16 interrupt.
17778  *  0b1..Enables the CRC16 interrupt.
17779  */
17780 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
17781 #define USB_ERREN_DFN8EN_MASK (0x8U)
17782 #define USB_ERREN_DFN8EN_SHIFT (3U)
17783 /*! DFN8EN - DFN8 Interrupt Enable
17784  *  0b0..Disables the DFN8 interrupt.
17785  *  0b1..Enables the DFN8 interrupt.
17786  */
17787 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
17788 #define USB_ERREN_BTOERREN_MASK (0x10U)
17789 #define USB_ERREN_BTOERREN_SHIFT (4U)
17790 /*! BTOERREN - BTOERR Interrupt Enable
17791  *  0b0..Disables the BTOERR interrupt.
17792  *  0b1..Enables the BTOERR interrupt.
17793  */
17794 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
17795 #define USB_ERREN_DMAERREN_MASK (0x20U)
17796 #define USB_ERREN_DMAERREN_SHIFT (5U)
17797 /*! DMAERREN - DMAERR Interrupt Enable
17798  *  0b0..Disables the DMAERR interrupt.
17799  *  0b1..Enables the DMAERR interrupt.
17800  */
17801 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
17802 #define USB_ERREN_OWNERREN_MASK (0x40U)
17803 #define USB_ERREN_OWNERREN_SHIFT (6U)
17804 /*! OWNERREN - OWNERR Interrupt Enable
17805  *  0b0..Disables the OWNERR interrupt.
17806  *  0b1..Enables the OWNERR interrupt.
17807  */
17808 #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
17809 #define USB_ERREN_BTSERREN_MASK (0x80U)
17810 #define USB_ERREN_BTSERREN_SHIFT (7U)
17811 /*! BTSERREN - BTSERR Interrupt Enable
17812  *  0b0..Disables the BTSERR interrupt.
17813  *  0b1..Enables the BTSERR interrupt.
17814  */
17815 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
17816 /*! @} */
17817 
17818 /*! @name STAT - Status register */
17819 /*! @{ */
17820 #define USB_STAT_ODD_MASK (0x4U)
17821 #define USB_STAT_ODD_SHIFT (2U)
17822 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
17823 #define USB_STAT_TX_MASK (0x8U)
17824 #define USB_STAT_TX_SHIFT (3U)
17825 /*! TX - Transmit Indicator
17826  *  0b0..The most recent transaction was a receive operation.
17827  *  0b1..The most recent transaction was a transmit operation.
17828  */
17829 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
17830 #define USB_STAT_ENDP_MASK (0xF0U)
17831 #define USB_STAT_ENDP_SHIFT (4U)
17832 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
17833 /*! @} */
17834 
17835 /*! @name CTL - Control register */
17836 /*! @{ */
17837 #define USB_CTL_USBENSOFEN_MASK (0x1U)
17838 #define USB_CTL_USBENSOFEN_SHIFT (0U)
17839 /*! USBENSOFEN - USB Enable
17840  *  0b0..Disables the USB Module.
17841  *  0b1..Enables the USB Module.
17842  */
17843 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
17844 #define USB_CTL_ODDRST_MASK (0x2U)
17845 #define USB_CTL_ODDRST_SHIFT (1U)
17846 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
17847 #define USB_CTL_RESUME_MASK (0x4U)
17848 #define USB_CTL_RESUME_SHIFT (2U)
17849 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
17850 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
17851 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
17852 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
17853 #define USB_CTL_RESET_MASK (0x10U)
17854 #define USB_CTL_RESET_SHIFT (4U)
17855 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
17856 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
17857 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
17858 #define USB_CTL_TXSUSPENDTOKENBUSY(x) \
17859     (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
17860 #define USB_CTL_SE0_MASK (0x40U)
17861 #define USB_CTL_SE0_SHIFT (6U)
17862 /*! SE0 - Live USB Single Ended Zero signal
17863  */
17864 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
17865 #define USB_CTL_JSTATE_MASK (0x80U)
17866 #define USB_CTL_JSTATE_SHIFT (7U)
17867 /*! JSTATE - Live USB differential receiver JSTATE signal
17868  */
17869 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
17870 /*! @} */
17871 
17872 /*! @name ADDR - Address register */
17873 /*! @{ */
17874 #define USB_ADDR_ADDR_MASK (0x7FU)
17875 #define USB_ADDR_ADDR_SHIFT (0U)
17876 /*! ADDR - USB Address
17877  */
17878 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
17879 #define USB_ADDR_LSEN_MASK (0x80U)
17880 #define USB_ADDR_LSEN_SHIFT (7U)
17881 /*! LSEN - Low Speed Enable bit
17882  */
17883 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
17884 /*! @} */
17885 
17886 /*! @name BDTPAGE1 - BDT Page register 1 */
17887 /*! @{ */
17888 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
17889 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
17890 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
17891 /*! @} */
17892 
17893 /*! @name FRMNUML - Frame Number register Low */
17894 /*! @{ */
17895 #define USB_FRMNUML_FRM_MASK (0xFFU)
17896 #define USB_FRMNUML_FRM_SHIFT (0U)
17897 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
17898 /*! @} */
17899 
17900 /*! @name FRMNUMH - Frame Number register High */
17901 /*! @{ */
17902 #define USB_FRMNUMH_FRM_MASK (0x7U)
17903 #define USB_FRMNUMH_FRM_SHIFT (0U)
17904 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
17905 /*! @} */
17906 
17907 /*! @name TOKEN - Token register */
17908 /*! @{ */
17909 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
17910 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
17911 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
17912 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
17913 #define USB_TOKEN_TOKENPID_SHIFT (4U)
17914 /*! TOKENPID
17915  *  0b0001..OUT Token. USB Module performs an OUT (TX) transaction.
17916  *  0b1001..IN Token. USB Module performs an In (RX) transaction.
17917  *  0b1101..SETUP Token. USB Module performs a SETUP (TX) transaction
17918  */
17919 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
17920 /*! @} */
17921 
17922 /*! @name SOFTHLD - SOF Threshold register */
17923 /*! @{ */
17924 #define USB_SOFTHLD_CNT_MASK (0xFFU)
17925 #define USB_SOFTHLD_CNT_SHIFT (0U)
17926 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
17927 /*! @} */
17928 
17929 /*! @name BDTPAGE2 - BDT Page Register 2 */
17930 /*! @{ */
17931 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
17932 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
17933 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
17934 /*! @} */
17935 
17936 /*! @name BDTPAGE3 - BDT Page Register 3 */
17937 /*! @{ */
17938 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
17939 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
17940 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
17941 /*! @} */
17942 
17943 /*! @name ENDPT - Endpoint Control register */
17944 /*! @{ */
17945 #define USB_ENDPT_EPHSHK_MASK (0x1U)
17946 #define USB_ENDPT_EPHSHK_SHIFT (0U)
17947 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
17948 #define USB_ENDPT_EPSTALL_MASK (0x2U)
17949 #define USB_ENDPT_EPSTALL_SHIFT (1U)
17950 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
17951 #define USB_ENDPT_EPTXEN_MASK (0x4U)
17952 #define USB_ENDPT_EPTXEN_SHIFT (2U)
17953 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
17954 #define USB_ENDPT_EPRXEN_MASK (0x8U)
17955 #define USB_ENDPT_EPRXEN_SHIFT (3U)
17956 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
17957 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
17958 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
17959 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
17960 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
17961 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
17962 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
17963 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
17964 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
17965 /*! HOSTWOHUB
17966  *  0b0..Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
17967  *  0b1..Low-speed device directly connected. No hub, or no low-speed device attached.
17968  */
17969 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
17970 /*! @} */
17971 
17972 /* The count of USB_ENDPT */
17973 #define USB_ENDPT_COUNT (16U)
17974 
17975 /*! @name USBCTRL - USB Control register */
17976 /*! @{ */
17977 #define USB_USBCTRL_UARTSEL_MASK (0x10U)
17978 #define USB_USBCTRL_UARTSEL_SHIFT (4U)
17979 /*! UARTSEL
17980  *  0b0..USB signals not used as UART signals.
17981  *  0b1..USB signals used as UART signals.
17982  */
17983 #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
17984 #define USB_USBCTRL_UARTCHLS_MASK (0x20U)
17985 #define USB_USBCTRL_UARTCHLS_SHIFT (5U)
17986 /*! UARTCHLS - UART Signal Channel Select
17987  *  0b0..USB DP/DM signals used as UART TX/RX.
17988  *  0b1..USB DP/DM signals used as UART RX/TX.
17989  */
17990 #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
17991 #define USB_USBCTRL_PDE_MASK (0x40U)
17992 #define USB_USBCTRL_PDE_SHIFT (6U)
17993 /*! PDE
17994  *  0b0..Weak pulldowns are disabled on D+ and D-.
17995  *  0b1..Weak pulldowns are enabled on D+ and D-.
17996  */
17997 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
17998 #define USB_USBCTRL_SUSP_MASK (0x80U)
17999 #define USB_USBCTRL_SUSP_SHIFT (7U)
18000 /*! SUSP
18001  *  0b0..USB transceiver is not in suspend state.
18002  *  0b1..USB transceiver is in suspend state.
18003  */
18004 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
18005 /*! @} */
18006 
18007 /*! @name OBSERVE - USB OTG Observe register */
18008 /*! @{ */
18009 #define USB_OBSERVE_DMPD_MASK (0x10U)
18010 #define USB_OBSERVE_DMPD_SHIFT (4U)
18011 /*! DMPD
18012  *  0b0..D- pulldown disabled.
18013  *  0b1..D- pulldown enabled.
18014  */
18015 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
18016 #define USB_OBSERVE_DPPD_MASK (0x40U)
18017 #define USB_OBSERVE_DPPD_SHIFT (6U)
18018 /*! DPPD
18019  *  0b0..D+ pulldown disabled.
18020  *  0b1..D+ pulldown enabled.
18021  */
18022 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
18023 #define USB_OBSERVE_DPPU_MASK (0x80U)
18024 #define USB_OBSERVE_DPPU_SHIFT (7U)
18025 /*! DPPU
18026  *  0b0..D+ pullup disabled.
18027  *  0b1..D+ pullup enabled.
18028  */
18029 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
18030 /*! @} */
18031 
18032 /*! @name CONTROL - USB OTG Control register */
18033 /*! @{ */
18034 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
18035 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
18036 /*! DPPULLUPNONOTG
18037  *  0b0..DP Pullup in non-OTG device mode is not enabled.
18038  *  0b1..DP Pullup in non-OTG device mode is enabled.
18039  */
18040 #define USB_CONTROL_DPPULLUPNONOTG(x) \
18041     (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
18042 /*! @} */
18043 
18044 /*! @name USBTRC0 - USB Transceiver Control register 0 */
18045 /*! @{ */
18046 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
18047 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
18048 /*! USB_RESUME_INT - USB Asynchronous Interrupt
18049  *  0b0..No interrupt was generated.
18050  *  0b1..Interrupt was generated because of the USB asynchronous interrupt.
18051  */
18052 #define USB_USBTRC0_USB_RESUME_INT(x) \
18053     (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
18054 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
18055 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
18056 /*! SYNC_DET - Synchronous USB Interrupt Detect
18057  *  0b0..Synchronous interrupt has not been detected.
18058  *  0b1..Synchronous interrupt has been detected.
18059  */
18060 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
18061 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
18062 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
18063 /*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status
18064  */
18065 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) \
18066     (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
18067 #define USB_USBTRC0_VREDG_DET_MASK (0x8U)
18068 #define USB_USBTRC0_VREDG_DET_SHIFT (3U)
18069 /*! VREDG_DET - VREGIN Rising Edge Interrupt Detect
18070  *  0b0..VREGIN rising edge interrupt has not been detected.
18071  *  0b1..VREGIN rising edge interrupt has been detected.
18072  */
18073 #define USB_USBTRC0_VREDG_DET(x) \
18074     (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
18075 #define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
18076 #define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
18077 /*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect
18078  *  0b0..VREGIN falling edge interrupt has not been detected.
18079  *  0b1..VREGIN falling edge interrupt has been detected.
18080  */
18081 #define USB_USBTRC0_VFEDG_DET(x) \
18082     (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
18083 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
18084 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
18085 /*! USBRESMEN - Asynchronous Resume Interrupt Enable
18086  *  0b0..USB asynchronous wakeup from suspend mode disabled.
18087  *  0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the
18088  *       synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+
18089  *       and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
18090  */
18091 #define USB_USBTRC0_USBRESMEN(x) \
18092     (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
18093 #define USB_USBTRC0_USBRESET_MASK (0x80U)
18094 #define USB_USBTRC0_USBRESET_SHIFT (7U)
18095 /*! USBRESET - USB Reset
18096  *  0b0..Normal USB module operation.
18097  *  0b1..Returns the USB module to its reset state.
18098  */
18099 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
18100 /*! @} */
18101 
18102 /*! @name USBFRMADJUST - Frame Adjust Register */
18103 /*! @{ */
18104 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
18105 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
18106 /*! ADJ - Frame Adjustment
18107  */
18108 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
18109 /*! @} */
18110 
18111 /*! @name MISCCTRL - Miscellaneous Control register */
18112 /*! @{ */
18113 #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
18114 #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
18115 /*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode
18116  *  0b0..SOF_TOK interrupt is set when byte times SOF threshold is reached.
18117  *  0b1..SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped.
18118  */
18119 #define USB_MISCCTRL_SOFDYNTHLD(x) \
18120     (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
18121 #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
18122 #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
18123 /*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select
18124  *  0b0..SOF_TOK interrupt is set according to SOF threshold value.
18125  *  0b1..SOF_TOK interrupt is set when SOF counter reaches 0.
18126  */
18127 #define USB_MISCCTRL_SOFBUSSET(x) \
18128     (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
18129 #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
18130 #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
18131 /*! OWNERRISODIS - OWN Error Detect for ISO IN / ISO OUT Disable
18132  *  0b0..OWN error detect for ISO IN / ISO OUT is not disabled.
18133  *  0b1..OWN error detect for ISO IN / ISO OUT is disabled.
18134  */
18135 #define USB_MISCCTRL_OWNERRISODIS(x) \
18136     (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
18137 #define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
18138 #define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
18139 /*! VREDG_EN - VREGIN Rising Edge Interrupt Enable
18140  *  0b0..VREGIN rising edge interrupt disabled.
18141  *  0b1..VREGIN rising edge interrupt enabled.
18142  */
18143 #define USB_MISCCTRL_VREDG_EN(x) \
18144     (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
18145 #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
18146 #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
18147 /*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable
18148  *  0b0..VREGIN falling edge interrupt disabled.
18149  *  0b1..VREGIN falling edge interrupt enabled.
18150  */
18151 #define USB_MISCCTRL_VFEDG_EN(x) \
18152     (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
18153 /*! @} */
18154 
18155 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
18156 /*! @{ */
18157 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
18158 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
18159 /*! RESTART_IFRTRIM_EN - Restart from IFR trim value
18160  *  0b0..Trim fine adjustment always works based on the previous updated trim fine value (default)
18161  *  0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is
18162  * desasserted
18163  */
18164 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x)                                  \
18165     (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & \
18166      USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
18167 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
18168 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
18169 /*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
18170  *  0b0..Always works in tracking phase after the first time rough to track transition (default)
18171  *  0b1..Go back to rough stage whenever bus reset or bus resume occurs
18172  */
18173 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x)                                  \
18174     (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & \
18175      USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
18176 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
18177 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
18178 /*! CLOCK_RECOVER_EN - Crystal-less USB enable
18179  *  0b0..Disable clock recovery block (default)
18180  *  0b1..Enable clock recovery block
18181  */
18182 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x)                                  \
18183     (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & \
18184      USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
18185 /*! @} */
18186 
18187 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
18188 /*! @{ */
18189 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
18190 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
18191 /*! OVF_ERROR_EN
18192  *  0b0..The interrupt will be masked
18193  *  0b1..The interrupt will be enabled (default)
18194  */
18195 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)                                  \
18196     (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & \
18197      USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
18198 /*! @} */
18199 
18200 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
18201 /*! @{ */
18202 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
18203 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
18204 /*! OVF_ERROR
18205  *  0b0..No interrupt is reported
18206  *  0b1..Unmasked interrupt has been generated
18207  */
18208 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)                                  \
18209     (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & \
18210      USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
18211 /*! @} */
18212 
18213 /*!
18214  * @}
18215  */ /* end of group USB_Register_Masks */
18216 
18217 /* USB - Peripheral instance base addresses */
18218 /** Peripheral USB0 base address */
18219 #define USB0_BASE (0x40055000u)
18220 /** Peripheral USB0 base pointer */
18221 #define USB0 ((USB_Type *)USB0_BASE)
18222 /** Array initializer of USB peripheral base addresses */
18223 #define USB_BASE_ADDRS \
18224     {                  \
18225         USB0_BASE      \
18226     }
18227 /** Array initializer of USB peripheral base pointers */
18228 #define USB_BASE_PTRS \
18229     {                 \
18230         USB0          \
18231     }
18232 /** Interrupt vectors for the USB peripheral type */
18233 #define USB_IRQS  \
18234     {             \
18235         USB0_IRQn \
18236     }
18237 
18238 /*!
18239  * @}
18240  */ /* end of group USB_Peripheral_Access_Layer */
18241 
18242 /* ----------------------------------------------------------------------------
18243    -- VREF Peripheral Access Layer
18244    ---------------------------------------------------------------------------- */
18245 
18246 /*!
18247  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
18248  * @{
18249  */
18250 
18251 /** VREF - Register Layout Typedef */
18252 typedef struct
18253 {
18254     __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
18255     __IO uint8_t SC;  /**< VREF Status and Control Register, offset: 0x1 */
18256     uint8_t RESERVED_0[3];
18257     __IO uint8_t TRM4; /**< VREF Trim Register 4, offset: 0x5 */
18258 } VREF_Type;
18259 
18260 /* ----------------------------------------------------------------------------
18261    -- VREF Register Masks
18262    ---------------------------------------------------------------------------- */
18263 
18264 /*!
18265  * @addtogroup VREF_Register_Masks VREF Register Masks
18266  * @{
18267  */
18268 
18269 /*! @name TRM - VREF Trim Register */
18270 /*! @{ */
18271 #define VREF_TRM_TRIM_MASK (0x3FU)
18272 #define VREF_TRM_TRIM_SHIFT (0U)
18273 /*! TRIM - Trim bits
18274  *  0b000000..Min
18275  *  0b000001..Max-(31 mV)
18276  *  0b111111..Max
18277  */
18278 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
18279 #define VREF_TRM_CHOPEN_MASK (0x40U)
18280 #define VREF_TRM_CHOPEN_SHIFT (6U)
18281 /*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the
18282  *    internal analog offset will be minimized.
18283  *  0b0..Chop oscillator is disabled.
18284  *  0b1..Chop oscillator is enabled.
18285  */
18286 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
18287 #define VREF_TRM_FLIP_MASK (0x80U)
18288 #define VREF_TRM_FLIP_SHIFT (7U)
18289 #define VREF_TRM_FLIP(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_FLIP_SHIFT)) & VREF_TRM_FLIP_MASK)
18290 /*! @} */
18291 
18292 /*! @name SC - VREF Status and Control Register */
18293 /*! @{ */
18294 #define VREF_SC_MODE_LV_MASK (0x3U)
18295 #define VREF_SC_MODE_LV_SHIFT (0U)
18296 /*! MODE_LV - Buffer Mode selection
18297  *  0b00..Bandgap on only, for stabilization and startup
18298  *  0b01..High power buffer mode enabled
18299  *  0b10..Low-power buffer mode enabled
18300  *  0b11..Reserved
18301  */
18302 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
18303 #define VREF_SC_VREFST_MASK (0x4U)
18304 #define VREF_SC_VREFST_SHIFT (2U)
18305 /*! VREFST - Internal Voltage Reference stable
18306  *  0b0..The module is disabled or not stable.
18307  *  0b1..The module is stable.
18308  */
18309 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
18310 #define VREF_SC_TMUXEN_MASK (0x8U)
18311 #define VREF_SC_TMUXEN_SHIFT (3U)
18312 /*! TMUXEN - Test MUX enable
18313  *  0b0..Disabled
18314  *  0b1..Enabled
18315  */
18316 #define VREF_SC_TMUXEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_TMUXEN_SHIFT)) & VREF_SC_TMUXEN_MASK)
18317 #define VREF_SC_TRESEN_MASK (0x10U)
18318 #define VREF_SC_TRESEN_SHIFT (4U)
18319 /*! TRESEN - Test second order curvature compensation enable
18320  *  0b0..Disabled
18321  *  0b1..Enabled
18322  */
18323 #define VREF_SC_TRESEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_TRESEN_SHIFT)) & VREF_SC_TRESEN_MASK)
18324 #define VREF_SC_ICOMPEN_MASK (0x20U)
18325 #define VREF_SC_ICOMPEN_SHIFT (5U)
18326 /*! ICOMPEN - Second order curvature compensation enable
18327  *  0b0..Disabled
18328  *  0b1..Enabled
18329  */
18330 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
18331 #define VREF_SC_REGEN_MASK (0x40U)
18332 #define VREF_SC_REGEN_SHIFT (6U)
18333 /*! REGEN - Regulator enable
18334  *  0b0..Internal 1.75 V regulator is disabled.
18335  *  0b1..Internal 1.75 V regulator is enabled.
18336  */
18337 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
18338 #define VREF_SC_VREFEN_MASK (0x80U)
18339 #define VREF_SC_VREFEN_SHIFT (7U)
18340 /*! VREFEN - Internal Voltage Reference enable
18341  *  0b0..The module is disabled.
18342  *  0b1..The module is enabled.
18343  */
18344 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
18345 /*! @} */
18346 
18347 /*! @name TRM4 - VREF Trim Register 4 */
18348 /*! @{ */
18349 #define VREF_TRM4_TRIM2V1_MASK (0x3FU)
18350 #define VREF_TRM4_TRIM2V1_SHIFT (0U)
18351 /*! TRIM2V1 - VREF 2.1V Trim Bits
18352  */
18353 #define VREF_TRM4_TRIM2V1(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_TRIM2V1_SHIFT)) & VREF_TRM4_TRIM2V1_MASK)
18354 #define VREF_TRM4_VREF2V1_EN_MASK (0x80U)
18355 #define VREF_TRM4_VREF2V1_EN_SHIFT (7U)
18356 /*! VREF2V1_EN - Internal Voltage Reference (2.1V) Enable
18357  *  0b0..VREF 2.1V is enabled
18358  *  0b1..VREF 2.1V is disabled
18359  */
18360 #define VREF_TRM4_VREF2V1_EN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK)
18361 /*! @} */
18362 
18363 /*!
18364  * @}
18365  */ /* end of group VREF_Register_Masks */
18366 
18367 /* VREF - Peripheral instance base addresses */
18368 /** Peripheral VREF base address */
18369 #define VREF_BASE (0x40072000u)
18370 /** Peripheral VREF base pointer */
18371 #define VREF ((VREF_Type *)VREF_BASE)
18372 /** Array initializer of VREF peripheral base addresses */
18373 #define VREF_BASE_ADDRS \
18374     {                   \
18375         VREF_BASE       \
18376     }
18377 /** Array initializer of VREF peripheral base pointers */
18378 #define VREF_BASE_PTRS \
18379     {                  \
18380         VREF           \
18381     }
18382 
18383 /*!
18384  * @}
18385  */ /* end of group VREF_Peripheral_Access_Layer */
18386 
18387 /* ----------------------------------------------------------------------------
18388    -- WDOG Peripheral Access Layer
18389    ---------------------------------------------------------------------------- */
18390 
18391 /*!
18392  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
18393  * @{
18394  */
18395 
18396 /** WDOG - Register Layout Typedef */
18397 typedef struct
18398 {
18399     __IO uint32_t CS;    /**< Watchdog Control and Status Register, offset: 0x0 */
18400     __IO uint32_t CNT;   /**< Watchdog Counter Register, offset: 0x4 */
18401     __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
18402     __IO uint32_t WIN;   /**< Watchdog Window Register, offset: 0xC */
18403 } WDOG_Type;
18404 
18405 /* ----------------------------------------------------------------------------
18406    -- WDOG Register Masks
18407    ---------------------------------------------------------------------------- */
18408 
18409 /*!
18410  * @addtogroup WDOG_Register_Masks WDOG Register Masks
18411  * @{
18412  */
18413 
18414 /*! @name CS - Watchdog Control and Status Register */
18415 /*! @{ */
18416 #define WDOG_CS_STOP_MASK (0x1U)
18417 #define WDOG_CS_STOP_SHIFT (0U)
18418 /*! STOP - Stop Enable
18419  *  0b0..Watchdog disabled in chip stop mode.
18420  *  0b1..Watchdog enabled in chip stop mode.
18421  */
18422 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
18423 #define WDOG_CS_WAIT_MASK (0x2U)
18424 #define WDOG_CS_WAIT_SHIFT (1U)
18425 /*! WAIT - Wait Enable
18426  *  0b0..Watchdog disabled in chip wait mode.
18427  *  0b1..Watchdog enabled in chip wait mode.
18428  */
18429 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
18430 #define WDOG_CS_DBG_MASK (0x4U)
18431 #define WDOG_CS_DBG_SHIFT (2U)
18432 /*! DBG - Debug Enable
18433  *  0b0..Watchdog disabled in chip debug mode.
18434  *  0b1..Watchdog enabled in chip debug mode.
18435  */
18436 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
18437 #define WDOG_CS_TST_MASK (0x18U)
18438 #define WDOG_CS_TST_SHIFT (3U)
18439 /*! TST - Watchdog Test
18440  *  0b00..Watchdog test mode disabled.
18441  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
18442  *        use this setting to indicate that the watchdog is functioning normally in user mode.
18443  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
18444  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
18445  */
18446 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
18447 #define WDOG_CS_UPDATE_MASK (0x20U)
18448 #define WDOG_CS_UPDATE_SHIFT (5U)
18449 /*! UPDATE - Allow updates
18450  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a
18451  * reset. 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after
18452  * performing the unlock write sequence.
18453  */
18454 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
18455 #define WDOG_CS_INT_MASK (0x40U)
18456 #define WDOG_CS_INT_SHIFT (6U)
18457 /*! INT - Watchdog Interrupt
18458  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
18459  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
18460  */
18461 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
18462 #define WDOG_CS_EN_MASK (0x80U)
18463 #define WDOG_CS_EN_SHIFT (7U)
18464 /*! EN - Watchdog Enable
18465  *  0b0..Watchdog disabled.
18466  *  0b1..Watchdog enabled.
18467  */
18468 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
18469 #define WDOG_CS_CLK_MASK (0x300U)
18470 #define WDOG_CS_CLK_SHIFT (8U)
18471 /*! CLK - Watchdog Clock
18472  *  0b00..Bus clock.
18473  *  0b01..Internal low-power oscillator (LPOCLK).
18474  *  0b10..8 MHz internal reference clock.
18475  *  0b11..External clock source.
18476  */
18477 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
18478 #define WDOG_CS_PRES_MASK (0x1000U)
18479 #define WDOG_CS_PRES_SHIFT (12U)
18480 /*! PRES - Watchdog Prescalar
18481  *  0b0..256 prescalar disabled.
18482  *  0b1..256 prescalar enabled.
18483  */
18484 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
18485 #define WDOG_CS_CMD32EN_MASK (0x2000U)
18486 #define WDOG_CS_CMD32EN_SHIFT (13U)
18487 /*! CMD32EN
18488  *  0b0..Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
18489  *  0b1..Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
18490  */
18491 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
18492 #define WDOG_CS_FLG_MASK (0x4000U)
18493 #define WDOG_CS_FLG_SHIFT (14U)
18494 /*! FLG - Watchdog Interrupt Flag
18495  *  0b0..No interrupt occurred.
18496  *  0b1..An interrupt occurred.
18497  */
18498 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
18499 #define WDOG_CS_WIN_MASK (0x8000U)
18500 #define WDOG_CS_WIN_SHIFT (15U)
18501 /*! WIN - Watchdog Window
18502  *  0b0..Window mode disabled.
18503  *  0b1..Window mode enabled.
18504  */
18505 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
18506 /*! @} */
18507 
18508 /*! @name CNT - Watchdog Counter Register */
18509 /*! @{ */
18510 #define WDOG_CNT_CNTLOW_MASK (0xFFU)
18511 #define WDOG_CNT_CNTLOW_SHIFT (0U)
18512 /*! CNTLOW - Low byte of the Watchdog Counter
18513  */
18514 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
18515 #define WDOG_CNT_CNTHIGH_MASK (0xFF00U)
18516 #define WDOG_CNT_CNTHIGH_SHIFT (8U)
18517 /*! CNTHIGH - High byte of the Watchdog Counter
18518  */
18519 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
18520 /*! @} */
18521 
18522 /*! @name TOVAL - Watchdog Timeout Value Register */
18523 /*! @{ */
18524 #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU)
18525 #define WDOG_TOVAL_TOVALLOW_SHIFT (0U)
18526 /*! TOVALLOW - Low byte of the timeout value
18527  */
18528 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
18529 #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
18530 #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U)
18531 /*! TOVALHIGH - High byte of the timeout value;
18532  */
18533 #define WDOG_TOVAL_TOVALHIGH(x) \
18534     (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
18535 /*! @} */
18536 
18537 /*! @name WIN - Watchdog Window Register */
18538 /*! @{ */
18539 #define WDOG_WIN_WINLOW_MASK (0xFFU)
18540 #define WDOG_WIN_WINLOW_SHIFT (0U)
18541 /*! WINLOW - Low byte of Watchdog Window
18542  */
18543 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
18544 #define WDOG_WIN_WINHIGH_MASK (0xFF00U)
18545 #define WDOG_WIN_WINHIGH_SHIFT (8U)
18546 /*! WINHIGH - High byte of Watchdog Window
18547  */
18548 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
18549 /*! @} */
18550 
18551 /*!
18552  * @}
18553  */ /* end of group WDOG_Register_Masks */
18554 
18555 /* WDOG - Peripheral instance base addresses */
18556 /** Peripheral WDOG0 base address */
18557 #define WDOG0_BASE (0x40076000u)
18558 /** Peripheral WDOG0 base pointer */
18559 #define WDOG0 ((WDOG_Type *)WDOG0_BASE)
18560 /** Array initializer of WDOG peripheral base addresses */
18561 #define WDOG_BASE_ADDRS \
18562     {                   \
18563         WDOG0_BASE      \
18564     }
18565 /** Array initializer of WDOG peripheral base pointers */
18566 #define WDOG_BASE_PTRS \
18567     {                  \
18568         WDOG0          \
18569     }
18570 /** Interrupt vectors for the WDOG peripheral type */
18571 #define WDOG_IRQS  \
18572     {              \
18573         WDOG0_IRQn \
18574     }
18575 #define WDOG_UPDATE_KEY (0xD928C520U)
18576 #define WDOG_REFRESH_KEY (0xB480A602U)
18577 
18578 /*!
18579  * @}
18580  */ /* end of group WDOG_Peripheral_Access_Layer */
18581 
18582 /*
18583 ** End of section using anonymous unions
18584 */
18585 
18586 #if defined(__ARMCC_VERSION)
18587 #if (__ARMCC_VERSION >= 6010050)
18588 #pragma clang diagnostic pop
18589 #else
18590 #pragma pop
18591 #endif
18592 #elif defined(__CWCC__)
18593 #pragma pop
18594 #elif defined(__GNUC__)
18595 /* leave anonymous unions enabled */
18596 #elif defined(__IAR_SYSTEMS_ICC__)
18597 #pragma language = default
18598 #else
18599 #error Not supported compiler type
18600 #endif
18601 
18602 /*!
18603  * @}
18604  */ /* end of group Peripheral_access_layer */
18605 
18606 /* ----------------------------------------------------------------------------
18607    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
18608    ---------------------------------------------------------------------------- */
18609 
18610 /*!
18611  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
18612  * @{
18613  */
18614 
18615 #if defined(__ARMCC_VERSION)
18616 #if (__ARMCC_VERSION >= 6010050)
18617 #pragma clang system_header
18618 #endif
18619 #elif defined(__IAR_SYSTEMS_ICC__)
18620 #pragma system_include
18621 #endif
18622 
18623 /**
18624  * @brief Mask and left-shift a bit field value for use in a register bit range.
18625  * @param field Name of the register bit field.
18626  * @param value Value of the bit field.
18627  * @return Masked and shifted value.
18628  */
18629 #define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK))
18630 /**
18631  * @brief Mask and right-shift a register value to extract a bit field value.
18632  * @param field Name of the register bit field.
18633  * @param value Value of the register.
18634  * @return Masked and shifted bit field value.
18635  */
18636 #define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT))
18637 
18638 /*!
18639  * @}
18640  */ /* end of group Bit_Field_Generic_Macros */
18641 
18642 /* ----------------------------------------------------------------------------
18643    -- SDK Compatibility
18644    ---------------------------------------------------------------------------- */
18645 
18646 /*!
18647  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
18648  * @{
18649  */
18650 
18651 #define FPTA_BASE FGPIOA_BASE
18652 #define FPTA FGPIOA
18653 #define PTA_BASE GPIOA_BASE
18654 #define PTA GPIOA
18655 #define PTB_BASE GPIOB_BASE
18656 #define PTB GPIOB
18657 #define PTC_BASE GPIOC_BASE
18658 #define PTC GPIOC
18659 #define PTD_BASE GPIOD_BASE
18660 #define PTD GPIOD
18661 #define PTE_BASE GPIOE_BASE
18662 #define PTE GPIOE
18663 #define LPTimer_IRQn LPTMR0_IRQn
18664 #define LPTimer_IRQHandler LPTMR0_IRQHandler
18665 #define TRNG0 TRNG
18666 #define CAU CAU0
18667 #define CAU_BASE CAU0_BASE
18668 
18669 /*!
18670  * @}
18671  */ /* end of group SDK_Compatibility_Symbols */
18672 
18673 #endif /* _K32L2A31A_H_ */
18674