1 /*
2  * Copyright 2022 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_PM_DEVICE_H_
9 #define _FSL_PM_DEVICE_H_
10 
11 #include "fsl_common.h"
12 
13 #include "fsl_pm_config.h"
14 
15 /*!
16  * @addtogroup PM Framework: Power Manager Framework
17  * @brief This section includes Power Mode macros, System Constraints macros, and Wakeup source macros.
18  * @{
19  */
20 
21 /*!
22  * @name Power Mode Definition
23  * @{
24  */
25 
26 /* Power Mode Index */
27 #define PM_LP_STATE_SLEEP                (0U)
28 #define PM_LP_STATE_DEEP_SLEEP           (1U)
29 #define PM_LP_STATE_DEEP_POWER_DOWN      (2U)
30 #define PM_LP_STATE_FULL_DEEP_POWER_DOWN (3U)
31 #define PM_LP_STATE_NO_CONSTRAINT        (0xFFU)
32 
33 /* @} */
34 
35 /* Temporary workaround as enumeration for PORCORE is missing in fsl_power header file. Will be removed once supported. */
36 #define kPDRUNCFG_LP_PORCORE (pd_bit_t)(MAKE_PD_BITS(PDRCFG0, 8U))
37 
38 /* Helper macros */
39 #define PM_RESC_MASK(resc_masks, resc) (resc_masks->rescMask[resc / 32L] >> (resc % 32L)) & 1U
40 #define PM_RESC_GROUP(resc_groups, resc) (resc_groups->groupSlice[resc / 8] >> (4 * (resc % 8))) & 0xFU
41 
42 /*!
43  * @name System basic resource constraints definitions.
44  * @{
45  */
46 
47 /*! @brief Available constraints for resources
48  *
49  *  The constraints below are grouped together in 3 groups
50  */
51 
52 typedef enum _resc_name
53 {
54     /* Peripherals and RAMs that do not have separate retention bit */
55     kResc_MAIN_CLK       = 0,   /*!< Main Clock */
56     kResc_VDDCOREREG_HP     ,   /*!< VDDCORE Regulator */
57     kResc_PMCREF_HP         ,   /*!< PMC Reference */
58     kResc_HVD1V8            ,   /*!< 1.8V High-Voltage Detect */
59     kResc_PORCORE_HP        ,   /*!< VDDCORE Power-On Reset monitor */
60     kResc_LVDCORE_HP        ,   /*!< VDDCORE Low-Voltage Detect */
61     kResc_HVDCORE           ,   /*!< VDDCORE High-Voltage Detect */
62     kResc_SYSXTAL           ,   /*!< System crystal oscillator */
63     kResc_LPOSC             ,   /*!< Low-Power Oscillator */
64     kResc_FRO               ,   /*!< Free-Running Oscillator */
65     kResc_SYSPLLLDO         ,   /*!< LDO for System PLL */
66     kResc_SYSPLLANA         ,   /*!< Analog for System PLL */
67     kResc_AUDIOPLLLDO       ,   /*!< LDO for Audio PLL */
68     kResc_AUDIOPLLANA       ,   /*!< Analog for Audio PLL */
69     kResc_ADC_ACTIVE        ,   /*!< ADC Powered */
70     kResc_ADC_TEMP          ,   /*!< ADC Temperature sensor */
71     kResc_PMC_TEMP          ,   /*!< PMC Temperature sensor */
72     kResc_ACMP              ,   /*!< Analog Comparator */
73     kResc_SRAM_PQ           ,   /*!< PowerQuad SRAM */
74     kResc_SRAM_CASPER       ,   /*!< CASPER SRAM */
75     kResc_DSP               ,   /*!< DSP */
76     kResc_MIPIDSI           ,   /*!< MIPI-DSI */
77     kResc_OTP               ,   /*!< OTP */
78     kResc_ROM               ,   /*!< ROM */
79 
80     /* dedicated peripheral SRAMs that have 2 bits each in PDSLEEPCFG1 */
81     kResc_SRAM_FLEXSPI0     ,   /*!< FlexSPI0 SRAM */
82     kResc_SRAM_FLEXSPI1     ,   /*!< FlexSPI1 SRAM */
83     kResc_SRAM_USB          ,   /*!< USB SRAM */
84     kResc_SRAM_USDHC0       ,   /*!< uSDHC0 SRAM */
85     kResc_SRAM_USDHC1       ,   /*!< uSDHC1 SRAM */
86     kResc_SRAM_GPU          ,   /*!< GPU SRAM */
87     kResc_SRAM_SMARTDMA     ,   /*!< SmartDMA SRAM */
88     kResc_SRAM_MIPIDSI      ,   /*!< MIPI-DSI SRAM */
89     kResc_SRAM_LCDIF        ,   /*!< LCD Interface SRAM */
90 
91     /* System SRAMs that have bits in both PDSLEEPCFG2 & 3 */
92     kResc_SRAM0_32KB        ,   /*!< SRAM partition0 */
93     kResc_SRAM1_32KB        ,   /*!< SRAM partition1 */
94     kResc_SRAM2_32KB        ,   /*!< SRAM partition2 */
95     kResc_SRAM3_32KB        ,   /*!< SRAM partition3 */
96     kResc_SRAM4_32KB        ,   /*!< SRAM partition4 */
97     kResc_SRAM5_32KB        ,   /*!< SRAM partition5 */
98     kResc_SRAM6_32KB        ,   /*!< SRAM partition6 */
99     kResc_SRAM7_32KB        ,   /*!< SRAM partition7 */
100     kResc_SRAM8_64KB        ,   /*!< SRAM partition8 */
101     kResc_SRAM9_64KB        ,   /*!< SRAM partition9 */
102     kResc_SRAM10_64KB       ,   /*!< SRAM partition10 */
103     kResc_SRAM11_64KB       ,   /*!< SRAM partition11 */
104     kResc_SRAM12_128KB      ,   /*!< SRAM partition12 */
105     kResc_SRAM13_128KB      ,   /*!< SRAM partition13 */
106     kResc_SRAM14_128KB      ,   /*!< SRAM partition14 */
107     kResc_SRAM15_128KB      ,   /*!< SRAM partition15 */
108     kResc_SRAM16_256KB      ,   /*!< SRAM partition16 */
109     kResc_SRAM17_256KB      ,   /*!< SRAM partition17 */
110     kResc_SRAM18_256KB      ,   /*!< SRAM partition18 */
111     kResc_SRAM19_256KB      ,   /*!< SRAM partition19 */
112     kResc_SRAM20_256KB      ,   /*!< SRAM partition20 */
113     kResc_SRAM21_256KB      ,   /*!< SRAM partition21 */
114     kResc_SRAM22_256KB      ,   /*!< SRAM partition22 */
115     kResc_SRAM23_256KB      ,   /*!< SRAM partition23 */
116     kResc_SRAM24_256KB      ,   /*!< SRAM partition24 */
117     kResc_SRAM25_256KB      ,   /*!< SRAM partition25 */
118     kResc_SRAM26_256KB      ,   /*!< SRAM partition26 */
119     kResc_SRAM27_256KB      ,   /*!< SRAM partition27 */
120     kResc_SRAM28_256KB      ,   /*!< SRAM partition28 */
121     kResc_SRAM29_256KB      ,   /*!< SRAM partition29 */
122     kResc_SRAM30_256KB      ,   /*!< SRAM partition30 */
123     kResc_SRAM31_256KB      ,   /*!< SRAM partition31 */
124 
125     kResc_MaxNum            ,   /*!< Maximum number of supported constraints */
126 } resc_name_t;
127 
128 /* Macros for Resource Constraint Group Types */
129 #define RESC_GROUP_PRAMS_START          kResc_SRAM_FLEXSPI0
130 #define RESC_GROUP_PRAMS_END            kResc_SRAM_LCDIF
131 #define RESC_GROUP_PRAMS_SIZE           RESC_GROUP_PRAMS_END - RESC_GROUP_PRAMS_START + 1
132 
133 #define RESC_GROUP_SRAMS_START          kResc_SRAM0_32KB
134 #define RESC_GROUP_SRAMS_END            kResc_SRAM31_256KB
135 #define RESC_GROUP_SRAMS_SIZE           RESC_GROUP_SRAMS_END - RESC_GROUP_SRAMS_START + 1
136 
137 #define RESC_GROUP_PERIPHERALS_START    kResc_MAIN_CLK
138 #define RESC_GROUP_PERIPHERALS_END      kResc_ROM
139 #define RESC_GROUP_PERIPHERALS_SIZE     RESC_GROUP_PERIPHERALS_END - RESC_GROUP_PERIPHERALS_START + 1
140 
141 /*!
142  * @brief Structure for peripheral SRAM resources, or bits in PDSLEEPCFG
143  *
144  */
145 typedef struct _enabled_resources_prams
146 {
147     uint32_t apd_mask; /*!< PDSLEEPCFG1 mask for Array PD */
148     uint32_t ppd_mask; /*!< PDSLEEPCFG1 mask for Periphery PD */
149 } enabled_resources_prams_t;
150 
151 /*!
152  * @brief Structure for other peripheral resources, or bit in PDSLEEPCFG
153  *
154  */
155 typedef struct _enabled_resources_peripherals
156 {
157     uint8_t  group; /*!< Group for this enabled resource */
158     uint32_t mask;  /*!< Mask in group for this enabled resource */
159 } enabled_resources_peripherals_t;
160 
161 
162 /* Constraints used by application. */
163 #define PM_RESC_MAIN_CLK_ON         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_MAIN_CLK)
164 #define PM_RESC_VDDCOREREG_HP       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_VDDCOREREG_HP)
165 #define PM_RESC_PMCREF_HP           PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMCREF_HP)
166 #define PM_RESC_HVD1V8_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVD1V8)
167 #define PM_RESC_PORCORE_HP          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PORCORE_HP)
168 #define PM_RESC_LVDCORE_HP          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LVDCORE_HP)
169 #define PM_RESC_HVDCORE_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_HVDCORE)
170 #define PM_RESC_SYSXTAL_ON          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SYSXTAL)
171 #define PM_RESC_LPOSC_ON            PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_LPOSC)
172 #define PM_RESC_FRO_192M96M_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_FRO)
173 #define PM_RESC_SYSPLLLDO_ON        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SYSPLLLDO)
174 #define PM_RESC_SYSPLLANA_ON        PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SYSPLLANA)
175 #define PM_RESC_AUDIOPLLLDO_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDIOPLLLDO)
176 #define PM_RESC_AUDIOPLLANA_ON      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_AUDIOPLLANA)
177 #define PM_RESC_ADC_TEMP_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ADC_TEMP)
178 #define PM_RESC_PMC_TEMP_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_PMC_TEMP)
179 #define PM_RESC_ACMP_ACTIVE         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ACMP)
180 #define PM_RESC_PQ_SRAM_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_PQ)
181 #define PM_RESC_CASPER_SRAM_ACTIVE  PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CASPER)
182 #define PM_RESC_DSP_ACTIVE          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_DSP)
183 #define PM_RESC_MIPIDSI_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_MIPIDSI)
184 #define PM_RESC_OTP_ACTIVE          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_OTP)
185 #define PM_RESC_ROM_ACTIVE          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ROM)
186 
187 /* Note, to keep the ADC active in Sleep and Deep Sleep modes, the application must ensure the
188  * ADC CTRL[DOZEN] bit is clear.  The fsl_lpadc driver configures this bit with the
189  * LPADC_Init() API.
190  */
191 #define PM_RESC_ADC_ACTIVE          PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_ADC_ACTIVE)
192 
193 #define PM_RESC_FLEXSPI0_SRAM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_FLEXSPI0)
194 #define PM_RESC_FLEXSPI0_SRAM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_FLEXSPI0)
195 
196 #define PM_RESC_FLEXSPI1_SRAM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_FLEXSPI1)
197 #define PM_RESC_FLEXSPI1_SRAM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_FLEXSPI1)
198 
199 #define PM_RESC_USB_SRAM_ACTIVE         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_USB)
200 #define PM_RESC_USB_SRAM_RETENTION      PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USB)
201 
202 #define PM_RESC_USDHC0_SRAM_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_USDHC0)
203 #define PM_RESC_USDHC0_SRAM_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC0)
204 
205 #define PM_RESC_USDHC1_SRAM_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_USDHC1)
206 #define PM_RESC_USDHC1_SRAM_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_USDHC1)
207 
208 #define PM_RESC_GPU_SRAM_ACTIVE         PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_GPU)
209 #define PM_RESC_GPU_SRAM_RETENTION      PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_GPU)
210 
211 #define PM_RESC_SMARTDMA_SRAM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_SMARTDMA)
212 #define PM_RESC_SMARTDMA_SRAM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_SMARTDMA)
213 
214 #define PM_RESC_MIPIDSI_SRAM_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_MIPIDSI)
215 #define PM_RESC_MIPIDSI_SRAM_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_MIPIDSI)
216 
217 #define PM_RESC_LCDIF_SRAM_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM_LCDIF)
218 #define PM_RESC_LCDIF_SRAM_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_LCDIF)
219 
220 #define PM_RESC_SRAM0_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM0_32KB)
221 #define PM_RESC_SRAM0_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM0_32KB)
222 
223 #define PM_RESC_SRAM1_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM1_32KB)
224 #define PM_RESC_SRAM1_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM1_32KB)
225 
226 #define PM_RESC_SRAM2_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM2_32KB)
227 #define PM_RESC_SRAM2_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM2_32KB)
228 
229 #define PM_RESC_SRAM3_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM3_32KB)
230 #define PM_RESC_SRAM3_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM3_32KB)
231 
232 #define PM_RESC_SRAM4_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM4_32KB)
233 #define PM_RESC_SRAM4_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM4_32KB)
234 
235 #define PM_RESC_SRAM5_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM5_32KB)
236 #define PM_RESC_SRAM5_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM5_32KB)
237 
238 #define PM_RESC_SRAM6_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM6_32KB)
239 #define PM_RESC_SRAM6_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM6_32KB)
240 
241 #define PM_RESC_SRAM7_32KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM7_32KB)
242 #define PM_RESC_SRAM7_32KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM7_32KB)
243 
244 #define PM_RESC_SRAM8_64KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM8_64KB)
245 #define PM_RESC_SRAM8_64KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM8_64KB)
246 
247 #define PM_RESC_SRAM9_64KB_ACTIVE       PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM9_64KB)
248 #define PM_RESC_SRAM9_64KB_RETENTION    PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM9_64KB)
249 
250 #define PM_RESC_SRAM10_64KB_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM10_64KB)
251 #define PM_RESC_SRAM10_64KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM10_64KB)
252 
253 #define PM_RESC_SRAM11_64KB_ACTIVE      PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM11_64KB)
254 #define PM_RESC_SRAM11_64KB_RETENTION   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM11_64KB)
255 
256 #define PM_RESC_SRAM12_128KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM12_128KB)
257 #define PM_RESC_SRAM12_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM12_128KB)
258 
259 #define PM_RESC_SRAM13_128KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM13_128KB)
260 #define PM_RESC_SRAM13_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM13_128KB)
261 
262 #define PM_RESC_SRAM14_128KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM14_128KB)
263 #define PM_RESC_SRAM14_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM14_128KB)
264 
265 #define PM_RESC_SRAM15_128KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM15_128KB)
266 #define PM_RESC_SRAM15_128KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM15_128KB)
267 
268 #define PM_RESC_SRAM16_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM16_256KB)
269 #define PM_RESC_SRAM16_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM16_256KB)
270 
271 #define PM_RESC_SRAM17_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM17_256KB)
272 #define PM_RESC_SRAM17_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM17_256KB)
273 
274 #define PM_RESC_SRAM18_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM18_256KB)
275 #define PM_RESC_SRAM18_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM18_256KB)
276 
277 #define PM_RESC_SRAM19_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM19_256KB)
278 #define PM_RESC_SRAM19_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM19_256KB)
279 
280 #define PM_RESC_SRAM20_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM20_256KB)
281 #define PM_RESC_SRAM20_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM20_256KB)
282 
283 #define PM_RESC_SRAM21_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM21_256KB)
284 #define PM_RESC_SRAM21_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM21_256KB)
285 
286 #define PM_RESC_SRAM22_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM22_256KB)
287 #define PM_RESC_SRAM22_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM22_256KB)
288 
289 #define PM_RESC_SRAM23_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM23_256KB)
290 #define PM_RESC_SRAM23_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM23_256KB)
291 
292 #define PM_RESC_SRAM24_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM24_256KB)
293 #define PM_RESC_SRAM24_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM24_256KB)
294 
295 #define PM_RESC_SRAM25_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM25_256KB)
296 #define PM_RESC_SRAM25_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM25_256KB)
297 
298 #define PM_RESC_SRAM26_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM26_256KB)
299 #define PM_RESC_SRAM26_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM26_256KB)
300 
301 #define PM_RESC_SRAM27_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM27_256KB)
302 #define PM_RESC_SRAM27_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM27_256KB)
303 
304 #define PM_RESC_SRAM28_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM28_256KB)
305 #define PM_RESC_SRAM28_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM28_256KB)
306 
307 #define PM_RESC_SRAM29_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM29_256KB)
308 #define PM_RESC_SRAM29_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM29_256KB)
309 
310 #define PM_RESC_SRAM30_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM30_256KB)
311 #define PM_RESC_SRAM30_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM30_256KB)
312 
313 #define PM_RESC_SRAM31_256KB_ACTIVE     PM_ENCODE_RESC(PM_RESOURCE_FULL_ON,      kResc_SRAM31_256KB)
314 #define PM_RESC_SRAM31_256KB_RETENTION  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM31_256KB)
315 
316 #if FSL_PM_SUPPORT_WAKEUP_SOURCE_MANAGER
317 
318 #endif
319 
320 #endif /* _FSL_PM_DEVICE_H_ */
321