1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40 /* clang-format off */
41 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42 !!GlobalInfo
43 product: Clocks v4.1
44 processor: MKV58F1M0xxx24
45 package_id: MKV58F1M0VLQ24
46 mcu_data: ksdk2_0
47 processor_version: 4.0.0
48 board: TWR-KV58F220M
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50 /* clang-format on */
51
52 #include "fsl_smc.h"
53 #include "clock_config.h"
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
59 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
60 #define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */
61 #define SIM_ENET_1588T_CLK_SEL_CLKIN_CLK 3U /*!< SDHC clock select: CLKIN (External bypass clock) */
62 #define SIM_ENET_RMII_CLK_SEL_CLKIN_CLK 1U /*!< SDHC clock select: CLKIN (External bypass clock) */
63 #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
64 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
65 #define SIM_TRACE_CLK_DIV_1 0U /*!< Trace clock divider divisor: divided by 1 */
66 #define SIM_TRACE_CLK_FRAC_1 0U /*!< Trace clock divider fraction: multiplied by 1 */
67 #define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /*!< Trace clock select: Core/system clock */
68 #define SIM_WDOG_CLK_SEL_LPO_CLK 0U /*!< WDOG clock select: LPO clock */
69
70 /*******************************************************************************
71 * Variables
72 ******************************************************************************/
73 /* System clock frequency. */
74 extern uint32_t SystemCoreClock;
75
76 /*******************************************************************************
77 * Code
78 ******************************************************************************/
79 /*FUNCTION**********************************************************************
80 *
81 * Function Name : CLOCK_CONFIG_SetSimSafeDivs
82 * Description : This function sets the system clock dividers in SIM to safe
83 * value.
84 *
85 *END**************************************************************************/
CLOCK_CONFIG_SetSimSafeDivs(void)86 static void CLOCK_CONFIG_SetSimSafeDivs(void)
87 {
88 SIM->CLKDIV1 = 0x01170000U;
89 }
90
91 /*FUNCTION**********************************************************************
92 *
93 * Function Name : CLOCK_CONFIG_FllStableDelay
94 * Description : This function is used to delay for FLL stable.
95 *
96 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)97 static void CLOCK_CONFIG_FllStableDelay(void)
98 {
99 uint32_t i = 30000U;
100 while (i--)
101 {
102 __NOP();
103 }
104 }
105
106 /*FUNCTION**********************************************************************
107 *
108 * Function Name : CLOCK_CONFIG_SetWdogClock
109 * Description : Set WDOG clock source.
110 * Param src : The value to set WDOG clock source.
111 *
112 *END**************************************************************************/
CLOCK_CONFIG_SetWdogClock(uint8_t src)113 static void CLOCK_CONFIG_SetWdogClock(uint8_t src)
114 {
115 SIM->WDOGC = ((SIM->WDOGC & ~SIM_WDOGC_WDOGCLKS_MASK) | SIM_WDOGC_WDOGCLKS(src));
116 }
117
118 /*FUNCTION**********************************************************************
119 *
120 * Function Name : CLOCK_CONFIG_EnableTraceDivFrac
121 * Description : Enable TRACE divider fraction and divisor.
122 *
123 *END**************************************************************************/
CLOCK_CONFIG_EnableTraceDivFrac()124 static void CLOCK_CONFIG_EnableTraceDivFrac()
125 {
126 SIM->CLKDIV4 |= SIM_CLKDIV4_TRACEDIVEN_MASK;
127 }
128
129 /*FUNCTION**********************************************************************
130 *
131 * Function Name : CLOCK_CONFIG_SetRmii0Clock
132 * Description : Set RMII clock source.
133 * Param src : The value to set RMII clock source.
134 *
135 *END**************************************************************************/
CLOCK_CONFIG_SetRmii0Clock(uint32_t src)136 static void CLOCK_CONFIG_SetRmii0Clock(uint32_t src)
137 {
138 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
139 }
140
141 /*******************************************************************************
142 ************************ BOARD_InitBootClocks function ************************
143 ******************************************************************************/
BOARD_InitBootClocks(void)144 void BOARD_InitBootClocks(void)
145 {
146 BOARD_BootClockRUN();
147 }
148
149 /*******************************************************************************
150 ********************** Configuration BOARD_BootClockRUN ***********************
151 ******************************************************************************/
152 /* clang-format off */
153 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
154 !!Configuration
155 name: BOARD_BootClockRUN
156 called_from_default_init: true
157 outputs:
158 - {id: Bus_clock.outFreq, value: 83.88608 MHz}
159 - {id: CLKOUT.outFreq, value: 41.94304 MHz}
160 - {id: Core_clock.outFreq, value: 83.88608 MHz}
161 - {id: ENET1588TSCLK.outFreq, value: 50 MHz}
162 - {id: ERCLK32K.outFreq, value: 1 kHz}
163 - {id: Flash_clock.outFreq, value: 20.97152 MHz}
164 - {id: FlexBus_clock.outFreq, value: 41.94304 MHz}
165 - {id: LPO_clock.outFreq, value: 1 kHz}
166 - {id: MCGFFCLK.outFreq, value: 32.768 kHz}
167 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
168 - {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
169 - {id: RMIICLK.outFreq, value: 50 MHz}
170 - {id: System_clock.outFreq, value: 83.88608 MHz}
171 - {id: TRACECLKIN.outFreq, value: 83.88608 MHz}
172 - {id: WDOGCLK.outFreq, value: 1 kHz}
173 settings:
174 - {id: CLKOUTConfig, value: 'yes'}
175 - {id: ENETTimeSrcConfig, value: 'yes'}
176 - {id: MCG.FCRDIV.scale, value: '1'}
177 - {id: MCG.FLL_mul.scale, value: '2560', locked: true}
178 - {id: MCG.FRDIV.scale, value: '32'}
179 - {id: MCG.PRDIV.scale, value: '4'}
180 - {id: MCG.VDIV.scale, value: '32'}
181 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
182 - {id: MCG_C2_RANGE0_CFG, value: High}
183 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
184 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
185 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
186 - {id: RMIISrcConfig, value: 'yes'}
187 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
188 - {id: SIM.OUTDIV3.scale, value: '2'}
189 - {id: SIM.OUTDIV4.scale, value: '4'}
190 - {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT}
191 - {id: SIM.TIMESRCSEL.sel, value: SIM.ENET_1588_CLK_EXT}
192 - {id: TraceClkConfig, value: 'yes'}
193 - {id: WDOGClkConfig, value: 'yes'}
194 sources:
195 - {id: OSC.OSC.outFreq, value: 50 MHz}
196 - {id: SIM.ENET_1588_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
197 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
198 /* clang-format on */
199
200 /*******************************************************************************
201 * Variables for BOARD_BootClockRUN configuration
202 ******************************************************************************/
203 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
204 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
205 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
206 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
207 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
208 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
209 .drs = kMCG_DrsHigh, /* High frequency range */
210 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
211 .pll0Config =
212 {
213 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
214 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
215 .vdiv = 0x10U, /* VCO divider: multiplied by 32 */
216 },
217 };
218 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
219 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
220 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
221 .clkdiv1 = 0x130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /4 */
222 };
223 const osc_config_t oscConfig_BOARD_BootClockRUN = {
224 .freq = 0U, /* Oscillator frequency: 0Hz */
225 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
226 .workMode = kOSC_ModeExt, /* Use external clock */
227 .oscerConfig = {
228 .enableMode =
229 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
230 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
231 }};
232
233 /*******************************************************************************
234 * Code for BOARD_BootClockRUN configuration
235 ******************************************************************************/
BOARD_BootClockRUN(void)236 void BOARD_BootClockRUN(void)
237 {
238 /* Set the system clock dividers in SIM to safe value. */
239 CLOCK_CONFIG_SetSimSafeDivs();
240 /* Set MCG to FEI mode. */
241 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
242 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
243 CLOCK_CONFIG_FllStableDelay);
244 #else
245 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
246 #endif
247 /* Configure the Internal Reference clock (MCGIRCLK). */
248 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
249 mcgConfig_BOARD_BootClockRUN.fcrdiv);
250 /* Set the clock configuration in SIM module. */
251 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
252 /* Set SystemCoreClock variable. */
253 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
254 /* Set enet timestamp clock source. */
255 CLOCK_SetEnetTime0Clock(SIM_ENET_1588T_CLK_SEL_CLKIN_CLK);
256 /* Set RMII clock source. */
257 CLOCK_CONFIG_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_CLKIN_CLK);
258 /* Set WDOG clock source. */
259 CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_LPO_CLK);
260 /* Set CLKOUT source. */
261 CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
262 /* Set debug trace clock source. */
263 CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK, SIM_TRACE_CLK_DIV_1, SIM_TRACE_CLK_FRAC_1);
264 /* Enable debug trace divider divisor and fraction. */
265 CLOCK_CONFIG_EnableTraceDivFrac();
266 }
267
268 /*******************************************************************************
269 ********************* Configuration BOARD_BootClockVLPR ***********************
270 ******************************************************************************/
271 /* clang-format off */
272 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
273 !!Configuration
274 name: BOARD_BootClockVLPR
275 outputs:
276 - {id: Bus_clock.outFreq, value: 4 MHz}
277 - {id: Core_clock.outFreq, value: 4 MHz}
278 - {id: ERCLK32K.outFreq, value: 1 kHz}
279 - {id: Flash_clock.outFreq, value: 500 kHz}
280 - {id: FlexBus_clock.outFreq, value: 4 MHz}
281 - {id: LPO_clock.outFreq, value: 1 kHz}
282 - {id: MCGIRCLK.outFreq, value: 4 MHz}
283 - {id: System_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
284 - {id: WDOGCLK.outFreq, value: 1 kHz}
285 settings:
286 - {id: MCGMode, value: BLPI}
287 - {id: powerMode, value: VLPR}
288 - {id: MCG.CLKS.sel, value: MCG.IRCS}
289 - {id: MCG.FCRDIV.scale, value: '1'}
290 - {id: MCG.FRDIV.scale, value: '32'}
291 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
292 - {id: MCG.PRDIV.scale, value: '4'}
293 - {id: MCG.VDIV.scale, value: '32'}
294 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
295 - {id: MCG_C2_RANGE0_CFG, value: High}
296 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
297 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
298 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
299 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
300 - {id: SIM.OUTDIV4.scale, value: '8'}
301 - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
302 - {id: SIM.TRACECLKSEL.sel, value: MCG.MCGOUTCLK}
303 - {id: WDOGClkConfig, value: 'yes'}
304 sources:
305 - {id: OSC.OSC.outFreq, value: 50 MHz}
306 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
307 /* clang-format on */
308
309 /*******************************************************************************
310 * Variables for BOARD_BootClockVLPR configuration
311 ******************************************************************************/
312 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
313 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
314 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
315 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
316 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
317 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
318 .drs = kMCG_DrsLow, /* Low frequency range */
319 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
320 .pll0Config =
321 {
322 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
323 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
324 .vdiv = 0x10U, /* VCO divider: multiplied by 32 */
325 },
326 };
327 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
328 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
329 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
330 .clkdiv1 = 0x70000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /8 */
331 };
332 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
333 .freq = 0U, /* Oscillator frequency: 0Hz */
334 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
335 .workMode = kOSC_ModeExt, /* Use external clock */
336 .oscerConfig = {
337 .enableMode =
338 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
339 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
340 }};
341
342 /*******************************************************************************
343 * Code for BOARD_BootClockVLPR configuration
344 ******************************************************************************/
BOARD_BootClockVLPR(void)345 void BOARD_BootClockVLPR(void)
346 {
347 /* Set the system clock dividers in SIM to safe value. */
348 CLOCK_CONFIG_SetSimSafeDivs();
349 /* Set MCG to BLPI mode. */
350 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
351 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
352 /* Set the clock configuration in SIM module. */
353 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
354 /* Set VLPR power mode. */
355 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
356 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
357 SMC_SetPowerModeVlpr(SMC, false);
358 #else
359 SMC_SetPowerModeVlpr(SMC);
360 #endif
361 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
362 {
363 }
364 /* Set SystemCoreClock variable. */
365 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
366 /* Set WDOG clock source. */
367 CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_LPO_CLK);
368 }
369
