1 /*
2 * Copyright 2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13 /* clang-format off */
14 /*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16 !!GlobalInfo
17 product: Pins v9.0
18 processor: MKM34Z256xxx7
19 package_id: MKM34Z256VLQ7
20 mcu_data: ksdk2_0
21 processor_version: 9.0.0
22 board: TWR-KM34Z75M
23 pin_labels:
24 - {pin_num: '113', pin_signal: LCD_P10/PTG3/SPI0_SCK/I2C0_SCL, label: 'J32[B7]/J12[1]/U4[6]/SPI0_SCK', identifier: FLASH_CLK}
25 - {pin_num: '112', pin_signal: LCD_P9/ADC0_SE11/PTG2/LLWU_P1/SPI0_PCS0, label: 'J32[B9]/J9[2]/U4[1]/SPI0_PCS0', identifier: FLASH_CS}
26 - {pin_num: '114', pin_signal: LCD_P11/PTG4/SPI0_MOSI/I2C0_SDA, label: 'J32[B10]/J15[1]/U4[5]/SPI0_MOSI', identifier: FLASH_SI}
27 - {pin_num: '115', pin_signal: LCD_P12/PTG5/SPI0_MISO/LPTMR0_ALT2, label: 'J32[B11]/J13[2]/U4[2]/SPI0_MISO', identifier: FLASH_SO}
28 - {pin_num: '125', pin_signal: PTH7/UART1_RTS_b/SPI1_SCK/XBAR_OUT7, label: 'J32[B21]'}
29 - {pin_num: '130', pin_signal: LCD_P21/PTI2/LLWU_P22/LPUART0_RX, label: 'J32[B23]'}
30 - {pin_num: '91', pin_signal: PTE5/LLWU_P6/QTMR0_TMR3/UART2_RTS_b/EWM_OUT_b, label: 'J32[B35]'}
31 - {pin_num: '102', pin_signal: LCD_P4/PTF5/SPI1_MISO/I2C1_SCL, label: 'J32[B44]/J23[9]/J25[14]/SPI1_MISO'}
32 - {pin_num: '103', pin_signal: LCD_P5/PTF6/LLWU_P3/SPI1_MOSI/I2C1_SDA, label: 'J32[B45]/J23[10]/J25[13]/SPI1_MOSI'}
33 - {pin_num: '100', pin_signal: LCD_P2/PTF3/LLWU_P20/SPI1_PCS0/LPTMR0_ALT2/UART0_RX, label: 'J32[B46]/J23[11]/J25[16]/SPI1_PCS0'}
34 - {pin_num: '101', pin_signal: LCD_P3/PTF4/SPI1_SCK/LPTMR0_ALT1/UART0_TX, label: 'J32[B48]/J23[12]/J25[15]/SPI1_SCK'}
35 - {pin_num: '118', pin_signal: LCD_P15/PTH0/LPUART0_CTS_b, label: 'J32[B55]/J32[B56]'}
36 - {pin_num: '119', pin_signal: LCD_P16/PTH1/LPUART0_RTS_b, label: 'J32[B57]/J32[B58]'}
37 - {pin_num: '120', pin_signal: LCD_P17/PTH2/LPUART0_RX, label: 'J32[B59]/J32[B60]'}
38 - {pin_num: '121', pin_signal: LCD_P18/PTH3/LPUART0_TX, label: 'J32[B61]/J32[B62]'}
39 - {pin_num: '79', pin_signal: CMP0_IN4/PTD7/LLWU_P7/I2C0_SCL/XBAR_IN4/UART3_RX, label: 'J32[A7]/J10[1]/U5[4]/I2C0_SCL', identifier: ACCEL_SCL}
40 - {pin_num: '80', pin_signal: PTE0/I2C0_SDA/XBAR_OUT4/UART3_TX/CLKOUT, label: 'J32[A8]/J11[1]/U5[6]/I2C0_SDA', identifier: ACCEL_SDA}
41 - {pin_num: '124', pin_signal: PTH6/UART1_CTS_b/SPI1_PCS0/XBAR_IN7, label: 'J32[A9]'}
42 - {pin_num: '90', pin_signal: PTE4/LPTMR0_ALT1/UART2_CTS_b/EWM_IN, label: 'J32[A35]'}
43 - {pin_num: '126', pin_signal: CMP0_IN5/PTI0/LLWU_P21/UART1_RX/XBAR_IN8/SPI1_MISO/SPI1_MOSI, label: 'J32[A43]'}
44 - {pin_num: '127', pin_signal: PTI1/UART1_TX/XBAR_OUT8/SPI1_MOSI/SPI1_MISO, label: 'J32[A44]'}
45 - {pin_num: '65', pin_signal: CMP0_IN1/PTD2/LLWU_P10/UART1_RX/SPI0_SCK/XBAR_IN3, label: 'J32[A63]'}
46 - {pin_num: '83', pin_signal: PTE1/RESET_b, label: 'J28[2]/J22[20]/J24[10]', identifier: RESET}
47 - {pin_num: '7', pin_signal: LCD_P47/PTI7/UART2_TX, label: UART2_TX, identifier: DEBUG_UART_TX}
48 - {pin_num: '6', pin_signal: LCD_P46/PTI6/UART2_RX, label: UART2_RX, identifier: DEBUG_UART_RX}
49 - {pin_num: '66', pin_signal: PTJ5/LPUART0_TX, label: 'J14[1]/U5[11]/INT1', identifier: ACCEL_INT1}
50 - {pin_num: '67', pin_signal: PTJ6/LLWU_P18/LPUART0_RX, label: 'J16[1]/U5[9]/INT2', identifier: ACCEL_INT2}
51 - {pin_num: '62', pin_signal: PTJ3/LPUART0_RTS_b/CMP2_OUT, label: D3/GRN, identifier: LED_GREEN}
52 - {pin_num: '63', pin_signal: PTJ4/LPUART0_CTS_b, label: D4/RED, identifier: LED_RED}
53 - {pin_num: '61', pin_signal: CMP0_IN0/PTD0/LLWU_P11/UART0_RX/XBAR_IN2, label: 'J17[2]/J19[1]/J25[17]/D5/ORANGE/IRDRJ/CMP0_IN0', identifier: LED_ORANGE;IR_RX}
54 - {pin_num: '26', pin_signal: LCD_P38/PTB7/AFE_CLK, label: 'DS1[1]/LCD_P38', identifier: LCD_P38}
55 - {pin_num: '24', pin_signal: LCD_P36/PTB5, label: 'DS1[2]/LCD_P36', identifier: LCD_P36}
56 - {pin_num: '22', pin_signal: LCD_P34/PTB3, label: 'DS1[3]/LCD_P34', identifier: LCD_P34}
57 - {pin_num: '20', pin_signal: LCD_P32/PTB1/LLWU_P17, label: 'DS1[4]/LCD_P32', identifier: LCD_P32}
58 - {pin_num: '16', pin_signal: LCD_P31/PTB0, label: 'DS1[5]/LCD_P31', identifier: LCD_P31}
59 - {pin_num: '12', pin_signal: LCD_P29/PTA6/LLWU_P14/XBAR_IN0, label: 'DS1[6]/LCD_P29', identifier: LCD_P29}
60 - {pin_num: '8', pin_signal: LCD_P25/PTA2, label: 'DS1[7]/LCD_P25', identifier: LCD_P25}
61 - {pin_num: '4', pin_signal: LCD_P23/PTA0/LLWU_P16, label: 'DS1[8]/LCD_P23', identifier: LCD_P23}
62 - {pin_num: '31', pin_signal: LCD_P43/PTC4, label: 'DS1[9]/LCD_P43', identifier: LCD_P43}
63 - {pin_num: '25', pin_signal: LCD_P37/CMP1_IN0/PTB6, label: 'DS1[10]/LCD_P37', identifier: LCD_P37}
64 - {pin_num: '23', pin_signal: LCD_P35/PTB4, label: 'DS1[11]/LCD_P35', identifier: LCD_P35}
65 - {pin_num: '21', pin_signal: LCD_P33/PTB2, label: 'DS1[12]/LCD_P33', identifier: LCD_P33}
66 - {pin_num: '17', pin_signal: LCD_P50/PTJ2, label: 'DS1[13]/LCD_P50', identifier: LCD_P50}
67 - {pin_num: '13', pin_signal: LCD_P30/PTA7/XBAR_OUT0, label: 'DS1[14]/LCD_P30', identifier: LCD_P30}
68 - {pin_num: '117', pin_signal: LCD_P14/PTG7, label: 'DS1[28]/LCD_P14', identifier: LCD_P14}
69 - {pin_num: '123', pin_signal: LCD_P20/PTH5, label: 'DS1[27]/LCD_P20', identifier: LCD_P20}
70 - {pin_num: '131', pin_signal: LCD_P22/PTI3/LPUART0_TX/CMP2_OUT, label: 'DS1[26]/LCD_P22', identifier: LCD_P22}
71 - {pin_num: '139', pin_signal: LCD_P56/PTL3/EWM_IN, label: 'DS1[25]/LCD_P56', identifier: LCD_P56}
72 - {pin_num: '141', pin_signal: LCD_P58/PTL5/LLWU_P23, label: 'DS1[24]/LCD_P58', identifier: LCD_P58}
73 - {pin_num: '116', pin_signal: LCD_P13/PTG6/LLWU_P0/LPTMR0_ALT3, label: 'DS1[23]/LCD_P13', identifier: LCD_P13}
74 - {pin_num: '122', pin_signal: LCD_P19/PTH4, label: 'DS1[22]/LCD_P19', identifier: LCD_P19}
75 - {pin_num: '140', pin_signal: LCD_P57/PTL4/EWM_OUT_b, label: 'DS1[21]/LCD_P57', identifier: LCD_P57}
76 - {pin_num: '142', pin_signal: LCD_P59/PTL6, label: 'DS1[20]/LCD_P59', identifier: LCD_P59}
77 - {pin_num: '143', pin_signal: LCD_P44/PTI4, label: 'DS1[19]/LCD_P44', identifier: LCD_P44}
78 - {pin_num: '11', pin_signal: LCD_P28/PTA5/CMP0_OUT, label: 'DS1[18]/LCD_P28', identifier: LCD_P28}
79 - {pin_num: '9', pin_signal: LCD_P26/PTA3, label: 'DS1[17]/LCD_P26', identifier: LCD_P26}
80 - {pin_num: '5', pin_signal: LCD_P24/PTA1, label: 'DS1[16]/LCD_P24', identifier: LCD_P24}
81 - {pin_num: '3', pin_signal: LCD_P45/PTI5, label: 'DS1[15]/LCD_P45', identifier: LCD_P45}
82 - {pin_num: '10', pin_signal: LCD_P27/PTA4/LLWU_P15/NMI_b, label: SW1, identifier: SW1}
83 - {pin_num: '64', pin_signal: PTD1/UART1_TX/SPI0_PCS0/XBAR_OUT3/QTMR0_TMR3, label: SW2, identifier: SW2}
84 - {pin_num: '129', pin_signal: LCD_P55/PTL2/XBAR_OUT10, label: 'J18[1]/J25[23]/IRDTJ/XBAR0_OUT10', identifier: IR_TX}
85 - {pin_num: '95', pin_signal: LCD_P0/ADC0_SE8/CMP2_IN4/PTF1/QTMR0_TMR0/XBAR_OUT6, label: 'J21[1]/POT_5K', identifier: ADC_POT}
86 - {pin_num: '96', pin_signal: LCD_P1/ADC0_SE9/CMP2_IN5/PTF2/CMP1_OUT/RTC_CLKOUT, label: 'J20[1]/TEMP_SENSE', identifier: ADC_TEMP}
87 - {pin_num: '84', pin_signal: EXTAL0/PTE2/EWM_IN/XBAR_IN6/I2C1_SDA, label: 'J4[2]/Y2[3]/EXTAL_8MHz', identifier: EXTAL0}
88 - {pin_num: '85', pin_signal: XTAL0/PTE3/EWM_OUT_b/AFE_CLK/I2C1_SCL, label: 'J7[2]/Y2[1]/XTAL_8MHz', identifier: XTAL0}
89 - {pin_num: '34', pin_signal: EXTAL32, label: 'Y1[2]/EXTAL_32K', identifier: EXTAL_32K}
90 - {pin_num: '33', pin_signal: XTAL32, label: 'Y1[1]/XTAL_32K', identifier: XTAL_32K}
91 - {pin_num: '70', pin_signal: ADC0_SE12/PTK0, label: 'J22[12]/TWRPI-ADC2'}
92 - {pin_num: '75', pin_signal: ADC0_SE13/PTK1, label: 'J22[8]/TWRPI-ADC0'}
93 - {pin_num: '78', pin_signal: ADC0_SE5a/PTD6/LLWU_P8/LPTMR0_ALT2/CMP1_OUT/UART3_RTS_b, label: 'J22[18]/TWRPI-ID1'}
94 - {pin_num: '77', pin_signal: ADC0_SE4a/PTD5/LPTMR0_ALT3/QTMR0_TMR0/UART3_CTS_b, label: 'J22[17]/TWRPI-ID0'}
95 - {pin_num: '76', pin_signal: ADC0_SE3/PTD4/LLWU_P9/UART1_RTS_b/SPI0_MISO, label: 'J22[9]/TWRPI-ADC1'}
96 - {pin_num: '15', pin_signal: LCD_P49/PTJ1/I2C1_SCL, label: 'J23[3]/I2C1_SCL'}
97 - {pin_num: '14', pin_signal: LCD_P48/PTJ0/I2C1_SDA, label: 'J23[4]/I2C1_SDA'}
98 - {pin_num: '68', pin_signal: PTJ7, label: 'J23[15]'}
99 - {pin_num: '30', pin_signal: LCD_P42/CMP0_IN3/PTC3/LLWU_P13/UART3_RX, label: 'J23[17]/UART3_RX'}
100 - {pin_num: '28', pin_signal: LCD_P40/CMP1_IN1/PTC1/UART3_CTS_b, label: 'J23[19]/UART3_CTS'}
101 - {pin_num: '69', pin_signal: PTD3/UART1_CTS_b/SPI0_MOSI, label: 'J23[16]'}
102 - {pin_num: '29', pin_signal: LCD_P41/PTC2/UART3_TX/XBAR_OUT1, label: 'J23[18]/UART3_TX'}
103 - {pin_num: '27', pin_signal: LCD_P39/PTC0/UART3_RTS_b/XBAR_IN1/PDB0_EXTRG, label: 'J23[20]/UART3_RTS'}
104 - {pin_num: '99', pin_signal: PTK6/UART1_TX, label: 'J25[9]/UART1_TX'}
105 - {pin_num: '106', pin_signal: LCD_P53/PTL0/I2C0_SDA, label: 'J25[11]/I2C0_SDA'}
106 - {pin_num: '128', pin_signal: LCD_P54/PTL1/XBAR_IN10, label: 'J25[19]/XBAR0_IN10'}
107 - {pin_num: '97', pin_signal: LCD_P51/PTK4/XBAR_IN9/AFE_CLK, label: 'J25[21]/AFE_CLK'}
108 - {pin_num: '42', pin_signal: TAMPER0, label: 'J25[2]'}
109 - {pin_num: '41', pin_signal: TAMPER1, label: 'J25[4]'}
110 - {pin_num: '40', pin_signal: TAMPER2, label: 'J25[6]'}
111 - {pin_num: '98', pin_signal: PTK5/UART1_RX, label: 'J25[8]/UART1_RX'}
112 - {pin_num: '105', pin_signal: LCD_P52/PTK7/I2C0_SCL/XBAR_OUT9, label: 'J25[12]/I2C0_SCL'}
113 - {pin_num: '104', pin_signal: LCD_P6/PTF7/QTMR0_TMR2/CLKOUT/CMP2_OUT, label: 'J25[18]/CLKOUT'}
114 - {pin_num: '110', pin_signal: LCD_P7/PTG0/QTMR0_TMR1/LPTMR0_ALT3, label: 'J25[20]/QTMR0_TMR1'}
115 - {pin_num: '81', pin_signal: ADC0_SE14/PTK2/UART0_TX, label: 'J25[22]/UART0_TX'}
116 - {pin_num: '82', pin_signal: ADC0_SE15/PTK3/LLWU_P19/UART0_RX, label: 'J25[24]/UART0_RX'}
117 - {pin_num: '92', pin_signal: CMP0_IN2/PTE6/LLWU_P5/XBAR_IN5/UART2_RX/I2C0_SCL/SWD_DIO, label: 'J24[2]/SWD_DIO_TGTMCU'}
118 - {pin_num: '93', pin_signal: ADC0_SE6a/PTE7/XBAR_OUT5/UART2_TX/I2C0_SDA/SWD_CLK, label: 'J24[4]/SWD_CLK_TGTMCU'}
119 - {pin_num: '53', pin_signal: VREF, label: 'J2[2]/VREF'}
120 - {pin_num: '50', pin_signal: VREFL, label: VREFL}
121 - {pin_num: '49', pin_signal: VREFH, label: VREFH}
122 - {pin_num: '88', pin_signal: VDDA, label: VDDA}
123 - {pin_num: '87', pin_signal: VSSA, label: VSSA}
124 - {pin_num: '133', pin_signal: VDD135, label: MCU_PWR}
125 - {pin_num: '89', pin_signal: VDD91, label: MCU_PWR}
126 - {pin_num: '18', pin_signal: VDD20, label: MCU_PWR}
127 - {pin_num: '43', pin_signal: AFE_VDDA, label: VDDA_AFE}
128 - {pin_num: '44', pin_signal: AFE_VSSA, label: VSSA_AFE}
129 - {pin_num: '132', pin_signal: VSS134, label: GND}
130 - {pin_num: '39', pin_signal: VSS41, label: GND}
131 - {pin_num: '86', pin_signal: VSS88, label: GND}
132 - {pin_num: '19', pin_signal: VSS21, label: GND}
133 - {pin_num: '1', pin_signal: NC3, label: GND}
134 - {pin_num: '2', pin_signal: NC4, label: GND}
135 - {pin_num: '35', pin_signal: NC37, label: GND}
136 - {pin_num: '36', pin_signal: NC38, label: GND}
137 - {pin_num: '38', pin_signal: NC40, label: GND}
138 - {pin_num: '37', pin_signal: NC39, label: GND}
139 - {pin_num: '56', pin_signal: NC58, label: GND}
140 - {pin_num: '57', pin_signal: NC59, label: GND}
141 - {pin_num: '71', pin_signal: NC73, label: GND}
142 - {pin_num: '72', pin_signal: NC74, label: GND}
143 - {pin_num: '73', pin_signal: NC75, label: GND}
144 - {pin_num: '74', pin_signal: NC76, label: GND}
145 - {pin_num: '107', pin_signal: NC109, label: GND}
146 - {pin_num: '108', pin_signal: NC110, label: GND}
147 - {pin_num: '109', pin_signal: NC111, label: GND}
148 - {pin_num: '144', pin_signal: NC2, label: GND}
149 - {pin_num: '45', pin_signal: AFE_SDADP0, label: 'J31[2]/AFE_SDADP0'}
150 - {pin_num: '46', pin_signal: AFE_SDADM0, label: 'J31[4]/AFE_SDADM0'}
151 - {pin_num: '47', pin_signal: AFE_SDADP1, label: 'J31[6]/AFE_SDADP1'}
152 - {pin_num: '48', pin_signal: AFE_SDADM1, label: 'J31[8]/AFE_SDADM1'}
153 - {pin_num: '52', pin_signal: AFE_SDADM2/CMP1_IN3, label: 'J31[12]/AFE_SDADM2'}
154 - {pin_num: '55', pin_signal: AFE_SDADM3/CMP1_IN5, label: 'J31[16]/AFE_SDADM3'}
155 - {pin_num: '51', pin_signal: AFE_SDADP2/CMP1_IN2, label: 'J31[10]/AFE_SDADP2'}
156 - {pin_num: '54', pin_signal: AFE_SDADP3/CMP1_IN4, label: 'J31[14]/AFE_SDADP3'}
157 - {pin_num: '58', pin_signal: ADC0_SE0/CMP2_IN0/PTC5/LLWU_P12/UART0_RTS_b, label: 'J31[18]/ADC0_SE0'}
158 - {pin_num: '59', pin_signal: ADC0_SE1/CMP2_IN1/PTC6/UART0_CTS_b/QTMR0_TMR1/PDB0_EXTRG, label: 'J31[20]/ADC0_SE1'}
159 - {pin_num: '60', pin_signal: ADC0_SE2/CMP2_IN2/PTC7/UART0_TX/XBAR_OUT2, label: 'J31[22]/ADC0_SE2'}
160 - {pin_num: '32', pin_signal: VBAT, label: 'J1[2]/VBAT'}
161 - {pin_num: '94', pin_signal: ADC0_SE7a/CMP2_IN3/PTF0/LLWU_P4/RTC_CLKOUT/QTMR0_TMR2/CMP0_OUT, label: NC}
162 - {pin_num: '111', pin_signal: LCD_P8/ADC0_SE10/PTG1/LLWU_P2/LPTMR0_ALT1, label: NC}
163 - {pin_num: '134', pin_signal: VLL3, label: 'J33[2]/VLL3'}
164 - {pin_num: '136', pin_signal: VLL1/LCD_P61/PTM1, label: VLL1}
165 - {pin_num: '135', pin_signal: VLL2/LCD_P60/PTM0, label: VLL2}
166 - {pin_num: '137', pin_signal: VCAP2/LCD_P62/PTM2, label: C83/VCAP2}
167 - {pin_num: '138', pin_signal: VCAP1/LCD_P63/PTM3, label: C83/VCAP1}
168 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
169 */
170 /* clang-format on */
171
172 #include "fsl_common.h"
173 #include "fsl_port.h"
174 #include "fsl_gpio.h"
175 #include "fsl_xbar.h"
176 #include "pin_mux.h"
177
178 /* FUNCTION ************************************************************************************************************
179 *
180 * Function Name : BOARD_InitBootPins
181 * Description : Calls initialization functions.
182 *
183 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)184 void BOARD_InitBootPins(void)
185 {
186 BOARD_InitPins();
187 BOARD_InitDEBUG_UARTPins();
188 }
189
190 /* clang-format off */
191 /*
192 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
193 BOARD_InitPins:
194 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
195 - pin_list: []
196 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
197 */
198 /* clang-format on */
199
200 /* FUNCTION ************************************************************************************************************
201 *
202 * Function Name : BOARD_InitPins
203 * Description : Configures pin routing and optionally pin electrical features.
204 *
205 * END ****************************************************************************************************************/
BOARD_InitPins(void)206 void BOARD_InitPins(void)
207 {
208 }
209
210 /* clang-format off */
211 /*
212 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
213 BOARD_InitButtonsPins:
214 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
215 - pin_list:
216 - {pin_num: '10', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: LCD_P27/PTA4/LLWU_P15/NMI_b, direction: INPUT, slew_rate: slow, open_drain: disable, pull_select: up,
217 pull_enable: enable}
218 - {pin_num: '64', peripheral: GPIOD, signal: 'GPIO, 1', pin_signal: PTD1/UART1_TX/SPI0_PCS0/XBAR_OUT3/QTMR0_TMR3, direction: INPUT, slew_rate: slow, open_drain: disable,
219 pull_select: up, pull_enable: enable}
220 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
221 */
222 /* clang-format on */
223
224 /* FUNCTION ************************************************************************************************************
225 *
226 * Function Name : BOARD_InitButtonsPins
227 * Description : Configures pin routing and optionally pin electrical features.
228 *
229 * END ****************************************************************************************************************/
BOARD_InitButtonsPins(void)230 void BOARD_InitButtonsPins(void)
231 {
232 /* PCTLA Clock Gate Control: Clock enabled */
233 CLOCK_EnableClock(kCLOCK_PortA);
234 /* PCTLD Clock Gate Control: Clock enabled */
235 CLOCK_EnableClock(kCLOCK_PortD);
236
237 gpio_pin_config_t SW1_config = {
238 .pinDirection = kGPIO_DigitalInput,
239 .outputLogic = 0U
240 };
241 /* Initialize GPIO functionality on pin PTA4 (pin 10) */
242 GPIO_PinInit(BOARD_SW1_GPIO, BOARD_SW1_PIN, &SW1_config);
243
244 gpio_pin_config_t SW2_config = {
245 .pinDirection = kGPIO_DigitalInput,
246 .outputLogic = 0U
247 };
248 /* Initialize GPIO functionality on pin PTD1 (pin 64) */
249 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
250
251 const port_pin_config_t SW1 = {/* Internal pull-up resistor is enabled */
252 kPORT_PullUp,
253 /* Slow slew rate is configured */
254 kPORT_SlowSlewRate,
255 /* Open drain is disabled */
256 kPORT_OpenDrainDisable,
257 /* Pin is configured as PTA4 */
258 kPORT_MuxAsGpio,
259 /* Pin Control Register fields [15:0] are not locked */
260 kPORT_UnlockRegister};
261 /* PORTA4 (pin 10) is configured as PTA4 */
262 PORT_SetPinConfig(BOARD_SW1_PORT, BOARD_SW1_PIN, &SW1);
263
264 const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */
265 kPORT_PullUp,
266 /* Slow slew rate is configured */
267 kPORT_SlowSlewRate,
268 /* Open drain is disabled */
269 kPORT_OpenDrainDisable,
270 /* Pin is configured as PTD1 */
271 kPORT_MuxAsGpio,
272 /* Pin Control Register fields [15:0] are not locked */
273 kPORT_UnlockRegister};
274 /* PORTD1 (pin 64) is configured as PTD1 */
275 PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
276 }
277
278 /* clang-format off */
279 /*
280 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
281 BOARD_InitLEDsPins:
282 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
283 - pin_list:
284 - {pin_num: '62', peripheral: GPIOJ, signal: 'GPIO, 3', pin_signal: PTJ3/LPUART0_RTS_b/CMP2_OUT, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow, open_drain: disable,
285 pull_select: down, pull_enable: disable}
286 - {pin_num: '63', peripheral: GPIOJ, signal: 'GPIO, 4', pin_signal: PTJ4/LPUART0_CTS_b, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow, open_drain: disable,
287 pull_select: down, pull_enable: disable}
288 - {pin_num: '61', peripheral: GPIOD, signal: 'GPIO, 0', pin_signal: CMP0_IN0/PTD0/LLWU_P11/UART0_RX/XBAR_IN2, identifier: LED_ORANGE, direction: OUTPUT, gpio_init_state: 'true',
289 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
290 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
291 */
292 /* clang-format on */
293
294 /* FUNCTION ************************************************************************************************************
295 *
296 * Function Name : BOARD_InitLEDsPins
297 * Description : Configures pin routing and optionally pin electrical features.
298 *
299 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)300 void BOARD_InitLEDsPins(void)
301 {
302 /* PCTLD Clock Gate Control: Clock enabled */
303 CLOCK_EnableClock(kCLOCK_PortD);
304 /* PCTLJ Clock Gate Control: Clock enabled */
305 CLOCK_EnableClock(kCLOCK_PortJ);
306
307 gpio_pin_config_t LED_ORANGE_config = {
308 .pinDirection = kGPIO_DigitalOutput,
309 .outputLogic = 1U
310 };
311 /* Initialize GPIO functionality on pin PTD0 (pin 61) */
312 GPIO_PinInit(BOARD_LED_ORANGE_GPIO, BOARD_LED_ORANGE_PIN, &LED_ORANGE_config);
313
314 gpio_pin_config_t LED_GREEN_config = {
315 .pinDirection = kGPIO_DigitalOutput,
316 .outputLogic = 1U
317 };
318 /* Initialize GPIO functionality on pin PTJ3 (pin 62) */
319 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
320
321 gpio_pin_config_t LED_RED_config = {
322 .pinDirection = kGPIO_DigitalOutput,
323 .outputLogic = 1U
324 };
325 /* Initialize GPIO functionality on pin PTJ4 (pin 63) */
326 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
327
328 const port_pin_config_t LED_ORANGE = {/* Internal pull-up/down resistor is disabled */
329 kPORT_PullDisable,
330 /* Slow slew rate is configured */
331 kPORT_SlowSlewRate,
332 /* Open drain is disabled */
333 kPORT_OpenDrainDisable,
334 /* Pin is configured as PTD0 */
335 kPORT_MuxAsGpio,
336 /* Pin Control Register fields [15:0] are not locked */
337 kPORT_UnlockRegister};
338 /* PORTD0 (pin 61) is configured as PTD0 */
339 PORT_SetPinConfig(BOARD_LED_ORANGE_PORT, BOARD_LED_ORANGE_PIN, &LED_ORANGE);
340
341 const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
342 kPORT_PullDisable,
343 /* Slow slew rate is configured */
344 kPORT_SlowSlewRate,
345 /* Open drain is disabled */
346 kPORT_OpenDrainDisable,
347 /* Pin is configured as PTJ3 */
348 kPORT_MuxAsGpio,
349 /* Pin Control Register fields [15:0] are not locked */
350 kPORT_UnlockRegister};
351 /* PORTJ3 (pin 62) is configured as PTJ3 */
352 PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
353
354 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
355 kPORT_PullDisable,
356 /* Slow slew rate is configured */
357 kPORT_SlowSlewRate,
358 /* Open drain is disabled */
359 kPORT_OpenDrainDisable,
360 /* Pin is configured as PTJ4 */
361 kPORT_MuxAsGpio,
362 /* Pin Control Register fields [15:0] are not locked */
363 kPORT_UnlockRegister};
364 /* PORTJ4 (pin 63) is configured as PTJ4 */
365 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
366 }
367
368 /* clang-format off */
369 /*
370 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
371 BOARD_InitACCELPins:
372 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
373 - pin_list:
374 - {pin_num: '80', peripheral: I2C0, signal: SDA, pin_signal: PTE0/I2C0_SDA/XBAR_OUT4/UART3_TX/CLKOUT, slew_rate: fast, open_drain: enable, pull_select: down, pull_enable: disable,
375 digital_filter: disable}
376 - {pin_num: '79', peripheral: I2C0, signal: SCL, pin_signal: CMP0_IN4/PTD7/LLWU_P7/I2C0_SCL/XBAR_IN4/UART3_RX, slew_rate: fast, open_drain: enable, pull_select: down,
377 pull_enable: disable}
378 - {pin_num: '66', peripheral: GPIOJ, signal: 'GPIO, 5', pin_signal: PTJ5/LPUART0_TX, direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: up, pull_enable: enable}
379 - {pin_num: '67', peripheral: GPIOJ, signal: 'GPIO, 6', pin_signal: PTJ6/LLWU_P18/LPUART0_RX, direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: up,
380 pull_enable: enable}
381 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
382 */
383 /* clang-format on */
384
385 /* FUNCTION ************************************************************************************************************
386 *
387 * Function Name : BOARD_InitACCELPins
388 * Description : Configures pin routing and optionally pin electrical features.
389 *
390 * END ****************************************************************************************************************/
BOARD_InitACCELPins(void)391 void BOARD_InitACCELPins(void)
392 {
393 /* PCTLD Clock Gate Control: Clock enabled */
394 CLOCK_EnableClock(kCLOCK_PortD);
395 /* PCTLE Clock Gate Control: Clock enabled */
396 CLOCK_EnableClock(kCLOCK_PortE);
397 /* PCTLJ Clock Gate Control: Clock enabled */
398 CLOCK_EnableClock(kCLOCK_PortJ);
399
400 gpio_pin_config_t ACCEL_INT1_config = {
401 .pinDirection = kGPIO_DigitalInput,
402 .outputLogic = 0U
403 };
404 /* Initialize GPIO functionality on pin PTJ5 (pin 66) */
405 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
406
407 gpio_pin_config_t ACCEL_INT2_config = {
408 .pinDirection = kGPIO_DigitalInput,
409 .outputLogic = 0U
410 };
411 /* Initialize GPIO functionality on pin PTJ6 (pin 67) */
412 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
413
414 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
415 kPORT_PullDisable,
416 /* Fast slew rate is configured */
417 kPORT_FastSlewRate,
418 /* Open drain is enabled */
419 kPORT_OpenDrainEnable,
420 /* Pin is configured as I2C0_SCL */
421 kPORT_MuxAlt2,
422 /* Pin Control Register fields [15:0] are not locked */
423 kPORT_UnlockRegister};
424 /* PORTD7 (pin 79) is configured as I2C0_SCL */
425 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
426 /* Configure digital filter */
427 PORT_EnablePinsDigitalFilter(
428 /* Digital filter is configured on port E */
429 PORTE,
430 /* Digital filter is configured for PORTE0 */
431 PORT_DFER_DFE_0_MASK,
432 /* Disable digital filter */
433 false);
434
435 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
436 kPORT_PullDisable,
437 /* Fast slew rate is configured */
438 kPORT_FastSlewRate,
439 /* Open drain is enabled */
440 kPORT_OpenDrainEnable,
441 /* Pin is configured as I2C0_SDA */
442 kPORT_MuxAlt2,
443 /* Pin Control Register fields [15:0] are not locked */
444 kPORT_UnlockRegister};
445 /* PORTE0 (pin 80) is configured as I2C0_SDA */
446 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
447
448 const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */
449 kPORT_PullUp,
450 /* Fast slew rate is configured */
451 kPORT_FastSlewRate,
452 /* Open drain is enabled */
453 kPORT_OpenDrainEnable,
454 /* Pin is configured as PTJ5 */
455 kPORT_MuxAsGpio,
456 /* Pin Control Register fields [15:0] are not locked */
457 kPORT_UnlockRegister};
458 /* PORTJ5 (pin 66) is configured as PTJ5 */
459 PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
460
461 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
462 kPORT_PullUp,
463 /* Fast slew rate is configured */
464 kPORT_FastSlewRate,
465 /* Open drain is enabled */
466 kPORT_OpenDrainEnable,
467 /* Pin is configured as PTJ6 */
468 kPORT_MuxAsGpio,
469 /* Pin Control Register fields [15:0] are not locked */
470 kPORT_UnlockRegister};
471 /* PORTJ6 (pin 67) is configured as PTJ6 */
472 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
473 }
474
475 /* clang-format off */
476 /*
477 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
478 BOARD_InitDEBUG_UARTPins:
479 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
480 - pin_list:
481 - {pin_num: '7', peripheral: UART2, signal: TX, pin_signal: LCD_P47/PTI7/UART2_TX, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
482 - {pin_num: '6', peripheral: UART2, signal: RX, pin_signal: LCD_P46/PTI6/UART2_RX, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
483 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
484 */
485 /* clang-format on */
486
487 /* FUNCTION ************************************************************************************************************
488 *
489 * Function Name : BOARD_InitDEBUG_UARTPins
490 * Description : Configures pin routing and optionally pin electrical features.
491 *
492 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)493 void BOARD_InitDEBUG_UARTPins(void)
494 {
495 /* PCTLI Clock Gate Control: Clock enabled */
496 CLOCK_EnableClock(kCLOCK_PortI);
497
498 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
499 kPORT_PullDisable,
500 /* Fast slew rate is configured */
501 kPORT_FastSlewRate,
502 /* Open drain is disabled */
503 kPORT_OpenDrainDisable,
504 /* Pin is configured as UART2_RX */
505 kPORT_MuxAlt2,
506 /* Pin Control Register fields [15:0] are not locked */
507 kPORT_UnlockRegister};
508 /* PORTI6 (pin 6) is configured as UART2_RX */
509 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
510
511 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
512 kPORT_PullDisable,
513 /* Fast slew rate is configured */
514 kPORT_FastSlewRate,
515 /* Open drain is disabled */
516 kPORT_OpenDrainDisable,
517 /* Pin is configured as UART2_TX */
518 kPORT_MuxAlt2,
519 /* Pin Control Register fields [15:0] are not locked */
520 kPORT_UnlockRegister};
521 /* PORTI7 (pin 7) is configured as UART2_TX */
522 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
523
524 SIM->MISC_CTL = ((SIM->MISC_CTL &
525 /* Mask bits to zero which are setting */
526 (~(SIM_MISC_CTL_UART2IRSEL_MASK)))
527
528 /* UART2 IrDA Select: Pad RX input PTI[6] or PTE[6] selected for RX input of UART2 and UART2
529 * TX signal is not used for modulation. */
530 | SIM_MISC_CTL_UART2IRSEL(MISC_CTL_UART2IRSEL_NONE));
531 }
532
533 /* clang-format off */
534 /*
535 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
536 BOARD_InitOSCPins:
537 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
538 - pin_list:
539 - {pin_num: '85', peripheral: OSC, signal: XTAL, pin_signal: XTAL0/PTE3/EWM_OUT_b/AFE_CLK/I2C1_SCL, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
540 pull_enable: no_init, digital_filter: no_init}
541 - {pin_num: '84', peripheral: OSC, signal: EXTAL, pin_signal: EXTAL0/PTE2/EWM_IN/XBAR_IN6/I2C1_SDA, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
542 pull_enable: no_init, digital_filter: no_init}
543 - {pin_num: '33', peripheral: RTC, signal: XTAL32, pin_signal: XTAL32}
544 - {pin_num: '34', peripheral: RTC, signal: EXTAL32, pin_signal: EXTAL32}
545 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
546 */
547 /* clang-format on */
548
549 /* FUNCTION ************************************************************************************************************
550 *
551 * Function Name : BOARD_InitOSCPins
552 * Description : Configures pin routing and optionally pin electrical features.
553 *
554 * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)555 void BOARD_InitOSCPins(void)
556 {
557 /* PCTLE Clock Gate Control: Clock enabled */
558 CLOCK_EnableClock(kCLOCK_PortE);
559
560 /* PORTE2 (pin 84) is configured as EXTAL0 */
561 PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
562
563 /* PORTE3 (pin 85) is configured as XTAL0 */
564 PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
565 }
566
567 /* clang-format off */
568 /*
569 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
570 BOARD_InitSPI_FLASHPins:
571 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
572 - pin_list:
573 - {pin_num: '114', peripheral: SPI0, signal: MOSI, pin_signal: LCD_P11/PTG4/SPI0_MOSI/I2C0_SDA, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down,
574 pull_enable: disable}
575 - {pin_num: '115', peripheral: SPI0, signal: MISO, pin_signal: LCD_P12/PTG5/SPI0_MISO/LPTMR0_ALT2, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: down,
576 pull_enable: disable}
577 - {pin_num: '113', peripheral: SPI0, signal: SCK, pin_signal: LCD_P10/PTG3/SPI0_SCK/I2C0_SCL, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down,
578 pull_enable: disable}
579 - {pin_num: '112', peripheral: SPI0, signal: PCS0, pin_signal: LCD_P9/ADC0_SE11/PTG2/LLWU_P1/SPI0_PCS0, direction: OUTPUT, slew_rate: fast, open_drain: disable,
580 pull_select: down, pull_enable: disable}
581 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
582 */
583 /* clang-format on */
584
585 /* FUNCTION ************************************************************************************************************
586 *
587 * Function Name : BOARD_InitSPI_FLASHPins
588 * Description : Configures pin routing and optionally pin electrical features.
589 *
590 * END ****************************************************************************************************************/
BOARD_InitSPI_FLASHPins(void)591 void BOARD_InitSPI_FLASHPins(void)
592 {
593 /* PCTLG Clock Gate Control: Clock enabled */
594 CLOCK_EnableClock(kCLOCK_PortG);
595
596 const port_pin_config_t FLASH_CS = {/* Internal pull-up/down resistor is disabled */
597 kPORT_PullDisable,
598 /* Fast slew rate is configured */
599 kPORT_FastSlewRate,
600 /* Open drain is disabled */
601 kPORT_OpenDrainDisable,
602 /* Pin is configured as SPI0_PCS0 */
603 kPORT_MuxAlt2,
604 /* Pin Control Register fields [15:0] are not locked */
605 kPORT_UnlockRegister};
606 /* PORTG2 (pin 112) is configured as SPI0_PCS0 */
607 PORT_SetPinConfig(BOARD_FLASH_CS_PORT, BOARD_FLASH_CS_PIN, &FLASH_CS);
608
609 const port_pin_config_t FLASH_CLK = {/* Internal pull-up/down resistor is disabled */
610 kPORT_PullDisable,
611 /* Fast slew rate is configured */
612 kPORT_FastSlewRate,
613 /* Open drain is disabled */
614 kPORT_OpenDrainDisable,
615 /* Pin is configured as SPI0_SCK */
616 kPORT_MuxAlt2,
617 /* Pin Control Register fields [15:0] are not locked */
618 kPORT_UnlockRegister};
619 /* PORTG3 (pin 113) is configured as SPI0_SCK */
620 PORT_SetPinConfig(BOARD_FLASH_CLK_PORT, BOARD_FLASH_CLK_PIN, &FLASH_CLK);
621
622 const port_pin_config_t FLASH_SI = {/* Internal pull-up/down resistor is disabled */
623 kPORT_PullDisable,
624 /* Fast slew rate is configured */
625 kPORT_FastSlewRate,
626 /* Open drain is disabled */
627 kPORT_OpenDrainDisable,
628 /* Pin is configured as SPI0_MOSI */
629 kPORT_MuxAlt2,
630 /* Pin Control Register fields [15:0] are not locked */
631 kPORT_UnlockRegister};
632 /* PORTG4 (pin 114) is configured as SPI0_MOSI */
633 PORT_SetPinConfig(BOARD_FLASH_SI_PORT, BOARD_FLASH_SI_PIN, &FLASH_SI);
634
635 const port_pin_config_t FLASH_SO = {/* Internal pull-up/down resistor is disabled */
636 kPORT_PullDisable,
637 /* Fast slew rate is configured */
638 kPORT_FastSlewRate,
639 /* Open drain is disabled */
640 kPORT_OpenDrainDisable,
641 /* Pin is configured as SPI0_MISO */
642 kPORT_MuxAlt2,
643 /* Pin Control Register fields [15:0] are not locked */
644 kPORT_UnlockRegister};
645 /* PORTG5 (pin 115) is configured as SPI0_MISO */
646 PORT_SetPinConfig(BOARD_FLASH_SO_PORT, BOARD_FLASH_SO_PIN, &FLASH_SO);
647 }
648
649 /* clang-format off */
650 /*
651 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
652 BOARD_InitInfra_RedPins:
653 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
654 - pin_list:
655 - {pin_num: '129', peripheral: SIM, signal: UART_MOD_AND_OUT, pin_signal: LCD_P55/PTL2/XBAR_OUT10, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
656 - {peripheral: SIM, signal: UART_MOD_CARR, pin_signal: RTC_CLK_Output}
657 - {peripheral: SIM, signal: UART_MOD_DATA, pin_signal: UART0_TX_output}
658 - {pin_num: '61', peripheral: CMP0, signal: 'IN, 0', pin_signal: CMP0_IN0/PTD0/LLWU_P11/UART0_RX/XBAR_IN2, identifier: IR_RX, slew_rate: fast, open_drain: disable,
659 pull_select: down, pull_enable: disable}
660 - {peripheral: UART0, signal: RX, pin_signal: CMP0_Output}
661 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
662 */
663 /* clang-format on */
664
665 /* FUNCTION ************************************************************************************************************
666 *
667 * Function Name : BOARD_InitInfra_RedPins
668 * Description : Configures pin routing and optionally pin electrical features.
669 *
670 * END ****************************************************************************************************************/
BOARD_InitInfra_RedPins(void)671 void BOARD_InitInfra_RedPins(void)
672 {
673 /* PCTLD Clock Gate Control: Clock enabled */
674 CLOCK_EnableClock(kCLOCK_PortD);
675 /* PCTLL Clock Gate Control: Clock enabled */
676 CLOCK_EnableClock(kCLOCK_PortL);
677 /* Peripheral Crossbar Clock Gate Control: Clock enabled */
678 CLOCK_EnableClock(kCLOCK_Xbar);
679
680 const port_pin_config_t IR_RX = {/* Internal pull-up/down resistor is disabled */
681 kPORT_PullDisable,
682 /* Fast slew rate is configured */
683 kPORT_FastSlewRate,
684 /* Open drain is disabled */
685 kPORT_OpenDrainDisable,
686 /* Pin is configured as CMP0_IN0 */
687 kPORT_PinDisabledOrAnalog,
688 /* Pin Control Register fields [15:0] are not locked */
689 kPORT_UnlockRegister};
690 /* PORTD0 (pin 61) is configured as CMP0_IN0 */
691 PORT_SetPinConfig(BOARD_IR_RX_PORT, BOARD_IR_RX_PIN, &IR_RX);
692
693 const port_pin_config_t IR_TX = {/* Internal pull-up/down resistor is disabled */
694 kPORT_PullDisable,
695 /* Fast slew rate is configured */
696 kPORT_FastSlewRate,
697 /* Open drain is disabled */
698 kPORT_OpenDrainDisable,
699 /* Pin is configured as XBAR_OUT10 */
700 kPORT_MuxAlt2,
701 /* Pin Control Register fields [15:0] are not locked */
702 kPORT_UnlockRegister};
703 /* PORTL2 (pin 129) is configured as XBAR_OUT10 */
704 PORT_SetPinConfig(BOARD_IR_TX_PORT, BOARD_IR_TX_PIN, &IR_TX);
705
706 SIM->MISC_CTL = ((SIM->MISC_CTL &
707 /* Mask bits to zero which are setting */
708 (~(SIM_MISC_CTL_UARTMODTYPE_MASK | SIM_MISC_CTL_UART0IRSEL_MASK)))
709
710 /* UART Modulation Type: TypeB (AND'ed) Modulation selected for IrDA. */
711 | SIM_MISC_CTL_UARTMODTYPE(MISC_CTL_UARTMODTYPE_TypeB)
712
713 /* UART0 IrDA Select: UART0 selected for IrDA modulation.
714 * UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13].
715 * UARTxIRSEL cannot configure XBAR_OUT[14] and XBAR_OUT[13] automatically, and they need
716 * extra configuration in XBAR.
717 * User should configure XBAR[14:13] accordingly. */
718 | SIM_MISC_CTL_UART0IRSEL(MISC_CTL_UART0IRSEL_IRDA));
719 /* UART TX Output (after modulation) output assigned to XBAR_IN14 input is connected
720 * to XBAR_OUT34 output assigned to XBAR Output pin 10 */
721 XBAR_SetSignalsConnection(XBAR, kXBAR_InputUartTxOutput, kXBAR_OutputXbOut10);
722 /* CMP0 Output output assigned to XBAR_IN11 input is connected
723 * to XBAR_OUT13 output assigned to UART Rx IrDA Input */
724 XBAR_SetSignalsConnection(XBAR, kXBAR_InputCmp0Output, kXBAR_OutputUartRxInput);
725 /* iRTC Clock Output output assigned to XBAR_IN10 input is connected
726 * to XBAR_OUT14 output assigned to SIM UART Tx IrDA Modulator Carrier Input */
727 XBAR_SetSignalsConnection(XBAR, kXBAR_InputRtcClockOutput, kXBAR_OutputUartTxModCarrier);
728 }
729
730 /* clang-format off */
731 /*
732 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
733 BOARD_InitPotentiometerPins:
734 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
735 - pin_list:
736 - {pin_num: '95', peripheral: ADC0, signal: 'SE, 8', pin_signal: LCD_P0/ADC0_SE8/CMP2_IN4/PTF1/QTMR0_TMR0/XBAR_OUT6, slew_rate: no_init, open_drain: no_init, pull_select: down,
737 pull_enable: disable}
738 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
739 */
740 /* clang-format on */
741
742 /* FUNCTION ************************************************************************************************************
743 *
744 * Function Name : BOARD_InitPotentiometerPins
745 * Description : Configures pin routing and optionally pin electrical features.
746 *
747 * END ****************************************************************************************************************/
BOARD_InitPotentiometerPins(void)748 void BOARD_InitPotentiometerPins(void)
749 {
750 /* PCTLF Clock Gate Control: Clock enabled */
751 CLOCK_EnableClock(kCLOCK_PortF);
752
753 /* PORTF1 (pin 95) is configured as ADC0_SE8 */
754 PORT_SetPinMux(BOARD_ADC_POT_PORT, BOARD_ADC_POT_PIN, kPORT_PinDisabledOrAnalog);
755
756 PORTF->PCR[1] = ((PORTF->PCR[1] &
757 /* Mask bits to zero which are setting */
758 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
759
760 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
761 * corresponding PE field is set. */
762 | PORT_PCR_PS(kPORT_PullDown)
763
764 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
765 | PORT_PCR_PE(kPORT_PullDisable));
766 }
767
768 /* clang-format off */
769 /*
770 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
771 BOARD_InitTemp_sensorPins:
772 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
773 - pin_list:
774 - {pin_num: '96', peripheral: ADC0, signal: 'SE, 9', pin_signal: LCD_P1/ADC0_SE9/CMP2_IN5/PTF2/CMP1_OUT/RTC_CLKOUT, slew_rate: no_init, open_drain: no_init, pull_select: down,
775 pull_enable: disable}
776 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
777 */
778 /* clang-format on */
779
780 /* FUNCTION ************************************************************************************************************
781 *
782 * Function Name : BOARD_InitTemp_sensorPins
783 * Description : Configures pin routing and optionally pin electrical features.
784 *
785 * END ****************************************************************************************************************/
BOARD_InitTemp_sensorPins(void)786 void BOARD_InitTemp_sensorPins(void)
787 {
788 /* PCTLF Clock Gate Control: Clock enabled */
789 CLOCK_EnableClock(kCLOCK_PortF);
790
791 /* PORTF2 (pin 96) is configured as ADC0_SE9 */
792 PORT_SetPinMux(BOARD_ADC_TEMP_PORT, BOARD_ADC_TEMP_PIN, kPORT_PinDisabledOrAnalog);
793
794 PORTF->PCR[2] = ((PORTF->PCR[2] &
795 /* Mask bits to zero which are setting */
796 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
797
798 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
799 * corresponding PE field is set. */
800 | PORT_PCR_PS(kPORT_PullDown)
801
802 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
803 | PORT_PCR_PE(kPORT_PullDisable));
804 }
805
806 /* clang-format off */
807 /*
808 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
809 BOARD_InitLCDPins:
810 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
811 - pin_list:
812 - {pin_num: '26', peripheral: LCD, signal: 'P, 38', pin_signal: LCD_P38/PTB7/AFE_CLK, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
813 - {pin_num: '24', peripheral: LCD, signal: 'P, 36', pin_signal: LCD_P36/PTB5, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
814 - {pin_num: '22', peripheral: LCD, signal: 'P, 34', pin_signal: LCD_P34/PTB3, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
815 - {pin_num: '20', peripheral: LCD, signal: 'P, 32', pin_signal: LCD_P32/PTB1/LLWU_P17, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
816 - {pin_num: '16', peripheral: LCD, signal: 'P, 31', pin_signal: LCD_P31/PTB0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
817 - {pin_num: '12', peripheral: LCD, signal: 'P, 29', pin_signal: LCD_P29/PTA6/LLWU_P14/XBAR_IN0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
818 - {pin_num: '8', peripheral: LCD, signal: 'P, 25', pin_signal: LCD_P25/PTA2, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
819 - {pin_num: '4', peripheral: LCD, signal: 'P, 23', pin_signal: LCD_P23/PTA0/LLWU_P16, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
820 - {pin_num: '31', peripheral: LCD, signal: 'P, 43', pin_signal: LCD_P43/PTC4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
821 - {pin_num: '25', peripheral: LCD, signal: 'P, 37', pin_signal: LCD_P37/CMP1_IN0/PTB6, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
822 - {pin_num: '23', peripheral: LCD, signal: 'P, 35', pin_signal: LCD_P35/PTB4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
823 - {pin_num: '21', peripheral: LCD, signal: 'P, 33', pin_signal: LCD_P33/PTB2, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
824 - {pin_num: '17', peripheral: LCD, signal: 'P, 50', pin_signal: LCD_P50/PTJ2, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
825 - {pin_num: '13', peripheral: LCD, signal: 'P, 30', pin_signal: LCD_P30/PTA7/XBAR_OUT0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
826 - {pin_num: '3', peripheral: LCD, signal: 'P, 45', pin_signal: LCD_P45/PTI5, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
827 - {pin_num: '5', peripheral: LCD, signal: 'P, 24', pin_signal: LCD_P24/PTA1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
828 - {pin_num: '9', peripheral: LCD, signal: 'P, 26', pin_signal: LCD_P26/PTA3, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
829 - {pin_num: '11', peripheral: LCD, signal: 'P, 28', pin_signal: LCD_P28/PTA5/CMP0_OUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
830 - {pin_num: '143', peripheral: LCD, signal: 'P, 44', pin_signal: LCD_P44/PTI4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
831 - {pin_num: '142', peripheral: LCD, signal: 'P, 59', pin_signal: LCD_P59/PTL6, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
832 - {pin_num: '140', peripheral: LCD, signal: 'P, 57', pin_signal: LCD_P57/PTL4/EWM_OUT_b, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
833 - {pin_num: '122', peripheral: LCD, signal: 'P, 19', pin_signal: LCD_P19/PTH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
834 - {pin_num: '116', peripheral: LCD, signal: 'P, 13', pin_signal: LCD_P13/PTG6/LLWU_P0/LPTMR0_ALT3, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
835 - {pin_num: '141', peripheral: LCD, signal: 'P, 58', pin_signal: LCD_P58/PTL5/LLWU_P23, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
836 - {pin_num: '139', peripheral: LCD, signal: 'P, 56', pin_signal: LCD_P56/PTL3/EWM_IN, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
837 - {pin_num: '131', peripheral: LCD, signal: 'P, 22', pin_signal: LCD_P22/PTI3/LPUART0_TX/CMP2_OUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
838 - {pin_num: '123', peripheral: LCD, signal: 'P, 20', pin_signal: LCD_P20/PTH5, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
839 - {pin_num: '117', peripheral: LCD, signal: 'P, 14', pin_signal: LCD_P14/PTG7, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
840 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
841 */
842 /* clang-format on */
843
844 /* FUNCTION ************************************************************************************************************
845 *
846 * Function Name : BOARD_InitLCDPins
847 * Description : Configures pin routing and optionally pin electrical features.
848 *
849 * END ****************************************************************************************************************/
BOARD_InitLCDPins(void)850 void BOARD_InitLCDPins(void)
851 {
852 /* PCTLA Clock Gate Control: Clock enabled */
853 CLOCK_EnableClock(kCLOCK_PortA);
854 /* PCTLB Clock Gate Control: Clock enabled */
855 CLOCK_EnableClock(kCLOCK_PortB);
856 /* PCTLC Clock Gate Control: Clock enabled */
857 CLOCK_EnableClock(kCLOCK_PortC);
858 /* PCTLG Clock Gate Control: Clock enabled */
859 CLOCK_EnableClock(kCLOCK_PortG);
860 /* PCTLH Clock Gate Control: Clock enabled */
861 CLOCK_EnableClock(kCLOCK_PortH);
862 /* PCTLI Clock Gate Control: Clock enabled */
863 CLOCK_EnableClock(kCLOCK_PortI);
864 /* PCTLJ Clock Gate Control: Clock enabled */
865 CLOCK_EnableClock(kCLOCK_PortJ);
866 /* PCTLL Clock Gate Control: Clock enabled */
867 CLOCK_EnableClock(kCLOCK_PortL);
868
869 const port_pin_config_t LCD_P23 = {/* Internal pull-up/down resistor is disabled */
870 kPORT_PullDisable,
871 /* Fast slew rate is configured */
872 kPORT_FastSlewRate,
873 /* Open drain is disabled */
874 kPORT_OpenDrainDisable,
875 /* Pin is configured as LCD_P23 */
876 kPORT_PinDisabledOrAnalog,
877 /* Pin Control Register fields [15:0] are not locked */
878 kPORT_UnlockRegister};
879 /* PORTA0 (pin 4) is configured as LCD_P23 */
880 PORT_SetPinConfig(BOARD_LCD_P23_PORT, BOARD_LCD_P23_PIN, &LCD_P23);
881
882 const port_pin_config_t LCD_P24 = {/* Internal pull-up/down resistor is disabled */
883 kPORT_PullDisable,
884 /* Fast slew rate is configured */
885 kPORT_FastSlewRate,
886 /* Open drain is disabled */
887 kPORT_OpenDrainDisable,
888 /* Pin is configured as LCD_P24 */
889 kPORT_PinDisabledOrAnalog,
890 /* Pin Control Register fields [15:0] are not locked */
891 kPORT_UnlockRegister};
892 /* PORTA1 (pin 5) is configured as LCD_P24 */
893 PORT_SetPinConfig(BOARD_LCD_P24_PORT, BOARD_LCD_P24_PIN, &LCD_P24);
894
895 const port_pin_config_t LCD_P25 = {/* Internal pull-up/down resistor is disabled */
896 kPORT_PullDisable,
897 /* Fast slew rate is configured */
898 kPORT_FastSlewRate,
899 /* Open drain is disabled */
900 kPORT_OpenDrainDisable,
901 /* Pin is configured as LCD_P25 */
902 kPORT_PinDisabledOrAnalog,
903 /* Pin Control Register fields [15:0] are not locked */
904 kPORT_UnlockRegister};
905 /* PORTA2 (pin 8) is configured as LCD_P25 */
906 PORT_SetPinConfig(BOARD_LCD_P25_PORT, BOARD_LCD_P25_PIN, &LCD_P25);
907
908 const port_pin_config_t LCD_P26 = {/* Internal pull-up/down resistor is disabled */
909 kPORT_PullDisable,
910 /* Fast slew rate is configured */
911 kPORT_FastSlewRate,
912 /* Open drain is disabled */
913 kPORT_OpenDrainDisable,
914 /* Pin is configured as LCD_P26 */
915 kPORT_PinDisabledOrAnalog,
916 /* Pin Control Register fields [15:0] are not locked */
917 kPORT_UnlockRegister};
918 /* PORTA3 (pin 9) is configured as LCD_P26 */
919 PORT_SetPinConfig(BOARD_LCD_P26_PORT, BOARD_LCD_P26_PIN, &LCD_P26);
920
921 const port_pin_config_t LCD_P28 = {/* Internal pull-up/down resistor is disabled */
922 kPORT_PullDisable,
923 /* Fast slew rate is configured */
924 kPORT_FastSlewRate,
925 /* Open drain is disabled */
926 kPORT_OpenDrainDisable,
927 /* Pin is configured as LCD_P28 */
928 kPORT_PinDisabledOrAnalog,
929 /* Pin Control Register fields [15:0] are not locked */
930 kPORT_UnlockRegister};
931 /* PORTA5 (pin 11) is configured as LCD_P28 */
932 PORT_SetPinConfig(BOARD_LCD_P28_PORT, BOARD_LCD_P28_PIN, &LCD_P28);
933
934 const port_pin_config_t LCD_P29 = {/* Internal pull-up/down resistor is disabled */
935 kPORT_PullDisable,
936 /* Fast slew rate is configured */
937 kPORT_FastSlewRate,
938 /* Open drain is disabled */
939 kPORT_OpenDrainDisable,
940 /* Pin is configured as LCD_P29 */
941 kPORT_PinDisabledOrAnalog,
942 /* Pin Control Register fields [15:0] are not locked */
943 kPORT_UnlockRegister};
944 /* PORTA6 (pin 12) is configured as LCD_P29 */
945 PORT_SetPinConfig(BOARD_LCD_P29_PORT, BOARD_LCD_P29_PIN, &LCD_P29);
946
947 const port_pin_config_t LCD_P30 = {/* Internal pull-up/down resistor is disabled */
948 kPORT_PullDisable,
949 /* Fast slew rate is configured */
950 kPORT_FastSlewRate,
951 /* Open drain is disabled */
952 kPORT_OpenDrainDisable,
953 /* Pin is configured as LCD_P30 */
954 kPORT_PinDisabledOrAnalog,
955 /* Pin Control Register fields [15:0] are not locked */
956 kPORT_UnlockRegister};
957 /* PORTA7 (pin 13) is configured as LCD_P30 */
958 PORT_SetPinConfig(BOARD_LCD_P30_PORT, BOARD_LCD_P30_PIN, &LCD_P30);
959
960 const port_pin_config_t LCD_P31 = {/* Internal pull-up/down resistor is disabled */
961 kPORT_PullDisable,
962 /* Fast slew rate is configured */
963 kPORT_FastSlewRate,
964 /* Open drain is disabled */
965 kPORT_OpenDrainDisable,
966 /* Pin is configured as LCD_P31 */
967 kPORT_PinDisabledOrAnalog,
968 /* Pin Control Register fields [15:0] are not locked */
969 kPORT_UnlockRegister};
970 /* PORTB0 (pin 16) is configured as LCD_P31 */
971 PORT_SetPinConfig(BOARD_LCD_P31_PORT, BOARD_LCD_P31_PIN, &LCD_P31);
972
973 const port_pin_config_t LCD_P32 = {/* Internal pull-up/down resistor is disabled */
974 kPORT_PullDisable,
975 /* Fast slew rate is configured */
976 kPORT_FastSlewRate,
977 /* Open drain is disabled */
978 kPORT_OpenDrainDisable,
979 /* Pin is configured as LCD_P32 */
980 kPORT_PinDisabledOrAnalog,
981 /* Pin Control Register fields [15:0] are not locked */
982 kPORT_UnlockRegister};
983 /* PORTB1 (pin 20) is configured as LCD_P32 */
984 PORT_SetPinConfig(BOARD_LCD_P32_PORT, BOARD_LCD_P32_PIN, &LCD_P32);
985
986 const port_pin_config_t LCD_P33 = {/* Internal pull-up/down resistor is disabled */
987 kPORT_PullDisable,
988 /* Fast slew rate is configured */
989 kPORT_FastSlewRate,
990 /* Open drain is disabled */
991 kPORT_OpenDrainDisable,
992 /* Pin is configured as LCD_P33 */
993 kPORT_PinDisabledOrAnalog,
994 /* Pin Control Register fields [15:0] are not locked */
995 kPORT_UnlockRegister};
996 /* PORTB2 (pin 21) is configured as LCD_P33 */
997 PORT_SetPinConfig(BOARD_LCD_P33_PORT, BOARD_LCD_P33_PIN, &LCD_P33);
998
999 const port_pin_config_t LCD_P34 = {/* Internal pull-up/down resistor is disabled */
1000 kPORT_PullDisable,
1001 /* Fast slew rate is configured */
1002 kPORT_FastSlewRate,
1003 /* Open drain is disabled */
1004 kPORT_OpenDrainDisable,
1005 /* Pin is configured as LCD_P34 */
1006 kPORT_PinDisabledOrAnalog,
1007 /* Pin Control Register fields [15:0] are not locked */
1008 kPORT_UnlockRegister};
1009 /* PORTB3 (pin 22) is configured as LCD_P34 */
1010 PORT_SetPinConfig(BOARD_LCD_P34_PORT, BOARD_LCD_P34_PIN, &LCD_P34);
1011
1012 const port_pin_config_t LCD_P35 = {/* Internal pull-up/down resistor is disabled */
1013 kPORT_PullDisable,
1014 /* Fast slew rate is configured */
1015 kPORT_FastSlewRate,
1016 /* Open drain is disabled */
1017 kPORT_OpenDrainDisable,
1018 /* Pin is configured as LCD_P35 */
1019 kPORT_PinDisabledOrAnalog,
1020 /* Pin Control Register fields [15:0] are not locked */
1021 kPORT_UnlockRegister};
1022 /* PORTB4 (pin 23) is configured as LCD_P35 */
1023 PORT_SetPinConfig(BOARD_LCD_P35_PORT, BOARD_LCD_P35_PIN, &LCD_P35);
1024
1025 const port_pin_config_t LCD_P36 = {/* Internal pull-up/down resistor is disabled */
1026 kPORT_PullDisable,
1027 /* Fast slew rate is configured */
1028 kPORT_FastSlewRate,
1029 /* Open drain is disabled */
1030 kPORT_OpenDrainDisable,
1031 /* Pin is configured as LCD_P36 */
1032 kPORT_PinDisabledOrAnalog,
1033 /* Pin Control Register fields [15:0] are not locked */
1034 kPORT_UnlockRegister};
1035 /* PORTB5 (pin 24) is configured as LCD_P36 */
1036 PORT_SetPinConfig(BOARD_LCD_P36_PORT, BOARD_LCD_P36_PIN, &LCD_P36);
1037
1038 const port_pin_config_t LCD_P37 = {/* Internal pull-up/down resistor is disabled */
1039 kPORT_PullDisable,
1040 /* Fast slew rate is configured */
1041 kPORT_FastSlewRate,
1042 /* Open drain is disabled */
1043 kPORT_OpenDrainDisable,
1044 /* Pin is configured as LCD_P37 */
1045 kPORT_PinDisabledOrAnalog,
1046 /* Pin Control Register fields [15:0] are not locked */
1047 kPORT_UnlockRegister};
1048 /* PORTB6 (pin 25) is configured as LCD_P37 */
1049 PORT_SetPinConfig(BOARD_LCD_P37_PORT, BOARD_LCD_P37_PIN, &LCD_P37);
1050
1051 const port_pin_config_t LCD_P38 = {/* Internal pull-up/down resistor is disabled */
1052 kPORT_PullDisable,
1053 /* Fast slew rate is configured */
1054 kPORT_FastSlewRate,
1055 /* Open drain is disabled */
1056 kPORT_OpenDrainDisable,
1057 /* Pin is configured as LCD_P38 */
1058 kPORT_PinDisabledOrAnalog,
1059 /* Pin Control Register fields [15:0] are not locked */
1060 kPORT_UnlockRegister};
1061 /* PORTB7 (pin 26) is configured as LCD_P38 */
1062 PORT_SetPinConfig(BOARD_LCD_P38_PORT, BOARD_LCD_P38_PIN, &LCD_P38);
1063
1064 const port_pin_config_t LCD_P43 = {/* Internal pull-up/down resistor is disabled */
1065 kPORT_PullDisable,
1066 /* Fast slew rate is configured */
1067 kPORT_FastSlewRate,
1068 /* Open drain is disabled */
1069 kPORT_OpenDrainDisable,
1070 /* Pin is configured as LCD_P43 */
1071 kPORT_PinDisabledOrAnalog,
1072 /* Pin Control Register fields [15:0] are not locked */
1073 kPORT_UnlockRegister};
1074 /* PORTC4 (pin 31) is configured as LCD_P43 */
1075 PORT_SetPinConfig(BOARD_LCD_P43_PORT, BOARD_LCD_P43_PIN, &LCD_P43);
1076
1077 const port_pin_config_t LCD_P13 = {/* Internal pull-up/down resistor is disabled */
1078 kPORT_PullDisable,
1079 /* Fast slew rate is configured */
1080 kPORT_FastSlewRate,
1081 /* Open drain is disabled */
1082 kPORT_OpenDrainDisable,
1083 /* Pin is configured as LCD_P13 */
1084 kPORT_PinDisabledOrAnalog,
1085 /* Pin Control Register fields [15:0] are not locked */
1086 kPORT_UnlockRegister};
1087 /* PORTG6 (pin 116) is configured as LCD_P13 */
1088 PORT_SetPinConfig(BOARD_LCD_P13_PORT, BOARD_LCD_P13_PIN, &LCD_P13);
1089
1090 const port_pin_config_t LCD_P14 = {/* Internal pull-up/down resistor is disabled */
1091 kPORT_PullDisable,
1092 /* Fast slew rate is configured */
1093 kPORT_FastSlewRate,
1094 /* Open drain is disabled */
1095 kPORT_OpenDrainDisable,
1096 /* Pin is configured as LCD_P14 */
1097 kPORT_PinDisabledOrAnalog,
1098 /* Pin Control Register fields [15:0] are not locked */
1099 kPORT_UnlockRegister};
1100 /* PORTG7 (pin 117) is configured as LCD_P14 */
1101 PORT_SetPinConfig(BOARD_LCD_P14_PORT, BOARD_LCD_P14_PIN, &LCD_P14);
1102
1103 const port_pin_config_t LCD_P19 = {/* Internal pull-up/down resistor is disabled */
1104 kPORT_PullDisable,
1105 /* Fast slew rate is configured */
1106 kPORT_FastSlewRate,
1107 /* Open drain is disabled */
1108 kPORT_OpenDrainDisable,
1109 /* Pin is configured as LCD_P19 */
1110 kPORT_PinDisabledOrAnalog,
1111 /* Pin Control Register fields [15:0] are not locked */
1112 kPORT_UnlockRegister};
1113 /* PORTH4 (pin 122) is configured as LCD_P19 */
1114 PORT_SetPinConfig(BOARD_LCD_P19_PORT, BOARD_LCD_P19_PIN, &LCD_P19);
1115
1116 const port_pin_config_t LCD_P20 = {/* Internal pull-up/down resistor is disabled */
1117 kPORT_PullDisable,
1118 /* Fast slew rate is configured */
1119 kPORT_FastSlewRate,
1120 /* Open drain is disabled */
1121 kPORT_OpenDrainDisable,
1122 /* Pin is configured as LCD_P20 */
1123 kPORT_PinDisabledOrAnalog,
1124 /* Pin Control Register fields [15:0] are not locked */
1125 kPORT_UnlockRegister};
1126 /* PORTH5 (pin 123) is configured as LCD_P20 */
1127 PORT_SetPinConfig(BOARD_LCD_P20_PORT, BOARD_LCD_P20_PIN, &LCD_P20);
1128
1129 const port_pin_config_t LCD_P22 = {/* Internal pull-up/down resistor is disabled */
1130 kPORT_PullDisable,
1131 /* Fast slew rate is configured */
1132 kPORT_FastSlewRate,
1133 /* Open drain is disabled */
1134 kPORT_OpenDrainDisable,
1135 /* Pin is configured as LCD_P22 */
1136 kPORT_PinDisabledOrAnalog,
1137 /* Pin Control Register fields [15:0] are not locked */
1138 kPORT_UnlockRegister};
1139 /* PORTI3 (pin 131) is configured as LCD_P22 */
1140 PORT_SetPinConfig(BOARD_LCD_P22_PORT, BOARD_LCD_P22_PIN, &LCD_P22);
1141
1142 const port_pin_config_t LCD_P44 = {/* Internal pull-up/down resistor is disabled */
1143 kPORT_PullDisable,
1144 /* Fast slew rate is configured */
1145 kPORT_FastSlewRate,
1146 /* Open drain is disabled */
1147 kPORT_OpenDrainDisable,
1148 /* Pin is configured as LCD_P44 */
1149 kPORT_PinDisabledOrAnalog,
1150 /* Pin Control Register fields [15:0] are not locked */
1151 kPORT_UnlockRegister};
1152 /* PORTI4 (pin 143) is configured as LCD_P44 */
1153 PORT_SetPinConfig(BOARD_LCD_P44_PORT, BOARD_LCD_P44_PIN, &LCD_P44);
1154
1155 const port_pin_config_t LCD_P45 = {/* Internal pull-up/down resistor is disabled */
1156 kPORT_PullDisable,
1157 /* Fast slew rate is configured */
1158 kPORT_FastSlewRate,
1159 /* Open drain is disabled */
1160 kPORT_OpenDrainDisable,
1161 /* Pin is configured as LCD_P45 */
1162 kPORT_PinDisabledOrAnalog,
1163 /* Pin Control Register fields [15:0] are not locked */
1164 kPORT_UnlockRegister};
1165 /* PORTI5 (pin 3) is configured as LCD_P45 */
1166 PORT_SetPinConfig(BOARD_LCD_P45_PORT, BOARD_LCD_P45_PIN, &LCD_P45);
1167
1168 const port_pin_config_t LCD_P50 = {/* Internal pull-up/down resistor is disabled */
1169 kPORT_PullDisable,
1170 /* Fast slew rate is configured */
1171 kPORT_FastSlewRate,
1172 /* Open drain is disabled */
1173 kPORT_OpenDrainDisable,
1174 /* Pin is configured as LCD_P50 */
1175 kPORT_PinDisabledOrAnalog,
1176 /* Pin Control Register fields [15:0] are not locked */
1177 kPORT_UnlockRegister};
1178 /* PORTJ2 (pin 17) is configured as LCD_P50 */
1179 PORT_SetPinConfig(BOARD_LCD_P50_PORT, BOARD_LCD_P50_PIN, &LCD_P50);
1180
1181 const port_pin_config_t LCD_P56 = {/* Internal pull-up/down resistor is disabled */
1182 kPORT_PullDisable,
1183 /* Fast slew rate is configured */
1184 kPORT_FastSlewRate,
1185 /* Open drain is disabled */
1186 kPORT_OpenDrainDisable,
1187 /* Pin is configured as LCD_P56 */
1188 kPORT_PinDisabledOrAnalog,
1189 /* Pin Control Register fields [15:0] are not locked */
1190 kPORT_UnlockRegister};
1191 /* PORTL3 (pin 139) is configured as LCD_P56 */
1192 PORT_SetPinConfig(BOARD_LCD_P56_PORT, BOARD_LCD_P56_PIN, &LCD_P56);
1193
1194 const port_pin_config_t LCD_P57 = {/* Internal pull-up/down resistor is disabled */
1195 kPORT_PullDisable,
1196 /* Fast slew rate is configured */
1197 kPORT_FastSlewRate,
1198 /* Open drain is disabled */
1199 kPORT_OpenDrainDisable,
1200 /* Pin is configured as LCD_P57 */
1201 kPORT_PinDisabledOrAnalog,
1202 /* Pin Control Register fields [15:0] are not locked */
1203 kPORT_UnlockRegister};
1204 /* PORTL4 (pin 140) is configured as LCD_P57 */
1205 PORT_SetPinConfig(BOARD_LCD_P57_PORT, BOARD_LCD_P57_PIN, &LCD_P57);
1206
1207 const port_pin_config_t LCD_P58 = {/* Internal pull-up/down resistor is disabled */
1208 kPORT_PullDisable,
1209 /* Fast slew rate is configured */
1210 kPORT_FastSlewRate,
1211 /* Open drain is disabled */
1212 kPORT_OpenDrainDisable,
1213 /* Pin is configured as LCD_P58 */
1214 kPORT_PinDisabledOrAnalog,
1215 /* Pin Control Register fields [15:0] are not locked */
1216 kPORT_UnlockRegister};
1217 /* PORTL5 (pin 141) is configured as LCD_P58 */
1218 PORT_SetPinConfig(BOARD_LCD_P58_PORT, BOARD_LCD_P58_PIN, &LCD_P58);
1219
1220 const port_pin_config_t LCD_P59 = {/* Internal pull-up/down resistor is disabled */
1221 kPORT_PullDisable,
1222 /* Fast slew rate is configured */
1223 kPORT_FastSlewRate,
1224 /* Open drain is disabled */
1225 kPORT_OpenDrainDisable,
1226 /* Pin is configured as LCD_P59 */
1227 kPORT_PinDisabledOrAnalog,
1228 /* Pin Control Register fields [15:0] are not locked */
1229 kPORT_UnlockRegister};
1230 /* PORTL6 (pin 142) is configured as LCD_P59 */
1231 PORT_SetPinConfig(BOARD_LCD_P59_PORT, BOARD_LCD_P59_PIN, &LCD_P59);
1232 }
1233 /***********************************************************************************************************************
1234 * EOF
1235 **********************************************************************************************************************/
1236
