1 /*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /* clang-format off */
9 /*
10 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11 !!GlobalInfo
12 product: Pins v5.0
13 processor: MKE18F512xxx16
14 package_id: MKE18F512VLL16
15 mcu_data: ksdk2_0
16 processor_version: 0.0.19
17 board: TWR-KE18F
18 pin_labels:
19 - {pin_num: '1', pin_signal: PTE16/FTM2_CH7/FXIO_D3/TRGMUX_OUT7, label: 'J20[6]'}
20 - {pin_num: '2', pin_signal: PTE15/FTM2_CH6/FXIO_D2/TRGMUX_OUT6, label: 'J20[5]'}
21 - {pin_num: '3', pin_signal: ADC2_SE1/PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/FXIO_D1/TRGMUX_OUT2, label: 'J20[4]/J15[B11]/LPSPI1_SIN'}
22 - {pin_num: '4', pin_signal: ADC2_SE0/PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/FXIO_D0/TRGMUX_OUT1, label: 'J15[B7]/J20[3]/LPSPI1_SCK'}
23 - {pin_num: '5', pin_signal: ADC2_SE13/PTE11/PWT_IN1/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5, label: 'J15[B34]/J20[8]/FTM2_CH5'}
24 - {pin_num: '6', pin_signal: ADC2_SE12/PTE10/CLKOUT/FTM2_CH4/FXIO_D4/TRGMUX_OUT4, label: 'J15[B25]/J20[7]/CLKOUT'}
25 - {pin_num: '8', pin_signal: PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN, label: 'J6[2]/CAN0_TX', identifier: CAN0_TX}
26 - {pin_num: '9', pin_signal: PTE4/BUSOUT/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT_b, label: 'J7[2]/CAN0_RX', identifier: CAN0_RX}
27 - {pin_num: '15', pin_signal: EXTAL/PTB7/LPI2C0_SCL, label: 'J24[2]/EXTAL', identifier: EXTAL0}
28 - {pin_num: '16', pin_signal: XTAL/PTB6/LPI2C0_SDA, label: 'X2[1]/XTAL', identifier: XTAL0}
29 - {pin_num: '17', pin_signal: ACMP2_IN3/PTE14/FTM0_FLT1/FTM2_FLT1, label: TP4/IRRX, identifier: IRRX_CMP_IN}
30 - {pin_num: '18', pin_signal: PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/ACMP2_OUT, label: 'J15[A41]/PTC6/LPUART1_RX', identifier: IRRX_CMP_OUT}
31 - {pin_num: '19', pin_signal: PTE12/FTM0_FLT3/LPUART2_TX, label: 'J15[B61]'}
32 - {pin_num: '20', pin_signal: PTD17/FTM0_FLT2/LPUART2_RX, label: 'J15[B62]'}
33 - {pin_num: '21', pin_signal: ACMP2_IN0/PTD16/FTM0_CH1, label: 'J15[B59]/D5[1]/TRI_RED', identifier: LED_RED2}
34 - {pin_num: '22', pin_signal: ACMP2_IN1/PTD15/FTM0_CH0, label: 'J15[B60]/D5[4]/TRI_GR', identifier: LED_GREEN2}
35 - {pin_num: '23', pin_signal: ACMP2_IN2/DAC0_OUT/PTE9/FTM0_CH7/LPUART2_CTS, label: 'J15[A32]/DAC0_OUT/PTE9_ELEV'}
36 - {pin_num: '26', pin_signal: ACMP0_IN3/PTE8/FTM0_CH6, label: 'J15[B56]'}
37 - {pin_num: '27', pin_signal: PTB5/FTM0_CH5/LPSPI0_PCS1/TRGMUX_IN0/ACMP1_OUT, label: 'J15[B57]/D5[3]/TRI_BL', identifier: LED_BLUE}
38 - {pin_num: '28', pin_signal: ACMP1_IN2/PTB4/FTM0_CH4/LPSPI0_SOUT/TRGMUX_IN1, label: 'J15[B58]'}
39 - {pin_num: '29', pin_signal: ADC0_SE11/ACMP0_IN4/EXTAL32/PTC3/FTM0_CH3/CAN0_TX, label: 'Y1[1]/EXTAL32', identifier: EXTAL32}
40 - {pin_num: '30', pin_signal: ADC0_SE10/ACMP0_IN5/XTAL32/PTC2/FTM0_CH2/CAN0_RX, label: 'Y1[2]/XTAL32', identifier: XTAL32}
41 - {pin_num: '31', pin_signal: PTD7/LPUART2_TX/FTM2_FLT3, label: 'J15[A10]'}
42 - {pin_num: '32', pin_signal: PTD6/LPUART2_RX/FTM2_FLT2, label: 'J15[A11]/SW3', identifier: SW3}
43 - {pin_num: '33', pin_signal: PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/PWT_IN2/TRGMUX_IN7, label: 'J15[B23]'}
44 - {pin_num: '34', pin_signal: PTD12/FTM2_CH2/LPI2C1_HREQ/LPUART2_RTS, label: 'J15[B22]'}
45 - {pin_num: '35', pin_signal: PTD11/FTM2_CH1/FTM2_QD_PHA/LPUART2_CTS, label: 'J15[A34]/FTM2_QD_PHA'}
46 - {pin_num: '36', pin_signal: PTD10/FTM2_CH0/FTM2_QD_PHB, label: 'J15[A33]/FTM2_QD_PHB'}
47 - {pin_num: '39', pin_signal: ADC0_SE9/ACMP1_IN3/PTC1/FTM0_CH1/FTM1_CH7, label: 'J15[B33]/FTM1_CH7'}
48 - {pin_num: '40', pin_signal: ADC0_SE8/ACMP1_IN4/PTC0/FTM0_CH0/FTM1_CH6, label: 'J15[B24]/FTM1_CH6'}
49 - {pin_num: '41', pin_signal: ACMP1_IN5/PTD9/LPI2C1_SCL/FTM2_FLT3/FTM1_CH5, label: 'J15[B50]/LPI2C1_SCL'}
50 - {pin_num: '42', pin_signal: PTD8/LPI2C1_SDA/FTM2_FLT2/FTM1_CH4, label: 'J15[B51]/LPI2C1_SDA'}
51 - {pin_num: '44', pin_signal: ADC0_SE14/PTC16/FTM1_FLT2/LPI2C1_SDAS, label: 'J15[B55]'}
52 - {pin_num: '45', pin_signal: ADC0_SE13/ACMP2_IN4/PTC15/FTM1_CH3, label: 'U4[16]/FTM1_CH3/RST_FXOS8700CQ', identifier: ACCEL_I2C_RST}
53 - {pin_num: '46', pin_signal: ADC0_SE12/ACMP2_IN5/PTC14/FTM1_CH2, label: 'J9[1]/ADC0_SE12/POT_5K', identifier: POT_5K}
54 - {pin_num: '47', pin_signal: ADC0_SE7/PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2, label: 'J15[A53]/ADC0_SE7'}
55 - {pin_num: '48', pin_signal: ADC0_SE6/PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3, label: 'J15[A35]/ADC0_SE6'}
56 - {pin_num: '49', pin_signal: PTC13/FTM3_CH7/FTM2_CH7, label: 'D9[C]/FTM3_CH7/LEDOR', identifier: LED_ORANGE}
57 - {pin_num: '50', pin_signal: PTC12/FTM3_CH6/FTM2_CH6, label: 'D8[C]/FTM3_CH6/LEDYL', identifier: LED_YELLOW}
58 - {pin_num: '100', pin_signal: PTA8/FXIO_D6/FTM3_FLT3, label: 'J20[9]'}
59 - {pin_num: '99', pin_signal: PTA9/FXIO_D7/FTM3_FLT2/FTM1_FLT3, label: 'J20[10]'}
60 - {pin_num: '98', pin_signal: PTA4/ACMP0_OUT/EWM_OUT_b/JTAG_TMS/SWD_DIO, label: 'J10[2]/J12[1]/SWD_DIO_TGTMCU'}
61 - {pin_num: '97', pin_signal: PTA5/TCLK1/JTAG_TRST_b/RESET_b, label: 'J10[10]/J13[1]/J15[A62]/J15[A63]/RST_TGTMCU_b'}
62 - {pin_num: '96', pin_signal: ACMP0_IN2/PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK, label: 'J10[4]/J11[1]/SWD_CLK_TGTMCU'}
63 - {pin_num: '95', pin_signal: PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI, label: 'J10[8]/TDI'}
64 - {pin_num: '94', pin_signal: ADC2_SE7/PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/FTM1_FLT2, label: 'J15[B48]/SPI0_SCK'}
65 - {pin_num: '93', pin_signal: ADC2_SE6/PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/FTM1_FLT1, label: 'J15[B44]/SPI0_SIN'}
66 - {pin_num: '92', pin_signal: PTA10/FTM1_CH4/LPUART0_TX/FXIO_D0/JTAG_TDO/noetm_Trace_SWO, label: 'J10[6]/TDO'}
67 - {pin_num: '91', pin_signal: PTA11/FTM1_CH5/LPUART0_RX/FXIO_D1, label: FTM1_CH5}
68 - {pin_num: '90', pin_signal: ADC2_SE5/PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS, label: 'J15[A50]'}
69 - {pin_num: '89', pin_signal: ADC2_SE4/PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS, label: 'J15[A51]'}
70 - {pin_num: '85', pin_signal: ADC1_SE10/PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/PWT_IN3/LPUART1_CTS, label: 'J15[B45]/LPSPI0_SOUT'}
71 - {pin_num: '84', pin_signal: ADC1_SE11/ACMP0_IN6/PTE6/LPSPI0_PCS2/FTM3_CH7/LPUART1_RTS, label: 'J15[B46]/LPSPI0_PCS2'}
72 - {pin_num: '83', pin_signal: ADC1_SE12/PTA15/FTM1_CH2/LPSPI0_PCS3, label: 'J15[B52]/ADC1_SE12'}
73 - {pin_num: '82', pin_signal: ADC1_SE13/PTA16/FTM1_CH3/LPSPI1_PCS2, label: 'J15[B8]/LPSPI1_PCS2'}
74 - {pin_num: '81', pin_signal: ADC1_SE4/PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2, label: 'J15[A41]/PTE3/LPUART1_RX', identifier: IRRX_UART}
75 - {pin_num: '80', pin_signal: ADC1_SE5/PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3, label: 'J15[A42]/TP5/LPUART1_TX/IRTX', identifier: IRTX}
76 - {pin_num: '79', pin_signal: ADC0_SE0/ACMP0_IN0/PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3, label: THER_A/ADC0_SE0, identifier: THER_A}
77 - {pin_num: '78', pin_signal: ADC0_SE1/ACMP0_IN1/PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0, label: THER_B/ADC0_SE1, identifier: THER_B}
78 - {pin_num: '77', pin_signal: ADC2_SE11/PTB8/FTM3_CH0, label: 'J15[A29]/ADC2_SE11'}
79 - {pin_num: '76', pin_signal: ADC2_SE10/PTB9/FTM3_CH1/LPI2C0_SCLS, label: 'J15[B27]/ADC2_SE10'}
80 - {pin_num: '75', pin_signal: ADC2_SE9/PTB10/FTM3_CH2/LPI2C0_SDAS, label: 'J15[B28]/ADC2_SE9'}
81 - {pin_num: '74', pin_signal: ADC2_SE8/PTB11/FTM3_CH3/LPI2C0_HREQ, label: 'J15[A30]/ADC2_SE8'}
82 - {pin_num: '73', pin_signal: ADC1_SE0/PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT_b/LPUART0_RX, label: 'J15[A8]/U4[6]/LPI2C0_SDA', identifier: ACCEL_I2C_SDA}
83 - {pin_num: '72', pin_signal: ADC1_SE1/PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/LPUART0_TX, label: 'J15[A7]/U4[4]/LPI2C0_SCL', identifier: ACCEL_I2C_SCL}
84 - {pin_num: '71', pin_signal: ADC1_SE2/PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/TRGMUX_IN5, label: 'J15A[B10]/LPSPI1_SOUT'}
85 - {pin_num: '70', pin_signal: ADC1_SE3/PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/TRGMUX_IN4/NMI_b, label: 'J15[B9]/SW2/LPSPI1_PCS0', identifier: SW2}
86 - {pin_num: '69', pin_signal: ADC1_SE6/ACMP1_IN6/PTD4/FTM0_FLT3/FTM3_FLT3, label: 'J15[A27]/ADC1_SE6'}
87 - {pin_num: '68', pin_signal: ADC1_SE7/PTB12/FTM0_CH0/FTM3_FLT2, label: 'J15[A40]/FTM0_CH0'}
88 - {pin_num: '67', pin_signal: ADC1_SE8/ADC2_SE8/PTB13/FTM0_CH1/FTM3_FLT1, label: 'J15[A39]/FTM0_CH1'}
89 - {pin_num: '66', pin_signal: ADC1_SE9/ADC2_SE9/PTB14/FTM0_CH2/LPSPI1_SCK, label: 'J15[A38]/FTM0_CH2'}
90 - {pin_num: '65', pin_signal: ADC1_SE14/PTB15/FTM0_CH3/LPSPI1_SIN, label: 'J15[A37]/FTM0_CH3'}
91 - {pin_num: '64', pin_signal: ADC1_SE15/PTB16/FTM0_CH4/LPSPI1_SOUT, label: 'J15[B40]/FTM0_CH4'}
92 - {pin_num: '63', pin_signal: ADC2_SE3/PTB17/FTM0_CH5/LPSPI1_PCS3, label: 'J15[B39]/FTM0_CH5'}
93 - {pin_num: '62', pin_signal: PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT_b, label: 'J15[B35]'}
94 - {pin_num: '59', pin_signal: ADC2_SE2/ACMP2_IN6/PTE7/FTM0_CH7/FTM3_FLT0, label: 'J15[B30]/ADC2_SE2'}
95 - {pin_num: '58', pin_signal: ADC0_SE2/ACMP1_IN0/PTA6/FTM0_FLT1/LPSPI1_PCS1/LPUART1_CTS, label: 'J15[A28]/ADC0_SE2'}
96 - {pin_num: '57', pin_signal: ADC0_SE3/ACMP1_IN1/PTA7/FTM0_FLT2/RTC_CLKIN/LPUART1_RTS, label: 'J15[B29]/ADC0_SE3'}
97 - {pin_num: '56', pin_signal: ADC2_SE14/PTC8/LPUART1_RX/FTM1_FLT0/LPUART0_CTS, label: 'J15[A9]/LPUART0_CTS'}
98 - {pin_num: '55', pin_signal: ADC2_SE15/PTC9/LPUART1_TX/FTM1_FLT1/LPUART0_RTS, label: 'J15[B21]/LPUART0_RTS'}
99 - {pin_num: '54', pin_signal: ADC0_SE4/ADC1_SE14/PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/PWT_IN3, label: 'J5[2]/LPUART0_RX_TGTMCU', identifier: DEBUG_UART_RX}
100 - {pin_num: '53', pin_signal: ADC0_SE5/ADC1_SE15/PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0, label: 'J3[2]/LPUART0_TX_TGTMCU', identifier: DEBUG_UART_TX}
101 - {pin_num: '52', pin_signal: PTC10/FTM3_CH4, label: 'D6[C]/FTM3_CH4/LEDRD', identifier: LED_RED1}
102 - {pin_num: '51', pin_signal: PTC11/FTM3_CH5, label: 'D7[C]/FTM3_CH5/LEDGR', identifier: LED_GREEN1}
103 - {pin_num: '7', pin_signal: PTE13/FTM2_FLT0, label: NC}
104 - {pin_num: '10', pin_signal: VDD10, label: MCU_VDD}
105 - {pin_num: '87', pin_signal: VDD88, label: MCU_VDD}
106 - {pin_num: '61', pin_signal: VDD62, label: MCU_VDD}
107 - {pin_num: '38', pin_signal: VDD39, label: MCU_VDD}
108 - {pin_num: '11', pin_signal: VDDA, label: VDDA}
109 - {pin_num: '14', pin_signal: VSS15, label: GND}
110 - {pin_num: '37', pin_signal: VSS38, label: GND}
111 - {pin_num: '60', pin_signal: VSS61, label: GND}
112 - {pin_num: '86', pin_signal: VSS87, label: GND}
113 - {pin_num: '12', pin_signal: VREFH, label: VREFH}
114 - {pin_num: '13', pin_signal: VREFL, label: GND}
115 - {pin_num: '24', pin_signal: PTD14/FTM2_CH5/CLKOUT, label: NC}
116 - {pin_num: '25', pin_signal: PTD13/FTM2_CH4/RTC_CLKOUT, label: NC}
117 - {pin_num: '43', pin_signal: ADC0_SE15/PTC17/FTM1_FLT3/LPI2C1_SCLS, label: NC}
118 - {pin_num: '88', pin_signal: PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/BUSOUT, label: NC}
119 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
120 */
121 /* clang-format on */
122
123 #include "fsl_common.h"
124 #include "fsl_port.h"
125 #include "fsl_gpio.h"
126 #include "pin_mux.h"
127
128 /* FUNCTION ************************************************************************************************************
129 *
130 * Function Name : BOARD_InitBootPins
131 * Description : Calls initialization functions.
132 *
133 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)134 void BOARD_InitBootPins(void)
135 {
136 BOARD_InitPins();
137 BOARD_InitDEBUG_UARTPins();
138 }
139
140 /* clang-format off */
141 /*
142 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
143 BOARD_InitPins:
144 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
145 - pin_list:
146 - {pin_num: '92', peripheral: CoreDebug, signal: TRACE_SWO, pin_signal: PTA10/FTM1_CH4/LPUART0_TX/FXIO_D0/JTAG_TDO/noetm_Trace_SWO, pull_select: down}
147 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
148 */
149 /* clang-format on */
150
151 /* FUNCTION ************************************************************************************************************
152 *
153 * Function Name : BOARD_InitPins
154 * Description : Configures pin routing and optionally pin electrical features.
155 *
156 * END ****************************************************************************************************************/
BOARD_InitPins(void)157 void BOARD_InitPins(void)
158 {
159 /* Clock Control: Clock enabled */
160 CLOCK_EnableClock(kCLOCK_PortA);
161
162 /* PORTA10 (pin 92) is configured as noetm_Trace_SWO */
163 PORT_SetPinMux(PORTA, 10U, kPORT_MuxAlt7);
164
165 PORTA->PCR[10] = ((PORTA->PCR[10] &
166 /* Mask bits to zero which are setting */
167 (~(PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK)))
168
169 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
170 * corresponding PE field is set. */
171 | PORT_PCR_PS(kPORT_PullDown));
172 }
173
174 /* clang-format off */
175 /*
176 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
177 BOARD_InitLEDsPins:
178 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
179 - pin_list:
180 - {pin_num: '50', peripheral: GPIOC, signal: 'GPIO, 12', pin_signal: PTC12/FTM3_CH6/FTM2_CH6, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low, pull_select: down,
181 pull_enable: disable, passive_filter: disable, digital_filter: disable}
182 - {pin_num: '52', peripheral: GPIOC, signal: 'GPIO, 10', pin_signal: PTC10/FTM3_CH4, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low, pull_select: down,
183 pull_enable: disable, passive_filter: disable, digital_filter: disable}
184 - {pin_num: '49', peripheral: GPIOC, signal: 'GPIO, 13', pin_signal: PTC13/FTM3_CH7/FTM2_CH7, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low, pull_select: down,
185 pull_enable: disable, passive_filter: disable, digital_filter: disable}
186 - {pin_num: '51', peripheral: GPIOC, signal: 'GPIO, 11', pin_signal: PTC11/FTM3_CH5, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low, pull_select: down,
187 pull_enable: disable, passive_filter: disable, digital_filter: disable}
188 - {pin_num: '27', peripheral: GPIOB, signal: 'GPIO, 5', pin_signal: PTB5/FTM0_CH5/LPSPI0_PCS1/TRGMUX_IN0/ACMP1_OUT, direction: OUTPUT, gpio_init_state: 'true',
189 drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
190 - {pin_num: '22', peripheral: GPIOD, signal: 'GPIO, 15', pin_signal: ACMP2_IN1/PTD15/FTM0_CH0, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low,
191 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
192 - {pin_num: '21', peripheral: GPIOD, signal: 'GPIO, 16', pin_signal: ACMP2_IN0/PTD16/FTM0_CH1, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low,
193 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
194 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
195 */
196 /* clang-format on */
197
198 /* FUNCTION ************************************************************************************************************
199 *
200 * Function Name : BOARD_InitLEDsPins
201 * Description : Configures pin routing and optionally pin electrical features.
202 *
203 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)204 void BOARD_InitLEDsPins(void)
205 {
206 /* Clock Control: Clock enabled */
207 CLOCK_EnableClock(kCLOCK_PortB);
208 /* Clock Control: Clock enabled */
209 CLOCK_EnableClock(kCLOCK_PortC);
210 /* Clock Control: Clock enabled */
211 CLOCK_EnableClock(kCLOCK_PortD);
212
213 gpio_pin_config_t LED_BLUE_config = {
214 .pinDirection = kGPIO_DigitalOutput,
215 .outputLogic = 1U
216 };
217 /* Initialize GPIO functionality on pin PTB5 (pin 27) */
218 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
219
220 gpio_pin_config_t LED_RED1_config = {
221 .pinDirection = kGPIO_DigitalOutput,
222 .outputLogic = 1U
223 };
224 /* Initialize GPIO functionality on pin PTC10 (pin 52) */
225 GPIO_PinInit(BOARD_LED_RED1_GPIO, BOARD_LED_RED1_PIN, &LED_RED1_config);
226
227 gpio_pin_config_t LED_GREEN1_config = {
228 .pinDirection = kGPIO_DigitalOutput,
229 .outputLogic = 1U
230 };
231 /* Initialize GPIO functionality on pin PTC11 (pin 51) */
232 GPIO_PinInit(BOARD_LED_GREEN1_GPIO, BOARD_LED_GREEN1_PIN, &LED_GREEN1_config);
233
234 gpio_pin_config_t LED_YELLOW_config = {
235 .pinDirection = kGPIO_DigitalOutput,
236 .outputLogic = 1U
237 };
238 /* Initialize GPIO functionality on pin PTC12 (pin 50) */
239 GPIO_PinInit(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_PIN, &LED_YELLOW_config);
240
241 gpio_pin_config_t LED_ORANGE_config = {
242 .pinDirection = kGPIO_DigitalOutput,
243 .outputLogic = 1U
244 };
245 /* Initialize GPIO functionality on pin PTC13 (pin 49) */
246 GPIO_PinInit(BOARD_LED_ORANGE_GPIO, BOARD_LED_ORANGE_PIN, &LED_ORANGE_config);
247
248 gpio_pin_config_t LED_GREEN2_config = {
249 .pinDirection = kGPIO_DigitalOutput,
250 .outputLogic = 1U
251 };
252 /* Initialize GPIO functionality on pin PTD15 (pin 22) */
253 GPIO_PinInit(BOARD_LED_GREEN2_GPIO, BOARD_LED_GREEN2_PIN, &LED_GREEN2_config);
254
255 gpio_pin_config_t LED_RED2_config = {
256 .pinDirection = kGPIO_DigitalOutput,
257 .outputLogic = 1U
258 };
259 /* Initialize GPIO functionality on pin PTD16 (pin 21) */
260 GPIO_PinInit(BOARD_LED_RED2_GPIO, BOARD_LED_RED2_PIN, &LED_RED2_config);
261 /* Configure digital filter */
262 PORT_EnablePinsDigitalFilter(
263 /* Digital filter is configured on port B */
264 PORTB,
265 /* Digital filter is configured for PORTB0 */
266 PORT_DFER_DFE_5_MASK,
267 /* Disable digital filter */
268 false);
269
270 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
271 kPORT_PullDisable,
272 /* Passive filter is disabled */
273 kPORT_PassiveFilterDisable,
274 /* Low drive strength is configured */
275 kPORT_LowDriveStrength,
276 /* Pin is configured as PTB5 */
277 kPORT_MuxAsGpio,
278 /* Pin Control Register fields [15:0] are not locked */
279 kPORT_UnlockRegister};
280 /* PORTB5 (pin 27) is configured as PTB5 */
281 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
282 /* Configure digital filter */
283 PORT_EnablePinsDigitalFilter(
284 /* Digital filter is configured on port C */
285 PORTC,
286 /* Digital filter is configured for PORTC0 */
287 PORT_DFER_DFE_10_MASK
288 /* Digital filter is configured for PORTC1 */
289 | PORT_DFER_DFE_11_MASK
290 /* Digital filter is configured for PORTC2 */
291 | PORT_DFER_DFE_12_MASK
292 /* Digital filter is configured for PORTC3 */
293 | PORT_DFER_DFE_13_MASK,
294 /* Disable digital filter */
295 false);
296
297 const port_pin_config_t LED_RED1 = {/* Internal pull-up/down resistor is disabled */
298 kPORT_PullDisable,
299 /* Passive filter is disabled */
300 kPORT_PassiveFilterDisable,
301 /* Low drive strength is configured */
302 kPORT_LowDriveStrength,
303 /* Pin is configured as PTC10 */
304 kPORT_MuxAsGpio,
305 /* Pin Control Register fields [15:0] are not locked */
306 kPORT_UnlockRegister};
307 /* PORTC10 (pin 52) is configured as PTC10 */
308 PORT_SetPinConfig(BOARD_LED_RED1_PORT, BOARD_LED_RED1_PIN, &LED_RED1);
309
310 const port_pin_config_t LED_GREEN1 = {/* Internal pull-up/down resistor is disabled */
311 kPORT_PullDisable,
312 /* Passive filter is disabled */
313 kPORT_PassiveFilterDisable,
314 /* Low drive strength is configured */
315 kPORT_LowDriveStrength,
316 /* Pin is configured as PTC11 */
317 kPORT_MuxAsGpio,
318 /* Pin Control Register fields [15:0] are not locked */
319 kPORT_UnlockRegister};
320 /* PORTC11 (pin 51) is configured as PTC11 */
321 PORT_SetPinConfig(BOARD_LED_GREEN1_PORT, BOARD_LED_GREEN1_PIN, &LED_GREEN1);
322
323 const port_pin_config_t LED_YELLOW = {/* Internal pull-up/down resistor is disabled */
324 kPORT_PullDisable,
325 /* Passive filter is disabled */
326 kPORT_PassiveFilterDisable,
327 /* Low drive strength is configured */
328 kPORT_LowDriveStrength,
329 /* Pin is configured as PTC12 */
330 kPORT_MuxAsGpio,
331 /* Pin Control Register fields [15:0] are not locked */
332 kPORT_UnlockRegister};
333 /* PORTC12 (pin 50) is configured as PTC12 */
334 PORT_SetPinConfig(BOARD_LED_YELLOW_PORT, BOARD_LED_YELLOW_PIN, &LED_YELLOW);
335
336 const port_pin_config_t LED_ORANGE = {/* Internal pull-up/down resistor is disabled */
337 kPORT_PullDisable,
338 /* Passive filter is disabled */
339 kPORT_PassiveFilterDisable,
340 /* Low drive strength is configured */
341 kPORT_LowDriveStrength,
342 /* Pin is configured as PTC13 */
343 kPORT_MuxAsGpio,
344 /* Pin Control Register fields [15:0] are not locked */
345 kPORT_UnlockRegister};
346 /* PORTC13 (pin 49) is configured as PTC13 */
347 PORT_SetPinConfig(BOARD_LED_ORANGE_PORT, BOARD_LED_ORANGE_PIN, &LED_ORANGE);
348 /* Configure digital filter */
349 PORT_EnablePinsDigitalFilter(
350 /* Digital filter is configured on port D */
351 PORTD,
352 /* Digital filter is configured for PORTD0 */
353 PORT_DFER_DFE_15_MASK
354 /* Digital filter is configured for PORTD1 */
355 | PORT_DFER_DFE_16_MASK,
356 /* Disable digital filter */
357 false);
358
359 const port_pin_config_t LED_GREEN2 = {/* Internal pull-up/down resistor is disabled */
360 kPORT_PullDisable,
361 /* Passive filter is disabled */
362 kPORT_PassiveFilterDisable,
363 /* Low drive strength is configured */
364 kPORT_LowDriveStrength,
365 /* Pin is configured as PTD15 */
366 kPORT_MuxAsGpio,
367 /* Pin Control Register fields [15:0] are not locked */
368 kPORT_UnlockRegister};
369 /* PORTD15 (pin 22) is configured as PTD15 */
370 PORT_SetPinConfig(BOARD_LED_GREEN2_PORT, BOARD_LED_GREEN2_PIN, &LED_GREEN2);
371
372 const port_pin_config_t LED_RED2 = {/* Internal pull-up/down resistor is disabled */
373 kPORT_PullDisable,
374 /* Passive filter is disabled */
375 kPORT_PassiveFilterDisable,
376 /* Low drive strength is configured */
377 kPORT_LowDriveStrength,
378 /* Pin is configured as PTD16 */
379 kPORT_MuxAsGpio,
380 /* Pin Control Register fields [15:0] are not locked */
381 kPORT_UnlockRegister};
382 /* PORTD16 (pin 21) is configured as PTD16 */
383 PORT_SetPinConfig(BOARD_LED_RED2_PORT, BOARD_LED_RED2_PIN, &LED_RED2);
384 }
385
386 /* clang-format off */
387 /*
388 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
389 BOARD_InitBUTTONSPins:
390 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
391 - pin_list:
392 - {pin_num: '70', peripheral: GPIOD, signal: 'GPIO, 3', pin_signal: ADC1_SE3/PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/TRGMUX_IN4/NMI_b, direction: INPUT, drive_strength: low,
393 pull_select: up, pull_enable: disable, passive_filter: disable, digital_filter: disable}
394 - {pin_num: '32', peripheral: GPIOD, signal: 'GPIO, 6', pin_signal: PTD6/LPUART2_RX/FTM2_FLT2, direction: INPUT, drive_strength: low, pull_select: up, pull_enable: disable,
395 passive_filter: disable, digital_filter: disable}
396 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
397 */
398 /* clang-format on */
399
400 /* FUNCTION ************************************************************************************************************
401 *
402 * Function Name : BOARD_InitBUTTONSPins
403 * Description : Configures pin routing and optionally pin electrical features.
404 *
405 * END ****************************************************************************************************************/
BOARD_InitBUTTONSPins(void)406 void BOARD_InitBUTTONSPins(void)
407 {
408 /* Clock Control: Clock enabled */
409 CLOCK_EnableClock(kCLOCK_PortD);
410
411 gpio_pin_config_t SW2_config = {
412 .pinDirection = kGPIO_DigitalInput,
413 .outputLogic = 0U
414 };
415 /* Initialize GPIO functionality on pin PTD3 (pin 70) */
416 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
417
418 gpio_pin_config_t SW3_config = {
419 .pinDirection = kGPIO_DigitalInput,
420 .outputLogic = 0U
421 };
422 /* Initialize GPIO functionality on pin PTD6 (pin 32) */
423 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
424 /* Configure digital filter */
425 PORT_EnablePinsDigitalFilter(
426 /* Digital filter is configured on port D */
427 PORTD,
428 /* Digital filter is configured for PORTD0 */
429 PORT_DFER_DFE_3_MASK
430 /* Digital filter is configured for PORTD1 */
431 | PORT_DFER_DFE_6_MASK,
432 /* Disable digital filter */
433 false);
434
435 /* PORTD3 (pin 70) is configured as PTD3 */
436 PORT_SetPinMux(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_MuxAsGpio);
437
438 PORTD->PCR[3] =
439 ((PORTD->PCR[3] &
440 /* Mask bits to zero which are setting */
441 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK)))
442
443 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE
444 * field is set. */
445 | PORT_PCR_PS(kPORT_PullUp)
446
447 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
448 | PORT_PCR_PE(kPORT_PullDisable)
449
450 /* Passive Filter Enable: Passive input filter is disabled on the corresponding pin. */
451 | PORT_PCR_PFE(kPORT_PassiveFilterDisable)
452
453 /* Drive Strength Enable: Low drive strength is configured on the corresponding pin, if pin is
454 * configured as a digital output. */
455 | PORT_PCR_DSE(kPORT_LowDriveStrength));
456
457 /* PORTD6 (pin 32) is configured as PTD6 */
458 PORT_SetPinMux(BOARD_SW3_PORT, BOARD_SW3_PIN, kPORT_MuxAsGpio);
459
460 PORTD->PCR[6] =
461 ((PORTD->PCR[6] &
462 /* Mask bits to zero which are setting */
463 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK)))
464
465 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE
466 * field is set. */
467 | PORT_PCR_PS(kPORT_PullUp)
468
469 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
470 | PORT_PCR_PE(kPORT_PullDisable)
471
472 /* Passive Filter Enable: Passive input filter is disabled on the corresponding pin. */
473 | PORT_PCR_PFE(kPORT_PassiveFilterDisable)
474
475 /* Drive Strength Enable: Low drive strength is configured on the corresponding pin, if pin is
476 * configured as a digital output. */
477 | PORT_PCR_DSE(kPORT_LowDriveStrength));
478 }
479
480 /* clang-format off */
481 /*
482 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
483 BOARD_InitOSCPins:
484 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
485 - pin_list:
486 - {pin_num: '30', peripheral: OSC32, signal: XTAL32, pin_signal: ADC0_SE10/ACMP0_IN5/XTAL32/PTC2/FTM0_CH2/CAN0_RX, drive_strength: no_init, pull_select: no_init,
487 pull_enable: no_init, passive_filter: no_init, digital_filter: no_init}
488 - {pin_num: '29', peripheral: OSC32, signal: EXTAL32, pin_signal: ADC0_SE11/ACMP0_IN4/EXTAL32/PTC3/FTM0_CH3/CAN0_TX, drive_strength: no_init, pull_select: no_init,
489 pull_enable: no_init, passive_filter: no_init, digital_filter: no_init}
490 - {pin_num: '16', peripheral: SCG, signal: XTAL0, pin_signal: XTAL/PTB6/LPI2C0_SDA, drive_strength: no_init, pull_select: no_init, pull_enable: no_init, passive_filter: no_init,
491 digital_filter: no_init}
492 - {pin_num: '15', peripheral: SCG, signal: EXTAL0, pin_signal: EXTAL/PTB7/LPI2C0_SCL, drive_strength: no_init, pull_select: no_init, pull_enable: no_init, passive_filter: no_init,
493 digital_filter: no_init}
494 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
495 */
496 /* clang-format on */
497
498 /* FUNCTION ************************************************************************************************************
499 *
500 * Function Name : BOARD_InitOSCPins
501 * Description : Configures pin routing and optionally pin electrical features.
502 *
503 * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)504 void BOARD_InitOSCPins(void)
505 {
506 /* Clock Control: Clock enabled */
507 CLOCK_EnableClock(kCLOCK_PortB);
508 /* Clock Control: Clock enabled */
509 CLOCK_EnableClock(kCLOCK_PortC);
510
511 /* PORTB6 (pin 16) is configured as XTAL */
512 PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
513
514 /* PORTB7 (pin 15) is configured as EXTAL */
515 PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
516
517 /* PORTC2 (pin 30) is configured as XTAL32 */
518 PORT_SetPinMux(BOARD_XTAL32_PORT, BOARD_XTAL32_PIN, kPORT_PinDisabledOrAnalog);
519
520 /* PORTC3 (pin 29) is configured as EXTAL32 */
521 PORT_SetPinMux(BOARD_EXTAL32_PORT, BOARD_EXTAL32_PIN, kPORT_PinDisabledOrAnalog);
522 }
523
524 /* clang-format off */
525 /*
526 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
527 BOARD_InitACCELPins:
528 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
529 - pin_list:
530 - {pin_num: '72', peripheral: LPI2C0, signal: SCL, pin_signal: ADC1_SE1/PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/LPUART0_TX, direction: OUTPUT, drive_strength: low, pull_select: down,
531 pull_enable: disable, passive_filter: disable, digital_filter: disable}
532 - {pin_num: '73', peripheral: LPI2C0, signal: SDA, pin_signal: ADC1_SE0/PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT_b/LPUART0_RX, direction: INPUT, drive_strength: low, pull_select: down,
533 pull_enable: disable, passive_filter: disable, digital_filter: disable}
534 - {pin_num: '45', peripheral: GPIOC, signal: 'GPIO, 15', pin_signal: ADC0_SE13/ACMP2_IN4/PTC15/FTM1_CH3, direction: OUTPUT, gpio_init_state: 'false', drive_strength: low,
535 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
536 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
537 */
538 /* clang-format on */
539
540 /* FUNCTION ************************************************************************************************************
541 *
542 * Function Name : BOARD_InitACCELPins
543 * Description : Configures pin routing and optionally pin electrical features.
544 *
545 * END ****************************************************************************************************************/
BOARD_InitACCELPins(void)546 void BOARD_InitACCELPins(void)
547 {
548 /* Clock Control: Clock enabled */
549 CLOCK_EnableClock(kCLOCK_PortA);
550 /* Clock Control: Clock enabled */
551 CLOCK_EnableClock(kCLOCK_PortC);
552
553 gpio_pin_config_t ACCEL_I2C_RST_config = {
554 .pinDirection = kGPIO_DigitalOutput,
555 .outputLogic = 0U
556 };
557 /* Initialize GPIO functionality on pin PTC15 (pin 45) */
558 GPIO_PinInit(BOARD_ACCEL_I2C_RST_GPIO, BOARD_ACCEL_I2C_RST_PIN, &ACCEL_I2C_RST_config);
559 /* Configure digital filter */
560 PORT_EnablePinsDigitalFilter(
561 /* Digital filter is configured on port A */
562 PORTA,
563 /* Digital filter is configured for PORTA0 */
564 PORT_DFER_DFE_2_MASK
565 /* Digital filter is configured for PORTA1 */
566 | PORT_DFER_DFE_3_MASK,
567 /* Disable digital filter */
568 false);
569
570 const port_pin_config_t ACCEL_I2C_SDA = {/* Internal pull-up/down resistor is disabled */
571 kPORT_PullDisable,
572 /* Passive filter is disabled */
573 kPORT_PassiveFilterDisable,
574 /* Low drive strength is configured */
575 kPORT_LowDriveStrength,
576 /* Pin is configured as LPI2C0_SDA */
577 kPORT_MuxAlt3,
578 /* Pin Control Register fields [15:0] are not locked */
579 kPORT_UnlockRegister};
580 /* PORTA2 (pin 73) is configured as LPI2C0_SDA */
581 PORT_SetPinConfig(BOARD_ACCEL_I2C_SDA_PORT, BOARD_ACCEL_I2C_SDA_PIN, &ACCEL_I2C_SDA);
582
583 const port_pin_config_t ACCEL_I2C_SCL = {/* Internal pull-up/down resistor is disabled */
584 kPORT_PullDisable,
585 /* Passive filter is disabled */
586 kPORT_PassiveFilterDisable,
587 /* Low drive strength is configured */
588 kPORT_LowDriveStrength,
589 /* Pin is configured as LPI2C0_SCL */
590 kPORT_MuxAlt3,
591 /* Pin Control Register fields [15:0] are not locked */
592 kPORT_UnlockRegister};
593 /* PORTA3 (pin 72) is configured as LPI2C0_SCL */
594 PORT_SetPinConfig(BOARD_ACCEL_I2C_SCL_PORT, BOARD_ACCEL_I2C_SCL_PIN, &ACCEL_I2C_SCL);
595 /* Configure digital filter */
596 PORT_EnablePinsDigitalFilter(
597 /* Digital filter is configured on port C */
598 PORTC,
599 /* Digital filter is configured for PORTC0 */
600 PORT_DFER_DFE_15_MASK,
601 /* Disable digital filter */
602 false);
603
604 const port_pin_config_t ACCEL_I2C_RST = {/* Internal pull-up/down resistor is disabled */
605 kPORT_PullDisable,
606 /* Passive filter is disabled */
607 kPORT_PassiveFilterDisable,
608 /* Low drive strength is configured */
609 kPORT_LowDriveStrength,
610 /* Pin is configured as PTC15 */
611 kPORT_MuxAsGpio,
612 /* Pin Control Register fields [15:0] are not locked */
613 kPORT_UnlockRegister};
614 /* PORTC15 (pin 45) is configured as PTC15 */
615 PORT_SetPinConfig(BOARD_ACCEL_I2C_RST_PORT, BOARD_ACCEL_I2C_RST_PIN, &ACCEL_I2C_RST);
616 }
617
618 /* clang-format off */
619 /*
620 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
621 BOARD_InitTHERMISTORPins:
622 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
623 - pin_list:
624 - {pin_num: '79', peripheral: ADC0, signal: 'SE, 0', pin_signal: ADC0_SE0/ACMP0_IN0/PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3, drive_strength: low,
625 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
626 - {pin_num: '78', peripheral: ADC0, signal: 'SE, 1', pin_signal: ADC0_SE1/ACMP0_IN1/PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0, drive_strength: low,
627 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
628 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
629 */
630 /* clang-format on */
631
632 /* FUNCTION ************************************************************************************************************
633 *
634 * Function Name : BOARD_InitTHERMISTORPins
635 * Description : Configures pin routing and optionally pin electrical features.
636 *
637 * END ****************************************************************************************************************/
BOARD_InitTHERMISTORPins(void)638 void BOARD_InitTHERMISTORPins(void)
639 {
640 /* Clock Control: Clock enabled */
641 CLOCK_EnableClock(kCLOCK_PortA);
642 /* Configure digital filter */
643 PORT_EnablePinsDigitalFilter(
644 /* Digital filter is configured on port A */
645 PORTA,
646 /* Digital filter is configured for PORTA0 */
647 PORT_DFER_DFE_0_MASK
648 /* Digital filter is configured for PORTA1 */
649 | PORT_DFER_DFE_1_MASK,
650 /* Disable digital filter */
651 false);
652
653 const port_pin_config_t THER_A = {/* Internal pull-up/down resistor is disabled */
654 kPORT_PullDisable,
655 /* Passive filter is disabled */
656 kPORT_PassiveFilterDisable,
657 /* Low drive strength is configured */
658 kPORT_LowDriveStrength,
659 /* Pin is configured as ADC0_SE0 */
660 kPORT_PinDisabledOrAnalog,
661 /* Pin Control Register fields [15:0] are not locked */
662 kPORT_UnlockRegister};
663 /* PORTA0 (pin 79) is configured as ADC0_SE0 */
664 PORT_SetPinConfig(BOARD_THER_A_PORT, BOARD_THER_A_PIN, &THER_A);
665
666 const port_pin_config_t THER_B = {/* Internal pull-up/down resistor is disabled */
667 kPORT_PullDisable,
668 /* Passive filter is disabled */
669 kPORT_PassiveFilterDisable,
670 /* Low drive strength is configured */
671 kPORT_LowDriveStrength,
672 /* Pin is configured as ADC0_SE1 */
673 kPORT_PinDisabledOrAnalog,
674 /* Pin Control Register fields [15:0] are not locked */
675 kPORT_UnlockRegister};
676 /* PORTA1 (pin 78) is configured as ADC0_SE1 */
677 PORT_SetPinConfig(BOARD_THER_B_PORT, BOARD_THER_B_PIN, &THER_B);
678 }
679
680 /* clang-format off */
681 /*
682 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
683 BOARD_InitPOTPins:
684 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
685 - pin_list:
686 - {pin_num: '46', peripheral: ADC0, signal: 'SE, 12', pin_signal: ADC0_SE12/ACMP2_IN5/PTC14/FTM1_CH2, drive_strength: low, pull_select: down, pull_enable: disable,
687 passive_filter: disable, digital_filter: disable}
688 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
689 */
690 /* clang-format on */
691
692 /* FUNCTION ************************************************************************************************************
693 *
694 * Function Name : BOARD_InitPOTPins
695 * Description : Configures pin routing and optionally pin electrical features.
696 *
697 * END ****************************************************************************************************************/
BOARD_InitPOTPins(void)698 void BOARD_InitPOTPins(void)
699 {
700 /* Clock Control: Clock enabled */
701 CLOCK_EnableClock(kCLOCK_PortC);
702 /* Configure digital filter */
703 PORT_EnablePinsDigitalFilter(
704 /* Digital filter is configured on port C */
705 PORTC,
706 /* Digital filter is configured for PORTC0 */
707 PORT_DFER_DFE_14_MASK,
708 /* Disable digital filter */
709 false);
710
711 const port_pin_config_t POT_5K = {/* Internal pull-up/down resistor is disabled */
712 kPORT_PullDisable,
713 /* Passive filter is disabled */
714 kPORT_PassiveFilterDisable,
715 /* Low drive strength is configured */
716 kPORT_LowDriveStrength,
717 /* Pin is configured as ADC0_SE12 */
718 kPORT_PinDisabledOrAnalog,
719 /* Pin Control Register fields [15:0] are not locked */
720 kPORT_UnlockRegister};
721 /* PORTC14 (pin 46) is configured as ADC0_SE12 */
722 PORT_SetPinConfig(BOARD_POT_5K_PORT, BOARD_POT_5K_PIN, &POT_5K);
723 }
724
725 /* clang-format off */
726 /*
727 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
728 BOARD_InitIRPins:
729 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
730 - pin_list:
731 - {pin_num: '80', peripheral: LPUART1, signal: TX, pin_signal: ADC1_SE5/PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3, drive_strength: low, pull_select: down, pull_enable: disable,
732 passive_filter: disable, digital_filter: disable}
733 - {pin_num: '17', peripheral: CMP2, signal: 'IN, 3', pin_signal: ACMP2_IN3/PTE14/FTM0_FLT1/FTM2_FLT1, drive_strength: low, pull_select: down, pull_enable: disable,
734 passive_filter: disable, digital_filter: disable}
735 - {pin_num: '18', peripheral: CMP2, signal: OUT, pin_signal: PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/ACMP2_OUT, drive_strength: low, pull_select: down,
736 pull_enable: disable, passive_filter: disable, digital_filter: disable}
737 - {pin_num: '81', peripheral: LPUART1, signal: RX, pin_signal: ADC1_SE4/PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2, drive_strength: low, pull_select: down, pull_enable: disable,
738 passive_filter: disable, digital_filter: disable}
739 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
740 */
741 /* clang-format on */
742
743 /* FUNCTION ************************************************************************************************************
744 *
745 * Function Name : BOARD_InitIRPins
746 * Description : Configures pin routing and optionally pin electrical features.
747 *
748 * END ****************************************************************************************************************/
BOARD_InitIRPins(void)749 void BOARD_InitIRPins(void)
750 {
751 /* Clock Control: Clock enabled */
752 CLOCK_EnableClock(kCLOCK_PortC);
753 /* Clock Control: Clock enabled */
754 CLOCK_EnableClock(kCLOCK_PortE);
755 /* Configure digital filter */
756 PORT_EnablePinsDigitalFilter(
757 /* Digital filter is configured on port C */
758 PORTC,
759 /* Digital filter is configured for PORTC0 */
760 PORT_DFER_DFE_6_MASK
761 /* Digital filter is configured for PORTC1 */
762 | PORT_DFER_DFE_7_MASK,
763 /* Disable digital filter */
764 false);
765
766 const port_pin_config_t IRRX_UART = {/* Internal pull-up/down resistor is disabled */
767 kPORT_PullDisable,
768 /* Passive filter is disabled */
769 kPORT_PassiveFilterDisable,
770 /* Low drive strength is configured */
771 kPORT_LowDriveStrength,
772 /* Pin is configured as LPUART1_RX */
773 kPORT_MuxAlt2,
774 /* Pin Control Register fields [15:0] are not locked */
775 kPORT_UnlockRegister};
776 /* PORTC6 (pin 81) is configured as LPUART1_RX */
777 PORT_SetPinConfig(BOARD_IRRX_UART_PORT, BOARD_IRRX_UART_PIN, &IRRX_UART);
778
779 const port_pin_config_t IRTX = {/* Internal pull-up/down resistor is disabled */
780 kPORT_PullDisable,
781 /* Passive filter is disabled */
782 kPORT_PassiveFilterDisable,
783 /* Low drive strength is configured */
784 kPORT_LowDriveStrength,
785 /* Pin is configured as LPUART1_TX */
786 kPORT_MuxAlt2,
787 /* Pin Control Register fields [15:0] are not locked */
788 kPORT_UnlockRegister};
789 /* PORTC7 (pin 80) is configured as LPUART1_TX */
790 PORT_SetPinConfig(BOARD_IRTX_PORT, BOARD_IRTX_PIN, &IRTX);
791 /* Configure digital filter */
792 PORT_EnablePinsDigitalFilter(
793 /* Digital filter is configured on port E */
794 PORTE,
795 /* Digital filter is configured for PORTE0 */
796 PORT_DFER_DFE_3_MASK
797 /* Digital filter is configured for PORTE1 */
798 | PORT_DFER_DFE_14_MASK,
799 /* Disable digital filter */
800 false);
801
802 const port_pin_config_t IRRX_CMP_IN = {/* Internal pull-up/down resistor is disabled */
803 kPORT_PullDisable,
804 /* Passive filter is disabled */
805 kPORT_PassiveFilterDisable,
806 /* Low drive strength is configured */
807 kPORT_LowDriveStrength,
808 /* Pin is configured as ACMP2_IN3 */
809 kPORT_PinDisabledOrAnalog,
810 /* Pin Control Register fields [15:0] are not locked */
811 kPORT_UnlockRegister};
812 /* PORTE14 (pin 17) is configured as ACMP2_IN3 */
813 PORT_SetPinConfig(BOARD_IRRX_CMP_IN_PORT, BOARD_IRRX_CMP_IN_PIN, &IRRX_CMP_IN);
814
815 const port_pin_config_t IRRX_CMP_OUT = {/* Internal pull-up/down resistor is disabled */
816 kPORT_PullDisable,
817 /* Passive filter is disabled */
818 kPORT_PassiveFilterDisable,
819 /* Low drive strength is configured */
820 kPORT_LowDriveStrength,
821 /* Pin is configured as ACMP2_OUT */
822 kPORT_MuxAlt7,
823 /* Pin Control Register fields [15:0] are not locked */
824 kPORT_UnlockRegister};
825 /* PORTE3 (pin 18) is configured as ACMP2_OUT */
826 PORT_SetPinConfig(BOARD_IRRX_CMP_OUT_PORT, BOARD_IRRX_CMP_OUT_PIN, &IRRX_CMP_OUT);
827 }
828
829 /* clang-format off */
830 /*
831 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
832 BOARD_InitCANPins:
833 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
834 - pin_list:
835 - {pin_num: '8', peripheral: CAN0, signal: TX, pin_signal: PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN, drive_strength: low, pull_select: down, pull_enable: disable,
836 passive_filter: disable, digital_filter: disable}
837 - {pin_num: '9', peripheral: CAN0, signal: RX, pin_signal: PTE4/BUSOUT/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT_b, drive_strength: low, pull_select: down, pull_enable: disable,
838 passive_filter: disable, digital_filter: disable}
839 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
840 */
841 /* clang-format on */
842
843 /* FUNCTION ************************************************************************************************************
844 *
845 * Function Name : BOARD_InitCANPins
846 * Description : Configures pin routing and optionally pin electrical features.
847 *
848 * END ****************************************************************************************************************/
BOARD_InitCANPins(void)849 void BOARD_InitCANPins(void)
850 {
851 /* Clock Control: Clock enabled */
852 CLOCK_EnableClock(kCLOCK_PortE);
853 /* Configure digital filter */
854 PORT_EnablePinsDigitalFilter(
855 /* Digital filter is configured on port E */
856 PORTE,
857 /* Digital filter is configured for PORTE0 */
858 PORT_DFER_DFE_4_MASK
859 /* Digital filter is configured for PORTE1 */
860 | PORT_DFER_DFE_5_MASK,
861 /* Disable digital filter */
862 false);
863
864 const port_pin_config_t CAN0_RX = {/* Internal pull-up/down resistor is disabled */
865 kPORT_PullDisable,
866 /* Passive filter is disabled */
867 kPORT_PassiveFilterDisable,
868 /* Low drive strength is configured */
869 kPORT_LowDriveStrength,
870 /* Pin is configured as CAN0_RX */
871 kPORT_MuxAlt5,
872 /* Pin Control Register fields [15:0] are not locked */
873 kPORT_UnlockRegister};
874 /* PORTE4 (pin 9) is configured as CAN0_RX */
875 PORT_SetPinConfig(BOARD_CAN0_RX_PORT, BOARD_CAN0_RX_PIN, &CAN0_RX);
876
877 const port_pin_config_t CAN0_TX = {/* Internal pull-up/down resistor is disabled */
878 kPORT_PullDisable,
879 /* Passive filter is disabled */
880 kPORT_PassiveFilterDisable,
881 /* Low drive strength is configured */
882 kPORT_LowDriveStrength,
883 /* Pin is configured as CAN0_TX */
884 kPORT_MuxAlt5,
885 /* Pin Control Register fields [15:0] are not locked */
886 kPORT_UnlockRegister};
887 /* PORTE5 (pin 8) is configured as CAN0_TX */
888 PORT_SetPinConfig(BOARD_CAN0_TX_PORT, BOARD_CAN0_TX_PIN, &CAN0_TX);
889 }
890
891 /* clang-format off */
892 /*
893 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
894 BOARD_InitDEBUG_UARTPins:
895 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
896 - pin_list:
897 - {pin_num: '53', peripheral: LPUART0, signal: TX, pin_signal: ADC0_SE5/ADC1_SE15/PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0, drive_strength: low, pull_select: up, pull_enable: enable,
898 passive_filter: disable, digital_filter: disable}
899 - {pin_num: '54', peripheral: LPUART0, signal: RX, pin_signal: ADC0_SE4/ADC1_SE14/PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/PWT_IN3, drive_strength: low, pull_select: up,
900 pull_enable: enable, passive_filter: disable, digital_filter: disable}
901 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
902 */
903 /* clang-format on */
904
905 /* FUNCTION ************************************************************************************************************
906 *
907 * Function Name : BOARD_InitDEBUG_UARTPins
908 * Description : Configures pin routing and optionally pin electrical features.
909 *
910 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)911 void BOARD_InitDEBUG_UARTPins(void)
912 {
913 /* Clock Control: Clock enabled */
914 CLOCK_EnableClock(kCLOCK_PortB);
915 /* Configure digital filter */
916 PORT_EnablePinsDigitalFilter(
917 /* Digital filter is configured on port B */
918 PORTB,
919 /* Digital filter is configured for PORTB0 */
920 PORT_DFER_DFE_0_MASK
921 /* Digital filter is configured for PORTB1 */
922 | PORT_DFER_DFE_1_MASK,
923 /* Disable digital filter */
924 false);
925
926 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up resistor is enabled */
927 kPORT_PullUp,
928 /* Passive filter is disabled */
929 kPORT_PassiveFilterDisable,
930 /* Low drive strength is configured */
931 kPORT_LowDriveStrength,
932 /* Pin is configured as LPUART0_RX */
933 kPORT_MuxAlt2,
934 /* Pin Control Register fields [15:0] are not locked */
935 kPORT_UnlockRegister};
936 /* PORTB0 (pin 54) is configured as LPUART0_RX */
937 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
938
939 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up resistor is enabled */
940 kPORT_PullUp,
941 /* Passive filter is disabled */
942 kPORT_PassiveFilterDisable,
943 /* Low drive strength is configured */
944 kPORT_LowDriveStrength,
945 /* Pin is configured as LPUART0_TX */
946 kPORT_MuxAlt2,
947 /* Pin Control Register fields [15:0] are not locked */
948 kPORT_UnlockRegister};
949 /* PORTB1 (pin 53) is configured as LPUART0_TX */
950 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
951 }
952 /***********************************************************************************************************************
953 * EOF
954 **********************************************************************************************************************/
955
