1 /* 2 * Copyright 2017-2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*********************************************************************************************************************** 9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 **********************************************************************************************************************/ 12 13 #ifndef _PIN_MUX_H_ 14 #define _PIN_MUX_H_ 15 16 /*********************************************************************************************************************** 17 * Definitions 18 **********************************************************************************************************************/ 19 20 /*! @brief Direction type */ 21 typedef enum _pin_mux_direction 22 { 23 kPIN_MUX_DirectionInput = 0U, /* Input direction */ 24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */ 25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ 26 } pin_mux_direction_t; 27 28 /*! 29 * @addtogroup pin_mux 30 * @{ 31 */ 32 33 /*********************************************************************************************************************** 34 * API 35 **********************************************************************************************************************/ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 /*! 42 * @brief Calls initialization functions. 43 * 44 */ 45 void BOARD_InitBootPins(void); 46 47 /*! 48 * @brief Configures pin routing and optionally pin electrical features. 49 * 50 */ 51 void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ 52 53 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 54 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 55 #define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ 56 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 57 58 /*! @name PIO0_11 (number 10), CN6[10]/CN8[3]/D4/PIO0_11/M_PIO0_11 59 @{ */ 60 /* Routed pin properties */ 61 /*! 62 * @brief Peripheral name */ 63 #define BOARD_INITLEDSPINS_LED_BLUE_PERIPHERAL GPIO 64 /*! 65 * @brief Signal name */ 66 #define BOARD_INITLEDSPINS_LED_BLUE_SIGNAL PIO0 67 /*! 68 * @brief Signal channel */ 69 #define BOARD_INITLEDSPINS_LED_BLUE_CHANNEL 11 70 /*! 71 * @brief Routed pin name */ 72 #define BOARD_INITLEDSPINS_LED_BLUE_PIN_NAME PIO0_11 73 /*! 74 * @brief Label */ 75 #define BOARD_INITLEDSPINS_LED_BLUE_LABEL "CN6[10]/CN8[3]/D4/PIO0_11/M_PIO0_11" 76 /*! 77 * @brief Identifier */ 78 #define BOARD_INITLEDSPINS_LED_BLUE_NAME "LED_BLUE" 79 /*! 80 * @brief Direction */ 81 #define BOARD_INITLEDSPINS_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput 82 83 /* Symbols to be used with GPIO driver */ 84 /*! 85 * @brief GPIO peripheral base pointer */ 86 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO 87 /*! 88 * @brief GPIO pin number */ 89 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 11U 90 /*! 91 * @brief GPIO pin mask */ 92 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 11U) 93 /*! 94 * @brief PORT device index: 0 */ 95 #define BOARD_INITLEDSPINS_LED_BLUE_PORT 0U 96 /*! 97 * @brief PORT pin number */ 98 #define BOARD_INITLEDSPINS_LED_BLUE_PIN 11U 99 /*! 100 * @brief PORT pin mask */ 101 #define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 11U) 102 /* @} */ 103 104 /*! @name PIO0_12 (number 5), S2/CN8[6]/CN6[5]/D3/M_PIO0_12/PIO0_12 105 @{ */ 106 /* Routed pin properties */ 107 /*! 108 * @brief Peripheral name */ 109 #define BOARD_INITLEDSPINS_LED_GREEN_PERIPHERAL GPIO 110 /*! 111 * @brief Signal name */ 112 #define BOARD_INITLEDSPINS_LED_GREEN_SIGNAL PIO0 113 /*! 114 * @brief Signal channel */ 115 #define BOARD_INITLEDSPINS_LED_GREEN_CHANNEL 12 116 /*! 117 * @brief Routed pin name */ 118 #define BOARD_INITLEDSPINS_LED_GREEN_PIN_NAME PIO0_12 119 /*! 120 * @brief Label */ 121 #define BOARD_INITLEDSPINS_LED_GREEN_LABEL "S2/CN8[6]/CN6[5]/D3/M_PIO0_12/PIO0_12" 122 /*! 123 * @brief Identifier */ 124 #define BOARD_INITLEDSPINS_LED_GREEN_NAME "LED_GREEN" 125 /*! 126 * @brief Direction */ 127 #define BOARD_INITLEDSPINS_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput 128 129 /* Symbols to be used with GPIO driver */ 130 /*! 131 * @brief GPIO peripheral base pointer */ 132 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO 133 /*! 134 * @brief GPIO pin number */ 135 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 12U 136 /*! 137 * @brief GPIO pin mask */ 138 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 12U) 139 /*! 140 * @brief PORT device index: 0 */ 141 #define BOARD_INITLEDSPINS_LED_GREEN_PORT 0U 142 /*! 143 * @brief PORT pin number */ 144 #define BOARD_INITLEDSPINS_LED_GREEN_PIN 12U 145 /*! 146 * @brief PORT pin mask */ 147 #define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 12U) 148 /* @} */ 149 150 /*! @name PIO0_13 (number 4), S1/CN8[4]/CN6[4]/D2/M_PIO0_13/PIO0_13 151 @{ */ 152 /* Routed pin properties */ 153 /*! 154 * @brief Peripheral name */ 155 #define BOARD_INITLEDSPINS_LED_RED_PERIPHERAL GPIO 156 /*! 157 * @brief Signal name */ 158 #define BOARD_INITLEDSPINS_LED_RED_SIGNAL PIO0 159 /*! 160 * @brief Signal channel */ 161 #define BOARD_INITLEDSPINS_LED_RED_CHANNEL 13 162 /*! 163 * @brief Routed pin name */ 164 #define BOARD_INITLEDSPINS_LED_RED_PIN_NAME PIO0_13 165 /*! 166 * @brief Label */ 167 #define BOARD_INITLEDSPINS_LED_RED_LABEL "S1/CN8[4]/CN6[4]/D2/M_PIO0_13/PIO0_13" 168 /*! 169 * @brief Identifier */ 170 #define BOARD_INITLEDSPINS_LED_RED_NAME "LED_RED" 171 /*! 172 * @brief Direction */ 173 #define BOARD_INITLEDSPINS_LED_RED_DIRECTION kPIN_MUX_DirectionOutput 174 175 /* Symbols to be used with GPIO driver */ 176 /*! 177 * @brief GPIO peripheral base pointer */ 178 #define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO 179 /*! 180 * @brief GPIO pin number */ 181 #define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 13U 182 /*! 183 * @brief GPIO pin mask */ 184 #define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 13U) 185 /*! 186 * @brief PORT device index: 0 */ 187 #define BOARD_INITLEDSPINS_LED_RED_PORT 0U 188 /*! 189 * @brief PORT pin number */ 190 #define BOARD_INITLEDSPINS_LED_RED_PIN 13U 191 /*! 192 * @brief PORT pin mask */ 193 #define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 13U) 194 /* @} */ 195 196 /*! 197 * @brief Configures pin routing and optionally pin electrical features. 198 * 199 */ 200 void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M0P */ 201 202 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 203 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 204 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 205 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 206 207 /*! @name PIO0_0 (number 22), CN7[3]/CN8[8]/JP2/PIO0_0 208 @{ */ 209 /* Routed pin properties */ 210 /*! 211 * @brief Peripheral name */ 212 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PERIPHERAL USART0 213 /*! 214 * @brief Signal name */ 215 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_SIGNAL RXD 216 /*! 217 * @brief Routed pin name */ 218 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_NAME PIO0_0 219 /*! 220 * @brief Label */ 221 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_LABEL "CN7[3]/CN8[8]/JP2/PIO0_0" 222 /*! 223 * @brief Identifier */ 224 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_NAME "DEBUG_UART_RX" 225 /*! 226 * @brief PORT device index: 0 */ 227 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U 228 /*! 229 * @brief PORT pin number */ 230 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 0U 231 /*! 232 * @brief PORT pin mask */ 233 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 0U) 234 /* @} */ 235 236 /*! @name PIO0_4 (number 7), CN6[7]/CN8[7]/CN5[5]/JP24/PIO0_4 237 @{ */ 238 /* Routed pin properties */ 239 /*! 240 * @brief Peripheral name */ 241 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PERIPHERAL USART0 242 /*! 243 * @brief Signal name */ 244 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_SIGNAL TXD 245 /*! 246 * @brief Routed pin name */ 247 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_NAME PIO0_4 248 /*! 249 * @brief Label */ 250 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_LABEL "CN6[7]/CN8[7]/CN5[5]/JP24/PIO0_4" 251 /*! 252 * @brief Identifier */ 253 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_NAME "DEBUG_UART_TX" 254 /*! 255 * @brief PORT device index: 0 */ 256 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U 257 /*! 258 * @brief PORT pin number */ 259 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 4U 260 /*! 261 * @brief PORT pin mask */ 262 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 4U) 263 /* @} */ 264 265 /*! 266 * @brief Configures pin routing and optionally pin electrical features. 267 * 268 */ 269 void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M0P */ 270 271 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 272 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 273 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 274 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 275 276 /*! @name SWCLK (number 8), CN6[8]/CN1[4]/U1[16]/SWCLK_PIO0_3 277 @{ */ 278 /* Routed pin properties */ 279 /*! 280 * @brief Peripheral name */ 281 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PERIPHERAL SWD 282 /*! 283 * @brief Signal name */ 284 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_SIGNAL SWCLK 285 /*! 286 * @brief Routed pin name */ 287 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_NAME SWCLK 288 /*! 289 * @brief Label */ 290 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_LABEL "CN6[8]/CN1[4]/U1[16]/SWCLK_PIO0_3" 291 /*! 292 * @brief Identifier */ 293 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_NAME "DEBUG_SWD_SWDCLK" 294 /*! 295 * @brief PORT device index: 0 */ 296 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U 297 /*! 298 * @brief PORT pin number */ 299 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 3U 300 /*! 301 * @brief PORT pin mask */ 302 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 3U) 303 /* @} */ 304 305 /*! @name SWDIO (number 9), CN6[9]/CN1[2]/U1[17]/SWDIO_PIO0_2 306 @{ */ 307 /* Routed pin properties */ 308 /*! 309 * @brief Peripheral name */ 310 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PERIPHERAL SWD 311 /*! 312 * @brief Signal name */ 313 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_SIGNAL SWDIO 314 /*! 315 * @brief Routed pin name */ 316 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_NAME SWDIO 317 /*! 318 * @brief Label */ 319 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_LABEL "CN6[9]/CN1[2]/U1[17]/SWDIO_PIO0_2" 320 /*! 321 * @brief Identifier */ 322 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_NAME "DEBUG_SWD_SWDIO" 323 /*! 324 * @brief PORT device index: 0 */ 325 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U 326 /*! 327 * @brief PORT pin number */ 328 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 2U 329 /*! 330 * @brief PORT pin mask */ 331 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 2U) 332 /* @} */ 333 334 /*! @name RESETN (number 6), CN6[6]/CN1[10]/S3/CN4[3]/U1[3]/U1[8]/TRST_P0_5 335 @{ */ 336 /* Routed pin properties */ 337 /*! 338 * @brief Peripheral name */ 339 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PERIPHERAL SYSCON 340 /*! 341 * @brief Signal name */ 342 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_SIGNAL RESETN 343 /*! 344 * @brief Routed pin name */ 345 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN_NAME RESETN 346 /*! 347 * @brief Label */ 348 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_LABEL "CN6[6]/CN1[10]/S3/CN4[3]/U1[3]/U1[8]/TRST_P0_5" 349 /*! 350 * @brief Identifier */ 351 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_NAME "DEBUG_SWD_RESETN" 352 /*! 353 * @brief PORT device index: 0 */ 354 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PORT 0U 355 /*! 356 * @brief PORT pin number */ 357 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN 5U 358 /*! 359 * @brief PORT pin mask */ 360 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN_MASK (1U << 5U) 361 /* @} */ 362 363 /*! 364 * @brief Configures pin routing and optionally pin electrical features. 365 * 366 */ 367 void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M0P */ 368 369 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 370 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 371 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 372 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 373 374 /*! @name PIO0_14 (number 23), CN7[2]/CN3[1]/JP4/PIO0_14 375 @{ */ 376 /* Routed pin properties */ 377 #define BOARD_INITI2CPINS_I2C_SCL_PERIPHERAL I2C0 /*!<@brief Peripheral name */ 378 #define BOARD_INITI2CPINS_I2C_SCL_SIGNAL SCL /*!<@brief Signal name */ 379 #define BOARD_INITI2CPINS_I2C_SCL_PIN_NAME PIO0_14 /*!<@brief Routed pin name */ 380 #define BOARD_INITI2CPINS_I2C_SCL_LABEL "CN7[2]/CN3[1]/JP4/PIO0_14" /*!<@brief Label */ 381 #define BOARD_INITI2CPINS_I2C_SCL_NAME "I2C_SCL" /*!<@brief Identifier */ 382 #define BOARD_INITI2CPINS_I2C_SCL_PORT 0U /*!<@brief PORT device index: 0 */ 383 #define BOARD_INITI2CPINS_I2C_SCL_PIN 14U /*!<@brief PORT pin number */ 384 #define BOARD_INITI2CPINS_I2C_SCL_PIN_MASK (1U << 14U) /*!<@brief PORT pin mask */ 385 /* @} */ 386 387 /*! @name PIO0_7 (number 20), CN7[5]/CN3[2]/JP23/CN5[4]/PIO0_7 388 @{ */ 389 /* Routed pin properties */ 390 /*! 391 * @brief Peripheral name */ 392 #define BOARD_INITI2CPINS_I2C_SDA_PERIPHERAL I2C0 393 /*! 394 * @brief Signal name */ 395 #define BOARD_INITI2CPINS_I2C_SDA_SIGNAL SDA 396 /*! 397 * @brief Routed pin name */ 398 #define BOARD_INITI2CPINS_I2C_SDA_PIN_NAME PIO0_7 399 /*! 400 * @brief Label */ 401 #define BOARD_INITI2CPINS_I2C_SDA_LABEL "CN7[5]/CN3[2]/JP23/CN5[4]/PIO0_7" 402 /*! 403 * @brief Identifier */ 404 #define BOARD_INITI2CPINS_I2C_SDA_NAME "I2C_SDA" 405 /*! 406 * @brief PORT device index: 0 */ 407 #define BOARD_INITI2CPINS_I2C_SDA_PORT 0U 408 /*! 409 * @brief PORT pin number */ 410 #define BOARD_INITI2CPINS_I2C_SDA_PIN 7U 411 /*! 412 * @brief PORT pin mask */ 413 #define BOARD_INITI2CPINS_I2C_SDA_PIN_MASK (1U << 7U) 414 /* @} */ 415 416 /*! 417 * @brief Configures pin routing and optionally pin electrical features. 418 * 419 */ 420 void BOARD_InitI2CPins(void); /* Function assigned for the Cortex-M0P */ 421 422 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 423 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 424 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 425 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 426 427 /*! @name PIO0_13 (number 4), S1/CN8[4]/CN6[4]/D2/M_PIO0_13/PIO0_13 428 @{ */ 429 /* Routed pin properties */ 430 /*! 431 * @brief Peripheral name */ 432 #define BOARD_INITBUTTONSPINS_S1_PERIPHERAL GPIO 433 /*! 434 * @brief Signal name */ 435 #define BOARD_INITBUTTONSPINS_S1_SIGNAL PIO0 436 /*! 437 * @brief Signal channel */ 438 #define BOARD_INITBUTTONSPINS_S1_CHANNEL 13 439 /*! 440 * @brief Routed pin name */ 441 #define BOARD_INITBUTTONSPINS_S1_PIN_NAME PIO0_13 442 /*! 443 * @brief Label */ 444 #define BOARD_INITBUTTONSPINS_S1_LABEL "S1/CN8[4]/CN6[4]/D2/M_PIO0_13/PIO0_13" 445 /*! 446 * @brief Identifier */ 447 #define BOARD_INITBUTTONSPINS_S1_NAME "S1" 448 /*! 449 * @brief Direction */ 450 #define BOARD_INITBUTTONSPINS_S1_DIRECTION kPIN_MUX_DirectionInput 451 452 /* Symbols to be used with GPIO driver */ 453 /*! 454 * @brief GPIO peripheral base pointer */ 455 #define BOARD_INITBUTTONSPINS_S1_GPIO GPIO 456 /*! 457 * @brief GPIO pin number */ 458 #define BOARD_INITBUTTONSPINS_S1_GPIO_PIN 13U 459 /*! 460 * @brief GPIO pin mask */ 461 #define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 13U) 462 /*! 463 * @brief PORT device index: 0 */ 464 #define BOARD_INITBUTTONSPINS_S1_PORT 0U 465 /*! 466 * @brief PORT pin number */ 467 #define BOARD_INITBUTTONSPINS_S1_PIN 13U 468 /*! 469 * @brief PORT pin mask */ 470 #define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 13U) 471 /* @} */ 472 473 /*! @name PIO0_12 (number 5), S2/CN8[6]/CN6[5]/D3/M_PIO0_12/PIO0_12 474 @{ */ 475 /* Routed pin properties */ 476 /*! 477 * @brief Peripheral name */ 478 #define BOARD_INITBUTTONSPINS_S2_PERIPHERAL GPIO 479 /*! 480 * @brief Signal name */ 481 #define BOARD_INITBUTTONSPINS_S2_SIGNAL PIO0 482 /*! 483 * @brief Signal channel */ 484 #define BOARD_INITBUTTONSPINS_S2_CHANNEL 12 485 /*! 486 * @brief Routed pin name */ 487 #define BOARD_INITBUTTONSPINS_S2_PIN_NAME PIO0_12 488 /*! 489 * @brief Label */ 490 #define BOARD_INITBUTTONSPINS_S2_LABEL "S2/CN8[6]/CN6[5]/D3/M_PIO0_12/PIO0_12" 491 /*! 492 * @brief Identifier */ 493 #define BOARD_INITBUTTONSPINS_S2_NAME "S2" 494 /*! 495 * @brief Direction */ 496 #define BOARD_INITBUTTONSPINS_S2_DIRECTION kPIN_MUX_DirectionInput 497 498 /* Symbols to be used with GPIO driver */ 499 /*! 500 * @brief GPIO peripheral base pointer */ 501 #define BOARD_INITBUTTONSPINS_S2_GPIO GPIO 502 /*! 503 * @brief GPIO pin number */ 504 #define BOARD_INITBUTTONSPINS_S2_GPIO_PIN 12U 505 /*! 506 * @brief GPIO pin mask */ 507 #define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 12U) 508 /*! 509 * @brief PORT device index: 0 */ 510 #define BOARD_INITBUTTONSPINS_S2_PORT 0U 511 /*! 512 * @brief PORT pin number */ 513 #define BOARD_INITBUTTONSPINS_S2_PIN 12U 514 /*! 515 * @brief PORT pin mask */ 516 #define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 12U) 517 /* @} */ 518 519 /*! 520 * @brief Configures pin routing and optionally pin electrical features. 521 * 522 */ 523 void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M0P */ 524 525 #if defined(__cplusplus) 526 } 527 #endif 528 529 /*! 530 * @} 531 */ 532 #endif /* _PIN_MUX_H_ */ 533 534 /*********************************************************************************************************************** 535 * EOF 536 **********************************************************************************************************************/ 537
