1 /* 2 * Copyright 2017-2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*********************************************************************************************************************** 9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 **********************************************************************************************************************/ 12 13 #ifndef _PIN_MUX_H_ 14 #define _PIN_MUX_H_ 15 16 /*********************************************************************************************************************** 17 * Definitions 18 **********************************************************************************************************************/ 19 20 /*! @brief Direction type */ 21 typedef enum _pin_mux_direction 22 { 23 kPIN_MUX_DirectionInput = 0U, /* Input direction */ 24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */ 25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ 26 } pin_mux_direction_t; 27 28 /*! 29 * @addtogroup pin_mux 30 * @{ 31 */ 32 33 /*********************************************************************************************************************** 34 * API 35 **********************************************************************************************************************/ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 /*! 42 * @brief Calls initialization functions. 43 * 44 */ 45 void BOARD_InitBootPins(void); 46 47 /*! 48 * @brief Configures pin routing and optionally pin electrical features. 49 * 50 */ 51 void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ 52 53 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 54 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 55 #define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ 56 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 57 58 /*! @name PIO0_8 (number 14), CN5[7]/CN3[25]/CN6[4]/LD19/LD20/LD4/PB3/PIO0_8_RXD_User_GPIO2_LED1 59 @{ */ 60 /* Routed pin properties */ 61 /*! 62 * @brief Peripheral name */ 63 #define BOARD_INITLEDSPINS_LED_BLUE_PERIPHERAL GPIO 64 /*! 65 * @brief Signal name */ 66 #define BOARD_INITLEDSPINS_LED_BLUE_SIGNAL PIO0 67 /*! 68 * @brief Signal channel */ 69 #define BOARD_INITLEDSPINS_LED_BLUE_CHANNEL 8 70 /*! 71 * @brief Routed pin name */ 72 #define BOARD_INITLEDSPINS_LED_BLUE_PIN_NAME PIO0_8 73 /*! 74 * @brief Label */ 75 #define BOARD_INITLEDSPINS_LED_BLUE_LABEL "CN5[7]/CN3[25]/CN6[4]/LD19/LD20/LD4/PB3/PIO0_8_RXD_User_GPIO2_LED1" 76 /*! 77 * @brief Identifier */ 78 #define BOARD_INITLEDSPINS_LED_BLUE_NAME "LED_BLUE" 79 /*! 80 * @brief Direction */ 81 #define BOARD_INITLEDSPINS_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput 82 83 /* Symbols to be used with GPIO driver */ 84 /*! 85 * @brief GPIO peripheral base pointer */ 86 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO 87 /*! 88 * @brief GPIO pin number */ 89 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 8U 90 /*! 91 * @brief GPIO pin mask */ 92 #define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 8U) 93 /*! 94 * @brief PORT device index: 0 */ 95 #define BOARD_INITLEDSPINS_LED_BLUE_PORT 0U 96 /*! 97 * @brief PORT pin number */ 98 #define BOARD_INITLEDSPINS_LED_BLUE_PIN 8U 99 /*! 100 * @brief PORT pin mask */ 101 #define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 8U) 102 /* @} */ 103 104 /*! @name PIO0_9 (number 13), CN5[8]/CN6[1]/CN3[28]/LD21/LD22/LD5/PIO0_9_TXD_GPIO1_LED2 105 @{ */ 106 /* Routed pin properties */ 107 /*! 108 * @brief Peripheral name */ 109 #define BOARD_INITLEDSPINS_LED_RED_PERIPHERAL GPIO 110 /*! 111 * @brief Signal name */ 112 #define BOARD_INITLEDSPINS_LED_RED_SIGNAL PIO0 113 /*! 114 * @brief Signal channel */ 115 #define BOARD_INITLEDSPINS_LED_RED_CHANNEL 9 116 /*! 117 * @brief Routed pin name */ 118 #define BOARD_INITLEDSPINS_LED_RED_PIN_NAME PIO0_9 119 /*! 120 * @brief Label */ 121 #define BOARD_INITLEDSPINS_LED_RED_LABEL "CN5[8]/CN6[1]/CN3[28]/LD21/LD22/LD5/PIO0_9_TXD_GPIO1_LED2" 122 /*! 123 * @brief Identifier */ 124 #define BOARD_INITLEDSPINS_LED_RED_NAME "LED_RED" 125 /*! 126 * @brief Direction */ 127 #define BOARD_INITLEDSPINS_LED_RED_DIRECTION kPIN_MUX_DirectionOutput 128 129 /* Symbols to be used with GPIO driver */ 130 /*! 131 * @brief GPIO peripheral base pointer */ 132 #define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO 133 /*! 134 * @brief GPIO pin number */ 135 #define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 9U 136 /*! 137 * @brief GPIO pin mask */ 138 #define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 9U) 139 /*! 140 * @brief PORT device index: 0 */ 141 #define BOARD_INITLEDSPINS_LED_RED_PORT 0U 142 /*! 143 * @brief PORT pin number */ 144 #define BOARD_INITLEDSPINS_LED_RED_PIN 9U 145 /*! 146 * @brief PORT pin mask */ 147 #define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 9U) 148 /* @} */ 149 150 /*! @name PIO0_12 (number 4), CN4[4]/CN3[26]/CN3[24]/CN6[3]/CN9[1]/LD23/LD24/LD6/PB1/PIO0_12_ISP_GPIO0_LED3 151 @{ */ 152 /* Routed pin properties */ 153 /*! 154 * @brief Peripheral name */ 155 #define BOARD_INITLEDSPINS_LED_GREEN_PERIPHERAL GPIO 156 /*! 157 * @brief Signal name */ 158 #define BOARD_INITLEDSPINS_LED_GREEN_SIGNAL PIO0 159 /*! 160 * @brief Signal channel */ 161 #define BOARD_INITLEDSPINS_LED_GREEN_CHANNEL 12 162 /*! 163 * @brief Routed pin name */ 164 #define BOARD_INITLEDSPINS_LED_GREEN_PIN_NAME PIO0_12 165 /*! 166 * @brief Label */ 167 #define BOARD_INITLEDSPINS_LED_GREEN_LABEL "CN4[4]/CN3[26]/CN3[24]/CN6[3]/CN9[1]/LD23/LD24/LD6/PB1/PIO0_12_ISP_GPIO0_LED3" 168 /*! 169 * @brief Identifier */ 170 #define BOARD_INITLEDSPINS_LED_GREEN_NAME "LED_GREEN" 171 /*! 172 * @brief Direction */ 173 #define BOARD_INITLEDSPINS_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput 174 175 /* Symbols to be used with GPIO driver */ 176 /*! 177 * @brief GPIO peripheral base pointer */ 178 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO 179 /*! 180 * @brief GPIO pin number */ 181 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 12U 182 /*! 183 * @brief GPIO pin mask */ 184 #define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 12U) 185 /*! 186 * @brief PORT device index: 0 */ 187 #define BOARD_INITLEDSPINS_LED_GREEN_PORT 0U 188 /*! 189 * @brief PORT pin number */ 190 #define BOARD_INITLEDSPINS_LED_GREEN_PIN 12U 191 /*! 192 * @brief PORT pin mask */ 193 #define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 12U) 194 /* @} */ 195 196 /*! 197 * @brief Configures pin routing and optionally pin electrical features. 198 * 199 */ 200 void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M0P */ 201 202 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 203 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 204 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 205 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 206 207 /*! @name PIO0_4 (number 6), CN4[6]/CN3[32]/PIO0_4_TXD_SCK 208 @{ */ 209 /* Routed pin properties */ 210 /*! 211 * @brief Peripheral name */ 212 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PERIPHERAL USART0 213 /*! 214 * @brief Signal name */ 215 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_SIGNAL TXD 216 /*! 217 * @brief Routed pin name */ 218 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_NAME PIO0_4 219 /*! 220 * @brief Label */ 221 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_LABEL "CN4[6]/CN3[32]/PIO0_4_TXD_SCK" 222 /*! 223 * @brief Identifier */ 224 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_NAME "DEBUG_UART_TX" 225 /*! 226 * @brief PORT device index: 0 */ 227 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U 228 /*! 229 * @brief PORT pin number */ 230 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 4U 231 /*! 232 * @brief PORT pin mask */ 233 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 4U) 234 /* @} */ 235 236 /*! @name PIO0_0 (number 19), CN5[2]/CN3[31]/PIO0_0_RXD 237 @{ */ 238 /* Routed pin properties */ 239 /*! 240 * @brief Peripheral name */ 241 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PERIPHERAL USART0 242 /*! 243 * @brief Signal name */ 244 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_SIGNAL RXD 245 /*! 246 * @brief Routed pin name */ 247 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_NAME PIO0_0 248 /*! 249 * @brief Label */ 250 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_LABEL "CN5[2]/CN3[31]/PIO0_0_RXD" 251 /*! 252 * @brief Identifier */ 253 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_NAME "DEBUG_UART_RX" 254 /*! 255 * @brief PORT device index: 0 */ 256 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U 257 /*! 258 * @brief PORT pin number */ 259 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 0U 260 /*! 261 * @brief PORT pin mask */ 262 #define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 0U) 263 /* @} */ 264 265 /*! 266 * @brief Configures pin routing and optionally pin electrical features. 267 * 268 */ 269 void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M0P */ 270 271 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 272 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 273 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 274 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 275 276 /*! @name SWCLK (number 7), CN2[4]/CN4[7]/U3[16]/PIO0_3_SWCLK 277 @{ */ 278 /* Routed pin properties */ 279 /*! 280 * @brief Peripheral name */ 281 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_PERIPHERAL SWD 282 /*! 283 * @brief Signal name */ 284 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_SIGNAL SWCLK 285 /*! 286 * @brief Routed pin name */ 287 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_PIN_NAME SWCLK 288 /*! 289 * @brief Label */ 290 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_LABEL "CN2[4]/CN4[7]/U3[16]/PIO0_3_SWCLK" 291 /*! 292 * @brief Identifier */ 293 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_NAME "DEBUG_SWD_SWCLK" 294 /*! 295 * @brief PORT device index: 0 */ 296 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_PORT 0U 297 /*! 298 * @brief PORT pin number */ 299 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_PIN 3U 300 /*! 301 * @brief PORT pin mask */ 302 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWCLK_PIN_MASK (1U << 3U) 303 /* @} */ 304 305 /*! @name SWDIO (number 8), CN2[2]/CN4[8]/U3[17]/PIO0_2_SWDIO 306 @{ */ 307 /* Routed pin properties */ 308 /*! 309 * @brief Peripheral name */ 310 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PERIPHERAL SWD 311 /*! 312 * @brief Signal name */ 313 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_SIGNAL SWDIO 314 /*! 315 * @brief Routed pin name */ 316 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_NAME SWDIO 317 /*! 318 * @brief Label */ 319 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_LABEL "CN2[2]/CN4[8]/U3[17]/PIO0_2_SWDIO" 320 /*! 321 * @brief Identifier */ 322 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_NAME "DEBUG_SWD_SWDIO" 323 /*! 324 * @brief PORT device index: 0 */ 325 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U 326 /*! 327 * @brief PORT pin number */ 328 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 2U 329 /*! 330 * @brief PORT pin mask */ 331 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 2U) 332 /* @} */ 333 334 /*! @name RESETN (number 5), CN4[5]/CN2[10]/CN3[3]/U3[3]/U3[8]/PB2/PIO0_5_nRST 335 @{ */ 336 /* Routed pin properties */ 337 /*! 338 * @brief Peripheral name */ 339 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PERIPHERAL SYSCON 340 /*! 341 * @brief Signal name */ 342 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_SIGNAL RESETN 343 /*! 344 * @brief Routed pin name */ 345 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN_NAME RESETN 346 /*! 347 * @brief Label */ 348 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_LABEL "CN4[5]/CN2[10]/CN3[3]/U3[3]/U3[8]/PB2/PIO0_5_nRST" 349 /*! 350 * @brief Identifier */ 351 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_NAME "DEBUG_SWD_RESETN" 352 /*! 353 * @brief PORT device index: 0 */ 354 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PORT 0U 355 /*! 356 * @brief PORT pin number */ 357 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN 5U 358 /*! 359 * @brief PORT pin mask */ 360 #define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_RESETN_PIN_MASK (1U << 5U) 361 /* @} */ 362 363 /*! 364 * @brief Configures pin routing and optionally pin electrical features. 365 * 366 */ 367 void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M0P */ 368 369 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 370 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 371 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 372 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 373 374 /*! @name PIO0_16 (number 1), CN4[1]/CN3[15]/CN7[1]/U7[2]/PIO0_16_SCL 375 @{ */ 376 /* Routed pin properties */ 377 /*! 378 * @brief Peripheral name */ 379 #define BOARD_INITI2CPINS_I2C_SCL_PERIPHERAL I2C0 380 /*! 381 * @brief Signal name */ 382 #define BOARD_INITI2CPINS_I2C_SCL_SIGNAL SCL 383 /*! 384 * @brief Routed pin name */ 385 #define BOARD_INITI2CPINS_I2C_SCL_PIN_NAME PIO0_16 386 /*! 387 * @brief Label */ 388 #define BOARD_INITI2CPINS_I2C_SCL_LABEL "CN4[1]/CN3[15]/CN7[1]/U7[2]/PIO0_16_SCL" 389 /*! 390 * @brief Identifier */ 391 #define BOARD_INITI2CPINS_I2C_SCL_NAME "I2C_SCL" 392 /*! 393 * @brief PORT device index: 0 */ 394 #define BOARD_INITI2CPINS_I2C_SCL_PORT 0U 395 /*! 396 * @brief PORT pin number */ 397 #define BOARD_INITI2CPINS_I2C_SCL_PIN 16U 398 /*! 399 * @brief PORT pin mask */ 400 #define BOARD_INITI2CPINS_I2C_SCL_PIN_MASK (1U << 16U) 401 /* @} */ 402 403 /*! @name PIO0_10 (number 10), CN4[10]/CN3[16]/CN7[2]/U7[1]/PIO0_10_SDA 404 @{ */ 405 /* Routed pin properties */ 406 /*! 407 * @brief Peripheral name */ 408 #define BOARD_INITI2CPINS_I2C_SDA_PERIPHERAL I2C0 409 /*! 410 * @brief Signal name */ 411 #define BOARD_INITI2CPINS_I2C_SDA_SIGNAL SDA 412 /*! 413 * @brief Routed pin name */ 414 #define BOARD_INITI2CPINS_I2C_SDA_PIN_NAME PIO0_10 415 /*! 416 * @brief Label */ 417 #define BOARD_INITI2CPINS_I2C_SDA_LABEL "CN4[10]/CN3[16]/CN7[2]/U7[1]/PIO0_10_SDA" 418 /*! 419 * @brief Identifier */ 420 #define BOARD_INITI2CPINS_I2C_SDA_NAME "I2C_SDA" 421 /*! 422 * @brief PORT device index: 0 */ 423 #define BOARD_INITI2CPINS_I2C_SDA_PORT 0U 424 /*! 425 * @brief PORT pin number */ 426 #define BOARD_INITI2CPINS_I2C_SDA_PIN 10U 427 /*! 428 * @brief PORT pin mask */ 429 #define BOARD_INITI2CPINS_I2C_SDA_PIN_MASK (1U << 10U) 430 /* @} */ 431 432 /*! 433 * @brief Configures pin routing and optionally pin electrical features. 434 * 435 */ 436 void BOARD_InitI2CPins(void); /* Function assigned for the Cortex-M0P */ 437 438 #define IOCON_PIO_HYS_EN 0x20u /*!<@brief Enable hysteresis */ 439 #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input not invert */ 440 #define IOCON_PIO_MODE_PULLUP 0x10u /*!<@brief Selects pull-up function */ 441 #define IOCON_PIO_OD_DI 0x00u /*!<@brief Disables Open-drain function */ 442 443 /*! @name PIO0_8 (number 14), CN5[7]/CN3[25]/CN6[4]/LD19/LD20/LD4/PB3/PIO0_8_RXD_User_GPIO2_LED1 444 @{ */ 445 /* Routed pin properties */ 446 /*! 447 * @brief Peripheral name */ 448 #define BOARD_INITBUTTONSPINS_User_PB3_PERIPHERAL GPIO 449 /*! 450 * @brief Signal name */ 451 #define BOARD_INITBUTTONSPINS_User_PB3_SIGNAL PIO0 452 /*! 453 * @brief Signal channel */ 454 #define BOARD_INITBUTTONSPINS_User_PB3_CHANNEL 8 455 /*! 456 * @brief Routed pin name */ 457 #define BOARD_INITBUTTONSPINS_User_PB3_PIN_NAME PIO0_8 458 /*! 459 * @brief Label */ 460 #define BOARD_INITBUTTONSPINS_User_PB3_LABEL "CN5[7]/CN3[25]/CN6[4]/LD19/LD20/LD4/PB3/PIO0_8_RXD_User_GPIO2_LED1" 461 /*! 462 * @brief Identifier */ 463 #define BOARD_INITBUTTONSPINS_User_PB3_NAME "User_PB3" 464 /*! 465 * @brief Direction */ 466 #define BOARD_INITBUTTONSPINS_User_PB3_DIRECTION kPIN_MUX_DirectionInput 467 468 /* Symbols to be used with GPIO driver */ 469 /*! 470 * @brief GPIO peripheral base pointer */ 471 #define BOARD_INITBUTTONSPINS_User_PB3_GPIO GPIO 472 /*! 473 * @brief GPIO pin number */ 474 #define BOARD_INITBUTTONSPINS_User_PB3_GPIO_PIN 8U 475 /*! 476 * @brief GPIO pin mask */ 477 #define BOARD_INITBUTTONSPINS_User_PB3_GPIO_PIN_MASK (1U << 8U) 478 /*! 479 * @brief PORT device index: 0 */ 480 #define BOARD_INITBUTTONSPINS_User_PB3_PORT 0U 481 /*! 482 * @brief PORT pin number */ 483 #define BOARD_INITBUTTONSPINS_User_PB3_PIN 8U 484 /*! 485 * @brief PORT pin mask */ 486 #define BOARD_INITBUTTONSPINS_User_PB3_PIN_MASK (1U << 8U) 487 /* @} */ 488 489 /*! @name PIO0_12 (number 4), CN4[4]/CN3[26]/CN3[24]/CN6[3]/CN9[1]/LD23/LD24/LD6/PB1/PIO0_12_ISP_GPIO0_LED3 490 @{ */ 491 /* Routed pin properties */ 492 /*! 493 * @brief Peripheral name */ 494 #define BOARD_INITBUTTONSPINS_ISP_PB1_PERIPHERAL GPIO 495 /*! 496 * @brief Signal name */ 497 #define BOARD_INITBUTTONSPINS_ISP_PB1_SIGNAL PIO0 498 /*! 499 * @brief Signal channel */ 500 #define BOARD_INITBUTTONSPINS_ISP_PB1_CHANNEL 12 501 /*! 502 * @brief Routed pin name */ 503 #define BOARD_INITBUTTONSPINS_ISP_PB1_PIN_NAME PIO0_12 504 /*! 505 * @brief Label */ 506 #define BOARD_INITBUTTONSPINS_ISP_PB1_LABEL "CN4[4]/CN3[26]/CN3[24]/CN6[3]/CN9[1]/LD23/LD24/LD6/PB1/PIO0_12_ISP_GPIO0_LED3" 507 /*! 508 * @brief Identifier */ 509 #define BOARD_INITBUTTONSPINS_ISP_PB1_NAME "ISP_PB1" 510 /*! 511 * @brief Direction */ 512 #define BOARD_INITBUTTONSPINS_ISP_PB1_DIRECTION kPIN_MUX_DirectionInput 513 514 /* Symbols to be used with GPIO driver */ 515 /*! 516 * @brief GPIO peripheral base pointer */ 517 #define BOARD_INITBUTTONSPINS_ISP_PB1_GPIO GPIO 518 /*! 519 * @brief GPIO pin number */ 520 #define BOARD_INITBUTTONSPINS_ISP_PB1_GPIO_PIN 12U 521 /*! 522 * @brief GPIO pin mask */ 523 #define BOARD_INITBUTTONSPINS_ISP_PB1_GPIO_PIN_MASK (1U << 12U) 524 /*! 525 * @brief PORT device index: 0 */ 526 #define BOARD_INITBUTTONSPINS_ISP_PB1_PORT 0U 527 /*! 528 * @brief PORT pin number */ 529 #define BOARD_INITBUTTONSPINS_ISP_PB1_PIN 12U 530 /*! 531 * @brief PORT pin mask */ 532 #define BOARD_INITBUTTONSPINS_ISP_PB1_PIN_MASK (1U << 12U) 533 /* @} */ 534 535 /*! 536 * @brief Configures pin routing and optionally pin electrical features. 537 * 538 */ 539 void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M0P */ 540 541 #if defined(__cplusplus) 542 } 543 #endif 544 545 /*! 546 * @} 547 */ 548 #endif /* _PIN_MUX_H_ */ 549 550 /*********************************************************************************************************************** 551 * EOF 552 **********************************************************************************************************************/ 553
