1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /*
10 * How to set up clock using clock driver functions:
11 *
12 * 1. Setup clock sources.
13 *
14 * 2. Setup voltage for the fastest of the clock outputs
15 *
16 * 3. Set up wait states of the flash.
17 *
18 * 4. Set up all dividers.
19 *
20 * 5. Set up all selectors to provide selected clocks.
21 */
22
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v5.0
26 processor: LPC54S018J4M
27 package_id: LPC54S018J4MET180
28 mcu_data: ksdk2_0
29 processor_version: 0.0.0
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32 #include "fsl_power.h"
33 #include "fsl_clock.h"
34 #include "clock_config.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43 /* System clock frequency. */
44 extern uint32_t SystemCoreClock;
45
46 /*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
BOARD_InitBootClocks(void)49 void BOARD_InitBootClocks(void)
50 {
51 BOARD_BootClockPLL180M();
52 }
53
54 /*******************************************************************************
55 ******************** Configuration BOARD_BootClockFRO12M **********************
56 ******************************************************************************/
57 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58 !!Configuration
59 name: BOARD_BootClockFRO12M
60 outputs:
61 - {id: FRO12M_clock.outFreq, value: 12 MHz}
62 - {id: FROHF_clock.outFreq, value: 48 MHz}
63 - {id: MAIN_clock.outFreq, value: 12 MHz}
64 - {id: System_clock.outFreq, value: 12 MHz}
65 settings:
66 - {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
67 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
68
69 /*******************************************************************************
70 * Variables for BOARD_BootClockFRO12M configuration
71 ******************************************************************************/
72 /*******************************************************************************
73 * Code for BOARD_BootClockFRO12M configuration
74 ******************************************************************************/
BOARD_BootClockFRO12M(void)75 void BOARD_BootClockFRO12M(void)
76 {
77 /*!< Set up the clock sources */
78 /*!< Set up FRO */
79 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
80 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
81 accidentally being below the voltage for current speed */
82 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
83 before calling this API since this API is implemented in ROM code */
84 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
85 POWER_SetVoltageForFreq(
86 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
87
88 /*!< Set up dividers */
89 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
90
91 /*!< Set up clock selectors - Attach clocks to the peripheries */
92 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
93 /* Set SystemCoreClock variable. */
94 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
95 }
96
97 /*******************************************************************************
98 ******************* Configuration BOARD_BootClockFROHF48M *********************
99 ******************************************************************************/
100 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
101 !!Configuration
102 name: BOARD_BootClockFROHF48M
103 outputs:
104 - {id: FRO12M_clock.outFreq, value: 12 MHz}
105 - {id: FROHF_clock.outFreq, value: 48 MHz}
106 - {id: MAIN_clock.outFreq, value: 48 MHz}
107 - {id: System_clock.outFreq, value: 48 MHz}
108 settings:
109 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
110 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
111
112 /*******************************************************************************
113 * Variables for BOARD_BootClockFROHF48M configuration
114 ******************************************************************************/
115 /*******************************************************************************
116 * Code for BOARD_BootClockFROHF48M configuration
117 ******************************************************************************/
BOARD_BootClockFROHF48M(void)118 void BOARD_BootClockFROHF48M(void)
119 {
120 /*!< Set up the clock sources */
121 /*!< Set up FRO */
122 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
123 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
124 accidentally being below the voltage for current speed */
125 POWER_SetVoltageForFreq(
126 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
127 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
128 before calling this API since this API is implemented in ROM code */
129 CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
130
131 /*!< Set up dividers */
132 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
133
134 /*!< Set up clock selectors - Attach clocks to the peripheries */
135 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
136 /* Set SystemCoreClock variable. */
137 SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
138 }
139
140 /*******************************************************************************
141 ******************* Configuration BOARD_BootClockFROHF96M *********************
142 ******************************************************************************/
143 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
144 !!Configuration
145 name: BOARD_BootClockFROHF96M
146 called_from_default_init: true
147 outputs:
148 - {id: FRO12M_clock.outFreq, value: 12 MHz}
149 - {id: FROHF_clock.outFreq, value: 96 MHz}
150 - {id: MAIN_clock.outFreq, value: 96 MHz}
151 - {id: System_clock.outFreq, value: 96 MHz}
152 settings:
153 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
154 sources:
155 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
156 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
157
158 /*******************************************************************************
159 * Variables for BOARD_BootClockFROHF96M configuration
160 ******************************************************************************/
161 /*******************************************************************************
162 * Code for BOARD_BootClockFROHF96M configuration
163 ******************************************************************************/
BOARD_BootClockFROHF96M(void)164 void BOARD_BootClockFROHF96M(void)
165 {
166 /*!< Set up the clock sources */
167 /*!< Set up FRO */
168 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
169 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
170 accidentally being below the voltage for current speed */
171 POWER_SetVoltageForFreq(
172 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
173 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
174 before calling this API since this API is implemented in ROM code */
175 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
176
177 /*!< Set up dividers */
178 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
179
180 /*!< Set up clock selectors - Attach clocks to the peripheries */
181 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
182 /* Set SystemCoreClock variable. */
183 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
184 }
185
186 /*******************************************************************************
187 ******************** Configuration BOARD_BootClockPLL180M *********************
188 ******************************************************************************/
189 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
190 !!Configuration
191 name: BOARD_BootClockPLL180M
192 outputs:
193 - {id: FRO12M_clock.outFreq, value: 12 MHz}
194 - {id: FROHF_clock.outFreq, value: 48 MHz}
195 - {id: MAIN_clock.outFreq, value: 180 MHz}
196 - {id: SYSPLL_clock.outFreq, value: 180 MHz}
197 - {id: System_clock.outFreq, value: 180 MHz}
198 settings:
199 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
200 - {id: SYSCON.M_MULT.scale, value: '30', locked: true}
201 - {id: SYSCON.N_DIV.scale, value: '1', locked: true}
202 - {id: SYSCON.PDEC.scale, value: '2', locked: true}
203 - {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
204 sources:
205 - {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
206 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
207
208 /*******************************************************************************
209 * Variables for BOARD_BootClockPLL180M configuration
210 ******************************************************************************/
211 /*******************************************************************************
212 * Code for BOARD_BootClockPLL180M configuration
213 ******************************************************************************/
BOARD_BootClockPLL180M(void)214 void BOARD_BootClockPLL180M(void)
215 {
216 /*!< Set up the clock sources */
217 /*!< Set up FRO */
218 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
219 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
220 accidentally being below the voltage for current speed */
221 POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
222 SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
223 SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
224 POWER_SetVoltageForFreq(
225 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
226 /*!< Set up SYS PLL */
227 const pll_setup_t pllSetup = {
228 .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
229 .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
230 .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
231 .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
232 .pllRate = 180000000U,
233 .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
234 CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
235 CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
236
237 /*!< Set up dividers */
238 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
239
240 /*!< Set up clock selectors - Attach clocks to the peripheries */
241 CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
242 SYSCON->MAINCLKSELA =
243 ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
244 SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
245 /* Set SystemCoreClock variable. */
246 SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
247 }
248
