1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Setup voltage for the fastest of the clock outputs
18 *
19 * 3. Set up wait states of the flash.
20 *
21 * 4. Set up all dividers.
22 *
23 * 5. Set up all selectors to provide selected clocks.
24 */
25
26 /* clang-format off */
27 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
28 !!GlobalInfo
29 product: Clocks v7.0
30 processor: LPC54628J512
31 package_id: LPC54628J512ET180
32 mcu_data: ksdk2_0
33 processor_version: 0.8.3
34 board: LPCXpresso54628
35 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
36 /* clang-format on */
37
38 #include "fsl_power.h"
39 #include "fsl_clock.h"
40 #include "clock_config.h"
41
42 /*******************************************************************************
43 * Definitions
44 ******************************************************************************/
45
46 /*******************************************************************************
47 * Variables
48 ******************************************************************************/
49 /* System clock frequency. */
50 extern uint32_t SystemCoreClock;
51
52 /*******************************************************************************
53 ************************ BOARD_InitBootClocks function ************************
54 ******************************************************************************/
BOARD_InitBootClocks(void)55 void BOARD_InitBootClocks(void)
56 {
57 BOARD_BootClockPLL220M();
58 }
59
60 /*******************************************************************************
61 ******************** Configuration BOARD_BootClockFRO12M **********************
62 ******************************************************************************/
63 /* clang-format off */
64 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
65 !!Configuration
66 name: BOARD_BootClockFRO12M
67 outputs:
68 - {id: FRO12M_clock.outFreq, value: 12 MHz}
69 - {id: FROHF_clock.outFreq, value: 48 MHz}
70 - {id: MAIN_clock.outFreq, value: 12 MHz}
71 - {id: System_clock.outFreq, value: 12 MHz}
72 settings:
73 - {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
74 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
75 /* clang-format on */
76
77 /*******************************************************************************
78 * Variables for BOARD_BootClockFRO12M configuration
79 ******************************************************************************/
80 /*******************************************************************************
81 * Code for BOARD_BootClockFRO12M configuration
82 ******************************************************************************/
BOARD_BootClockFRO12M(void)83 void BOARD_BootClockFRO12M(void)
84 {
85 /*!< Set up the clock sources */
86 /*!< Set up FRO */
87 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
88 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
89 accidentally being below the voltage for current speed */
90 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
91 before calling this API since this API is implemented in ROM code */
92 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
93 POWER_SetVoltageForFreq(
94 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
95 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
96
97 /*!< Set up dividers */
98 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
99
100 /*!< Set up clock selectors - Attach clocks to the peripheries */
101 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
102 /* Set SystemCoreClock variable. */
103 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
104 }
105
106 /*******************************************************************************
107 ******************* Configuration BOARD_BootClockFROHF48M *********************
108 ******************************************************************************/
109 /* clang-format off */
110 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
111 !!Configuration
112 name: BOARD_BootClockFROHF48M
113 outputs:
114 - {id: FRO12M_clock.outFreq, value: 12 MHz}
115 - {id: FROHF_clock.outFreq, value: 48 MHz}
116 - {id: MAIN_clock.outFreq, value: 48 MHz}
117 - {id: System_clock.outFreq, value: 48 MHz}
118 settings:
119 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
120 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
121 /* clang-format on */
122
123 /*******************************************************************************
124 * Variables for BOARD_BootClockFROHF48M configuration
125 ******************************************************************************/
126 /*******************************************************************************
127 * Code for BOARD_BootClockFROHF48M configuration
128 ******************************************************************************/
BOARD_BootClockFROHF48M(void)129 void BOARD_BootClockFROHF48M(void)
130 {
131 /*!< Set up the clock sources */
132 /*!< Set up FRO */
133 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
134 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
135 accidentally being below the voltage for current speed */
136 POWER_SetVoltageForFreq(
137 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
138 CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
139
140 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
141 before calling this API since this API is implemented in ROM code */
142 CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
143
144 /*!< Set up dividers */
145 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
146
147 /*!< Set up clock selectors - Attach clocks to the peripheries */
148 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
149 /* Set SystemCoreClock variable. */
150 SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
151 }
152
153 /*******************************************************************************
154 ******************* Configuration BOARD_BootClockFROHF96M *********************
155 ******************************************************************************/
156 /* clang-format off */
157 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
158 !!Configuration
159 name: BOARD_BootClockFROHF96M
160 outputs:
161 - {id: FRO12M_clock.outFreq, value: 12 MHz}
162 - {id: FROHF_clock.outFreq, value: 96 MHz}
163 - {id: MAIN_clock.outFreq, value: 96 MHz}
164 - {id: System_clock.outFreq, value: 96 MHz}
165 settings:
166 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
167 sources:
168 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
169 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
170 /* clang-format on */
171
172 /*******************************************************************************
173 * Variables for BOARD_BootClockFROHF96M configuration
174 ******************************************************************************/
175 /*******************************************************************************
176 * Code for BOARD_BootClockFROHF96M configuration
177 ******************************************************************************/
BOARD_BootClockFROHF96M(void)178 void BOARD_BootClockFROHF96M(void)
179 {
180 /*!< Set up the clock sources */
181 /*!< Set up FRO */
182 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
183 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
184 accidentally being below the voltage for current speed */
185 POWER_SetVoltageForFreq(
186 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
187 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
188
189 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
190 before calling this API since this API is implemented in ROM code */
191 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
192
193 /*!< Set up dividers */
194 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
195
196 /*!< Set up clock selectors - Attach clocks to the peripheries */
197 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
198 /* Set SystemCoreClock variable. */
199 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
200 }
201
202 /*******************************************************************************
203 ******************** Configuration BOARD_BootClockPLL180M *********************
204 ******************************************************************************/
205 /* clang-format off */
206 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
207 !!Configuration
208 name: BOARD_BootClockPLL180M
209 outputs:
210 - {id: FRO12M_clock.outFreq, value: 12 MHz}
211 - {id: FROHF_clock.outFreq, value: 48 MHz}
212 - {id: MAIN_clock.outFreq, value: 180 MHz}
213 - {id: SYSPLL_clock.outFreq, value: 180 MHz}
214 - {id: System_clock.outFreq, value: 180 MHz}
215 settings:
216 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
217 - {id: SYSCON.M_MULT.scale, value: '30', locked: true}
218 - {id: SYSCON.N_DIV.scale, value: '1', locked: true}
219 - {id: SYSCON.PDEC.scale, value: '2', locked: true}
220 - {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
221 sources:
222 - {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
223 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
224 /* clang-format on */
225
226 /*******************************************************************************
227 * Variables for BOARD_BootClockPLL180M configuration
228 ******************************************************************************/
229 /*******************************************************************************
230 * Code for BOARD_BootClockPLL180M configuration
231 ******************************************************************************/
BOARD_BootClockPLL180M(void)232 void BOARD_BootClockPLL180M(void)
233 {
234 /*!< Set up the clock sources */
235 /*!< Set up FRO */
236 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
237 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
238 accidentally being below the voltage for current speed */
239 POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
240 SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
241 SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
242 POWER_SetVoltageForFreq(
243 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
244 CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
245
246 /*!< Set up SYS PLL */
247 const pll_setup_t pllSetup = {
248 .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
249 .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
250 .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
251 .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
252 .pllRate = 180000000U,
253 .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
254 CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
255 CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
256
257 /*!< Set up dividers */
258 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
259
260 /*!< Set up clock selectors - Attach clocks to the peripheries */
261 CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
262 SYSCON->MAINCLKSELA =
263 ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
264 SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
265 /* Set SystemCoreClock variable. */
266 SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
267 }
268
269 /*******************************************************************************
270 ******************** Configuration BOARD_BootClockPLL220M *********************
271 ******************************************************************************/
272 /* clang-format off */
273 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
274 !!Configuration
275 name: BOARD_BootClockPLL220M
276 called_from_default_init: true
277 outputs:
278 - {id: FRO12M_clock.outFreq, value: 12 MHz}
279 - {id: FROHF_clock.outFreq, value: 96 MHz}
280 - {id: MAIN_clock.outFreq, value: 220 MHz}
281 - {id: SYSPLL_clock.outFreq, value: 220 MHz}
282 - {id: System_clock.outFreq, value: 220 MHz}
283 - {id: USB0_clock.outFreq, value: 48 MHz}
284 settings:
285 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
286 - {id: SYSCON.M_MULT.scale, value: '110', locked: true}
287 - {id: SYSCON.N_DIV.scale, value: '3', locked: true}
288 - {id: SYSCON.PDEC.scale, value: '2', locked: true}
289 - {id: SYSCON.USB0CLKDIV.scale, value: '2'}
290 - {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
291 - {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
292 sources:
293 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
294 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
295 /* clang-format on */
296
297 /*******************************************************************************
298 * Variables for BOARD_BootClockPLL220M configuration
299 ******************************************************************************/
300 /*******************************************************************************
301 * Code for BOARD_BootClockPLL220M configuration
302 ******************************************************************************/
BOARD_BootClockPLL220M(void)303 void BOARD_BootClockPLL220M(void)
304 {
305 /*!< Set up the clock sources */
306 /*!< Set up FRO */
307 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
308 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
309 accidentally being below the voltage for current speed */
310 POWER_SetVoltageForFreq(
311 220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
312 CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
313
314 /*!< Set up SYS PLL */
315 const pll_setup_t pllSetup = {
316 .pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
317 .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
318 .pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
319 .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
320 .pllRate = 220000000U,
321 .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
322 CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
323 CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
324 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
325 before calling this API since this API is implemented in ROM code */
326 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
327
328 /*!< Set up dividers */
329 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
330 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
331 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to value 2 */
332
333 /*!< Set up clock selectors - Attach clocks to the peripheries */
334 CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
335 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */
336 SYSCON->MAINCLKSELA =
337 ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
338 SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
339 /* Set SystemCoreClock variable. */
340 SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
341 }
342
