1 /*
2  * Copyright (c) 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017,2019 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 /*
13  * How to set up clock using clock driver functions:
14  *
15  * 1. Setup clock sources.
16  *
17  * 2. Setup voltage for the fastest of the clock outputs
18  *
19  * 3. Set up wait states of the flash.
20  *
21  * 4. Set up all dividers.
22  *
23  * 5. Set up all selectors to provide selected clocks.
24  */
25 
26 /* clang-format off */
27 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
28 !!GlobalInfo
29 product: Clocks v7.0
30 processor: LPC54114J256
31 package_id: LPC54114J256BD64
32 mcu_data: ksdk2_0
33 processor_version: 0.7.1
34 board: LPCXpresso54114
35  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
36 /* clang-format on */
37 
38 #include "fsl_power.h"
39 #include "fsl_clock.h"
40 #include "clock_config.h"
41 
42 /*******************************************************************************
43  * Definitions
44  ******************************************************************************/
45 
46 /*******************************************************************************
47  * Variables
48  ******************************************************************************/
49 /* System clock frequency. */
50 extern uint32_t SystemCoreClock;
51 
52 /*******************************************************************************
53  ************************ BOARD_InitBootClocks function ************************
54  ******************************************************************************/
BOARD_InitBootClocks(void)55 void BOARD_InitBootClocks(void)
56 {
57     BOARD_BootClockPLL150M();
58 }
59 
60 /*******************************************************************************
61  ******************** Configuration BOARD_BootClockFRO12M **********************
62  ******************************************************************************/
63 /* clang-format off */
64 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
65 !!Configuration
66 name: BOARD_BootClockFRO12M
67 outputs:
68 - {id: System_clock.outFreq, value: 12 MHz}
69  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
70 /* clang-format on */
71 
72 /*******************************************************************************
73  * Variables for BOARD_BootClockFRO12M configuration
74  ******************************************************************************/
75 /*******************************************************************************
76  * Code for BOARD_BootClockFRO12M configuration
77  ******************************************************************************/
BOARD_BootClockFRO12M(void)78 void BOARD_BootClockFRO12M(void)
79 {
80 #ifndef SDK_SECONDARY_CORE
81     /*!< Set up the clock sources */
82     /*!< Set up FRO */
83     POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
84     CLOCK_SetupFROClocking(12000000U);    /*!< Set up FRO to the 12 MHz, just for sure */
85     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
86                                              accidentally being below the voltage for current speed */
87     POWER_SetVoltageForFreq(
88         12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
89     CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
90 
91     /*!< Set up dividers */
92     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
93 
94     /*!< Set up clock selectors - Attach clocks to the peripheries */
95     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
96     /*< Set SystemCoreClock variable. */
97     SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
98 #endif
99 }
100 
101 /*******************************************************************************
102  ******************* Configuration BOARD_BootClockFROHF48M *********************
103  ******************************************************************************/
104 /* clang-format off */
105 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
106 !!Configuration
107 name: BOARD_BootClockFROHF48M
108 outputs:
109 - {id: System_clock.outFreq, value: 48 MHz}
110 settings:
111 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
112  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
113 /* clang-format on */
114 
115 /*******************************************************************************
116  * Variables for BOARD_BootClockFROHF48M configuration
117  ******************************************************************************/
118 /*******************************************************************************
119  * Code for BOARD_BootClockFROHF48M configuration
120  ******************************************************************************/
BOARD_BootClockFROHF48M(void)121 void BOARD_BootClockFROHF48M(void)
122 {
123 #ifndef SDK_SECONDARY_CORE
124     /*!< Set up the clock sources */
125     /*!< Set up FRO */
126     POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
127     CLOCK_SetupFROClocking(12000000U);    /*!< Set up FRO to the 12 MHz, just for sure */
128     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
129                                              accidentally being below the voltage for current speed */
130     POWER_SetVoltageForFreq(
131         48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
132     CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
133 
134     CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
135 
136     /*!< Set up dividers */
137     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
138 
139     /*!< Set up clock selectors - Attach clocks to the peripheries */
140     CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
141     /*< Set SystemCoreClock variable. */
142     SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
143 #endif
144 }
145 
146 /*******************************************************************************
147  ******************* Configuration BOARD_BootClockFROHF96M *********************
148  ******************************************************************************/
149 /* clang-format off */
150 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
151 !!Configuration
152 name: BOARD_BootClockFROHF96M
153 outputs:
154 - {id: System_clock.outFreq, value: 96 MHz}
155 settings:
156 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
157 sources:
158 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
159  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
160 /* clang-format on */
161 
162 /*******************************************************************************
163  * Variables for BOARD_BootClockFROHF96M configuration
164  ******************************************************************************/
165 /*******************************************************************************
166  * Code for BOARD_BootClockFROHF96M configuration
167  ******************************************************************************/
BOARD_BootClockFROHF96M(void)168 void BOARD_BootClockFROHF96M(void)
169 {
170 #ifndef SDK_SECONDARY_CORE
171     /*!< Set up the clock sources */
172     /*!< Set up FRO */
173     POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
174     CLOCK_SetupFROClocking(12000000U);    /*!< Set up FRO to the 12 MHz, just for sure */
175     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
176                                              accidentally being below the voltage for current speed */
177     POWER_SetVoltageForFreq(
178         96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
179     CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
180 
181     CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
182 
183     /*!< Set up dividers */
184     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
185 
186     /*!< Set up clock selectors - Attach clocks to the peripheries */
187     CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
188     /*< Set SystemCoreClock variable. */
189     SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
190 #endif
191 }
192 
193 /*******************************************************************************
194  ******************** Configuration BOARD_BootClockPLL150M *********************
195  ******************************************************************************/
196 /* clang-format off */
197 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
198 !!Configuration
199 name: BOARD_BootClockPLL150M
200 called_from_default_init: true
201 outputs:
202 - {id: PLL_clock.outFreq, value: 150 MHz}
203 - {id: System_clock.outFreq, value: 150 MHz}
204 settings:
205 - {id: PLL_Mode, value: Normal}
206 - {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
207 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
208 - {id: SYSCON.M_MULT.scale, value: '150', locked: true}
209 - {id: SYSCON.N_DIV.scale, value: '12', locked: true}
210 - {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
211 - {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.fro_12m}
212  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
213 /* clang-format on */
214 
215 /*******************************************************************************
216  * Variables for BOARD_BootClockPLL150M configuration
217  ******************************************************************************/
218 /*******************************************************************************
219  * Code for BOARD_BootClockPLL150M configuration
220  ******************************************************************************/
BOARD_BootClockPLL150M(void)221 void BOARD_BootClockPLL150M(void)
222 {
223 #ifndef SDK_SECONDARY_CORE
224     /*!< Set up the clock sources */
225     /*!< Set up FRO */
226     POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
227     CLOCK_SetupFROClocking(12000000U);    /*!< Set up FRO to the 12 MHz, just for sure */
228     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
229                                              accidentally being below the voltage for current speed */
230     POWER_SetVoltageForFreq(
231         150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
232     CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
233 
234     /*!< Set up PLL */
235     CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Switch PLL clock source selector to FRO12M */
236     const pll_setup_t pllSetup = {
237         .syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELI(26U) | SYSCON_SYSPLLCTRL_SELP(31U) |
238                       SYSCON_SYSPLLCTRL_DIRECTO_MASK,
239         .syspllndec   = SYSCON_SYSPLLNDEC_NDEC(199U),
240         .syspllpdec   = SYSCON_SYSPLLPDEC_PDEC(2U),
241         .syspllssctrl = {(SYSCON_SYSPLLSSCTRL0_MDEC(9637U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK), 0x0U},
242         .pllRate      = 150000000U,
243         .flags        = PLL_SETUPFLAG_WAITLOCK};
244     CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
245 
246     /*!< Set up dividers */
247     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
248 
249     /*!< Set up clock selectors - Attach clocks to the peripheries */
250     CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
251     SYSCON->MAINCLKSELA =
252         ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
253          SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
254     /*< Set SystemCoreClock variable. */
255     SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
256 #endif
257 }
258