1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to set up clock using clock driver functions:
10 *
11 * 1. Setup clock sources.
12 *
13 * 2. Setup voltage for the fastest of the clock outputs
14 *
15 * 3. Set up wait states of the flash.
16 *
17 * 4. Set up all dividers.
18 *
19 * 5. Set up all selectors to provide selected clocks.
20 */
21
22 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23 !!GlobalInfo
24 product: Clocks v4.1
25 processor: LPC51U68
26 package_id: LPC51U68JBD64
27 mcu_data: ksdk2_0
28 processor_version: 3.0.1
29 board: LPCXpresso51u68
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32 #include "fsl_power.h"
33 #include "fsl_clock.h"
34 #include "clock_config.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43 /* System clock frequency. */
44 extern uint32_t SystemCoreClock;
45
46 /*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
BOARD_InitBootClocks(void)49 void BOARD_InitBootClocks(void)
50 {
51 BOARD_BootClockRUN();
52 }
53
54 /*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58 !!Configuration
59 name: BOARD_BootClockRUN
60 called_from_default_init: true
61 outputs:
62 - {id: PLL_clock.outFreq, value: 12 MHz}
63 - {id: SYSTICK_clock.outFreq, value: 12 MHz}
64 - {id: System_clock.outFreq, value: 12 MHz}
65 settings:
66 - {id: SYSCON.M_MULT.scale, value: '0', locked: true}
67 - {id: SYSCON.N_DIV.scale, value: '3', locked: true}
68 - {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.SYSPLLCLKSEL}
69 - {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.fro_12m}
70 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
71
72 /*******************************************************************************
73 * Variables for BOARD_BootClockRUN configuration
74 ******************************************************************************/
75 /*******************************************************************************
76 * Code for BOARD_BootClockRUN configuration
77 ******************************************************************************/
BOARD_BootClockRUN(void)78 void BOARD_BootClockRUN(void)
79 {
80 /*!< Set up the clock sources */
81 /*!< Set up FRO */
82 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
83 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
84 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
85 accidentally being below the voltage for current speed */
86 POWER_SetVoltageForFreq(
87 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
88 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
89
90 /*!< Set up PLL */
91 CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Switch PLL clock source selector to FRO12M */
92 const pll_setup_t pllSetup = {.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_BYPASS_MASK,
93 .syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U),
94 .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U),
95 .syspllssctrl = {0x0U, (SYSCON_SYSPLLSSCTRL1_MD(0U) | (uint32_t)(kSS_MF_512) |
96 (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))},
97 .pllRate = 12000000U,
98 .flags = PLL_SETUPFLAG_POWERUP};
99 CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
100
101 /* PLL in Fractional/Spread spectrum mode */
102 /* SYSTICK is used for waiting for PLL stabilization */
103
104 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SysTick divider counter and halt it */
105 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 3U, false); /*!< Set SysTick divider to value 3 */
106 SysTick->LOAD = 27999UL; /*!< Set SysTick count value */
107 SysTick->VAL = 0UL; /*!< Reset current count value */
108 SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /*!< Enable SYSTICK */
109 while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != SysTick_CTRL_COUNTFLAG_Msk)
110 {
111 } /*!< Waiting for PLL stabilization */
112 SysTick->CTRL = 0UL; /*!< Stop SYSTICK */
113
114 /*!< Set up dividers */
115 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
116 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */
117 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
118
119 /*!< Set up clock selectors - Attach clocks to the peripheries */
120 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
121 /*!< Set SystemCoreClock variable. */
122 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
123 }
124
125 /*******************************************************************************
126 ******************** Configuration BOARD_BootClockFRO12M **********************
127 ******************************************************************************/
128 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
129 !!Configuration
130 name: BOARD_BootClockFRO12M
131 outputs:
132 - {id: SYSTICK_clock.outFreq, value: 12 MHz}
133 - {id: System_clock.outFreq, value: 12 MHz}
134 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
135
136 /*******************************************************************************
137 * Variables for BOARD_BootClockFRO12M configuration
138 ******************************************************************************/
139 /*******************************************************************************
140 * Code for BOARD_BootClockFRO12M configuration
141 ******************************************************************************/
BOARD_BootClockFRO12M(void)142 void BOARD_BootClockFRO12M(void)
143 {
144 /*!< Set up the clock sources */
145 /*!< Set up FRO */
146 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
147 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
148 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
149 accidentally being below the voltage for current speed */
150 POWER_SetVoltageForFreq(
151 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
152 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
153
154 /*!< Set up dividers */
155 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
156 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */
157 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
158
159 /*!< Set up clock selectors - Attach clocks to the peripheries */
160 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
161 /*!< Set SystemCoreClock variable. */
162 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
163 }
164
165 /*******************************************************************************
166 ******************* Configuration BOARD_BootClockFROHF48M *********************
167 ******************************************************************************/
168 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
169 !!Configuration
170 name: BOARD_BootClockFROHF48M
171 outputs:
172 - {id: SYSTICK_clock.outFreq, value: 48 MHz}
173 - {id: System_clock.outFreq, value: 48 MHz}
174 settings:
175 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
176 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
177
178 /*******************************************************************************
179 * Variables for BOARD_BootClockFROHF48M configuration
180 ******************************************************************************/
181 /*******************************************************************************
182 * Code for BOARD_BootClockFROHF48M configuration
183 ******************************************************************************/
BOARD_BootClockFROHF48M(void)184 void BOARD_BootClockFROHF48M(void)
185 {
186 /*!< Set up the clock sources */
187 /*!< Set up FRO */
188 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
189 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
190 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
191 accidentally being below the voltage for current speed */
192 POWER_SetVoltageForFreq(
193 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
194 CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
195
196 CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
197
198 /*!< Set up dividers */
199 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
200 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */
201 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
202
203 /*!< Set up clock selectors - Attach clocks to the peripheries */
204 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
205 /*!< Set SystemCoreClock variable. */
206 SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
207 }
208
209 /*******************************************************************************
210 ******************* Configuration BOARD_BootClockFROHF96M *********************
211 ******************************************************************************/
212 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
213 !!Configuration
214 name: BOARD_BootClockFROHF96M
215 outputs:
216 - {id: SYSTICK_clock.outFreq, value: 96 MHz}
217 - {id: System_clock.outFreq, value: 96 MHz}
218 settings:
219 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
220 sources:
221 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
222 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
223
224 /*******************************************************************************
225 * Variables for BOARD_BootClockFROHF96M configuration
226 ******************************************************************************/
227 /*******************************************************************************
228 * Code for BOARD_BootClockFROHF96M configuration
229 ******************************************************************************/
BOARD_BootClockFROHF96M(void)230 void BOARD_BootClockFROHF96M(void)
231 {
232 /*!< Set up the clock sources */
233 /*!< Set up FRO */
234 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
235 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
236 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
237 accidentally being below the voltage for current speed */
238 POWER_SetVoltageForFreq(
239 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
240 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
241
242 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
243
244 /*!< Set up dividers */
245 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
246 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */
247 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
248
249 /*!< Set up clock selectors - Attach clocks to the peripheries */
250 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
251 /*!< Set SystemCoreClock variable. */
252 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
253 }
254
