1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MKV31F512xxx12
46 package_id: MKV31F512VLL12
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50 /* clang-format on */
51
52 #include "fsl_smc.h"
53 #include "clock_config.h"
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
59 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
60 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
61 #define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
62 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
63 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
64
65 /*******************************************************************************
66 * Variables
67 ******************************************************************************/
68 /* System clock frequency. */
69 extern uint32_t SystemCoreClock;
70
71 /*******************************************************************************
72 * Code
73 ******************************************************************************/
74 /*FUNCTION**********************************************************************
75 *
76 * Function Name : CLOCK_CONFIG_FllStableDelay
77 * Description : This function is used to delay for FLL stable.
78 *
79 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)80 static void CLOCK_CONFIG_FllStableDelay(void)
81 {
82 uint32_t i = 30000U;
83 while (i--)
84 {
85 __NOP();
86 }
87 }
88
89 /*******************************************************************************
90 ************************ BOARD_InitBootClocks function ************************
91 ******************************************************************************/
BOARD_InitBootClocks(void)92 void BOARD_InitBootClocks(void)
93 {
94 BOARD_BootClockRUN();
95 }
96
97 /*******************************************************************************
98 ********************** Configuration BOARD_BootClockRUN ***********************
99 ******************************************************************************/
100 /* clang-format off */
101 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
102 !!Configuration
103 name: BOARD_BootClockRUN
104 called_from_default_init: true
105 outputs:
106 - {id: Bus_clock.outFreq, value: 31.45728 MHz}
107 - {id: Core_clock.outFreq, value: 62.91456 MHz}
108 - {id: Flash_clock.outFreq, value: 15.72864 MHz}
109 - {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
110 - {id: LPO_clock.outFreq, value: 1 kHz}
111 - {id: LPUARTCLK.outFreq, value: 4 MHz}
112 - {id: MCGFFCLK.outFreq, value: 32.768 kHz}
113 - {id: MCGIRCLK.outFreq, value: 4 MHz}
114 - {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
115 - {id: System_clock.outFreq, value: 62.91456 MHz}
116 settings:
117 - {id: LPUARTClkConfig, value: 'yes'}
118 - {id: MCG.FCRDIV.scale, value: '1'}
119 - {id: MCG.FLL_mul.scale, value: '1920', locked: true}
120 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
121 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
122 - {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
123 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
124 - {id: SIM.OUTDIV2.scale, value: '2'}
125 - {id: SIM.OUTDIV3.scale, value: '4'}
126 - {id: SIM.OUTDIV4.scale, value: '4'}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128 /* clang-format on */
129
130 /*******************************************************************************
131 * Variables for BOARD_BootClockRUN configuration
132 ******************************************************************************/
133 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
134 {
135 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
136 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
137 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
138 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
139 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
140 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
141 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
142 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
143 .pll0Config =
144 {
145 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
146 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
147 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
148 },
149 };
150 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
151 {
152 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
153 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
154 .clkdiv1 = 0x1330000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
155 };
156 const osc_config_t oscConfig_BOARD_BootClockRUN =
157 {
158 .freq = 0U, /* Oscillator frequency: 0Hz */
159 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
160 .workMode = kOSC_ModeExt, /* Use external clock */
161 .oscerConfig =
162 {
163 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
164 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
165 }
166 };
167
168 /*******************************************************************************
169 * Code for BOARD_BootClockRUN configuration
170 ******************************************************************************/
BOARD_BootClockRUN(void)171 void BOARD_BootClockRUN(void)
172 {
173 /* Set the system clock dividers in SIM to safe value. */
174 CLOCK_SetSimSafeDivs();
175 /* Configure the Internal Reference clock (MCGIRCLK). */
176 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
177 mcgConfig_BOARD_BootClockRUN.ircs,
178 mcgConfig_BOARD_BootClockRUN.fcrdiv);
179 /* Set MCG to FEI mode. */
180 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
181 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
182 mcgConfig_BOARD_BootClockRUN.drs,
183 CLOCK_CONFIG_FllStableDelay);
184 #else
185 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
186 CLOCK_CONFIG_FllStableDelay);
187 #endif
188 /* Set the clock configuration in SIM module. */
189 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
190 /* Set SystemCoreClock variable. */
191 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
192 /* Set LPUART clock source. */
193 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
194 }
195
196 /*******************************************************************************
197 ********************* Configuration BOARD_BootClockHSRUN **********************
198 ******************************************************************************/
199 /* clang-format off */
200 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
201 !!Configuration
202 name: BOARD_BootClockHSRUN
203 outputs:
204 - {id: Bus_clock.outFreq, value: 41.94304 MHz}
205 - {id: Core_clock.outFreq, value: 83.88608 MHz}
206 - {id: Flash_clock.outFreq, value: 20.97152 MHz}
207 - {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
208 - {id: LPO_clock.outFreq, value: 1 kHz}
209 - {id: LPUARTCLK.outFreq, value: 4 MHz}
210 - {id: MCGFFCLK.outFreq, value: 32.768 kHz}
211 - {id: MCGIRCLK.outFreq, value: 4 MHz}
212 - {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
213 - {id: System_clock.outFreq, value: 83.88608 MHz}
214 settings:
215 - {id: powerMode, value: HSRUN}
216 - {id: LPUARTClkConfig, value: 'yes'}
217 - {id: MCG.FCRDIV.scale, value: '1'}
218 - {id: MCG.FLL_mul.scale, value: '2560'}
219 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
220 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
221 - {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
222 - {id: SIM.OUTDIV2.scale, value: '2'}
223 - {id: SIM.OUTDIV3.scale, value: '3'}
224 - {id: SIM.OUTDIV4.scale, value: '4'}
225 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
226 /* clang-format on */
227
228 /*******************************************************************************
229 * Variables for BOARD_BootClockHSRUN configuration
230 ******************************************************************************/
231 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
232 {
233 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
234 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
235 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
236 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
237 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
238 .drs = kMCG_DrsHigh, /* High frequency range */
239 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
240 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
241 .pll0Config =
242 {
243 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
244 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
245 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
246 },
247 };
248 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
249 {
250 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
251 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
252 .clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
253 };
254 const osc_config_t oscConfig_BOARD_BootClockHSRUN =
255 {
256 .freq = 0U, /* Oscillator frequency: 0Hz */
257 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
258 .workMode = kOSC_ModeExt, /* Use external clock */
259 .oscerConfig =
260 {
261 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
262 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
263 }
264 };
265
266 /*******************************************************************************
267 * Code for BOARD_BootClockHSRUN configuration
268 ******************************************************************************/
BOARD_BootClockHSRUN(void)269 void BOARD_BootClockHSRUN(void)
270 {
271 /* Set HSRUN power mode */
272 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
273 SMC_SetPowerModeHsrun(SMC);
274 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
275 {
276 }
277 /* Set the system clock dividers in SIM to safe value. */
278 CLOCK_SetSimSafeDivs();
279 /* Configure the Internal Reference clock (MCGIRCLK). */
280 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
281 mcgConfig_BOARD_BootClockHSRUN.ircs,
282 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
283 /* Set MCG to FEI mode. */
284 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
285 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32,
286 mcgConfig_BOARD_BootClockHSRUN.drs,
287 CLOCK_CONFIG_FllStableDelay);
288 #else
289 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs,
290 CLOCK_CONFIG_FllStableDelay);
291 #endif
292 /* Set the clock configuration in SIM module. */
293 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
294 /* Set SystemCoreClock variable. */
295 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
296 /* Set LPUART clock source. */
297 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
298 }
299
300 /*******************************************************************************
301 ********************* Configuration BOARD_BootClockVLPR ***********************
302 ******************************************************************************/
303 /* clang-format off */
304 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
305 !!Configuration
306 name: BOARD_BootClockVLPR
307 outputs:
308 - {id: Bus_clock.outFreq, value: 4 MHz}
309 - {id: Core_clock.outFreq, value: 4 MHz}
310 - {id: Flash_clock.outFreq, value: 800 kHz}
311 - {id: FlexBus_clock.outFreq, value: 2 MHz}
312 - {id: LPO_clock.outFreq, value: 1 kHz}
313 - {id: LPUARTCLK.outFreq, value: 4 MHz}
314 - {id: MCGIRCLK.outFreq, value: 4 MHz}
315 - {id: System_clock.outFreq, value: 4 MHz}
316 settings:
317 - {id: MCGMode, value: BLPI}
318 - {id: powerMode, value: VLPR}
319 - {id: LPUARTClkConfig, value: 'yes'}
320 - {id: MCG.CLKS.sel, value: MCG.IRCS}
321 - {id: MCG.FCRDIV.scale, value: '1'}
322 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
323 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
324 - {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
325 - {id: SIM.OUTDIV4.scale, value: '5'}
326 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
327 /* clang-format on */
328
329 /*******************************************************************************
330 * Variables for BOARD_BootClockVLPR configuration
331 ******************************************************************************/
332 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
333 {
334 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
335 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
336 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
337 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
338 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
339 .drs = kMCG_DrsLow, /* Low frequency range */
340 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
341 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
342 .pll0Config =
343 {
344 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
345 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
346 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
347 },
348 };
349 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
350 {
351 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
352 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
353 .clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
354 };
355 const osc_config_t oscConfig_BOARD_BootClockVLPR =
356 {
357 .freq = 0U, /* Oscillator frequency: 0Hz */
358 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
359 .workMode = kOSC_ModeExt, /* Use external clock */
360 .oscerConfig =
361 {
362 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
363 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
364 }
365 };
366
367 /*******************************************************************************
368 * Code for BOARD_BootClockVLPR configuration
369 ******************************************************************************/
BOARD_BootClockVLPR(void)370 void BOARD_BootClockVLPR(void)
371 {
372 /* Set the system clock dividers in SIM to safe value. */
373 CLOCK_SetSimSafeDivs();
374 /* Set MCG to BLPI mode. */
375 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
376 mcgConfig_BOARD_BootClockVLPR.ircs,
377 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
378 /* Set the clock configuration in SIM module. */
379 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
380 /* Set VLPR power mode. */
381 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
382 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
383 SMC_SetPowerModeVlpr(SMC, false);
384 #else
385 SMC_SetPowerModeVlpr(SMC);
386 #endif
387 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
388 {
389 }
390 /* Set SystemCoreClock variable. */
391 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
392 /* Set LPUART clock source. */
393 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
394 }
395
396
