1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13 /* clang-format off */
14 /*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16 !!GlobalInfo
17 product: Pins v4.1
18 processor: MKV11Z128xxx7
19 package_id: MKV11Z128VLF7
20 mcu_data: ksdk2_0
21 processor_version: 4.0.0
22 board: HVP-KV11Z75M
23 pin_labels:
24 - {pin_num: '26', pin_signal: PTA20/RESET_b, label: 'J3[10]/U2[21]/U5[11]/SW1/''/RESET''/''/RESET_ISOLATED''', identifier: RESET}
25 - {pin_num: '36', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/FTM3_FLT0, label: USER_LED_2, identifier: LED_RED}
26 - {pin_num: '43', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART0_RX/FTM0_CH2/FTM3_CH2/I2C0_SCL, label: 'MB_J11[B20]/MB_U9[4]/MB_USER_LED/J4[B20]/USER_LED', identifier: LED_GREEN}
27 - {pin_num: '17', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/EWM_IN/SWD_CLK, label: 'J3[4]/U4[11]/U5[13]/SWCLK/SWDCLK_ISOLATED'}
28 - {pin_num: '1', pin_signal: VDD1, label: 3V3}
29 - {pin_num: '22', pin_signal: VDD22, label: 3V3}
30 - {pin_num: '9', pin_signal: VDDA, label: 3V3A}
31 - {pin_num: '10', pin_signal: VREFH, label: 3V3A}
32 - {pin_num: '11', pin_signal: VREFL, label: AGND}
33 - {pin_num: '2', pin_signal: VSS2, label: GND}
34 - {pin_num: '12', pin_signal: VSSA, label: AGND}
35 - {pin_num: '23', pin_signal: VSS23, label: GND}
36 - {pin_num: '3', pin_signal: ADC0_SE1/ADC0_DP1/ADC1_SE0/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3, label: 'MB_J11[B8]/MB_TP41/MB_BEMF_sense_C/MB_Phase_C/J4[B8]/BEMF_C',
37 identifier: BEMF_C}
38 - {pin_num: '4', pin_signal: ADC0_DM1/ADC0_SE5/ADC1_SE5/PTE17/LLWU_P19/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3, label: 'MB_J11[A9]/MB_U2A[1]/MB_TP5/MB_Ipfc2/J4[A9]/I_pfc2',
39 identifier: I_PFC2}
40 - {pin_num: '5', pin_signal: ADC0_SE6/ADC1_SE1/ADC1_DP1/PTE18/LLWU_P20/SPI0_SOUT/UART1_CTS_b/I2C0_SDA/SPI0_SIN, label: 'MB_J11[B3]/MB_U8B[7]/MB_TP34/MB_I_sense_DCB/J4[B3]/I_dcb',
41 identifier: I_DCB}
42 - {pin_num: '6', pin_signal: ADC0_SE7/ADC1_SE7/ADC1_DM1/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL/SPI0_SOUT, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC',
43 identifier: I_PH_C}
44 - {pin_num: '7', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC', identifier: I_PH_C_2}
45 - {pin_num: '8', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX, label: 'MB_J11[B4]/MB_TP31/MB_V_sense_DCB/MB_DCB_Pos/J4[B4]/U_dcb', identifier: U_DCB}
46 - {pin_num: '15', pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, label: 'MB_J11[A14]/MB_U12[18]/MB_PWM_AT/J4[A14]/PWM0', identifier: PWM_AT}
47 - {pin_num: '16', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, label: 'MB_J11[A15]/MB_U12[12]/MB_PWM_AB/J4[A15]/PWM1', identifier: PWM_AB}
48 - {pin_num: '13', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, label: 'MB_J9[5]/MB_J11[B16]/MB_TP19/MB_ENC_Index/J4[B16]/TM2', identifier: ENC_INDEX}
49 - {pin_num: '14', pin_signal: ADC1_SE4/CMP1_IN4/DAC0_OUT/PTE30/FTM0_CH3/FTM_CLKIN1, label: 'MB_J11[A3]/MB_U11A[1]/MB_TP45/MB_I_sense_A/J4[A3]/I_phA', identifier: I_PH_A}
50 - {pin_num: '18', pin_signal: PTA1/UART0_RX/FTM2_CH0/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/FTM4_CH0, label: 'MB_J9[3]/MB_J11[B14]/MB_TP13/MB_ENC_PhaseA/J4[B14]/TM0', identifier: ENC_PHASE_A}
51 - {pin_num: '19', pin_signal: PTA2/UART0_TX/FTM2_CH1/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/FTM4_CH1, label: 'MB_J9[4]/MB_J11[B15]/MB_TP17/MB_ENC_PhaseB/J4[B15]/TM1', identifier: ENC_PHASE_B}
52 - {pin_num: '20', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/FTM2_FLT0/EWM_OUT_b/SWD_DIO, label: 'J3[2]/U4[3]/U5[14]/SWDIO/SWDIO_ISOLATED'}
53 - {pin_num: '21', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM4_FLT0/FTM0_FLT3/NMI_b, label: 'MB_J11[B22]/MB_PFC_zc_1/J4[B22]/MB_TP_26', identifier: PFC_ZC_1}
54 - {pin_num: '24', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, label: 'MB_J11[B28]/MB_Q3[1]/MB_Relay/J4[B28]/Relay', identifier: RELAY}
55 - {pin_num: '25', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'MB_J11[A26]/MB_U9[2]/MB_TP35/MB_FAULT_2/MB_Over-voltage_FAULT/J4[A26]/FAULT_2',
56 identifier: FAULT_2}
57 - {pin_num: '27', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, label: 'MB_J11[B6]/MB_TP44/MB_BEMF_sense_A/MB_Phase_A/J4[B6]/BEMF_A',
58 identifier: BEMF_A}
59 - {pin_num: '29', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, label: 'MB_J11[B7]/MB_TP43/MB_BEMF_sense_B/MB_Phase_B/J4[B7]/BEMF_B',
60 identifier: BEMF_B}
61 - {pin_num: '28', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX, label: 'MB_J11[A4]/MB_U11B[7]/MB_TP40/MB_I_sense_B/J4[A4]/I_phB',
62 identifier: I_PH_B}
63 - {pin_num: '30', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: 'MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in', identifier: V_IN}
64 - {pin_num: '31', pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN, label: 'MB_J3[2]/MB_J11[B27]/MB_U1[12]/MB_U3[26]/MB_TP2/MB_TP10/MB_RxD/J4[B27]/RxD', identifier: RXD}
65 - {pin_num: '32', pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, label: 'MB_J1[3]/MB_J11[B26]/MB_U1[13]/MB_U3[25]/MB_TP3/MB_TP7/MB_TxD/J4[B26]/TxD', identifier: TXD}
66 - {pin_num: '33', pin_signal: ADC1_SE11/PTC0/SPI0_PCS4/PDB_EXTRG0/CMP0_OUT/FTM0_FLT0/SPI0_PCS0, label: 'MB_J11[A25]/MB_U12[11]/MB_TP28/MB_FAULT/MB_FAULT_1/MB_PFC_overcurrent/J4[A25]/FAULT_1',
67 identifier: FAULT_1}
68 - {pin_num: '34', pin_signal: ADC1_SE3/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FTM2_CH0, label: 'MB_J11[B9]/MB_U12[2]/MB_TP38/MB_IPM_temp/J4[B9]/Temp_IPM', identifier: TEMP_IPM}
69 - {pin_num: '35', pin_signal: ADC0_SE11/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FTM2_CH1, label: 'MB_J11[A8]/MB_U2B[7]/MB_TP14/MB_Ipfc1/J4[A8]/I_pfc1', identifier: I_PFC1}
70 - {pin_num: '37', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, label: 'MB_J11[A17]/MB_U12[13]/MB_PWM_BB/J4[A17]/PWM3', identifier: PWM_BB}
71 - {pin_num: '38', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, label: 'MB_J11[A16]/MB_U12[19]/MB_PWM_BT/J4[A16]/PWM2', identifier: PWM_BT}
72 - {pin_num: '39', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL, label: 'MB_J11[A6]/MB_TP16/MB_TACHO/J4[A6]/TACHO', identifier: TACHO}
73 - {pin_num: '40', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA, label: 'MB_J11[B21]/MB_PFC_zc_2/J4[B21]/MB_TP_27', identifier: PFC_ZC_2}
74 - {pin_num: '41', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, label: 'MB_J2[4]/MB_J3[4]/MB_J11[A32]/MB_RxD_1/MB_RxD_EXT/U6[14]/J4[A32]/RxD1/UART1_TGT_MCU',
75 identifier: RXD_1;UART_RX_TGTMCU}
76 - {pin_num: '42', pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, label: 'MB_J1[1]/MB_J2[3]/MB_J11[A31]/MB_TxD_1/MB_TxD_EXT/U6[13]/J4[A31]/TxD_1/UART1_TX_TGTMCU',
77 identifier: TXD_1;UART_TX_TGTMCU}
78 - {pin_num: '45', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FTM2_CH0/EWM_IN/SPI0_PCS0, label: 'MB_J11[A18]/MB_U12[20]/MB_PWM_CT/J4[A18]/PWM4', identifier: PWM_CT}
79 - {pin_num: '46', pin_signal: ADC0_SE3/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FTM2_CH1/EWM_OUT_b/SPI0_SCK, label: 'MB_J11[A19]/MB_U12[14]/MB_PWM_CB/J4[A19]/PWM5', identifier: PWM_CB}
80 - {pin_num: '44', pin_signal: PTD3/SPI0_SIN/UART0_TX/FTM0_CH3/FTM3_CH3/I2C0_SDA, label: 'MB_J11[B25]/MB_U9[2]/MB_TP_35/MB_MCU_BRAKE/J4[B25]/MCU_BRAKE', identifier: MCU_BRAKE}
81 - {pin_num: '47', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, label: 'MB_J11[A22]/MB_U14[4]/MB_TP15/MB_PWM_PFC2/J4[A22]/PWM8',
82 identifier: PWM_PFC2}
83 - {pin_num: '48', pin_signal: PTD7/FTM4_CH1/UART0_TX/FTM0_CH1/FTM1_CH1/FTM0_FLT1/SPI0_SIN, label: 'MB_J11[A23]/MB_U14[2]/MB_TP12/MB_PWM_PFC1/J4[A23]/PWM9', identifier: PWM_PFC1}
84 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
85 */
86 /* clang-format on */
87
88 #include "fsl_common.h"
89 #include "fsl_port.h"
90 #include "fsl_gpio.h"
91 #include "pin_mux.h"
92
93 /* FUNCTION ************************************************************************************************************
94 *
95 * Function Name : BOARD_InitBootPins
96 * Description : Calls initialization functions.
97 *
98 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)99 void BOARD_InitBootPins(void)
100 {
101 BOARD_InitPins();
102 BOARD_InitDEBUG_UARTPins();
103 }
104
105 /* clang-format off */
106 /*
107 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
108 MB_InitMC_PWMPins:
109 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
110 - pin_list:
111 - {pin_num: '15', peripheral: FTM0, signal: 'CH, 0', pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, direction: OUTPUT}
112 - {pin_num: '37', peripheral: FTM0, signal: 'CH, 3', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, direction: OUTPUT}
113 - {pin_num: '38', peripheral: FTM0, signal: 'CH, 2', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, direction: OUTPUT}
114 - {pin_num: '45', peripheral: FTM0, signal: 'CH, 4', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FTM2_CH0/EWM_IN/SPI0_PCS0, direction: OUTPUT}
115 - {pin_num: '46', peripheral: FTM0, signal: 'CH, 5', pin_signal: ADC0_SE3/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FTM2_CH1/EWM_OUT_b/SPI0_SCK, direction: OUTPUT}
116 - {pin_num: '16', peripheral: FTM0, signal: 'CH, 1', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, direction: OUTPUT}
117 - {pin_num: '33', peripheral: FTM0, signal: 'FLT, 0', pin_signal: ADC1_SE11/PTC0/SPI0_PCS4/PDB_EXTRG0/CMP0_OUT/FTM0_FLT0/SPI0_PCS0}
118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
119 */
120 /* clang-format on */
121
122 /* FUNCTION ************************************************************************************************************
123 *
124 * Function Name : MB_InitMC_PWMPins
125 * Description : Configures pin routing and optionally pin electrical features.
126 *
127 * END ****************************************************************************************************************/
MB_InitMC_PWMPins(void)128 void MB_InitMC_PWMPins(void)
129 {
130 /* Port C Clock Gate Control: Clock enabled */
131 CLOCK_EnableClock(kCLOCK_PortC);
132 /* Port D Clock Gate Control: Clock enabled */
133 CLOCK_EnableClock(kCLOCK_PortD);
134 /* Port E Clock Gate Control: Clock enabled */
135 CLOCK_EnableClock(kCLOCK_PortE);
136
137 /* PORTC0 (pin 33) is configured as FTM0_FLT0 */
138 PORT_SetPinMux(MB_FAULT_1_PORT, MB_FAULT_1_PIN, kPORT_MuxAlt6);
139
140 /* PORTC4 (pin 37) is configured as FTM0_CH3 */
141 PORT_SetPinMux(MB_PWM_BB_PORT, MB_PWM_BB_PIN, kPORT_MuxAlt4);
142
143 /* PORTC5 (pin 38) is configured as FTM0_CH2 */
144 PORT_SetPinMux(MB_PWM_BT_PORT, MB_PWM_BT_PIN, kPORT_MuxAlt7);
145
146 /* PORTD4 (pin 45) is configured as FTM0_CH4 */
147 PORT_SetPinMux(MB_PWM_CT_PORT, MB_PWM_CT_PIN, kPORT_MuxAlt4);
148
149 /* PORTD5 (pin 46) is configured as FTM0_CH5 */
150 PORT_SetPinMux(MB_PWM_CB_PORT, MB_PWM_CB_PIN, kPORT_MuxAlt4);
151
152 /* PORTE24 (pin 15) is configured as FTM0_CH0 */
153 PORT_SetPinMux(MB_PWM_AT_PORT, MB_PWM_AT_PIN, kPORT_MuxAlt3);
154
155 /* PORTE25 (pin 16) is configured as FTM0_CH1 */
156 PORT_SetPinMux(MB_PWM_AB_PORT, MB_PWM_AB_PIN, kPORT_MuxAlt3);
157
158 SIM->SOPT4 = ((SIM->SOPT4 &
159 /* Mask bits to zero which are setting */
160 (~(SIM_SOPT4_FTM0FLT0_MASK)))
161
162 /* FTM0 Fault 0 Select: FTM0_FLT0 pin. */
163 | SIM_SOPT4_FTM0FLT0(SOPT4_FTM0FLT0_FTM));
164
165 SIM->SOPT8 =
166 ((SIM->SOPT8 &
167 /* Mask bits to zero which are setting */
168 (~(SIM_SOPT8_FTM0OCH0SRC_MASK | SIM_SOPT8_FTM0OCH1SRC_MASK | SIM_SOPT8_FTM0OCH2SRC_MASK | SIM_SOPT8_FTM0OCH3SRC_MASK | SIM_SOPT8_FTM0OCH4SRC_MASK | SIM_SOPT8_FTM0OCH5SRC_MASK)))
169
170 /* FTM0 channel 0 output PWM/OCMP mode source select: FTM0CH0 pin is the output of FTM0 channel 0
171 * PWM/OCMP. */
172 | SIM_SOPT8_FTM0OCH0SRC(SOPT8_FTM0OCH0SRC_NO_MODULATION)
173
174 /* FTM0 channel 1 output PWM/OCMP mode source select: FTM0CH1 pin is the output of FTM0 channel 1
175 * PWM/OCMP. */
176 | SIM_SOPT8_FTM0OCH1SRC(SOPT8_FTM0OCH1SRC_NO_MODULATION)
177
178 /* FTM0 channel 2 output PWM/OCMP mode source select: FTM0CH2 pin is the output of FTM0 channel 2
179 * PWM/OCMP. */
180 | SIM_SOPT8_FTM0OCH2SRC(SOPT8_FTM0OCH2SRC_NO_MODULATION)
181
182 /* FTM0 channel 3 output PWM/OCMP mode source select: FTM0CH3 pin is the output of FTM0 channel 3
183 * PWM/OCMP. */
184 | SIM_SOPT8_FTM0OCH3SRC(SOPT8_FTM0OCH3SRC_NO_MODULATION)
185
186 /* FTM0 channel 4 output PWM/OCMP mode source select: FTM0CH4 pin is the output of FTM0 channel 4
187 * PWM/OCMP. */
188 | SIM_SOPT8_FTM0OCH4SRC(SOPT8_FTM0OCH4SRC_NO_MODULATION)
189
190 /* FTM0 channel 5 output PWM/OCMP mode source select: FTM0CH5 pin is the output of FTM0 channel 5
191 * PWM/OCMP. */
192 | SIM_SOPT8_FTM0OCH5SRC(SOPT8_FTM0OCH5SRC_NO_MODULATION));
193 }
194
195 /* clang-format off */
196 /*
197 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
198 MB_InitPFCPins:
199 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
200 - pin_list:
201 - {pin_num: '40', peripheral: CMP0, signal: 'IN, 1', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA}
202 - {pin_num: '24', peripheral: GPIOA, signal: 'GPIO, 18', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, direction: OUTPUT, gpio_init_state: 'false'}
203 - {pin_num: '48', peripheral: FTM0, signal: 'CH, 1', pin_signal: PTD7/FTM4_CH1/UART0_TX/FTM0_CH1/FTM1_CH1/FTM0_FLT1/SPI0_SIN, direction: OUTPUT}
204 - {pin_num: '47', peripheral: FTM0, signal: 'CH, 0', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, direction: OUTPUT}
205 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
206 */
207 /* clang-format on */
208
209 /* FUNCTION ************************************************************************************************************
210 *
211 * Function Name : MB_InitPFCPins
212 * Description : Configures pin routing and optionally pin electrical features.
213 *
214 * END ****************************************************************************************************************/
MB_InitPFCPins(void)215 void MB_InitPFCPins(void)
216 {
217 /* Port A Clock Gate Control: Clock enabled */
218 CLOCK_EnableClock(kCLOCK_PortA);
219 /* Port C Clock Gate Control: Clock enabled */
220 CLOCK_EnableClock(kCLOCK_PortC);
221 /* Port D Clock Gate Control: Clock enabled */
222 CLOCK_EnableClock(kCLOCK_PortD);
223
224 gpio_pin_config_t RELAY_config = {
225 .pinDirection = kGPIO_DigitalOutput,
226 .outputLogic = 0U
227 };
228 /* Initialize GPIO functionality on pin PTA18 (pin 24) */
229 GPIO_PinInit(MB_RELAY_GPIO, MB_RELAY_PIN, &RELAY_config);
230
231 /* PORTA18 (pin 24) is configured as PTA18 */
232 PORT_SetPinMux(MB_RELAY_PORT, MB_RELAY_PIN, kPORT_MuxAsGpio);
233
234 /* PORTC7 (pin 40) is configured as CMP0_IN1 */
235 PORT_SetPinMux(MB_PFC_ZC_2_PORT, MB_PFC_ZC_2_PIN, kPORT_PinDisabledOrAnalog);
236
237 /* PORTD6 (pin 47) is configured as FTM0_CH0 */
238 PORT_SetPinMux(MB_PWM_PFC2_PORT, MB_PWM_PFC2_PIN, kPORT_MuxAlt4);
239
240 /* PORTD7 (pin 48) is configured as FTM0_CH1 */
241 PORT_SetPinMux(MB_PWM_PFC1_PORT, MB_PWM_PFC1_PIN, kPORT_MuxAlt4);
242
243 SIM->SOPT8 = ((SIM->SOPT8 &
244 /* Mask bits to zero which are setting */
245 (~(SIM_SOPT8_FTM0OCH0SRC_MASK | SIM_SOPT8_FTM0OCH1SRC_MASK)))
246
247 /* FTM0 channel 0 output PWM/OCMP mode source select: FTM0CH0 pin is the output of FTM0 channel
248 * 0 PWM/OCMP. */
249 | SIM_SOPT8_FTM0OCH0SRC(SOPT8_FTM0OCH0SRC_NO_MODULATION)
250
251 /* FTM0 channel 1 output PWM/OCMP mode source select: FTM0CH1 pin is the output of FTM0 channel
252 * 1 PWM/OCMP. */
253 | SIM_SOPT8_FTM0OCH1SRC(SOPT8_FTM0OCH1SRC_NO_MODULATION));
254 }
255
256 /* clang-format off */
257 /*
258 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
259 MB_InitANA_SENSPins:
260 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
261 - pin_list:
262 - {pin_num: '5', peripheral: ADC0, signal: 'SE, 6', pin_signal: ADC0_SE6/ADC1_SE1/ADC1_DP1/PTE18/LLWU_P20/SPI0_SOUT/UART1_CTS_b/I2C0_SDA/SPI0_SIN}
263 - {pin_num: '8', peripheral: ADC0, signal: 'SE, 4', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX}
264 - {pin_num: '34', peripheral: ADC1, signal: 'SE, 3', pin_signal: ADC1_SE3/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FTM2_CH0}
265 - {pin_num: '28', peripheral: ADC0, signal: 'SE, 9', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX}
266 - {pin_num: '7', peripheral: ADC0, signal: 'SE, 0', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX}
267 - {pin_num: '14', peripheral: ADC1, signal: 'SE, 4', pin_signal: ADC1_SE4/CMP1_IN4/DAC0_OUT/PTE30/FTM0_CH3/FTM_CLKIN1}
268 - {pin_num: '6', peripheral: ADC1, signal: 'SE, 7', pin_signal: ADC0_SE7/ADC1_SE7/ADC1_DM1/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL/SPI0_SOUT}
269 - {pin_num: '39', peripheral: CMP0, signal: 'IN, 0', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL}
270 - {pin_num: '30', peripheral: ADC1, signal: 'SE, 2', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0}
271 - {pin_num: '35', peripheral: ADC0, signal: 'SE, 11', pin_signal: ADC0_SE11/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FTM2_CH1}
272 - {pin_num: '4', peripheral: ADC0, signal: 'SE, 5', pin_signal: ADC0_DM1/ADC0_SE5/ADC1_SE5/PTE17/LLWU_P19/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3}
273 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
274 */
275 /* clang-format on */
276
277 /* FUNCTION ************************************************************************************************************
278 *
279 * Function Name : MB_InitANA_SENSPins
280 * Description : Configures pin routing and optionally pin electrical features.
281 *
282 * END ****************************************************************************************************************/
MB_InitANA_SENSPins(void)283 void MB_InitANA_SENSPins(void)
284 {
285 /* Port B Clock Gate Control: Clock enabled */
286 CLOCK_EnableClock(kCLOCK_PortB);
287 /* Port C Clock Gate Control: Clock enabled */
288 CLOCK_EnableClock(kCLOCK_PortC);
289 /* Port E Clock Gate Control: Clock enabled */
290 CLOCK_EnableClock(kCLOCK_PortE);
291
292 /* PORTB1 (pin 28) is configured as ADC0_SE9 */
293 PORT_SetPinMux(MB_I_PH_B_PORT, MB_I_PH_B_PIN, kPORT_PinDisabledOrAnalog);
294
295 /* PORTB3 (pin 30) is configured as ADC1_SE2 */
296 PORT_SetPinMux(MB_V_IN_PORT, MB_V_IN_PIN, kPORT_PinDisabledOrAnalog);
297
298 /* PORTC1 (pin 34) is configured as ADC1_SE3 */
299 PORT_SetPinMux(MB_TEMP_IPM_PORT, MB_TEMP_IPM_PIN, kPORT_PinDisabledOrAnalog);
300
301 /* PORTC2 (pin 35) is configured as ADC0_SE11 */
302 PORT_SetPinMux(MB_I_PFC1_PORT, MB_I_PFC1_PIN, kPORT_PinDisabledOrAnalog);
303
304 /* PORTC6 (pin 39) is configured as CMP0_IN0 */
305 PORT_SetPinMux(MB_TACHO_PORT, MB_TACHO_PIN, kPORT_PinDisabledOrAnalog);
306
307 /* PORTE17 (pin 4) is configured as ADC0_SE5 */
308 PORT_SetPinMux(MB_I_PFC2_PORT, MB_I_PFC2_PIN, kPORT_PinDisabledOrAnalog);
309
310 /* PORTE18 (pin 5) is configured as ADC0_SE6 */
311 PORT_SetPinMux(MB_I_DCB_PORT, MB_I_DCB_PIN, kPORT_PinDisabledOrAnalog);
312
313 /* PORTE19 (pin 6) is configured as ADC1_SE7 */
314 PORT_SetPinMux(MB_I_PH_C_PORT, MB_I_PH_C_PIN, kPORT_PinDisabledOrAnalog);
315
316 /* PORTE20 (pin 7) is configured as ADC0_SE0 */
317 PORT_SetPinMux(MB_I_PH_C_2_PORT, MB_I_PH_C_2_PIN, kPORT_PinDisabledOrAnalog);
318
319 /* PORTE21 (pin 8) is configured as ADC0_SE4 */
320 PORT_SetPinMux(MB_U_DCB_PORT, MB_U_DCB_PIN, kPORT_PinDisabledOrAnalog);
321
322 /* PORTE30 (pin 14) is configured as ADC1_SE4 */
323 PORT_SetPinMux(MB_I_PH_A_PORT, MB_I_PH_A_PIN, kPORT_PinDisabledOrAnalog);
324 }
325
326 /* clang-format off */
327 /*
328 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
329 MB_InitBEMFPins:
330 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
331 - pin_list:
332 - {pin_num: '27', peripheral: ADC0, signal: 'SE, 8', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX}
333 - {pin_num: '29', peripheral: ADC0, signal: 'SE, 10', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3}
334 - {pin_num: '3', peripheral: ADC0, signal: 'SE, 1', pin_signal: ADC0_SE1/ADC0_DP1/ADC1_SE0/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3}
335 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
336 */
337 /* clang-format on */
338
339 /* FUNCTION ************************************************************************************************************
340 *
341 * Function Name : MB_InitBEMFPins
342 * Description : Configures pin routing and optionally pin electrical features.
343 *
344 * END ****************************************************************************************************************/
MB_InitBEMFPins(void)345 void MB_InitBEMFPins(void)
346 {
347 /* Port B Clock Gate Control: Clock enabled */
348 CLOCK_EnableClock(kCLOCK_PortB);
349 /* Port E Clock Gate Control: Clock enabled */
350 CLOCK_EnableClock(kCLOCK_PortE);
351
352 /* PORTB0 (pin 27) is configured as ADC0_SE8 */
353 PORT_SetPinMux(MB_BEMF_A_PORT, MB_BEMF_A_PIN, kPORT_PinDisabledOrAnalog);
354
355 /* PORTB2 (pin 29) is configured as ADC0_SE10 */
356 PORT_SetPinMux(MB_BEMF_B_PORT, MB_BEMF_B_PIN, kPORT_PinDisabledOrAnalog);
357
358 /* PORTE16 (pin 3) is configured as ADC0_SE1 */
359 PORT_SetPinMux(MB_BEMF_C_PORT, MB_BEMF_C_PIN, kPORT_PinDisabledOrAnalog);
360 }
361
362 /* clang-format off */
363 /*
364 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
365 MB_InitENCPins:
366 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
367 - pin_list:
368 - {pin_num: '13', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, direction: INPUT}
369 - {pin_num: '18', peripheral: FTM2, signal: 'QD_PH, A', pin_signal: PTA1/UART0_RX/FTM2_CH0/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/FTM4_CH0}
370 - {pin_num: '19', peripheral: FTM2, signal: 'QD_PH, B', pin_signal: PTA2/UART0_TX/FTM2_CH1/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/FTM4_CH1}
371 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
372 */
373 /* clang-format on */
374
375 /* FUNCTION ************************************************************************************************************
376 *
377 * Function Name : MB_InitENCPins
378 * Description : Configures pin routing and optionally pin electrical features.
379 *
380 * END ****************************************************************************************************************/
MB_InitENCPins(void)381 void MB_InitENCPins(void)
382 {
383 /* Port A Clock Gate Control: Clock enabled */
384 CLOCK_EnableClock(kCLOCK_PortA);
385 /* Port E Clock Gate Control: Clock enabled */
386 CLOCK_EnableClock(kCLOCK_PortE);
387
388 gpio_pin_config_t ENC_INDEX_config = {
389 .pinDirection = kGPIO_DigitalInput,
390 .outputLogic = 0U
391 };
392 /* Initialize GPIO functionality on pin PTE29 (pin 13) */
393 GPIO_PinInit(MB_ENC_INDEX_GPIO, MB_ENC_INDEX_PIN, &ENC_INDEX_config);
394
395 /* PORTA1 (pin 18) is configured as FTM2_QD_PHA */
396 PORT_SetPinMux(MB_ENC_PHASE_A_PORT, MB_ENC_PHASE_A_PIN, kPORT_MuxAlt5);
397
398 /* PORTA2 (pin 19) is configured as FTM2_QD_PHB */
399 PORT_SetPinMux(MB_ENC_PHASE_B_PORT, MB_ENC_PHASE_B_PIN, kPORT_MuxAlt5);
400
401 /* PORTE29 (pin 13) is configured as PTE29 */
402 PORT_SetPinMux(MB_ENC_INDEX_PORT, MB_ENC_INDEX_PIN, kPORT_MuxAsGpio);
403 }
404
405 /* clang-format off */
406 /*
407 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
408 MB_InitUSB_UARTPins:
409 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
410 - pin_list:
411 - {pin_num: '32', peripheral: UART0, signal: TX, pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, direction: OUTPUT}
412 - {pin_num: '31', peripheral: UART0, signal: RX, pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN}
413 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
414 */
415 /* clang-format on */
416
417 /* FUNCTION ************************************************************************************************************
418 *
419 * Function Name : MB_InitUSB_UARTPins
420 * Description : Configures pin routing and optionally pin electrical features.
421 *
422 * END ****************************************************************************************************************/
MB_InitUSB_UARTPins(void)423 void MB_InitUSB_UARTPins(void)
424 {
425 /* Port B Clock Gate Control: Clock enabled */
426 CLOCK_EnableClock(kCLOCK_PortB);
427
428 /* PORTB16 (pin 31) is configured as UART0_RX */
429 PORT_SetPinMux(MB_RXD_PORT, MB_RXD_PIN, kPORT_MuxAlt3);
430
431 /* PORTB17 (pin 32) is configured as UART0_TX */
432 PORT_SetPinMux(MB_TXD_PORT, MB_TXD_PIN, kPORT_MuxAlt3);
433
434 SIM->SOPT5 = ((SIM->SOPT5 &
435 /* Mask bits to zero which are setting */
436 (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))
437
438 /* UART 0 Transmit Data Source Select: UART0_TX pin. */
439 | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)
440
441 /* UART 0 Receive Data Source Select: UART0_RX pin. */
442 | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX));
443 }
444
445 /* clang-format off */
446 /*
447 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
448 MB_InitEXT_UARTPins:
449 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
450 - pin_list:
451 - {pin_num: '42', peripheral: UART1, signal: TX, pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, identifier: TXD_1, direction: OUTPUT}
452 - {pin_num: '41', peripheral: UART1, signal: RX, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, identifier: RXD_1}
453 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
454 */
455 /* clang-format on */
456
457 /* FUNCTION ************************************************************************************************************
458 *
459 * Function Name : MB_InitEXT_UARTPins
460 * Description : Configures pin routing and optionally pin electrical features.
461 *
462 * END ****************************************************************************************************************/
MB_InitEXT_UARTPins(void)463 void MB_InitEXT_UARTPins(void)
464 {
465 /* Port D Clock Gate Control: Clock enabled */
466 CLOCK_EnableClock(kCLOCK_PortD);
467
468 /* PORTD0 (pin 41) is configured as UART1_RX */
469 PORT_SetPinMux(MB_RXD_1_PORT, MB_RXD_1_PIN, kPORT_MuxAlt5);
470
471 /* PORTD1 (pin 42) is configured as UART1_TX */
472 PORT_SetPinMux(MB_TXD_1_PORT, MB_TXD_1_PIN, kPORT_MuxAlt5);
473
474 SIM->SOPT5 = ((SIM->SOPT5 &
475 /* Mask bits to zero which are setting */
476 (~(SIM_SOPT5_UART1TXSRC_MASK | SIM_SOPT5_UART1RXSRC_MASK)))
477
478 /* UART 1 Transmit Data Source Select: UART1_TX pin. */
479 | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX)
480
481 /* UART 1 Receive Data Source Select: UART1_RX pin. */
482 | SIM_SOPT5_UART1RXSRC(SOPT5_UART1RXSRC_UART_RX));
483 }
484
485 /* clang-format off */
486 /*
487 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
488 MB_InitBRAKEPins:
489 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
490 - pin_list:
491 - {pin_num: '44', peripheral: GPIOD, signal: 'GPIO, 3', pin_signal: PTD3/SPI0_SIN/UART0_TX/FTM0_CH3/FTM3_CH3/I2C0_SDA, direction: OUTPUT, gpio_init_state: 'false'}
492 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
493 */
494 /* clang-format on */
495
496 /* FUNCTION ************************************************************************************************************
497 *
498 * Function Name : MB_InitBRAKEPins
499 * Description : Configures pin routing and optionally pin electrical features.
500 *
501 * END ****************************************************************************************************************/
MB_InitBRAKEPins(void)502 void MB_InitBRAKEPins(void)
503 {
504 /* Port D Clock Gate Control: Clock enabled */
505 CLOCK_EnableClock(kCLOCK_PortD);
506
507 gpio_pin_config_t MCU_BRAKE_config = {
508 .pinDirection = kGPIO_DigitalOutput,
509 .outputLogic = 0U
510 };
511 /* Initialize GPIO functionality on pin PTD3 (pin 44) */
512 GPIO_PinInit(MB_MCU_BRAKE_GPIO, MB_MCU_BRAKE_PIN, &MCU_BRAKE_config);
513
514 /* PORTD3 (pin 44) is configured as PTD3 */
515 PORT_SetPinMux(MB_MCU_BRAKE_PORT, MB_MCU_BRAKE_PIN, kPORT_MuxAsGpio);
516 }
517
518 /* clang-format off */
519 /*
520 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
521 MB_InitMISCPins:
522 - options: {prefix: MB_, coreID: core0, enableClock: 'true'}
523 - pin_list:
524 - {pin_num: '25', peripheral: GPIOA, signal: 'GPIO, 19', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, direction: INPUT}
525 - {peripheral: ADC0, signal: 'TRG, A', pin_signal: PDB0_CH0_TriggerA}
526 - {peripheral: ADC0, signal: 'TRG, B', pin_signal: PDB0_CH0_TriggerB}
527 - {peripheral: ADC1, signal: 'TRG, A', pin_signal: PDB0_CH1_TriggerA}
528 - {peripheral: ADC1, signal: 'TRG, B', pin_signal: PDB0_CH1_TriggerB}
529 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
530 */
531 /* clang-format on */
532
533 /* FUNCTION ************************************************************************************************************
534 *
535 * Function Name : MB_InitMISCPins
536 * Description : Configures pin routing and optionally pin electrical features.
537 *
538 * END ****************************************************************************************************************/
MB_InitMISCPins(void)539 void MB_InitMISCPins(void)
540 {
541 /* Port A Clock Gate Control: Clock enabled */
542 CLOCK_EnableClock(kCLOCK_PortA);
543
544 gpio_pin_config_t FAULT_2_config = {
545 .pinDirection = kGPIO_DigitalInput,
546 .outputLogic = 0U
547 };
548 /* Initialize GPIO functionality on pin PTA19 (pin 25) */
549 GPIO_PinInit(MB_FAULT_2_GPIO, MB_FAULT_2_PIN, &FAULT_2_config);
550
551 /* PORTA19 (pin 25) is configured as PTA19 */
552 PORT_SetPinMux(MB_FAULT_2_PORT, MB_FAULT_2_PIN, kPORT_MuxAsGpio);
553
554 SIM->SOPT7 = ((SIM->SOPT7 &
555 /* Mask bits to zero which are setting */
556 (~(SIM_SOPT7_ADC0ALTTRGEN_MASK | SIM_SOPT7_ADC1ALTTRGEN_MASK)))
557
558 /* Enable alternative conversion triggers for ADC0.
559 * : PDB0 CH0 triggers ADC0. */
560 | SIM_SOPT7_ADC0ALTTRGEN(SOPT7_ADC0ALTTRGEN_PDB0)
561
562 /* Enable alternative conversion triggers for ADC1.
563 * : PDB0 CH1 triggers ADC1. */
564 | SIM_SOPT7_ADC1ALTTRGEN(SOPT7_ADC1ALTTRGEN_PDB0));
565 }
566
567 /* clang-format off */
568 /*
569 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
570 BOARD_InitPins:
571 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
572 - pin_list: []
573 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
574 */
575 /* clang-format on */
576
577 /* FUNCTION ************************************************************************************************************
578 *
579 * Function Name : BOARD_InitPins
580 * Description : Configures pin routing and optionally pin electrical features.
581 *
582 * END ****************************************************************************************************************/
BOARD_InitPins(void)583 void BOARD_InitPins(void)
584 {
585 }
586
587 /* clang-format off */
588 /*
589 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
590 BOARD_InitDEBUG_UARTPins:
591 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
592 - pin_list:
593 - {pin_num: '41', peripheral: UART1, signal: RX, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, identifier: UART_RX_TGTMCU}
594 - {pin_num: '42', peripheral: UART1, signal: TX, pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, identifier: UART_TX_TGTMCU, direction: OUTPUT}
595 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
596 */
597 /* clang-format on */
598
599 /* FUNCTION ************************************************************************************************************
600 *
601 * Function Name : BOARD_InitDEBUG_UARTPins
602 * Description : Configures pin routing and optionally pin electrical features.
603 *
604 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)605 void BOARD_InitDEBUG_UARTPins(void)
606 {
607 /* Port D Clock Gate Control: Clock enabled */
608 CLOCK_EnableClock(kCLOCK_PortD);
609
610 /* PORTD0 (pin 41) is configured as UART1_RX */
611 PORT_SetPinMux(BOARD_UART_RX_TGTMCU_PORT, BOARD_UART_RX_TGTMCU_PIN, kPORT_MuxAlt5);
612
613 /* PORTD1 (pin 42) is configured as UART1_TX */
614 PORT_SetPinMux(BOARD_UART_TX_TGTMCU_PORT, BOARD_UART_TX_TGTMCU_PIN, kPORT_MuxAlt5);
615
616 SIM->SOPT5 = ((SIM->SOPT5 &
617 /* Mask bits to zero which are setting */
618 (~(SIM_SOPT5_UART1TXSRC_MASK | SIM_SOPT5_UART1RXSRC_MASK)))
619
620 /* UART 1 Transmit Data Source Select: UART1_TX pin. */
621 | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX)
622
623 /* UART 1 Receive Data Source Select: UART1_RX pin. */
624 | SIM_SOPT5_UART1RXSRC(SOPT5_UART1RXSRC_UART_RX));
625 }
626
627 /* clang-format off */
628 /*
629 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
630 BOARD_InitLEDsPins:
631 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
632 - pin_list:
633 - {pin_num: '36', peripheral: GPIOC, signal: 'GPIO, 3', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/FTM3_FLT0, direction: OUTPUT, gpio_init_state: 'false'}
634 - {pin_num: '43', peripheral: GPIOD, signal: 'GPIO, 2', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART0_RX/FTM0_CH2/FTM3_CH2/I2C0_SCL, direction: OUTPUT, gpio_init_state: 'false'}
635 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
636 */
637 /* clang-format on */
638
639 /* FUNCTION ************************************************************************************************************
640 *
641 * Function Name : BOARD_InitLEDsPins
642 * Description : Configures pin routing and optionally pin electrical features.
643 *
644 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)645 void BOARD_InitLEDsPins(void)
646 {
647 /* Port C Clock Gate Control: Clock enabled */
648 CLOCK_EnableClock(kCLOCK_PortC);
649 /* Port D Clock Gate Control: Clock enabled */
650 CLOCK_EnableClock(kCLOCK_PortD);
651
652 gpio_pin_config_t LED_RED_config = {
653 .pinDirection = kGPIO_DigitalOutput,
654 .outputLogic = 0U
655 };
656 /* Initialize GPIO functionality on pin PTC3 (pin 36) */
657 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
658
659 gpio_pin_config_t LED_GREEN_config = {
660 .pinDirection = kGPIO_DigitalOutput,
661 .outputLogic = 0U
662 };
663 /* Initialize GPIO functionality on pin PTD2 (pin 43) */
664 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
665
666 /* PORTC3 (pin 36) is configured as PTC3 */
667 PORT_SetPinMux(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, kPORT_MuxAsGpio);
668
669 /* PORTD2 (pin 43) is configured as PTD2 */
670 PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio);
671 }
672 /***********************************************************************************************************************
673 * EOF
674 **********************************************************************************************************************/
675
