1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40 /* clang-format off */
41 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42 !!GlobalInfo
43 product: Clocks v4.1
44 processor: MKV11Z128xxx7
45 package_id: MKV11Z128VLF7
46 mcu_data: ksdk2_0
47 processor_version: 4.0.0
48 board: HVP-KV11Z75M
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50 /* clang-format on */
51
52 #include "fsl_smc.h"
53 #include "clock_config.h"
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
59 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
60 #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
61
62 /*******************************************************************************
63 * Variables
64 ******************************************************************************/
65 /* System clock frequency. */
66 extern uint32_t SystemCoreClock;
67
68 /*******************************************************************************
69 * Code
70 ******************************************************************************/
71 /*FUNCTION**********************************************************************
72 *
73 * Function Name : CLOCK_CONFIG_FllStableDelay
74 * Description : This function is used to delay for FLL stable.
75 *
76 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)77 static void CLOCK_CONFIG_FllStableDelay(void)
78 {
79 uint32_t i = 30000U;
80 while (i--)
81 {
82 __NOP();
83 }
84 }
85
86 /*******************************************************************************
87 ************************ BOARD_InitBootClocks function ************************
88 ******************************************************************************/
BOARD_InitBootClocks(void)89 void BOARD_InitBootClocks(void)
90 {
91 BOARD_BootClockRUN();
92 }
93
94 /*******************************************************************************
95 ********************** Configuration BOARD_BootClockRUN ***********************
96 ******************************************************************************/
97 /* clang-format off */
98 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
99 !!Configuration
100 name: BOARD_BootClockRUN
101 called_from_default_init: true
102 outputs:
103 - {id: Bus_clock.outFreq, value: 20.97152 MHz}
104 - {id: Core_clock.outFreq, value: 62.91456 MHz}
105 - {id: ERCLK32K.outFreq, value: 1 kHz}
106 - {id: LPO_clock.outFreq, value: 1 kHz}
107 - {id: MCGFLLCLK.outFreq, value: 62.91456 MHz}
108 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
109 - {id: System_clock.outFreq, value: 62.91456 MHz}
110 settings:
111 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
112 - {id: MCG.FLL_mul.scale, value: '1920', locked: true}
113 - {id: MCG.FRDIV.scale, value: '256'}
114 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
115 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
116 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
117 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
118 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
119 - {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
120 - {id: SIM.FTMFFCLKSEL.sel, value: OSC.OSCERCLK}
121 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
122 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
123 - {id: SIM.OUTDIV4.scale, value: '3', locked: true}
124 - {id: SIM.OUTDIV5.scale, value: '1'}
125 sources:
126 - {id: OSC.OSC.outFreq, value: 10 MHz}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128 /* clang-format on */
129
130 /*******************************************************************************
131 * Variables for BOARD_BootClockRUN configuration
132 ******************************************************************************/
133 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
134 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
135 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
136 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
137 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
138 .frdiv = 0x3U, /* FLL reference clock divider: divided by 256 */
139 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
140 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
141 };
142 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
143 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
144 .clkdiv1 = 0x20000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
145 };
146 const osc_config_t oscConfig_BOARD_BootClockRUN = {
147 .freq = 0U, /* Oscillator frequency: 0Hz */
148 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
149 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
150 .oscerConfig = {
151 .enableMode =
152 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
153 }};
154
155 /*******************************************************************************
156 * Code for BOARD_BootClockRUN configuration
157 ******************************************************************************/
BOARD_BootClockRUN(void)158 void BOARD_BootClockRUN(void)
159 {
160 /* Set the system clock dividers in SIM to safe value. */
161 CLOCK_SetSimSafeDivs();
162 /* Set MCG to FEI mode. */
163 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
164 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
165 CLOCK_CONFIG_FllStableDelay);
166 #else
167 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
168 #endif
169 /* Configure the Internal Reference clock (MCGIRCLK). */
170 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
171 mcgConfig_BOARD_BootClockRUN.fcrdiv);
172 /* Set the clock configuration in SIM module. */
173 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
174 /* Set SystemCoreClock variable. */
175 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
176 }
177
178 /*******************************************************************************
179 ********************* Configuration BOARD_BootClockVLPR ***********************
180 ******************************************************************************/
181 /* clang-format off */
182 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
183 !!Configuration
184 name: BOARD_BootClockVLPR
185 outputs:
186 - {id: Bus_clock.outFreq, value: 800 kHz}
187 - {id: Core_clock.outFreq, value: 4 MHz}
188 - {id: ERCLK32K.outFreq, value: 1 kHz}
189 - {id: LPO_clock.outFreq, value: 1 kHz}
190 - {id: MCGIRCLK.outFreq, value: 4 MHz}
191 - {id: System_clock.outFreq, value: 4 MHz}
192 settings:
193 - {id: MCGMode, value: BLPI}
194 - {id: powerMode, value: VLPR}
195 - {id: MCG.CLKS.sel, value: MCG.IRCS}
196 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
197 - {id: MCG.FRDIV.scale, value: '32'}
198 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
199 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
200 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
201 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
202 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
203 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
204 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
205 - {id: SIM.OUTDIV4.scale, value: '5'}
206 - {id: SIM.OUTDIV5.scale, value: '1', locked: true}
207 sources:
208 - {id: OSC.OSC.outFreq, value: 10 MHz}
209 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
210 /* clang-format on */
211
212 /*******************************************************************************
213 * Variables for BOARD_BootClockVLPR configuration
214 ******************************************************************************/
215 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
216 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
217 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
218 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
219 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
220 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
221 .drs = kMCG_DrsLow, /* Low frequency range */
222 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
223 };
224 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
225 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
226 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
227 };
228 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
229 .freq = 0U, /* Oscillator frequency: 0Hz */
230 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
231 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
232 .oscerConfig = {
233 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
234 }};
235
236 /*******************************************************************************
237 * Code for BOARD_BootClockVLPR configuration
238 ******************************************************************************/
BOARD_BootClockVLPR(void)239 void BOARD_BootClockVLPR(void)
240 {
241 /* Set the system clock dividers in SIM to safe value. */
242 CLOCK_SetSimSafeDivs();
243 /* Set MCG to BLPI mode. */
244 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
245 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
246 /* Set the clock configuration in SIM module. */
247 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
248 /* Set VLPR power mode. */
249 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
250 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
251 SMC_SetPowerModeVlpr(SMC, false);
252 #else
253 SMC_SetPowerModeVlpr(SMC);
254 #endif
255 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
256 {
257 }
258 /* Set SystemCoreClock variable. */
259 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
260 }
261
