1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MKV11Z128xxx7
46 package_id: MKV11Z128VLF7
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50 /* clang-format on */
51
52 #include "fsl_smc.h"
53 #include "clock_config.h"
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
59 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
60 #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
61
62 /*******************************************************************************
63 * Variables
64 ******************************************************************************/
65 /* System clock frequency. */
66 extern uint32_t SystemCoreClock;
67
68 /*******************************************************************************
69 * Code
70 ******************************************************************************/
71 /*FUNCTION**********************************************************************
72 *
73 * Function Name : CLOCK_CONFIG_FllStableDelay
74 * Description : This function is used to delay for FLL stable.
75 *
76 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)77 static void CLOCK_CONFIG_FllStableDelay(void)
78 {
79 uint32_t i = 30000U;
80 while (i--)
81 {
82 __NOP();
83 }
84 }
85
86 /*******************************************************************************
87 ************************ BOARD_InitBootClocks function ************************
88 ******************************************************************************/
BOARD_InitBootClocks(void)89 void BOARD_InitBootClocks(void)
90 {
91 BOARD_BootClockRUN();
92 }
93
94 /*******************************************************************************
95 ********************** Configuration BOARD_BootClockRUN ***********************
96 ******************************************************************************/
97 /* clang-format off */
98 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
99 !!Configuration
100 name: BOARD_BootClockRUN
101 called_from_default_init: true
102 outputs:
103 - {id: Bus_clock.outFreq, value: 20.97152 MHz}
104 - {id: Core_clock.outFreq, value: 62.91456 MHz}
105 - {id: ERCLK32K.outFreq, value: 1 kHz}
106 - {id: LPO_clock.outFreq, value: 1 kHz}
107 - {id: MCGFLLCLK.outFreq, value: 62.91456 MHz}
108 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
109 - {id: System_clock.outFreq, value: 62.91456 MHz}
110 settings:
111 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
112 - {id: MCG.FLL_mul.scale, value: '1920', locked: true}
113 - {id: MCG.FRDIV.scale, value: '256'}
114 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
115 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
116 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
117 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
118 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
119 - {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
120 - {id: SIM.FTMFFCLKSEL.sel, value: OSC.OSCERCLK}
121 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
122 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
123 - {id: SIM.OUTDIV4.scale, value: '3', locked: true}
124 - {id: SIM.OUTDIV5.scale, value: '1'}
125 sources:
126 - {id: OSC.OSC.outFreq, value: 10 MHz}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128 /* clang-format on */
129
130 /*******************************************************************************
131 * Variables for BOARD_BootClockRUN configuration
132 ******************************************************************************/
133 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
134 {
135 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
136 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
137 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
138 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
139 .frdiv = 0x3U, /* FLL reference clock divider: divided by 256 */
140 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
141 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
142 };
143 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
144 {
145 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
146 .clkdiv1 = 0x20000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /3, OUTDIV5: /1, disabled */
147 };
148 const osc_config_t oscConfig_BOARD_BootClockRUN =
149 {
150 .freq = 0U, /* Oscillator frequency: 0Hz */
151 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
152 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
153 .oscerConfig =
154 {
155 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
156 }
157 };
158
159 /*******************************************************************************
160 * Code for BOARD_BootClockRUN configuration
161 ******************************************************************************/
BOARD_BootClockRUN(void)162 void BOARD_BootClockRUN(void)
163 {
164 /* Set the system clock dividers in SIM to safe value. */
165 CLOCK_SetSimSafeDivs();
166 /* Set MCG to FEI mode. */
167 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
168 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
169 mcgConfig_BOARD_BootClockRUN.drs,
170 CLOCK_CONFIG_FllStableDelay);
171 #else
172 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
173 CLOCK_CONFIG_FllStableDelay);
174 #endif
175 /* Configure the Internal Reference clock (MCGIRCLK). */
176 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
177 mcgConfig_BOARD_BootClockRUN.ircs,
178 mcgConfig_BOARD_BootClockRUN.fcrdiv);
179 /* Set the clock configuration in SIM module. */
180 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
181 /* Set SystemCoreClock variable. */
182 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
183 }
184
185 /*******************************************************************************
186 ********************* Configuration BOARD_BootClockVLPR ***********************
187 ******************************************************************************/
188 /* clang-format off */
189 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
190 !!Configuration
191 name: BOARD_BootClockVLPR
192 outputs:
193 - {id: Bus_clock.outFreq, value: 800 kHz}
194 - {id: Core_clock.outFreq, value: 4 MHz}
195 - {id: ERCLK32K.outFreq, value: 1 kHz}
196 - {id: LPO_clock.outFreq, value: 1 kHz}
197 - {id: MCGIRCLK.outFreq, value: 4 MHz}
198 - {id: System_clock.outFreq, value: 4 MHz}
199 settings:
200 - {id: MCGMode, value: BLPI}
201 - {id: powerMode, value: VLPR}
202 - {id: MCG.CLKS.sel, value: MCG.IRCS}
203 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
204 - {id: MCG.FRDIV.scale, value: '32'}
205 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
206 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
207 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
208 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
209 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
210 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
211 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
212 - {id: SIM.OUTDIV4.scale, value: '5'}
213 - {id: SIM.OUTDIV5.scale, value: '1', locked: true}
214 sources:
215 - {id: OSC.OSC.outFreq, value: 10 MHz}
216 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
217 /* clang-format on */
218
219 /*******************************************************************************
220 * Variables for BOARD_BootClockVLPR configuration
221 ******************************************************************************/
222 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
223 {
224 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
225 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
226 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
227 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
228 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
229 .drs = kMCG_DrsLow, /* Low frequency range */
230 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
231 };
232 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
233 {
234 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
235 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5, OUTDIV5: /1, disabled */
236 };
237 const osc_config_t oscConfig_BOARD_BootClockVLPR =
238 {
239 .freq = 0U, /* Oscillator frequency: 0Hz */
240 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
241 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
242 .oscerConfig =
243 {
244 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
245 }
246 };
247
248 /*******************************************************************************
249 * Code for BOARD_BootClockVLPR configuration
250 ******************************************************************************/
BOARD_BootClockVLPR(void)251 void BOARD_BootClockVLPR(void)
252 {
253 /* Set the system clock dividers in SIM to safe value. */
254 CLOCK_SetSimSafeDivs();
255 /* Set MCG to BLPI mode. */
256 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
257 mcgConfig_BOARD_BootClockVLPR.ircs,
258 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
259 /* Set the clock configuration in SIM module. */
260 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
261 /* Set VLPR power mode. */
262 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
263 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
264 SMC_SetPowerModeVlpr(SMC, false);
265 #else
266 SMC_SetPowerModeVlpr(SMC);
267 #endif
268 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
269 {
270 }
271 /* Set SystemCoreClock variable. */
272 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
273 }
274
275
