1 /*
2  * Copyright 2018-2019 NXP.
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /* clang-format off */
9 /*
10  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11 !!GlobalInfo
12 product: Pins v5.0
13 processor: MKV31F512xxx12
14 package_id: MKV31F512VLL12
15 mcu_data: ksdk2_0
16 processor_version: 0.0.18
17 board: FRDM-KV31F
18 pin_labels:
19 - {pin_num: '9', pin_signal: VSS9, label: GND}
20 - {pin_num: '25', pin_signal: VSSA, label: GND}
21 - {pin_num: '29', pin_signal: VSS29, label: GND}
22 - {pin_num: '41', pin_signal: VSS41, label: GND}
23 - {pin_num: '60', pin_signal: VSS60, label: GND}
24 - {pin_num: '74', pin_signal: VSS74, label: GND}
25 - {pin_num: '88', pin_signal: VSS88, label: GND}
26 - {pin_num: '8', pin_signal: VDD8, label: 'J9[1]/P3V3_KV31'}
27 - {pin_num: '30', pin_signal: VDD30, label: 'J9[1]/P3V3_KV31'}
28 - {pin_num: '40', pin_signal: VDD40, label: 'J9[1]/P3V3_KV31'}
29 - {pin_num: '61', pin_signal: VDD61, label: 'J9[1]/P3V3_KV31'}
30 - {pin_num: '75', pin_signal: VDD75, label: 'J9[1]/P3V3_KV31'}
31 - {pin_num: '89', pin_signal: VDD89, label: 'J9[1]/P3V3_KV31'}
32 - {pin_num: '24', pin_signal: VREFL, label: GND}
33 - {pin_num: '23', pin_signal: VREFH, label: 'J9[1]/P3V3_KV31'}
34 - {pin_num: '22', pin_signal: VDDA, label: 'J9[1]/P3V3_KV31'}
35 - {pin_num: '49', pin_signal: VSS49, label: GND}
36 - {pin_num: '48', pin_signal: VDD48, label: 'J9[1]/P3V3_KV31'}
37 - {pin_num: '1', pin_signal: ADC1_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/I2C1_SDA, label: 'J1[4]/UART1_TX', identifier: UART1_TX}
38 - {pin_num: '2', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN, label: 'J1[2]/UART1_RX/SPI1_SOUT', identifier: UART1_RX}
39 - {pin_num: '33', pin_signal: PTE26/CLKOUT32K, label: TP18}
40 - {pin_num: '3', pin_signal: ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b, label: 'J1[11]/LLWU_P1/ADC1_SE6a', identifier: ADC1_SE6a}
41 - {pin_num: '4', pin_signal: ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SPI1_SOUT, label: 'J1[13]/ADC1_SE7a', identifier: ADC1_SE7a}
42 - {pin_num: '5', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/LPUART0_TX, label: SW3, identifier: SW3}
43 - {pin_num: '6', pin_signal: PTE5/SPI1_PCS2/LPUART0_RX/FTM3_CH0, label: 'J1[6]/FTM3_CH0', identifier: FTM3_CH0}
44 - {pin_num: '7', pin_signal: PTE6/SPI1_PCS3/LPUART0_CTS_b/FTM3_CH1, label: 'J1[8]/FTM3_CH1', identifier: FTM3_CH1}
45 - {pin_num: '10', pin_signal: ADC0_SE4a/PTE16/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3, label: 'J1[15]', identifier: SPI0_PCS0}
46 - {pin_num: '11', pin_signal: ADC0_SE5a/PTE17/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3, label: 'J2[12]/SPI0_SCK', identifier: SPI0_SCK}
47 - {pin_num: '12', pin_signal: ADC0_SE6a/PTE18/SPI0_SOUT/UART2_CTS_b/I2C0_SDA, label: 'J2[8]/SPI0_SOUT', identifier: SPI0_SOUT}
48 - {pin_num: '13', pin_signal: ADC0_SE7a/PTE19/SPI0_SIN/UART2_RTS_b/I2C0_SCL, label: 'J2[10]/SPI0_SIN', identifier: SPI0_SIN}
49 - {pin_num: '14', pin_signal: ADC0_DP1, label: 'J4[1]/DIFF_ADC0_DP', identifier: DIFF_ADC0_DP}
50 - {pin_num: '15', pin_signal: ADC0_DM1, label: 'J4[3]/DIFF_ADC0_DM', identifier: DIFF_ADC0_DM}
51 - {pin_num: '16', pin_signal: ADC1_DP1/ADC0_DP2, label: RT1/THER_A, identifier: THER_A}
52 - {pin_num: '17', pin_signal: ADC1_DM1/ADC0_DM2, label: RT1/THER_B, identifier: THER_B}
53 - {pin_num: '18', pin_signal: ADC0_DP0/ADC1_DP3, label: 'J2[5]/ADC0_DP0', identifier: ADC0_DP0}
54 - {pin_num: '19', pin_signal: ADC0_DM0/ADC1_DM3, label: 'J4[5]/ADC0_DM0', identifier: ADC0_DM0}
55 - {pin_num: '20', pin_signal: ADC1_DP0/ADC0_DP3, label: 'J2[3]/ADC1_DP0', identifier: ADC1_DP0}
56 - {pin_num: '21', pin_signal: ADC1_DM0/ADC0_DM3, label: 'J4[5]/ADC1_DM0', identifier: ADC1_DM0}
57 - {pin_num: '26', pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18, label: 'J2[9]/ADC1_SE18', identifier: ADC1_SE18}
58 - {pin_num: '27', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23, label: 'J4[11]/DAC0_OUT', identifier: DAC0_OUT}
59 - {pin_num: '28', pin_signal: DAC1_OUT/CMP0_IN4/ADC1_SE23, label: 'J2[11]/ADC1_SE23', identifier: ADC1_SE23}
60 - {pin_num: '31', pin_signal: ADC0_SE17/PTE24/FTM0_CH0/I2C0_SCL/EWM_OUT_b, label: 'J2[2]/FTM0_CH0', identifier: FTM0_CH0}
61 - {pin_num: '32', pin_signal: ADC0_SE18/PTE25/FTM0_CH1/I2C0_SDA/EWM_IN, label: 'D4[3]/LEDRGB_BLUE', identifier: LED_BLUE}
62 - {pin_num: '34', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/EWM_IN/JTAG_TCLK/SWD_CLK/EZP_CLK, label: 'J9[4]/SWD_CLK_KV3x', identifier: SWD_CLK_KV3x}
63 - {pin_num: '35', pin_signal: PTA1/UART0_RX/FTM0_CH6/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/JTAG_TDI/EZP_DI, label: NC}
64 - {pin_num: '36', pin_signal: PTA2/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/JTAG_TDO/TRACE_SWO/EZP_DO, label: 'J9[6]/TRACE_SWO', identifier: TRACE_SWO}
65 - {pin_num: '37', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/FTM2_FLT0/EWM_OUT_b/JTAG_TMS/SWD_DIO, label: 'J9[2]/SWD_DIO_TGTMCU', identifier: SWD_DIO_TGTMCU}
66 - {pin_num: '38', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM0_FLT3/NMI_b/EZP_CS_b, label: SW2/NMI_b, identifier: SW2}
67 - {pin_num: '39', pin_signal: PTA5/FTM0_CH2/JTAG_TRST_b, label: 'J2[4]'}
68 - {pin_num: '42', pin_signal: PTA12/FTM1_CH0/FTM1_QD_PHA, label: 'J1[12]/FTM1_CH0/FTM1_QD_PHA'}
69 - {pin_num: '43', pin_signal: PTA13/LLWU_P4/FTM1_CH1/FTM1_QD_PHB, label: 'J1[3]/FTM1_CH1/FTM1_QD_PHB'}
70 - {pin_num: '44', pin_signal: PTA14/SPI0_PCS0/UART0_TX, label: NC}
71 - {pin_num: '45', pin_signal: PTA15/SPI0_SCK/UART0_RX, label: NC}
72 - {pin_num: '46', pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b, label: NC}
73 - {pin_num: '47', pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b, label: 'J2[15]/ADC1_SE17', identifier: ADC1_SE17}
74 - {pin_num: '50', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, label: 'X501[1]/EXTAL0', identifier: EXTAL0}
75 - {pin_num: '51', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'X501[3]/XTAL0', identifier: XTAL0}
76 - {pin_num: '52', pin_signal: RESET_b, label: 'J3[6]/J9[10]/J25[3]/U3[7]/RESET'}
77 - {pin_num: '53', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, label: 'J2[1]/ADC0_SE8'}
78 - {pin_num: '54', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX, label: 'J2[18]/ADC0_SE9/I2C0_SDA', identifier: ADC0_SE9}
79 - {pin_num: '55', pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, label: 'J2[20]/ADC0_SE12/I2C0_SCL', identifier: ADC0_SE12}
80 - {pin_num: '56', pin_signal: ADC0_SE13/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: 'J2[7]/ADC0_SE13', identifier: ADC0_SE13}
81 - {pin_num: '57', pin_signal: PTB9/SPI1_PCS1/LPUART0_CTS_b/FB_AD20, label: NC}
82 - {pin_num: '58', pin_signal: ADC1_SE14/PTB10/SPI1_PCS0/LPUART0_RX/FB_AD19/FTM0_FLT1, label: 'J2[19]/ADC1_SE14', identifier: ADC1_SE14}
83 - {pin_num: '59', pin_signal: ADC1_SE15/PTB11/SPI1_SCK/LPUART0_TX/FB_AD18/FTM0_FLT2, label: 'J4[6]/ADC1_SE15', identifier: ADC1_SE15}
84 - {pin_num: '62', pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, label: 'U7[4]/UART0_RX_TGTMCU', identifier: DEBUG_UART_RX}
85 - {pin_num: '63', pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, label: 'U10[1]/UART0_TX_TGTMCU', identifier: DEBUG_UART_TX}
86 - {pin_num: '64', pin_signal: PTB18/FTM2_CH0/FB_AD15/FTM2_QD_PHA, label: 'J3[3]/FTM2_CH0', identifier: FTM2_CH0}
87 - {pin_num: '65', pin_signal: PTB19/FTM2_CH1/FB_OE_b/FTM2_QD_PHB, label: 'J3[1]/FTM2_CH1', identifier: FTM2_CH1}
88 - {pin_num: '66', pin_signal: PTB20/FB_AD31/CMP0_OUT, label: 'J2[17]/CMP0_OUT', identifier: CMP0_OUT}
89 - {pin_num: '67', pin_signal: PTB21/FB_AD30/CMP1_OUT, label: 'J4[9]/CMP1_OUT', identifier: CMP1_OUT}
90 - {pin_num: '68', pin_signal: PTB22/FB_AD29, label: R64}
91 - {pin_num: '69', pin_signal: PTB23/SPI0_PCS5/FB_AD28, label: NC}
92 - {pin_num: '70', pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/FB_AD14/FTM0_FLT1/SPI0_PCS0, label: 'J4[8]/ADC0_SE14', identifier: ADC0_SE14}
93 - {pin_num: '71', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/LPUART0_RTS_b, label: 'J3[15]/FTM0_CH0', identifier: FTM0_CH0}
94 - {pin_num: '72', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/LPUART0_CTS_b, label: 'J3[13]/FTM0_CH1', identifier: FTM0_CH1}
95 - {pin_num: '73', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/LPUART0_RX, label: 'J1[14]/LLWU_P7/CMP1_IN1', identifier: CMP1_IN1}
96 - {pin_num: '76', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX, label: 'J3[9]/FTM0_CH3'}
97 - {pin_num: '77', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/FB_AD10/CMP0_OUT/FTM0_CH2, label: 'J3[11]/FTM0_CH2'}
98 - {pin_num: '78', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/FB_AD9/I2C0_SCL, label: 'J1[16]/LLWU_P10/CMP0_IN0', identifier: CMP0_IN0}
99 - {pin_num: '79', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/FB_AD8/I2C0_SDA, label: 'J2[13]/CMP0_IN1', identifier: CMP0_IN1}
100 - {pin_num: '80', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/FTM3_CH4/FB_AD7, label: 'J4[2]/ADC1_SE4b/CMP0_IN2'}
101 - {pin_num: '81', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/FB_AD6/FTM2_FLT0, label: 'J4[4]/ADC1_SE5b/CMP0_IN3'}
102 - {pin_num: '82', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/FB_AD5, label: 'J4[12]/ADC1_SE6b/I2C1_SCL'}
103 - {pin_num: '83', pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/FB_RW_b, label: 'J4[10]/ADC1_SE7b/I2C1_SDA'}
104 - {pin_num: '84', pin_signal: PTC12/FB_AD27/FTM3_FLT0, label: 'J1[1]'}
105 - {pin_num: '85', pin_signal: PTC13/FB_AD26, label: 'J1[10]'}
106 - {pin_num: '86', pin_signal: PTC14/FB_AD25, label: NC}
107 - {pin_num: '87', pin_signal: PTC15/FB_AD24, label: 'J1[5]'}
108 - {pin_num: '90', pin_signal: PTC16/LPUART0_RX/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b, label: 'J1[7]/LPUART0_RX', identifier: LPUART0_RX}
109 - {pin_num: '91', pin_signal: PTC17/LPUART0_TX/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b, label: 'J1[9]/LPUART0_TX', identifier: LPUART0_TX}
110 - {pin_num: '92', pin_signal: PTC18/LPUART0_RTS_b/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b, label: 'U8[9]/Sensor_INT2', identifier: ACCEL_INT2}
111 - {pin_num: '93', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b, label: 'U8[11]/INT1', identifier: ACCEL_INT1}
112 - {pin_num: '94', pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, label: 'D4[1]/LEDRGB_RED', identifier: LED_RED}
113 - {pin_num: '95', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/LPUART0_RX/I2C0_SCL, label: 'U8[4]/I2C0_SCL', identifier: ACCEL_SCL}
114 - {pin_num: '96', pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/LPUART0_TX/I2C0_SDA, label: 'U8[6]/I2C0_SDA', identifier: ACCEL_SDA}
115 - {pin_num: '97', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN/SPI1_PCS0, label: 'J3[7]/FTM0_CH4', identifier: FTM0_CH4}
116 - {pin_num: '98', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK, label: 'J3[5]/FTM0_CH5', identifier: FTM0_CH5}
117 - {pin_num: '99', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, label: 'J2[6]/SPI0_PCS3/FTM0_CH6'}
118 - {pin_num: '100', pin_signal: PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN, label: 'D4[4]/LEDRGB_GREEN', identifier: LED_GREEN}
119  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
120  */
121 /* clang-format on */
122 
123 #include "fsl_common.h"
124 #include "fsl_port.h"
125 #include "fsl_gpio.h"
126 #include "pin_mux.h"
127 
128 /* FUNCTION ************************************************************************************************************
129  *
130  * Function Name : BOARD_InitBootPins
131  * Description   : Calls initialization functions.
132  *
133  * END ****************************************************************************************************************/
BOARD_InitBootPins(void)134 void BOARD_InitBootPins(void)
135 {
136     BOARD_InitPins();
137     BOARD_InitDEBUG_UARTPins();
138 }
139 
140 /* clang-format off */
141 /*
142  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
143 BOARD_InitPins:
144 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
145 - pin_list:
146   - {pin_num: '36', peripheral: TPIU, signal: SWO, pin_signal: PTA2/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/JTAG_TDO/TRACE_SWO/EZP_DO, pull_select: down,
147     pull_enable: disable}
148  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
149  */
150 /* clang-format on */
151 
152 /* FUNCTION ************************************************************************************************************
153  *
154  * Function Name : BOARD_InitPins
155  * Description   : Configures pin routing and optionally pin electrical features.
156  *
157  * END ****************************************************************************************************************/
BOARD_InitPins(void)158 void BOARD_InitPins(void)
159 {
160     /* Port A Clock Gate Control: Clock enabled */
161     CLOCK_EnableClock(kCLOCK_PortA);
162 
163     /* PORTA2 (pin 36) is configured as TRACE_SWO */
164     PORT_SetPinMux(BOARD_TRACE_SWO_PORT, BOARD_TRACE_SWO_PIN, kPORT_MuxAlt7);
165 
166     PORTA->PCR[2] = ((PORTA->PCR[2] &
167                       /* Mask bits to zero which are setting */
168                       (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
169 
170                      /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
171                       * corresponding PE field is set. */
172                      | PORT_PCR_PS(kPORT_PullDown)
173 
174                      /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
175                      | PORT_PCR_PE(kPORT_PullDisable));
176 }
177 
178 /* clang-format off */
179 /*
180  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
181 BOARD_InitBUTTONsPins:
182 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
183 - pin_list:
184   - {pin_num: '5', peripheral: GPIOE, signal: 'GPIO, 4', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/LPUART0_TX, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: down,
185     pull_enable: disable}
186   - {pin_num: '38', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM0_FLT3/NMI_b/EZP_CS_b, direction: INPUT, slew_rate: fast, open_drain: disable,
187     pull_select: down, pull_enable: disable, passive_filter: disable}
188  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
189  */
190 /* clang-format on */
191 
192 /* FUNCTION ************************************************************************************************************
193  *
194  * Function Name : BOARD_InitBUTTONsPins
195  * Description   : Configures pin routing and optionally pin electrical features.
196  *
197  * END ****************************************************************************************************************/
BOARD_InitBUTTONsPins(void)198 void BOARD_InitBUTTONsPins(void)
199 {
200     /* Port A Clock Gate Control: Clock enabled */
201     CLOCK_EnableClock(kCLOCK_PortA);
202     /* Port E Clock Gate Control: Clock enabled */
203     CLOCK_EnableClock(kCLOCK_PortE);
204 
205     gpio_pin_config_t SW2_config = {
206         .pinDirection = kGPIO_DigitalInput,
207         .outputLogic = 0U
208     };
209     /* Initialize GPIO functionality on pin PTA4 (pin 38)  */
210     GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
211 
212     gpio_pin_config_t SW3_config = {
213         .pinDirection = kGPIO_DigitalInput,
214         .outputLogic = 0U
215     };
216     /* Initialize GPIO functionality on pin PTE4 (pin 5)  */
217     GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
218 
219     const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
220                                    kPORT_PullDisable,
221                                    /* Fast slew rate is configured */
222                                    kPORT_FastSlewRate,
223                                    /* Passive filter is disabled */
224                                    kPORT_PassiveFilterDisable,
225                                    /* Open drain is disabled */
226                                    kPORT_OpenDrainDisable,
227                                    /* Low drive strength is configured */
228                                    kPORT_LowDriveStrength,
229                                    /* Pin is configured as PTA4 */
230                                    kPORT_MuxAsGpio,
231                                    /* Pin Control Register fields [15:0] are not locked */
232                                    kPORT_UnlockRegister};
233     /* PORTA4 (pin 38) is configured as PTA4 */
234     PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
235 
236     const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */
237                                    kPORT_PullDisable,
238                                    /* Fast slew rate is configured */
239                                    kPORT_FastSlewRate,
240                                    /* Passive filter is disabled */
241                                    kPORT_PassiveFilterDisable,
242                                    /* Open drain is disabled */
243                                    kPORT_OpenDrainDisable,
244                                    /* Low drive strength is configured */
245                                    kPORT_LowDriveStrength,
246                                    /* Pin is configured as PTE4 */
247                                    kPORT_MuxAsGpio,
248                                    /* Pin Control Register fields [15:0] are not locked */
249                                    kPORT_UnlockRegister};
250     /* PORTE4 (pin 5) is configured as PTE4 */
251     PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
252 }
253 
254 /* clang-format off */
255 /*
256  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
257 BOARD_InitLEDsPins:
258 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
259 - pin_list:
260   - {pin_num: '32', peripheral: GPIOE, signal: 'GPIO, 25', pin_signal: ADC0_SE18/PTE25/FTM0_CH1/I2C0_SDA/EWM_IN, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
261     open_drain: disable, pull_select: down, pull_enable: disable}
262   - {pin_num: '94', peripheral: GPIOD, signal: 'GPIO, 1', pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, direction: OUTPUT, gpio_init_state: 'true',
263     slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable, digital_filter: disable}
264   - {pin_num: '100', peripheral: GPIOD, signal: 'GPIO, 7', pin_signal: PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
265     open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, digital_filter: disable}
266  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
267  */
268 /* clang-format on */
269 
270 /* FUNCTION ************************************************************************************************************
271  *
272  * Function Name : BOARD_InitLEDsPins
273  * Description   : Configures pin routing and optionally pin electrical features.
274  *
275  * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)276 void BOARD_InitLEDsPins(void)
277 {
278     /* Port D Clock Gate Control: Clock enabled */
279     CLOCK_EnableClock(kCLOCK_PortD);
280     /* Port E Clock Gate Control: Clock enabled */
281     CLOCK_EnableClock(kCLOCK_PortE);
282 
283     gpio_pin_config_t LED_RED_config = {
284         .pinDirection = kGPIO_DigitalOutput,
285         .outputLogic = 1U
286     };
287     /* Initialize GPIO functionality on pin PTD1 (pin 94)  */
288     GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
289 
290     gpio_pin_config_t LED_GREEN_config = {
291         .pinDirection = kGPIO_DigitalOutput,
292         .outputLogic = 1U
293     };
294     /* Initialize GPIO functionality on pin PTD7 (pin 100)  */
295     GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
296 
297     gpio_pin_config_t LED_BLUE_config = {
298         .pinDirection = kGPIO_DigitalOutput,
299         .outputLogic = 1U
300     };
301     /* Initialize GPIO functionality on pin PTE25 (pin 32)  */
302     GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
303     /* Configure digital filter */
304     PORT_EnablePinsDigitalFilter(
305         /* Digital filter is configured on port D */
306         PORTD,
307         /* Digital filter is configured for PORTD0 */
308           PORT_DFER_DFE_1_MASK
309             /* Digital filter is configured for PORTD1 */
310             | PORT_DFER_DFE_7_MASK,
311         /* Disable digital filter */
312         false);
313 
314     const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
315                                        kPORT_PullDisable,
316                                        /* Slow slew rate is configured */
317                                        kPORT_SlowSlewRate,
318                                        /* Passive filter is disabled */
319                                        kPORT_PassiveFilterDisable,
320                                        /* Open drain is disabled */
321                                        kPORT_OpenDrainDisable,
322                                        /* Low drive strength is configured */
323                                        kPORT_LowDriveStrength,
324                                        /* Pin is configured as PTD1 */
325                                        kPORT_MuxAsGpio,
326                                        /* Pin Control Register fields [15:0] are not locked */
327                                        kPORT_UnlockRegister};
328     /* PORTD1 (pin 94) is configured as PTD1 */
329     PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
330 
331     const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
332                                          kPORT_PullDisable,
333                                          /* Slow slew rate is configured */
334                                          kPORT_SlowSlewRate,
335                                          /* Passive filter is disabled */
336                                          kPORT_PassiveFilterDisable,
337                                          /* Open drain is disabled */
338                                          kPORT_OpenDrainDisable,
339                                          /* Low drive strength is configured */
340                                          kPORT_LowDriveStrength,
341                                          /* Pin is configured as PTD7 */
342                                          kPORT_MuxAsGpio,
343                                          /* Pin Control Register fields [15:0] are not locked */
344                                          kPORT_UnlockRegister};
345     /* PORTD7 (pin 100) is configured as PTD7 */
346     PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
347 
348     const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
349                                         kPORT_PullDisable,
350                                         /* Slow slew rate is configured */
351                                         kPORT_SlowSlewRate,
352                                         /* Passive filter is disabled */
353                                         kPORT_PassiveFilterDisable,
354                                         /* Open drain is disabled */
355                                         kPORT_OpenDrainDisable,
356                                         /* Low drive strength is configured */
357                                         kPORT_LowDriveStrength,
358                                         /* Pin is configured as PTE25 */
359                                         kPORT_MuxAsGpio,
360                                         /* Pin Control Register fields [15:0] are not locked */
361                                         kPORT_UnlockRegister};
362     /* PORTE25 (pin 32) is configured as PTE25 */
363     PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
364 }
365 
366 /* clang-format off */
367 /*
368  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
369 BOARD_InitDEBUG_UARTPins:
370 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
371 - pin_list:
372   - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, slew_rate: fast, open_drain: disable, pull_select: down,
373     pull_enable: disable}
374   - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, direction: OUTPUT, slew_rate: fast, open_drain: disable,
375     pull_select: down, pull_enable: disable}
376  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
377  */
378 /* clang-format on */
379 
380 /* FUNCTION ************************************************************************************************************
381  *
382  * Function Name : BOARD_InitDEBUG_UARTPins
383  * Description   : Configures pin routing and optionally pin electrical features.
384  *
385  * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)386 void BOARD_InitDEBUG_UARTPins(void)
387 {
388     /* Port B Clock Gate Control: Clock enabled */
389     CLOCK_EnableClock(kCLOCK_PortB);
390 
391     const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
392                                              kPORT_PullDisable,
393                                              /* Fast slew rate is configured */
394                                              kPORT_FastSlewRate,
395                                              /* Passive filter is disabled */
396                                              kPORT_PassiveFilterDisable,
397                                              /* Open drain is disabled */
398                                              kPORT_OpenDrainDisable,
399                                              /* Low drive strength is configured */
400                                              kPORT_LowDriveStrength,
401                                              /* Pin is configured as UART0_RX */
402                                              kPORT_MuxAlt3,
403                                              /* Pin Control Register fields [15:0] are not locked */
404                                              kPORT_UnlockRegister};
405     /* PORTB16 (pin 62) is configured as UART0_RX */
406     PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
407 
408     const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
409                                              kPORT_PullDisable,
410                                              /* Fast slew rate is configured */
411                                              kPORT_FastSlewRate,
412                                              /* Passive filter is disabled */
413                                              kPORT_PassiveFilterDisable,
414                                              /* Open drain is disabled */
415                                              kPORT_OpenDrainDisable,
416                                              /* Low drive strength is configured */
417                                              kPORT_LowDriveStrength,
418                                              /* Pin is configured as UART0_TX */
419                                              kPORT_MuxAlt3,
420                                              /* Pin Control Register fields [15:0] are not locked */
421                                              kPORT_UnlockRegister};
422     /* PORTB17 (pin 63) is configured as UART0_TX */
423     PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
424 
425     SIM->SOPT5 = ((SIM->SOPT5 &
426                    /* Mask bits to zero which are setting */
427                    (~(SIM_SOPT5_UART0TXSRC_MASK)))
428 
429                   /* UART 0 transmit data source select: UART0_TX pin. */
430                   | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
431 }
432 
433 /* clang-format off */
434 /*
435  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
436 BOARD_InitTHERPins:
437 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
438 - pin_list:
439   - {pin_num: '16', peripheral: ADC1, signal: 'DP, 1', pin_signal: ADC1_DP1/ADC0_DP2}
440   - {pin_num: '17', peripheral: ADC1, signal: 'DM, 1', pin_signal: ADC1_DM1/ADC0_DM2}
441  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
442  */
443 /* clang-format on */
444 
445 /* FUNCTION ************************************************************************************************************
446  *
447  * Function Name : BOARD_InitTHERPins
448  * Description   : Configures pin routing and optionally pin electrical features.
449  *
450  * END ****************************************************************************************************************/
BOARD_InitTHERPins(void)451 void BOARD_InitTHERPins(void)
452 {
453 }
454 
455 /* clang-format off */
456 /*
457  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
458 BOARD_InitACCELPins:
459 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
460 - pin_list:
461   - {pin_num: '95', peripheral: I2C0, signal: SCL, pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/LPUART0_RX/I2C0_SCL, slew_rate: fast, open_drain: enable,
462     pull_select: down, pull_enable: disable, digital_filter: disable}
463   - {pin_num: '96', peripheral: I2C0, signal: SDA, pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/LPUART0_TX/I2C0_SDA, slew_rate: fast, open_drain: enable, pull_select: down,
464     pull_enable: disable, digital_filter: disable}
465   - {pin_num: '92', peripheral: GPIOC, signal: 'GPIO, 18', pin_signal: PTC18/LPUART0_RTS_b/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b, direction: INPUT, open_drain: enable,
466     pull_select: up, pull_enable: enable}
467   - {pin_num: '93', peripheral: GPIOD, signal: 'GPIO, 0', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b, direction: INPUT,
468     open_drain: enable, pull_select: up, pull_enable: enable, digital_filter: disable}
469  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
470  */
471 /* clang-format on */
472 
473 /* FUNCTION ************************************************************************************************************
474  *
475  * Function Name : BOARD_InitACCELPins
476  * Description   : Configures pin routing and optionally pin electrical features.
477  *
478  * END ****************************************************************************************************************/
BOARD_InitACCELPins(void)479 void BOARD_InitACCELPins(void)
480 {
481     /* Port C Clock Gate Control: Clock enabled */
482     CLOCK_EnableClock(kCLOCK_PortC);
483     /* Port D Clock Gate Control: Clock enabled */
484     CLOCK_EnableClock(kCLOCK_PortD);
485 
486     gpio_pin_config_t ACCEL_INT2_config = {
487         .pinDirection = kGPIO_DigitalInput,
488         .outputLogic = 0U
489     };
490     /* Initialize GPIO functionality on pin PTC18 (pin 92)  */
491     GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
492 
493     gpio_pin_config_t ACCEL_INT1_config = {
494         .pinDirection = kGPIO_DigitalInput,
495         .outputLogic = 0U
496     };
497     /* Initialize GPIO functionality on pin PTD0 (pin 93)  */
498     GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
499 
500     /* PORTC18 (pin 92) is configured as PTC18 */
501     PORT_SetPinMux(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, kPORT_MuxAsGpio);
502 
503     PORTC->PCR[18] = ((PORTC->PCR[18] &
504                        /* Mask bits to zero which are setting */
505                        (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
506 
507                       /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
508                        * corresponding PE field is set. */
509                       | (uint32_t)(kPORT_PullUp)
510 
511                       /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
512                        * configured as a digital output. */
513                       | PORT_PCR_ODE(kPORT_OpenDrainEnable));
514     /* Configure digital filter */
515     PORT_EnablePinsDigitalFilter(
516         /* Digital filter is configured on port D */
517         PORTD,
518         /* Digital filter is configured for PORTD0 */
519           PORT_DFER_DFE_0_MASK
520             /* Digital filter is configured for PORTD1 */
521             | PORT_DFER_DFE_2_MASK
522             /* Digital filter is configured for PORTD2 */
523             | PORT_DFER_DFE_3_MASK,
524         /* Disable digital filter */
525         false);
526 
527     /* PORTD0 (pin 93) is configured as PTD0 */
528     PORT_SetPinMux(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, kPORT_MuxAsGpio);
529 
530     PORTD->PCR[0] = ((PORTD->PCR[0] &
531                       /* Mask bits to zero which are setting */
532                       (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
533 
534                      /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
535                       * corresponding PE field is set. */
536                      | (uint32_t)(kPORT_PullUp)
537 
538                      /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
539                       * configured as a digital output. */
540                      | PORT_PCR_ODE(kPORT_OpenDrainEnable));
541 
542     const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
543                                          kPORT_PullDisable,
544                                          /* Fast slew rate is configured */
545                                          kPORT_FastSlewRate,
546                                          /* Passive filter is disabled */
547                                          kPORT_PassiveFilterDisable,
548                                          /* Open drain is enabled */
549                                          kPORT_OpenDrainEnable,
550                                          /* Low drive strength is configured */
551                                          kPORT_LowDriveStrength,
552                                          /* Pin is configured as I2C0_SCL */
553                                          kPORT_MuxAlt7,
554                                          /* Pin Control Register fields [15:0] are not locked */
555                                          kPORT_UnlockRegister};
556     /* PORTD2 (pin 95) is configured as I2C0_SCL */
557     PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
558 
559     const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
560                                          kPORT_PullDisable,
561                                          /* Fast slew rate is configured */
562                                          kPORT_FastSlewRate,
563                                          /* Passive filter is disabled */
564                                          kPORT_PassiveFilterDisable,
565                                          /* Open drain is enabled */
566                                          kPORT_OpenDrainEnable,
567                                          /* Low drive strength is configured */
568                                          kPORT_LowDriveStrength,
569                                          /* Pin is configured as I2C0_SDA */
570                                          kPORT_MuxAlt7,
571                                          /* Pin Control Register fields [15:0] are not locked */
572                                          kPORT_UnlockRegister};
573     /* PORTD3 (pin 96) is configured as I2C0_SDA */
574     PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
575 }
576 
577 /* clang-format off */
578 /*
579  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
580 BOARD_InitOSCPins:
581 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
582 - pin_list:
583   - {pin_num: '50', peripheral: OSC, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
584     pull_enable: no_init}
585   - {pin_num: '51', peripheral: OSC, signal: XTAL0, pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
586     pull_enable: no_init}
587  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
588  */
589 /* clang-format on */
590 
591 /* FUNCTION ************************************************************************************************************
592  *
593  * Function Name : BOARD_InitOSCPins
594  * Description   : Configures pin routing and optionally pin electrical features.
595  *
596  * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)597 void BOARD_InitOSCPins(void)
598 {
599     /* Port A Clock Gate Control: Clock enabled */
600     CLOCK_EnableClock(kCLOCK_PortA);
601 
602     /* PORTA18 (pin 50) is configured as EXTAL0 */
603     PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
604 
605     /* PORTA19 (pin 51) is configured as XTAL0 */
606     PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
607 }
608 /***********************************************************************************************************************
609  * EOF
610  **********************************************************************************************************************/
611