1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
21 *
22 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
23 */
24
25 /* clang-format off */
26 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
27 !!GlobalInfo
28 product: Clocks v4.1
29 processor: MKL27Z64xxx4
30 package_id: MKL27Z64VLH4
31 mcu_data: ksdk2_0
32 processor_version: 4.0.0
33 board: FRDM-KL27Z
34 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
35 /* clang-format on */
36
37 #include "fsl_smc.h"
38 #include "clock_config.h"
39
40 /*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43 #define SIM_CLKOUT_SEL_IRC48M_CLK 7U /*!< CLKOUT pin clock select: IRC48M clock */
44 #define SIM_FLEXIO_CLK_SEL_IRC48M_CLK 1U /*!< FLEXIO clock select: IRC48M clock */
45 #define SIM_LPUART_CLK_SEL_IRC48M_CLK 1U /*!< LPUART clock select: IRC48M clock */
46 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
47 #define SIM_RTC_CLKOUT_SEL_OSCERCLK_CLK 1U /*!< RTC clock output select: OSCERCLK clock */
48 #define SIM_TPM_CLK_SEL_IRC48M_CLK 1U /*!< TPM clock select: IRC48M clock */
49 #define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */
50
51 /*******************************************************************************
52 * Variables
53 ******************************************************************************/
54 /* System clock frequency. */
55 extern uint32_t SystemCoreClock;
56
57 /*******************************************************************************
58 ************************ BOARD_InitBootClocks function ************************
59 ******************************************************************************/
BOARD_InitBootClocks(void)60 void BOARD_InitBootClocks(void)
61 {
62 BOARD_BootClockRUN();
63 }
64
65 /*******************************************************************************
66 ********************** Configuration BOARD_BootClockRUN ***********************
67 ******************************************************************************/
68 /* clang-format off */
69 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
70 !!Configuration
71 name: BOARD_BootClockRUN
72 called_from_default_init: true
73 outputs:
74 - {id: Bus_clock.outFreq, value: 24 MHz}
75 - {id: CLKOUT.outFreq, value: 48 MHz}
76 - {id: COPCLK.outFreq, value: 32.768 kHz}
77 - {id: Core_clock.outFreq, value: 48 MHz}
78 - {id: ERCLK32K.outFreq, value: 32.768 kHz}
79 - {id: FLEXIOCLK.outFreq, value: 48 MHz}
80 - {id: Flash_clock.outFreq, value: 24 MHz}
81 - {id: LPO_clock.outFreq, value: 1 kHz}
82 - {id: LPUART0CLK.outFreq, value: 48 MHz}
83 - {id: LPUART1CLK.outFreq, value: 48 MHz}
84 - {id: MCGIRCLK.outFreq, value: 8 MHz}
85 - {id: MCGPCLK.outFreq, value: 48 MHz}
86 - {id: OSCERCLK.outFreq, value: 32.768 kHz}
87 - {id: RTC_CLKOUT.outFreq, value: 32.768 kHz}
88 - {id: System_clock.outFreq, value: 48 MHz}
89 - {id: TPMCLK.outFreq, value: 48 MHz}
90 - {id: USB48MCLK.outFreq, value: 48 MHz}
91 settings:
92 - {id: MCGMode, value: HIRC}
93 - {id: CLKOUTConfig, value: 'yes'}
94 - {id: COPClkConfig, value: 'yes'}
95 - {id: FLEXIOClkConfig, value: 'yes'}
96 - {id: LPUART0ClkConfig, value: 'yes'}
97 - {id: LPUART1ClkConfig, value: 'yes'}
98 - {id: MCG.CLKS.sel, value: MCG.HIRC}
99 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
100 - {id: MCG_MC_HIRCEN_CFG, value: Enabled}
101 - {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
102 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
103 - {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
104 - {id: RTCCLKOUTConfig, value: 'yes'}
105 - {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
106 - {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
107 - {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
108 - {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
109 - {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
110 - {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
111 - {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
112 - {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
113 - {id: TPMClkConfig, value: 'yes'}
114 - {id: USBClkConfig, value: 'yes'}
115 sources:
116 - {id: MCG.HIRC.outFreq, value: 48 MHz}
117 - {id: OSC.OSC.outFreq, value: 32.768 kHz, enabled: true}
118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
119 /* clang-format on */
120
121 /*******************************************************************************
122 * Variables for BOARD_BootClockRUN configuration
123 ******************************************************************************/
124 const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
125 .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
126 .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
127 .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
128 .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
129 .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
130 .hircEnableInNotHircMode = true, /* HIRC source is enabled */
131 };
132 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
133 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
134 .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
135 };
136 const osc_config_t oscConfig_BOARD_BootClockRUN = {
137 .freq = 32768U, /* Oscillator frequency: 32768Hz */
138 .capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
139 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
140 .oscerConfig = {
141 .enableMode =
142 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
143 }};
144
145 /*******************************************************************************
146 * Code for BOARD_BootClockRUN configuration
147 ******************************************************************************/
BOARD_BootClockRUN(void)148 void BOARD_BootClockRUN(void)
149 {
150 /* Set the system clock dividers in SIM to safe value. */
151 CLOCK_SetSimSafeDivs();
152 /* Initializes OSC0 according to board configuration. */
153 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
154 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
155 /* Set MCG to HIRC mode. */
156 CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
157 /* Set the clock configuration in SIM module. */
158 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
159 /* Set SystemCoreClock variable. */
160 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
161 /* Set RTC_CLKOUT source. */
162 CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_OSCERCLK_CLK);
163 /* Enable USB FS clock. */
164 CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, SIM_USB_CLK_48000000HZ);
165 /* Set LPUART0 clock source. */
166 CLOCK_SetLpuart0Clock(SIM_LPUART_CLK_SEL_IRC48M_CLK);
167 /* Set LPUART1 clock source. */
168 CLOCK_SetLpuart1Clock(SIM_LPUART_CLK_SEL_IRC48M_CLK);
169 /* Set FLEXIO clock source. */
170 CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_IRC48M_CLK);
171 /* Set TPM clock source. */
172 CLOCK_SetTpmClock(SIM_TPM_CLK_SEL_IRC48M_CLK);
173 /* Set CLKOUT source. */
174 CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_IRC48M_CLK);
175 }
176
177 /*******************************************************************************
178 ********************* Configuration BOARD_BootClockVLPR ***********************
179 ******************************************************************************/
180 /* clang-format off */
181 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
182 !!Configuration
183 name: BOARD_BootClockVLPR
184 outputs:
185 - {id: Bus_clock.outFreq, value: 1 MHz}
186 - {id: Core_clock.outFreq, value: 2 MHz}
187 - {id: Flash_clock.outFreq, value: 1 MHz}
188 - {id: LPO_clock.outFreq, value: 1 kHz}
189 - {id: MCGIRCLK.outFreq, value: 2 MHz}
190 - {id: System_clock.outFreq, value: 2 MHz}
191 settings:
192 - {id: MCGMode, value: LIRC2M}
193 - {id: powerMode, value: VLPR}
194 - {id: MCG.LIRCDIV1.scale, value: '1', locked: true}
195 - {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
196 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
197 - {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
198 - {id: RTCCLKOUTConfig, value: 'yes'}
199 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
200 - {id: SIM.OUTDIV4.scale, value: '2', locked: true}
201 - {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
202 sources:
203 - {id: MCG.LIRC.outFreq, value: 2 MHz}
204 - {id: OSC.OSC.outFreq, value: 32.768 kHz}
205 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
206 /* clang-format on */
207
208 /*******************************************************************************
209 * Variables for BOARD_BootClockVLPR configuration
210 ******************************************************************************/
211 const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR = {
212 .outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
213 .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
214 .ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
215 .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
216 .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
217 .hircEnableInNotHircMode = false, /* HIRC source is not enabled */
218 };
219 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
220 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
221 .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
222 };
223 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
224 .freq = 0U, /* Oscillator frequency: 0Hz */
225 .capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
226 .workMode = kOSC_ModeExt, /* Use external clock */
227 .oscerConfig = {
228 .enableMode =
229 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
230 }};
231
232 /*******************************************************************************
233 * Code for BOARD_BootClockVLPR configuration
234 ******************************************************************************/
BOARD_BootClockVLPR(void)235 void BOARD_BootClockVLPR(void)
236 {
237 /* Set the system clock dividers in SIM to safe value. */
238 CLOCK_SetSimSafeDivs();
239 /* Set MCG to LIRC2M mode. */
240 CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
241 /* Set the clock configuration in SIM module. */
242 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
243 /* Set VLPR power mode. */
244 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
245 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
246 SMC_SetPowerModeVlpr(SMC, false);
247 #else
248 SMC_SetPowerModeVlpr(SMC);
249 #endif
250 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
251 {
252 }
253 /* Set SystemCoreClock variable. */
254 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
255 }
256
