1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
21 *
22 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
23 */
24
25 /* clang-format off */
26 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
27 !!GlobalInfo
28 product: Clocks v7.0
29 processor: MKL27Z64xxx4
30 package_id: MKL27Z64VLH4
31 mcu_data: ksdk2_0
32 processor_version: 0.7.1
33 board: FRDM-KL27Z
34 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
35 /* clang-format on */
36
37 #include "fsl_smc.h"
38 #include "clock_config.h"
39
40 /*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
44
45 /*******************************************************************************
46 * Variables
47 ******************************************************************************/
48 /* System clock frequency. */
49 extern uint32_t SystemCoreClock;
50
51 /*******************************************************************************
52 ************************ BOARD_InitBootClocks function ************************
53 ******************************************************************************/
BOARD_InitBootClocks(void)54 void BOARD_InitBootClocks(void)
55 {
56 BOARD_BootClockRUN();
57 }
58
59 /*******************************************************************************
60 ********************** Configuration BOARD_BootClockRUN ***********************
61 ******************************************************************************/
62 /* clang-format off */
63 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
64 !!Configuration
65 name: BOARD_BootClockRUN
66 called_from_default_init: true
67 outputs:
68 - {id: Bus_clock.outFreq, value: 24 MHz}
69 - {id: Core_clock.outFreq, value: 48 MHz}
70 - {id: Flash_clock.outFreq, value: 24 MHz}
71 - {id: LPO_clock.outFreq, value: 1 kHz}
72 - {id: MCGIRCLK.outFreq, value: 8 MHz}
73 - {id: MCGPCLK.outFreq, value: 48 MHz}
74 - {id: System_clock.outFreq, value: 48 MHz}
75 settings:
76 - {id: MCGMode, value: HIRC}
77 - {id: MCG.CLKS.sel, value: MCG.HIRC}
78 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
79 - {id: MCG_MC_HIRCEN_CFG, value: Enabled}
80 - {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
81 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
82 - {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
83 - {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
84 - {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
85 - {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
86 - {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
87 - {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
88 - {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
89 - {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
90 - {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
91 sources:
92 - {id: MCG.HIRC.outFreq, value: 48 MHz}
93 - {id: OSC.OSC.outFreq, value: 32.768 kHz}
94 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
95 /* clang-format on */
96
97 /*******************************************************************************
98 * Variables for BOARD_BootClockRUN configuration
99 ******************************************************************************/
100 const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
101 .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
102 .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
103 .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
104 .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
105 .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
106 .hircEnableInNotHircMode = true, /* HIRC source is enabled */
107 };
108 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
109 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
110 .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
111 };
112 const osc_config_t oscConfig_BOARD_BootClockRUN = {
113 .freq = 0U, /* Oscillator frequency: 0Hz */
114 .capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
115 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
116 .oscerConfig = {
117 .enableMode =
118 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
119 }};
120
121 /*******************************************************************************
122 * Code for BOARD_BootClockRUN configuration
123 ******************************************************************************/
BOARD_BootClockRUN(void)124 void BOARD_BootClockRUN(void)
125 {
126 /* Set the system clock dividers in SIM to safe value. */
127 CLOCK_SetSimSafeDivs();
128 /* Set MCG to HIRC mode. */
129 CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
130 /* Set the clock configuration in SIM module. */
131 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
132 /* Set SystemCoreClock variable. */
133 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
134 }
135
136 /*******************************************************************************
137 ********************* Configuration BOARD_BootClockVLPR ***********************
138 ******************************************************************************/
139 /* clang-format off */
140 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
141 !!Configuration
142 name: BOARD_BootClockVLPR
143 outputs:
144 - {id: Bus_clock.outFreq, value: 1 MHz}
145 - {id: Core_clock.outFreq, value: 2 MHz}
146 - {id: Flash_clock.outFreq, value: 1 MHz}
147 - {id: LPO_clock.outFreq, value: 1 kHz}
148 - {id: MCGIRCLK.outFreq, value: 2 MHz}
149 - {id: System_clock.outFreq, value: 2 MHz}
150 settings:
151 - {id: MCGMode, value: LIRC2M}
152 - {id: powerMode, value: VLPR}
153 - {id: MCG.LIRCDIV1.scale, value: '1', locked: true}
154 - {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
155 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
156 - {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
157 - {id: RTCCLKOUTConfig, value: 'yes'}
158 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
159 - {id: SIM.OUTDIV4.scale, value: '2', locked: true}
160 - {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
161 sources:
162 - {id: MCG.LIRC.outFreq, value: 2 MHz}
163 - {id: OSC.OSC.outFreq, value: 32.768 kHz}
164 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
165 /* clang-format on */
166
167 /*******************************************************************************
168 * Variables for BOARD_BootClockVLPR configuration
169 ******************************************************************************/
170 const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR = {
171 .outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
172 .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
173 .ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
174 .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
175 .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
176 .hircEnableInNotHircMode = false, /* HIRC source is not enabled */
177 };
178 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
179 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
180 .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
181 };
182 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
183 .freq = 0U, /* Oscillator frequency: 0Hz */
184 .capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
185 .workMode = kOSC_ModeExt, /* Use external clock */
186 .oscerConfig = {
187 .enableMode =
188 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
189 }};
190
191 /*******************************************************************************
192 * Code for BOARD_BootClockVLPR configuration
193 ******************************************************************************/
BOARD_BootClockVLPR(void)194 void BOARD_BootClockVLPR(void)
195 {
196 /* Set the system clock dividers in SIM to safe value. */
197 CLOCK_SetSimSafeDivs();
198 /* Set MCG to LIRC2M mode. */
199 CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
200 /* Set the clock configuration in SIM module. */
201 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
202 /* Set VLPR power mode. */
203 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
204 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
205 SMC_SetPowerModeVlpr(SMC, false);
206 #else
207 SMC_SetPowerModeVlpr(SMC);
208 #endif
209 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
210 {
211 }
212 /* Set SystemCoreClock variable. */
213 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
214 }
215
