1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13 /* clang-format off */
14 /*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16 !!GlobalInfo
17 product: Pins v4.1
18 processor: MKE16Z64xxx4
19 package_id: MKE16Z64VLF4
20 mcu_data: ksdk2_0
21 processor_version: 0.0.0
22 board: FRDM-KE16Z
23 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
24 */
25 /* clang-format on */
26
27 #include "fsl_common.h"
28 #include "fsl_port.h"
29 #include "fsl_gpio.h"
30 #include "pin_mux.h"
31
32 /* FUNCTION ************************************************************************************************************
33 *
34 * Function Name : BOARD_InitBootPins
35 * Description : Calls initialization functions.
36 *
37 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)38 void BOARD_InitBootPins(void)
39 {
40 BOARD_InitPins();
41 BOARD_InitDEBUG_UARTPins();
42 }
43
44 /* clang-format off */
45 /*
46 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
47 BOARD_InitPins:
48 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
49 - pin_list: []
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
51 */
52 /* clang-format on */
53
54 /* FUNCTION ************************************************************************************************************
55 *
56 * Function Name : BOARD_InitPins
57 * Description : Configures pin routing and optionally pin electrical features.
58 *
59 * END ****************************************************************************************************************/
BOARD_InitPins(void)60 void BOARD_InitPins(void)
61 {
62 }
63
64 /* clang-format off */
65 /*
66 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
67 BOARD_InitOSCPins:
68 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
69 - pin_list:
70 - {pin_num: '11', peripheral: SCG, signal: EXTAL0, pin_signal: EXTAL/PTB7/LPI2C0_SCL}
71 - {pin_num: '12', peripheral: SCG, signal: XTAL0, pin_signal: XTAL/PTB6/LPI2C0_SDA}
72 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
73 */
74 /* clang-format on */
75
76 /* FUNCTION ************************************************************************************************************
77 *
78 * Function Name : BOARD_InitOSCPins
79 * Description : Configures pin routing and optionally pin electrical features.
80 *
81 * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)82 void BOARD_InitOSCPins(void)
83 {
84 /* Clock Gate Control: 0x01u */
85 CLOCK_EnableClock(kCLOCK_PortB);
86
87 /* PORTB6 (pin 12) is configured as XTAL */
88 PORT_SetPinMux(BOARD_XTAL_PORT, BOARD_XTAL_PIN, kPORT_PinDisabledOrAnalog);
89
90 /* PORTB7 (pin 11) is configured as EXTAL */
91 PORT_SetPinMux(BOARD_EXTAL_PORT, BOARD_EXTAL_PIN, kPORT_PinDisabledOrAnalog);
92 }
93
94 /* clang-format off */
95 /*
96 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
97 BOARD_InitTOUCHPins:
98 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
99 - pin_list:
100 - {pin_num: '5', peripheral: TSI, signal: 'CH, 0', pin_signal: TSI0_CH0/PTE5/TCLK2/CAN0_TX/EWM_IN, drive_strength: low, pull_select: down, pull_enable: disable,
101 passive_filter: disable, digital_filter: disable}
102 - {pin_num: '6', peripheral: TSI, signal: 'CH, 1', pin_signal: TSI0_CH1/PTE4/BUSOUT/CAN0_RX/EWM_OUT_b, drive_strength: low, pull_select: down, pull_enable: disable,
103 passive_filter: disable}
104 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
105 */
106 /* clang-format on */
107
108 /* FUNCTION ************************************************************************************************************
109 *
110 * Function Name : BOARD_InitTOUCHPins
111 * Description : Configures pin routing and optionally pin electrical features.
112 *
113 * END ****************************************************************************************************************/
BOARD_InitTOUCHPins(void)114 void BOARD_InitTOUCHPins(void)
115 {
116 /* Clock Gate Control: 0x01u */
117 CLOCK_EnableClock(kCLOCK_PortE);
118 /* Configure digital filter */
119 PORT_EnablePinsDigitalFilter(
120 /* Digital filter is configured on port E */
121 PORTE,
122 /* Digital filter is configured for PORTE0 */
123 PORT_DFER_DFE_5_MASK,
124 /* Disable digital filter */
125 false);
126
127 const port_pin_config_t TSI_ELECTRODE2 = {/* Internal pull-up/down resistor is disabled */
128 kPORT_PullDisable,
129 /* Passive filter is disabled */
130 kPORT_PassiveFilterDisable,
131 /* Low drive strength is configured */
132 kPORT_LowDriveStrength,
133 /* Pin is configured as TSI0_CH1 */
134 kPORT_PinDisabledOrAnalog,
135 /* Pin Control Register fields [15:0] are not locked */
136 kPORT_UnlockRegister};
137 /* PORTE4 (pin 6) is configured as TSI0_CH1 */
138 PORT_SetPinConfig(BOARD_TSI_ELECTRODE2_PORT, BOARD_TSI_ELECTRODE2_PIN, &TSI_ELECTRODE2);
139
140 const port_pin_config_t TSI_ELECTRODE1 = {/* Internal pull-up/down resistor is disabled */
141 kPORT_PullDisable,
142 /* Passive filter is disabled */
143 kPORT_PassiveFilterDisable,
144 /* Low drive strength is configured */
145 kPORT_LowDriveStrength,
146 /* Pin is configured as TSI0_CH0 */
147 kPORT_PinDisabledOrAnalog,
148 /* Pin Control Register fields [15:0] are not locked */
149 kPORT_UnlockRegister};
150 /* PORTE5 (pin 5) is configured as TSI0_CH0 */
151 PORT_SetPinConfig(BOARD_TSI_ELECTRODE1_PORT, BOARD_TSI_ELECTRODE1_PIN, &TSI_ELECTRODE1);
152 }
153
154 /* clang-format off */
155 /*
156 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
157 BOARD_InitBUTTONSPins:
158 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
159 - pin_list:
160 - {pin_num: '33', peripheral: GPIOD, signal: 'GPIO, 3', pin_signal: PTD3/NMI_b, direction: INPUT, slew_rate: slow, open_drain: disable, drive_strength: low, pull_select: down,
161 pull_enable: disable, passive_filter: disable, digital_filter: disable}
162 - {pin_num: '34', peripheral: GPIOD, signal: 'GPIO, 2', pin_signal: PTD2, direction: INPUT, slew_rate: slow, open_drain: disable, drive_strength: low, pull_select: down,
163 pull_enable: disable, passive_filter: disable, digital_filter: disable}
164 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
165 */
166 /* clang-format on */
167
168 /* FUNCTION ************************************************************************************************************
169 *
170 * Function Name : BOARD_InitBUTTONSPins
171 * Description : Configures pin routing and optionally pin electrical features.
172 *
173 * END ****************************************************************************************************************/
BOARD_InitBUTTONSPins(void)174 void BOARD_InitBUTTONSPins(void)
175 {
176 /* Clock Gate Control: 0x01u */
177 CLOCK_EnableClock(kCLOCK_PortD);
178
179 gpio_pin_config_t SW3_config = {
180 .pinDirection = kGPIO_DigitalInput,
181 .outputLogic = 0U
182 };
183 /* Initialize GPIO functionality on pin PTD2 (pin 34) */
184 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
185
186 gpio_pin_config_t SW2_config = {
187 .pinDirection = kGPIO_DigitalInput,
188 .outputLogic = 0U
189 };
190 /* Initialize GPIO functionality on pin PTD3 (pin 33) */
191 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
192
193 const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */
194 kPORT_PullDisable,
195 /* Passive filter is disabled */
196 kPORT_PassiveFilterDisable,
197 /* Low drive strength is configured */
198 kPORT_LowDriveStrength,
199 /* Pin is configured as PTD2 */
200 kPORT_MuxAsGpio,
201 /* Pin Control Register fields [15:0] are not locked */
202 kPORT_UnlockRegister};
203 /* PORTD2 (pin 34) is configured as PTD2 */
204 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
205
206 const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
207 kPORT_PullDisable,
208 /* Passive filter is disabled */
209 kPORT_PassiveFilterDisable,
210 /* Low drive strength is configured */
211 kPORT_LowDriveStrength,
212 /* Pin is configured as PTD3 */
213 kPORT_MuxAsGpio,
214 /* Pin Control Register fields [15:0] are not locked */
215 kPORT_UnlockRegister};
216 /* PORTD3 (pin 33) is configured as PTD3 */
217 PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
218 }
219
220 /* clang-format off */
221 /*
222 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
223 BOARD_InitTHERMISTORPins:
224 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
225 - pin_list:
226 - {pin_num: '28', peripheral: ADC0, signal: 'SE, 3', pin_signal: ADC0_SE3/PTA7/FTM0_FLT2/LPSPI0_PCS3/RTC_CLKIN/LPUART1_RTS, drive_strength: low, pull_select: down,
227 pull_enable: disable, passive_filter: disable, digital_filter: disable}
228 - {pin_num: '29', peripheral: ADC0, signal: 'SE, 2', pin_signal: ADC0_SE2/PTA6/FTM0_FLT1/LPUART1_CTS, drive_strength: low, pull_select: down, pull_enable: disable,
229 passive_filter: disable, digital_filter: disable}
230 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
231 */
232 /* clang-format on */
233
234 /* FUNCTION ************************************************************************************************************
235 *
236 * Function Name : BOARD_InitTHERMISTORPins
237 * Description : Configures pin routing and optionally pin electrical features.
238 *
239 * END ****************************************************************************************************************/
BOARD_InitTHERMISTORPins(void)240 void BOARD_InitTHERMISTORPins(void)
241 {
242 /* Clock Gate Control: 0x01u */
243 CLOCK_EnableClock(kCLOCK_PortA);
244
245 const port_pin_config_t THER_B = {/* Internal pull-up/down resistor is disabled */
246 kPORT_PullDisable,
247 /* Passive filter is disabled */
248 kPORT_PassiveFilterDisable,
249 /* Low drive strength is configured */
250 kPORT_LowDriveStrength,
251 /* Pin is configured as ADC0_SE2 */
252 kPORT_PinDisabledOrAnalog,
253 /* Pin Control Register fields [15:0] are not locked */
254 kPORT_UnlockRegister};
255 /* PORTA6 (pin 29) is configured as ADC0_SE2 */
256 PORT_SetPinConfig(BOARD_THER_B_PORT, BOARD_THER_B_PIN, &THER_B);
257
258 const port_pin_config_t THER_A = {/* Internal pull-up/down resistor is disabled */
259 kPORT_PullDisable,
260 /* Passive filter is disabled */
261 kPORT_PassiveFilterDisable,
262 /* Low drive strength is configured */
263 kPORT_LowDriveStrength,
264 /* Pin is configured as ADC0_SE3 */
265 kPORT_PinDisabledOrAnalog,
266 /* Pin Control Register fields [15:0] are not locked */
267 kPORT_UnlockRegister};
268 /* PORTA7 (pin 28) is configured as ADC0_SE3 */
269 PORT_SetPinConfig(BOARD_THER_A_PORT, BOARD_THER_A_PIN, &THER_A);
270 }
271
272 /* clang-format off */
273 /*
274 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
275 BOARD_InitACCELPins:
276 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
277 - pin_list:
278 - {pin_num: '35', peripheral: LPI2C0, signal: SCL, pin_signal: PTA3/LPI2C0_SCL/EWM_IN/LPUART0_TX, drive_strength: low, pull_select: down, pull_enable: disable,
279 passive_filter: disable, digital_filter: disable}
280 - {pin_num: '36', peripheral: LPI2C0, signal: SDA, pin_signal: PTA2/LPI2C0_SDA/EWM_OUT_b/LPUART0_RX, drive_strength: low, pull_select: down, pull_enable: disable,
281 passive_filter: disable, digital_filter: disable}
282 - {pin_num: '32', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/FTM0_FLT3, direction: INPUT, gpio_interrupt: kPORT_InterruptOrDMADisabled, drive_strength: low,
283 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
284 - {pin_num: '41', peripheral: GPIOE, signal: 'GPIO, 6', pin_signal: PTE6/LPSPI0_PCS2/LPUART1_RTS, direction: OUTPUT, drive_strength: low, pull_select: down, pull_enable: disable,
285 passive_filter: disable, digital_filter: disable}
286 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
287 */
288 /* clang-format on */
289
290 /* FUNCTION ************************************************************************************************************
291 *
292 * Function Name : BOARD_InitACCELPins
293 * Description : Configures pin routing and optionally pin electrical features.
294 *
295 * END ****************************************************************************************************************/
BOARD_InitACCELPins(void)296 void BOARD_InitACCELPins(void)
297 {
298 /* Clock Gate Control: 0x01u */
299 CLOCK_EnableClock(kCLOCK_PortA);
300 /* Clock Gate Control: 0x01u */
301 CLOCK_EnableClock(kCLOCK_PortD);
302 /* Clock Gate Control: 0x01u */
303 CLOCK_EnableClock(kCLOCK_PortE);
304
305 gpio_pin_config_t ACCEL_INT_config = {
306 .pinDirection = kGPIO_DigitalInput,
307 .outputLogic = 0U
308 };
309 /* Initialize GPIO functionality on pin PTD4 (pin 32) */
310 GPIO_PinInit(BOARD_ACCEL_INT_GPIO, BOARD_ACCEL_INT_PIN, &ACCEL_INT_config);
311
312 gpio_pin_config_t ACCEL_RST_config = {
313 .pinDirection = kGPIO_DigitalOutput,
314 .outputLogic = 0U
315 };
316 /* Initialize GPIO functionality on pin PTE6 (pin 41) */
317 GPIO_PinInit(BOARD_ACCEL_RST_GPIO, BOARD_ACCEL_RST_PIN, &ACCEL_RST_config);
318
319 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
320 kPORT_PullDisable,
321 /* Passive filter is disabled */
322 kPORT_PassiveFilterDisable,
323 /* Low drive strength is configured */
324 kPORT_LowDriveStrength,
325 /* Pin is configured as LPI2C0_SDA */
326 kPORT_MuxAlt3,
327 /* Pin Control Register fields [15:0] are not locked */
328 kPORT_UnlockRegister};
329 /* PORTA2 (pin 36) is configured as LPI2C0_SDA */
330 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
331
332 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
333 kPORT_PullDisable,
334 /* Passive filter is disabled */
335 kPORT_PassiveFilterDisable,
336 /* Low drive strength is configured */
337 kPORT_LowDriveStrength,
338 /* Pin is configured as LPI2C0_SCL */
339 kPORT_MuxAlt3,
340 /* Pin Control Register fields [15:0] are not locked */
341 kPORT_UnlockRegister};
342 /* PORTA3 (pin 35) is configured as LPI2C0_SCL */
343 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
344
345 const port_pin_config_t ACCEL_INT = {/* Internal pull-up/down resistor is disabled */
346 kPORT_PullDisable,
347 /* Passive filter is disabled */
348 kPORT_PassiveFilterDisable,
349 /* Low drive strength is configured */
350 kPORT_LowDriveStrength,
351 /* Pin is configured as PTD4 */
352 kPORT_MuxAsGpio,
353 /* Pin Control Register fields [15:0] are not locked */
354 kPORT_UnlockRegister};
355 /* PORTD4 (pin 32) is configured as PTD4 */
356 PORT_SetPinConfig(BOARD_ACCEL_INT_PORT, BOARD_ACCEL_INT_PIN, &ACCEL_INT);
357
358 /* Interrupt configuration on PORTD4 (pin 32): Interrupt/DMA request is disabled */
359 PORT_SetPinInterruptConfig(BOARD_ACCEL_INT_PORT, BOARD_ACCEL_INT_PIN, kPORT_InterruptOrDMADisabled);
360 /* Configure digital filter */
361 PORT_EnablePinsDigitalFilter(
362 /* Digital filter is configured on port E */
363 PORTE,
364 /* Digital filter is configured for PORTE0 */
365 PORT_DFER_DFE_6_MASK,
366 /* Disable digital filter */
367 false);
368
369 const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */
370 kPORT_PullDisable,
371 /* Passive filter is disabled */
372 kPORT_PassiveFilterDisable,
373 /* Low drive strength is configured */
374 kPORT_LowDriveStrength,
375 /* Pin is configured as PTE6 */
376 kPORT_MuxAsGpio,
377 /* Pin Control Register fields [15:0] are not locked */
378 kPORT_UnlockRegister};
379 /* PORTE6 (pin 41) is configured as PTE6 */
380 PORT_SetPinConfig(BOARD_ACCEL_RST_PORT, BOARD_ACCEL_RST_PIN, &ACCEL_RST);
381 }
382
383 /* clang-format off */
384 /*
385 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
386 BOARD_InitDEBUG_UARTPins:
387 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
388 - pin_list:
389 - {pin_num: '26', peripheral: LPUART0, signal: TX, pin_signal: ADC0_SE5/PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0, drive_strength: low, pull_select: up, pull_enable: enable,
390 passive_filter: disable, digital_filter: disable}
391 - {pin_num: '27', peripheral: LPUART0, signal: RX, pin_signal: ADC0_SE4/PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/PWT_IN3, drive_strength: low, pull_select: up, pull_enable: enable,
392 passive_filter: disable, digital_filter: disable}
393 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
394 */
395 /* clang-format on */
396
397 /* FUNCTION ************************************************************************************************************
398 *
399 * Function Name : BOARD_InitDEBUG_UARTPins
400 * Description : Configures pin routing and optionally pin electrical features.
401 *
402 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)403 void BOARD_InitDEBUG_UARTPins(void)
404 {
405 /* Clock Gate Control: 0x01u */
406 CLOCK_EnableClock(kCLOCK_PortB);
407
408 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up resistor is enabled */
409 kPORT_PullUp,
410 /* Passive filter is disabled */
411 kPORT_PassiveFilterDisable,
412 /* Low drive strength is configured */
413 kPORT_LowDriveStrength,
414 /* Pin is configured as LPUART0_RX */
415 kPORT_MuxAlt2,
416 /* Pin Control Register fields [15:0] are not locked */
417 kPORT_UnlockRegister};
418 /* PORTB0 (pin 27) is configured as LPUART0_RX */
419 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
420
421 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up resistor is enabled */
422 kPORT_PullUp,
423 /* Passive filter is disabled */
424 kPORT_PassiveFilterDisable,
425 /* Low drive strength is configured */
426 kPORT_LowDriveStrength,
427 /* Pin is configured as LPUART0_TX */
428 kPORT_MuxAlt2,
429 /* Pin Control Register fields [15:0] are not locked */
430 kPORT_UnlockRegister};
431 /* PORTB1 (pin 26) is configured as LPUART0_TX */
432 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
433 }
434
435 /* clang-format off */
436 /*
437 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
438 BOARD_InitLEDsPins:
439 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
440 - pin_list:
441 - {pin_num: '1', peripheral: GPIOD, signal: 'GPIO, 1', pin_signal: TSI0_CH5/PTD1/FTM0_CH3/TRGMUX_OUT2, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low,
442 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
443 - {pin_num: '15', peripheral: GPIOB, signal: 'GPIO, 5', pin_signal: TSI0_CH9/PTB5/FTM0_CH5/LPSPI0_PCS1/TRGMUX_IN0, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low,
444 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
445 - {pin_num: '16', peripheral: GPIOB, signal: 'GPIO, 4', pin_signal: TSI0_CH8/PTB4/FTM0_CH4/LPSPI0_SOUT/TRGMUX_IN1, direction: OUTPUT, gpio_init_state: 'true', drive_strength: low,
446 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
447 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
448 */
449 /* clang-format on */
450
451 /* FUNCTION ************************************************************************************************************
452 *
453 * Function Name : BOARD_InitLEDsPins
454 * Description : Configures pin routing and optionally pin electrical features.
455 *
456 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)457 void BOARD_InitLEDsPins(void)
458 {
459 /* Clock Gate Control: 0x01u */
460 CLOCK_EnableClock(kCLOCK_PortB);
461 /* Clock Gate Control: 0x01u */
462 CLOCK_EnableClock(kCLOCK_PortD);
463
464 gpio_pin_config_t LED_GREEN_config = {
465 .pinDirection = kGPIO_DigitalOutput,
466 .outputLogic = 1U
467 };
468 /* Initialize GPIO functionality on pin PTB4 (pin 16) */
469 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
470
471 gpio_pin_config_t LED_RED_config = {
472 .pinDirection = kGPIO_DigitalOutput,
473 .outputLogic = 1U
474 };
475 /* Initialize GPIO functionality on pin PTB5 (pin 15) */
476 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
477
478 gpio_pin_config_t LED_BLUE_config = {
479 .pinDirection = kGPIO_DigitalOutput,
480 .outputLogic = 1U
481 };
482 /* Initialize GPIO functionality on pin PTD1 (pin 1) */
483 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
484
485 const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
486 kPORT_PullDisable,
487 /* Passive filter is disabled */
488 kPORT_PassiveFilterDisable,
489 /* Low drive strength is configured */
490 kPORT_LowDriveStrength,
491 /* Pin is configured as PTB4 */
492 kPORT_MuxAsGpio,
493 /* Pin Control Register fields [15:0] are not locked */
494 kPORT_UnlockRegister};
495 /* PORTB4 (pin 16) is configured as PTB4 */
496 PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
497
498 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
499 kPORT_PullDisable,
500 /* Passive filter is disabled */
501 kPORT_PassiveFilterDisable,
502 /* Low drive strength is configured */
503 kPORT_LowDriveStrength,
504 /* Pin is configured as PTB5 */
505 kPORT_MuxAsGpio,
506 /* Pin Control Register fields [15:0] are not locked */
507 kPORT_UnlockRegister};
508 /* PORTB5 (pin 15) is configured as PTB5 */
509 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
510
511 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
512 kPORT_PullDisable,
513 /* Passive filter is disabled */
514 kPORT_PassiveFilterDisable,
515 /* Low drive strength is configured */
516 kPORT_LowDriveStrength,
517 /* Pin is configured as PTD1 */
518 kPORT_MuxAsGpio,
519 /* Pin Control Register fields [15:0] are not locked */
520 kPORT_UnlockRegister};
521 /* PORTD1 (pin 1) is configured as PTD1 */
522 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
523 }
524
525 /* clang-format off */
526 /*
527 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
528 BOARD_InitCANPins:
529 - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
530 - pin_list:
531 - {pin_num: '39', peripheral: MSCAN, signal: TX, pin_signal: TSI0_CH16/PTC7/LPUART1_TX/CAN0_TX, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable,
532 digital_filter: disable}
533 - {pin_num: '40', peripheral: MSCAN, signal: RX, pin_signal: TSI0_CH15/PTC6/LPUART1_RX/CAN0_RX, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable,
534 digital_filter: disable}
535 - {pin_num: '24', peripheral: GPIOB, signal: 'GPIO, 3', pin_signal: ADC0_SE7/TSI0_CH21/PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2, direction: OUTPUT, drive_strength: low,
536 pull_select: down, pull_enable: disable, passive_filter: disable, digital_filter: disable}
537 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
538 */
539 /* clang-format on */
540
541 /* FUNCTION ************************************************************************************************************
542 *
543 * Function Name : BOARD_InitCANPins
544 * Description : Configures pin routing and optionally pin electrical features.
545 *
546 * END ****************************************************************************************************************/
BOARD_InitCANPins(void)547 void BOARD_InitCANPins(void)
548 {
549 /* Clock Gate Control: 0x01u */
550 CLOCK_EnableClock(kCLOCK_PortB);
551 /* Clock Gate Control: 0x01u */
552 CLOCK_EnableClock(kCLOCK_PortC);
553
554 gpio_pin_config_t CAN_STANDBY_config = {
555 .pinDirection = kGPIO_DigitalOutput,
556 .outputLogic = 0U
557 };
558 /* Initialize GPIO functionality on pin PTB3 (pin 24) */
559 GPIO_PinInit(BOARD_CAN_STANDBY_GPIO, BOARD_CAN_STANDBY_PIN, &CAN_STANDBY_config);
560
561 const port_pin_config_t CAN_STANDBY = {/* Internal pull-up/down resistor is disabled */
562 kPORT_PullDisable,
563 /* Passive filter is disabled */
564 kPORT_PassiveFilterDisable,
565 /* Low drive strength is configured */
566 kPORT_LowDriveStrength,
567 /* Pin is configured as PTB3 */
568 kPORT_MuxAsGpio,
569 /* Pin Control Register fields [15:0] are not locked */
570 kPORT_UnlockRegister};
571 /* PORTB3 (pin 24) is configured as PTB3 */
572 PORT_SetPinConfig(BOARD_CAN_STANDBY_PORT, BOARD_CAN_STANDBY_PIN, &CAN_STANDBY);
573
574 const port_pin_config_t CAN_RX = {/* Internal pull-up/down resistor is disabled */
575 kPORT_PullDisable,
576 /* Passive filter is disabled */
577 kPORT_PassiveFilterDisable,
578 /* Low drive strength is configured */
579 kPORT_LowDriveStrength,
580 /* Pin is configured as CAN0_RX */
581 kPORT_MuxAlt5,
582 /* Pin Control Register fields [15:0] are not locked */
583 kPORT_UnlockRegister};
584 /* PORTC6 (pin 40) is configured as CAN0_RX */
585 PORT_SetPinConfig(BOARD_CAN_RX_PORT, BOARD_CAN_RX_PIN, &CAN_RX);
586
587 const port_pin_config_t CAN_TX = {/* Internal pull-up/down resistor is disabled */
588 kPORT_PullDisable,
589 /* Passive filter is disabled */
590 kPORT_PassiveFilterDisable,
591 /* Low drive strength is configured */
592 kPORT_LowDriveStrength,
593 /* Pin is configured as CAN0_TX */
594 kPORT_MuxAlt5,
595 /* Pin Control Register fields [15:0] are not locked */
596 kPORT_UnlockRegister};
597 /* PORTC7 (pin 39) is configured as CAN0_TX */
598 PORT_SetPinConfig(BOARD_CAN_TX_PORT, BOARD_CAN_TX_PIN, &CAN_TX);
599 }
600 /***********************************************************************************************************************
601 * EOF
602 **********************************************************************************************************************/
603
